SII3132CNU TR - Silicon Image

SMSC UCS1002 Revision 1.4 (07-16-13)

DATASHEET

Datasheet

PRODUCT FEATURES

UCS1002-1

Programmable USB Port Power Controller

with Charger Emulation

General Description

The UCS1002 provides a USB port power switch for

precise control of up to 2.5 amperes continuous current

with over-current limit (OCL), dynamic thermal

management, latch or auto-recovery (low test current)

fault handling, selectable active low or high enable,

under- and over-voltage lockout, back-drive protection,

and back-voltage protection.

Split supply support for VS and VDD is an option for low

power in system standby states. This gives battery

operated applications, like notebook PCs, the ability to

detect attachments from a sleep or off state. After the

Attach Detection is flagged, the system can decide to

wake up and/or provide charging.

In addition to power switching and current limiting

modes, the UCS1002 will automatically charge a wide

variety of portable devices, including USB-IF BC1.2,

YD/T-1591 (2009), most Apple® and RIM®, and many

others. Nine preloaded charger emulation profiles

maximize compatibility coverage of peripheral devices.

As well, a customizable charger emulation profile is

available to accommodate unique existing and future

portable device handshaking / signature requirements.

This custom profile uses a unique stimulus and

response method referenced below.*

The UCS1002 also provides current monitoring to allow

intelligent management of system power and a Battery

Full option for controlled delivery of current regardless

of the host power state. This is especially important for

battery operated applications that want to provide power

in a standby and/or off state but do not want to drain the

battery excessively.

The UCS1002 is available in a 20-pin QFN 4 mm x

4 mm package.

Applications

Notebook and Netbook Computers

Tablets and E-book readers

Desktops and Monitors

Docking Stations and Printers

AC-DC wall adapters

Features

Port power switch with two current limit behaviors

— 2.9 V to 5.5 V source voltage range

— Up to 2.5 A current with 55 mΩ On Resistance

— Over-current trip or constant current limiting

— Soft turn-on circuitry

— Programmable current limit

— Dynamic thermal management

— Under- and over-voltage lockout

— Back-drive, back-voltage protection

— Latch or auto-recovery (low test current) fault handling

— Selectable active high or low power switch enable

— BC1.2 VBUS discharge port renegotiation function

Selectable / automatic cycling of USB data line

charger emulation profiles

— Customizable emulation profile uses a unique stimulus

and response method useful for future profiles*

— Supports charger emulation

— Allows for active cables

— USB-IF BC1.2 charging downstream port (CDP) &

dedicated charging port (DCP) modes, YD/T-1591, and

most Apple and RIM protocols standard; others as

defined via the SMBus 2.0 / I2C®

— USB 2.0 compliant high-speed data switch (in Pass-

through and CDP modes)

— Nine preloaded charger emulation profiles for maximum

compatibility coverage of peripheral devices

— One custom programmable charger emulation profile

for portable device support for fully host controlled

charger emulation

Fault Alert open-drain output

Self-contained current monitoring

Low power Attach Detection and open-drain A_DET#

Ultra low power Sleep state

Optional split supply support for VBUS and VDD for

low power in system standby states

Wake on Attach USB

SMBus 2.0 / I2C communications

— Supports Block Write and Read

— Multiple SMBus addresses

Wide operating temperature range: -40 °C to +85 °C

IEC61000-4-2 8 / 15 kV ESD immunity

UL recognized and EN/IEC 60950-1 (CB) certified

* Unique technology covered under the following US patents pending: 13/109,446; 13/149,529; 13/173,287; 13/233,949; 13/157,282;

12/978,371; 13/232,965.

Programmable USB Port Power Controller with Charger Emulation

Datasheet

Revision 1.4 (07-16-13) 2 SMSC UCS1002

DATASHEET

Block Diagram

Charger Control,

Measurement,

OCL

Interface,

Logic

SMCLK / S0

SMDATA / LATCH

A_DET#

ALERT#

Power

Switch

Temp

PWR_EN

DPOUT

DMOUT

DPIN

VDD

VS VBUS

DMIN

GND

USB 2.0 HS Data Switch

& Charger Emulator

COMM_SEL / ILIM

Attach Detector

SEL

EM_EN

VDD

UVLO,

OVLO

Programmable USB Port Power Controller with Charger Emulation

Datasheet

SMSC UCS1002 3 Revision 1.4 (07-16-13)

DATASHEET

REEL SIZE IS 4,000 PIECES

This product meets the halogen maximum concentration values per IEC61249-2-21

For RoHS compliance and environmental information, please visit www.smsc.com/rohs

Please contact your SMSC sales representative for additional documentation related to this product

such as application notes, anomaly sheets, and design guidelines.

ORDERING NUMBER PACKAGE FEATURES

UCS1002-1-BP-TR 20 pin QFN 4mm x 4mm

(RoHS compliant)

USB Port Power Controller with Charger

Emulation, 10W Emulation support,

Attachment Detection, Current

Monitoring, Current Rationing, and

Programmable SMBus address

Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for

construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC

reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications

before placing your product order. The provision of this information does not convey to the purchaser of the described semiconductor devices any licenses under any patent

rights or other intellectual property rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated

version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors

known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC products are not

designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property

damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of

this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC’s website at http://www.smsc.com. SMSC is a registered

trademark of Standard Microsystems Corporation (“SMSC”). Product names and company names are the trademarks of their respective holders.

The Microchip name and logo, and the Microchip logo are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES OF MERCHANTABILITY,

FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND ALL WARRANTIES ARISING FROM ANY COURSE

OF DEALING OR USAGE OF TRADE. IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL

DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT;

TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD

TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.

ORDERING INFORMATION:

Programmable USB Port Power Controller with Charger Emulation

Datasheet

Revision 1.4 (07-16-13) 4 SMSC UCS1002

DATASHEET

Table of Contents

Chapter 1 Terms and Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Chapter 2 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Chapter 3 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.1 ESD & Transient Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.1.1 Human Body Model (HBM) Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.1.2 Charged Device Model (CDM) Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.1.3 IEC61000-4-2 Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Chapter 4 Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.1 Operating Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.2 SMBus Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

4.2.1 System Management Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

4.2.2 SMBus and I2C Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

4.2.3 SMBus Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

4.2.4 I2C Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

4.3 Stand-alone Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Chapter 5 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

5.1 UCS1002 Power States. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

5.1.1 Off State Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

5.1.2 Sleep State Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

5.1.3 Detect State Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

5.1.4 Active State Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

5.1.5 Error State Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

5.2 Supply Voltages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

5.2.1 VDD Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

5.2.2 VS Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

5.2.3 Back-voltage Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

5.2.4 Back-drive Current Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

5.2.5 Under-voltage Lockout on VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

5.2.6 Over-voltage Detection and Lockout on VS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

5.3 Discrete Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

5.3.1 COMM_SEL / ILIM Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

5.3.2 SEL Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

5.3.3 M1, M2, and EM_EN Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

5.3.4 PWR_EN Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

5.3.5 Latch Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

5.3.6 S0 Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

5.4 Discrete Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

5.4.1 ALERT# and A_DET# Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

5.4.2 Interrupt Blanking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Chapter 6 USB High-speed Data Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

6.1 USB High-speed Data Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

6.1.1 USB-IF High-speed Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Programmable USB Port Power Controller with Charger Emulation

Datasheet

SMSC UCS1002 5 Revision 1.4 (07-16-13)

DATASHEET

Chapter 7 USB Port Power Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

7.1 USB Port Power Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

7.2 Current Limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

7.2.1 Current Limit Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

7.2.2 Short Circuit Output Current Limiting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

7.2.3 Soft Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

7.2.4 Current Limiting Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

7.3 Thermal Management and Voltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

7.3.1 Thermal Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

7.4 VBUS Discharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

7.5 Battery Full . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

7.5.1 Charge Rationing Interactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

7.6 Fault Handling Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

7.6.1 Auto-recovery Fault Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

7.6.2 Latched Fault Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Chapter 8 Detect State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

8.1 Device Attach / Removal Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

8.2 VBUS Bypass Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

8.3 Attach Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

8.4 Removal Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Chapter 9 Active State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

9.1 Active State Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

9.2 Active Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

9.3 BC1.2 Detection Renegotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

9.4 Data Pass-through (No Charger Emulation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

9.5 BC1.2 SDP (No Charger Emulation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

9.6 BC1.2 CDP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

9.6.1 BC1.2 CDP Charger Emulation Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

9.7 BC1.2 DCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

9.7.1 BC1.2 DCP Charger Emulation Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

9.8 Dedicated Charger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

9.8.1 Emulation Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

9.8.2 Emulation Cycling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

9.8.3 DCE Cycle Retry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

9.9 Current Limit Mode Associations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

9.10 No Handshake. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

9.11 Preloaded Charger Emulation Profiles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

9.11.1 BC1.2 DCP Charger Emulation Profile Within DCE Cycle . . . . . . . . . . . . . . . . . . . . . . . . . 65

9.11.2 Legacy 2 Charger Emulation Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

9.11.3 Legacy 1, 3, 4, and 6 Charger Emulation Profiles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

9.11.4 Legacy 5 Charger Emulation Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

9.11.5 Legacy 7 Charger Emulation Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

9.12 Custom Charger Emulation Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Chapter 10 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

10.1 Current Measurement Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

10.2 Total Accumulated Charge Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

10.3 Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Programmable USB Port Power Controller with Charger Emulation

Datasheet

Revision 1.4 (07-16-13) 6 SMSC UCS1002

DATASHEET

10.3.1 Other Status - 0Fh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

10.3.2 Interrupt Status - 10h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

10.3.3 General Status - 11h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

10.3.4 Profile Status 1 - 12h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

10.3.5 Profile Status 2 - 13h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

10.3.6 Pin Status Register - 14h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

10.4 Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

10.4.1 General Configuration - 15h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

10.4.2 Emulation Configuration - 16h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

10.4.3 Switch Configuration - 17h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

10.4.4 Attach Detection Configuration - 18h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

10.4.5 High-speed Switch Configuration - 25h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

10.5 Current Limit Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

10.6 Charge Rationing Threshold Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

10.7 Auto-recovery Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

10.8 IBUS_CHG Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

10.9 tDET_CHARGE Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

10.10 Preloaded Emulation Enable Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

10.10.1 BCS Emulation Enable - 20h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

10.10.2 Legacy Emulation Enable - 21h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

10.11 Preloaded Emulation Timeout Configuration Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

10.11.1 BCS Emulation Timeout Config - 22h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

10.11.2 Legacy Emulation Timeout Config 1 - 23h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

10.11.3 Legacy Emulation Timeout Config 2 - 24h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

10.12 Preloaded Emulation Configuration Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

10.12.1 Applied Charger Emulation - 30h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

10.12.2 Preloaded Emulation Configuration Registers 31h - 3Bh . . . . . . . . . . . . . . . . . . . . . . . . . 91

10.12.3 Preloaded Emulation Stimulus X - Config 1 - 31h, 35h, 39h . . . . . . . . . . . . . . . . . . . . . . . 92

10.12.4 BC1.2 Emulation Stimulus X - Config 2 - 32h, 36h, 3Ah . . . . . . . . . . . . . . . . . . . . . . . . . . 93

10.12.5 Emulation Stimulus X - Config 3 - 33h, 37h, 3Bh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

10.12.6 Emulation Stimulus X - Config 4 - 34h, 38h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

10.13 Custom Emulation Configuration Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

10.13.1 Custom Emulation Configuration - 40h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

10.13.2 Custom Stimulus / Response Pair X - Config 1 - 41h, 45h, 49h . . . . . . . . . . . . . . . . . . . 101

10.13.3 Custom Stimulus / Response Pair X - Config 2 - 42h, 46h, 4Ah . . . . . . . . . . . . . . . . . . . 101

10.13.4 Custom Stimulus / Response Pair X - Config 3 - 43h, 47h, 4Bh . . . . . . . . . . . . . . . . . . . 101

10.13.5 Custom Stimulus / Response Pair X - Config 4 - 44h, 48h, 4Ch . . . . . . . . . . . . . . . . . . . 102

10.14 Current Limiting Behavior Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

10.14.1 Applied Current Limiting Behavior - 50h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

10.14.2 Custom Current Limiting Behavior Configuration - 51h . . . . . . . . . . . . . . . . . . . . . . . . . . 102

10.15 Product ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

10.16 Manufacturer ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

10.17 Revision Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Chapter 11 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Chapter 12 Typical Operating Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Chapter 13 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Chapter 14 Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Programmable USB Port Power Controller with Charger Emulation

Datasheet

SMSC UCS1002 7 Revision 1.4 (07-16-13)

DATASHEET

List of Tables

Table 1.1 Terms and Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 2.1 UCS1002 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 2.2 Pin Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 3.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 3.2 Power Dissipation Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 3.3 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 3.4 ESD Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 4.1 UCS1002 Communication Mode and ILIM Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 4.2 SEL Pin Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 4.3 Protocol Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 4.4 Write Byte Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 4.5 Read Byte Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 4.6 Send Byte Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 4.7 Receive Byte Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 4.8 Block Write Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 4.9 Block Read Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 4.10 Stand-alone Fault and Attach Detection Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 5.1 Power States Control Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 7.1 Charge Rationing Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 7.2 Charge Rationing Reset Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 7.3 Effects of Changing Rationing Behavior after Threshold Reached . . . . . . . . . . . . . . . . . . . . . 55

Table 9.1 Active Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 9.2 Current Limit Mode Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Table 10.1 Register Set in Hexadecimal Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Table 10.2 Current Measurement Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Table 10.3 Total Accumulated Charge Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Table 10.4 Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Table 10.5 EM_STEP Bit Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Table 10.6 PWR_STATE Bit Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Table 10.7 Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Table 10.8 EM_RESET_TIME Bit Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Table 10.9 Discharge Time Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Table 10.10Attach / Removal Detection Threshold Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Table 10.11Current Limit Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Table 10.12ILIM_SW Bit Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Table 10.13Charge Rationing Threshold Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Table 10.14Auto-recovery Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Table 10.15tCYCLE Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Table 10.16TRST_SW Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Table 10.17VTST_SW Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Table 10.18IBUS_CHG Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Table 10.19tDET_CHARGE Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Table 10.20DC_TEMP_SET Bit Decode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Table 10.21DET_CHARGE_SET Bit Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Table 10.22Preloaded Emulation Enable Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Table 10.23Preloaded Emulation Timeout Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Table 10.24X_EM_TIMEOUT Bit Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Table 10.25Preloaded Emulation Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Table 10.26Applied Emulation Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Table 10.27Stimulus Delay Time Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Programmable USB Port Power Controller with Charger Emulation

Datasheet

Revision 1.4 (07-16-13) 8 SMSC UCS1002

DATASHEET

Table 10.28Stimulus Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Table 10.29Stimulus Response. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Table 10.30Response Magnitude Meaning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Table 10.31Voltage Divider Minimum Impedance Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Table 10.32Stimulus Response Resistor Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Table 10.33Stimulus Response Voltage Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Table 10.34Pull-Down Magnitude . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Table 10.35Stimulus Threshold Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Table 10.36Voltage Divider Ratio Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Table 10.37Custom Emulation Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Table 10.38Current Limit Behavior Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Table 10.39VBUS_MIN Threshold Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Table 10.40IBUS_R2MIN Threshold Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Table 10.41Product ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Table 10.42Manufacturer ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Table 10.43Revision Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Table 14.1 Customer Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Programmable USB Port Power Controller with Charger Emulation

Datasheet

SMSC UCS1002 9 Revision 1.4 (07-16-13)

DATASHEET

List of Figures

Figure 2.1 UCS1002 Pin Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 3.1 USB Rise Time / Fall Time Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 3.2 Description of DC Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 4.1 SMBus Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 5.1 UCS1002 Full-Featured System Configuration (SMBus Control) . . . . . . . . . . . . . . . . . . . . . 34

Figure 5.2 UCS1002 System Configuration (Charger Emulation, No SMBus, with USB Host) . . . . . . . 35

Figure 5.3 UCS1002 System Configuration (No SMBus, No Charger Emulation) . . . . . . . . . . . . . . . . . 36

Figure 5.4 UCS1002 System Configuration (No SMBus, No USB Host, with Charger Emulation). . . . . 37

Figure 5.5 Wake Timing via External Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 5.6 Wake Via SMBus Read with S0 = ‘0’ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 7.1 Trip Current Limiting Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 7.2 Constant Current Limiting (Variable Slope) Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 7.3 Error Recovery Timing (Short Circuit Example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Figure 8.1 Detect State VBUS Biasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Figure 11.1 UCS1002 Package View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Figure 11.2 UCS1002 Package Dimensions and Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Figure 12.1 USB-IF High-speed Eye Diagram (without data switch) . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Figure 12.2 USB-IF High-speed Eye Diagram (with data switch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Figure 12.3 Short Applied After Power Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Figure 12.4 Power Up Into A Short . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Figure 12.5 Internal Power Switch Short Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Figure 12.6 VBUS Discharge Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Figure 12.7 Data Switch Off Isolation vs. Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Figure 12.8 Data Switch Bandwidth vs. Frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Figure 12.9 Data Switch On Resistance vs. Temp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Figure 12.10Power Switch On Resistance vs. Temp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Figure 12.11RDCP_RES Resistance vs.Temp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Figure 12.12Power Switch On / Off Time vs. Temp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Figure 12.13VS Over-Voltage Threshold vs. Temp. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Figure 12.14VS Under Voltage Threshold vs. Temp. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Figure 12.15Detect State VBUS vs. IBUS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Figure 12.16Trip Current Limit Operation vs. Temp. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Figure 12.17IBUS Measurement Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Figure 12.18Active State Current vs. Temp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Figure 12.19Detect State Current vs. Temp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Figure 12.20Sleep State Current vs. Temp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Programmable USB Port Power Controller with Charger Emulation

Datasheet

Revision 1.4 (07-16-13) 10 SMSC UCS1002

DATASHEET

Chapter 1 Terms and Abbreviations

APPLICATION NOTE: The M1, M2, PWR_EN, and EM_EN pins each have configuration bits (<pin name>_SET in

Section 10.4.3, "Switch Configuration - 17h") that may be used to perform the same function

as the external pin state. These bits are accessed via the SMBus / I2C and are OR’d with

the respective pin. This OR’d combination of pin state and register bit is referenced as the

<pin name> control.

Table 1.1 Terms and Abbreviations

TERM /

ABBREVIATION DESCRIPTION

Active mode Active power state operation mode: Data Pass-through, BC1.2 SDP, BC1.2 CDP, BC1.2

DCP, or Dedicated Charger Emulation Cycle.

Attach Detection An Attach Detection event occurs when the current drawn by a portable device is greater

than IDET_QUAL for longer than tDET_QUAL.

attachment The physical insertion of a portable device into a USB port that UCS1002 is controlling.

CC Constant current

CDM Charged Device Model. JEDEC model for characterizing susceptibility of a device to

damage from ESD.

CDP or USB-IF

BC1.2 CDP

Charging downstream port. The combination of the UCS1002 CDP handshake and an

active standard USB host comprises a CDP. This enables a BC1.2 compliant portable

device to simultaneously draw current up to 1.5 A while data communication is active. The

USB high-speed data switch is closed in this mode.

charge enable When a charger emulation profile has been accepted by a portable device and charging

commences.

charger emulation

profile Representation of a charger comprised of DPOUT, DMOUT, and VBUS signalling which

make up a defined set of signatures or handshaking protocols.

connection USB-IF term which refers to establishing active USB communications between a USB host

and a USB device.

current limiting mode Determines the action that is performed when the IBUS current reaches the ILIM threshold.

Trip opens the port power switch. Constant current (variable slope) allows VBUS to be

dropped by the portable device.

DCE Dedicated charger emulation. Charger emulation in which the UCS1002 can deliver power

only (by default). No active USB data communication is possible when charging in this

mode (by default).

DCP or USB-IF

BC1.2 DCP

Dedicated Charging Port. This functions as a dedicated charger for a BC1.2 portable

device. This allows the portable device to draw currents up to 1.5 A with constant current

limiting (and beyond 1.5 A with trip current limiting). No USB communications are possible

(by default).

DC Dedicated charger. A charger which inherently does not have USB communications, such

as an A/C wall adapter.

disconnection USB-IF term which refers to the loss of active USB communications between a USB host

and a USB device.

Programmable USB Port Power Controller with Charger Emulation

Datasheet

SMSC UCS1002 11 Revision 1.4 (07-16-13)

DATASHEET

dynamic thermal

management

The UCS1002 automatically adjusts port power switch limits and modes to lower internal

power dissipation when the thermal regulation temperature value is approached.

enumeration A USB-specific term that indicates that a host is detecting and identifying USB devices.

handshake Application of a charger emulation profile that requires a response. Two-way

communication between the UCS1002 and the portable device.

HBM Human Body Model.

HSW High-speed switch.

IBUS_R2MIN Current limiter mode boundary.

ILIM The IBUS current threshold used in current limiting. In trip mode, when ILIM is reached,

the port power switch is opened. In constant current mode, when the current exceeds ILIM,

operation continues at a reduced voltage and increased current; if VBUS voltage drops

below VBUS_MIN, the port power switch is opened.

Legacy USB devices that require non-BC1.2 signatures be applied on the DPOUT and DMOUT

pins to enable charging.

OCL Over-current limit.

POR Power-on reset.

portable device USB device attached to the USB port.

power thief A USB device that does not follow the handshaking conventions of a BC1.2 device or

Legacy devices and draws current immediately upon receiving power (i.e., a USB book

light, portable fan, etc).

Removal Detection A Removal Detection event occurs when the current load on the VBUS pin drops to less

than IREM_QUAL for longer than tREM_QUAL.

removal The physical removal of a portable device from a USB port that the UCS1002 is controlling.

response An action, usually in response to a stimulus, in charger emulation performed by the

UCS1002 device via the USB data lines.

SDP or USB-IF SDP Standard downstream port. The combination of the UCS1002 high-speed switch being

closed with an upstream USB host present comprises a BC1.2 SDP. This enables a BC1.2

compliant portable device to simultaneously draw current up to 0.5 A while data

communication is active.

signature Application of a charger emulation profile without waiting for a response. One-way

communication from the UCS1002 to the portable device.

Stand-alone mode Indicates that the communications protocol is not active and all communications between

the UCS1002 and a controller are done via the external pins only (M1, M2, EM_EN,

PWR_EN, S0, and LATCH as inputs and ALERT# and A_DET# as outputs).

stimulus An event in charger emulation detected by the UCS1002 device via the USB data lines.

Table 1.1 Terms and Abbreviations (continued)

TERM /

ABBREVIATION DESCRIPTION

Programmable USB Port Power Controller with Charger Emulation

Datasheet

Revision 1.4 (07-16-13) 12 SMSC UCS1002

DATASHEET

Chapter 2 Pin Description

The pin types are described in Table 2.2. All pins are 5 V tolerant.

Figure 2.1 UCS1002 Pin Diagram

Table 2.1 UCS1002 Pin Description

NUMBER PIN NAME PIN FUNCTION PIN TYPE

IF PIN NOT USED

CONNECTION

1 M1 Active mode selector input #1 DI Connect to ground

or VDD (see

Note 2.3)

2 M2 Active mode selector input #2 DI Connect to ground

or VDD (see

Note 2.3)

3 VBUS1 Voltage output from Power Switch.

These pins must be tied together.

Hi-Power,

AIO

Note 2.1

Leave open

4 VBUS2

EM_EN

PWR_EN

COMM_SEL / ILIM

VBUS1

VBUS2

VS2

VDD

DPIN

SMCLK / S0

A_DET#

DPOUT

SEL

DMOUT

SMDATA / LATCH

DMIN

ALERT#

GND

VS1

GND FLAG

UCS1002

20-QFN 4mm x 4mm

Programmable USB Port Power Controller with Charger Emulation

Datasheet

SMSC UCS1002 13 Revision 1.4 (07-16-13)

DATASHEET

5 COMM_SEL /

ILIM

COMM_SEL - Selects SMBus address

or Stand-alone mode of operation

AIO n/a

ILIM - Selects the maximum current

limit at power-up

6 SEL Selects whether PWR_EN is active

high or active low and determines the

SMBus address

AIO n/a

7 VS1 Voltage input to Power Switch.

These pins must be tied together.

Hi-Power,

AIO

Connect to ground

8 VS2

9 VDD Main power supply input for chip

functionality

Power n/a

10 PWR_EN Port power switch enable input. Polarity

determined by SEL pin.

DI Connect to ground

or VDD (see

Note 2.3)

11 SMDATA /

LATCH

SMDATA - SMBus data input/output

(requires pull-up resistor)

DIOD n/a

LATCH - In Stand-alone mode, Latch /

Auto-recovery fault handling

mechanism selection input

12 SMCLK / S0 SMCLK - SMBus Clock Input (requires

pull-up resistor)

DI n/a

S0 - In Stand-alone mode, enables

Attach / Removal Detection feature

13 ALERT# Active low error event output flag

(requires pull-up resistor)

OD Connect to ground

14 DPIN USB data input (plus) AIO Connect to ground

or ground through

a resistor

15 DMIN USB data input (minus) AIO Connect to ground

or ground through

a resistor

16 DMOUT USB data output (minus) AIO (see

Note 2.2)

Connect to ground

17 DPOUT USB data output (plus) AIO (see

Note 2.2)

Connect to ground

18 A_DET# Active low Attach Detection output flag

(requires pull-up resistor)

OD Connect to ground

19 EM_EN Active mode selector input DI Connect to ground

or VDD (see

Note 2.3)

Table 2.1 UCS1002 Pin Description (continued)

NUMBER PIN NAME PIN FUNCTION PIN TYPE

IF PIN NOT USED

CONNECTION

Programmable USB Port Power Controller with Charger Emulation

Datasheet

Revision 1.4 (07-16-13) 14 SMSC UCS1002

DATASHEET

Note 2.1 Total leakage current from pins 3 and 4 (VBUS) to ground must be less than 100 µA for

proper attach / removal detection operation.

Note 2.2 It is recommended to use 2 MΩ pull-down resistors on the DPOUT pin and / or DMOUT

pin if a portable device stimulus is expected when using the Custom charger emulation

profile with the high-speed data switch open. The 2 MΩ value is based on BC1.1

impedance characteristics for Dedicated Charging Ports.

Note 2.3 To ensure operation, the PWR_EN pin must be enabled, as determined by the SEL pin

decode, when it is not driven by an external device. Furthermore, one of the M1, M2, or

EM_EN pins must be connected to VDD if all three are not driven from an external device.

If the PWR_EN is disabled or all of the M1, M2, and EM_EN are connected to ground, the

UCS1002 will remain in the Sleep or Detect state unless activated via the SMBus.

20 GND Ground Power n/a

Bottom Pad GND FLAG Thermal connection to ground plane Thermal Pad n/a

Table 2.2 Pin Types

PIN TYPE DESCRIPTION

Power This pin is used to supply power or ground to the device.

Hi-Power This pin is a high current pin.

AIO Analog Input / Output - this pin is used as an I/O for analog signals.

DI Digital Input - this pin is used as a digital input.

DIOD Open-drain Digital Input / Output - this pin is bidirectional. It is open-drain and requires a pull-

up resistor.

OD Open-drain Digital Output - used as a digital output. It is open-drain and requires a pull-up

resistor.

Table 2.1 UCS1002 Pin Description (continued)

NUMBER PIN NAME PIN FUNCTION PIN TYPE

IF PIN NOT USED

CONNECTION

Programmable USB Port Power Controller with Charger Emulation

Datasheet

SMSC UCS1002 15 Revision 1.4 (07-16-13)

DATASHEET

Chapter 3 Electrical Specifications

Note: Stresses above those listed could cause permanent damage to the UCS1002. This is a stress

rating only and functional operation of the UCS1002 at any other condition above those

indicated in the operation sections of this specification is not implied.

Note 3.1 A High K board uses a thermal via design with the thermal landing soldered to the PCB

ground plane with 0.3 mm (12 mil) diameter vias in a 3x3 matrix (9 total) at 0.5 mm (20 mil)

pitch. The board is multi-layer with 1-ounce internal power and ground planes and 2-ounce

copper traces on top and bottom. A Low K board is a two layer board without thermal via

design with 2-ounce copper traces on the top and bottom.

Table 3.1 Absolute Maximum Ratings

Voltage on VDD, VS, and VBUS pins -0.3 to 6 V

Pullup voltage (VPULLUP) -0.3 to VDD + 0.3

Data switch current (IHSW_ON), switch on ±50 mA

Port power switch current Internally limited

Data switch pin voltage to ground (DPOUT, DPIN, DMOUT,

DMIN); (VDD powered or unpowered)

-0.3 to VDD + 0.3 V

Differential voltage across open data switch (DPOUT - DPIN,

DMOUT - DMIN, DPIN - DPOUT, DMIN - DMOUT)

VDD V

Voltage on any other pin to ground -0.3 to VDD + 0.3 V

Current on any other pin ±10 mA

Package power dissipation See Ta b l e 3 . 2

Operating ambient temperature range -40 to 125 °C

Storage temperature range -55 to 150 °C

Table 3.2 Power Dissipation Summary

BOARD PKG θJC θJA

DERATING

FACTOR

ABOVE 25 °C

TA <

25 °C

POWER

RATING

TA =

70 °C

POWER

RATING

TA =

85 °C

POWER

RATING

High K

(see Note 3.1)

20-pin QFN

4 mm x 4 mm

6°C /

41 °C /

24.4 mW / °C 2193 mW 1095 mW 729 mW

Low K

(see Note 3.1)

20-pin QFN

4 mm x 4 mm

6°C /

60 °C /

16.67 mW /

°C

1498 mW 748 mW 498 mW

Programmable USB Port Power Controller with Charger Emulation

Datasheet

Revision 1.4 (07-16-13) 16 SMSC UCS1002

DATASHEET

Table 3.3 Electrical Specifications

VDD = 4.5 V to 5.5 V, VS = 2.9 V to 5.5 V, VPULLUP = 3V to 5.5V, T

A = -40 °C to 85 °C

all Typical values at VDD = VS = 5 V, TA = 27 °C unless otherwise noted.

CHARACTERISTIC SYMBOL MIN TYP MAX UNIT CONDITIONS

Power and Interrupts - DC

Supply Voltage VDD 4.5 5 5.5 V See Note 3.2

Source Voltage VS 2.9 5 5.5 V See Note 3.2

Supply Current in Active

(IDD_ACTIVE + IVS_ACT)

IACTIVE 650 750 µA Average current

IBUS = 0 mA

Supply Current in Sleep

(IDD_SLEEP + IVS_SLEEP)

ISLEEP 5 15 µA Average current

VPULLUP < VDD

Supply Current in Detect

(IDD_DETECT +

IVS_DETECT)

IDETECT 185 220 µA Average current

No portable device attached.

Power-on Reset

VS Low Threshold VS_UVLO 2.5 2.7 V VS voltage increasing

VS Low Hysteresis VS_UVLO_HYST 100 mV VS voltage decreasing

VDD Low Threshold VDD_TH 4 4.4 V VDD voltage increasing

VDD Low Hysteresis VDD_TH_HYST 500 mV VDD voltage decreasing

I/O Pins - SMCLK, SMDATA, EM_EN, M1, M2, PWR_EN, ALERT#, A_DET# - DC Parameters

Output Low Voltage VOL 0.4 V ISINK_IO = 8 mA

SMDATA, ALERT#, A_DET#

Input High Voltage VIH 2.0 V PWR_EN, EM_EN, M1, M2,

SMDATA, SMCLK

Input Low Voltage VIL 0.8 V PWR_EN, EM_EN, M1, M2,

EM_EN, SMDATA, SMCLK

Leakage Current ILEAK ±5 µA Powered or unpowered

VPULLUP <= VDD

TA < 85 °C

Interrupt Pins - AC Parameters

ALERT#, A_DET# Pin

Blanking Time

tBLANK 25 ms

ALERT# Pin Interrupt

Masking Time

tMASK 5ms

Programmable USB Port Power Controller with Charger Emulation

Datasheet

SMSC UCS1002 17 Revision 1.4 (07-16-13)

DATASHEET

SMBus / I2C Timing

Input Capacitance CIN 5pF

Clock Frequency fSMB 10 400 kHz

Spike Suppression tSP 50 ns

Bus Free Time Stop to

Start

tBUF 1.3 µs

Start Setup Time tSU:STA 0.6 µs

Start Hold Time tHD:STA 0.6 µs

Stop Setup Time tSU:STO 0.6 µs

Data Hold Time tHD:DAT 0 µs When transmitting to the

master

Data Hold Time tHD:DAT 0.3 µs When receiving from the

master

Data Setup Time tSU:DAT 0.6 µs

Clock Low Period tLOW 1.3 µs

Clock High Period tHIGH 0.6 µs

Clock / Data Fall Time tFALL 300 ns Min = 20+0.1CLOAD ns

Clock / Data Rise Time tRISE 300 ns Min = 20+0.1CLOAD ns

Capacitive Load CLOAD 400 pF Per bus line

Timeout tTIMEOUT 25 35 ms Disabled by default

Idle Reset tIDLE_RESET 350 µs Disabled by default.

High-speed Data Switch

High-speed Data Switch - DC Parameters

Switch Leakage Current IHSW_OFF ±0.5 µA Switch open - DPIN to DPOUT,

DMIN to DMOUT, or all four

pins to ground. VDD < VS.

Charger Resistance RCHG 2MΩDPOUT or DMOUT to VBUS or

ground, see Figure 3.2

BC1.2 DCP charger emulation

active

Table 3.3 Electrical Specifications (continued)

VDD = 4.5 V to 5.5 V, VS = 2.9 V to 5.5 V, VPULLUP = 3V to 5.5V, T

A = -40 °C to 85 °C

all Typical values at VDD = VS = 5 V, TA = 27 °C unless otherwise noted.

CHARACTERISTIC SYMBOL MIN TYP MAX UNIT CONDITIONS

Programmable USB Port Power Controller with Charger Emulation

Datasheet

Revision 1.4 (07-16-13) 18 SMSC UCS1002

DATASHEET

On Resistance RON_HSW 2ΩSwitch closed, VDD = 5 V

test current = 8 mA, test

voltage = 0.4 V, see Figure 3.2

On Resistance RON_HSW_1 5ΩSwitch closed, VDD = 5 V,

test current = 8 mA, test

voltage = 3.0 V, see Figure 3.2

Delta On Resistance ΔRON_HSW ±0.3 ΩSwitch closed, VDD = 5 V

ITST = 8 mA, VTST = 0 to 1.5 V,

see Figure 3.2

High-speed Data Switch - AC Parameters

DP, DM Capacitance to

Ground

CHSW_ON 4 pF Switch closed

VDD = 5 V

DP, DM Capacitance to

Ground

CHSW_OFF 2 pF Switch open

VDD = 5 V

Turn Off Time tHSW_OFF 400 µs Time from state control

(EM_EN, M1, M2) switch on to

switch off, RTERM = 50 Ω,

CLOAD = 5 pF

Turn On Time tHSW_ON 400 µs Time from state control

(EM_EN, M1, M2) switch off to

switch on, RTERM = 50 Ω,

CLOAD = 5 pF

Propagation Delay tPD 0.25 ns RTERM = 50 Ω, CLOAD = 5 pF

Propagation Delay Skew ΔtPD 25 ps RTERM = 50 Ω, CLOAD = 5 pF

Rise/Fall Time tF/R 10 ns RTERM = 50 Ω, CLOAD = 5 pF

DP - DM Crosstalk XTALK -40 dB RTERM = 50 Ω, CLOAD = 5 pF

Off Isolation OIRR -30 dB RTERM = 50 Ω, CLOAD = 5 pF

f = 240 MHz

-3dB Bandwidth BW 1100 MHz RTERM = 50 Ω, CLOAD = 1.5 pF

VDPOUT = VDMOUT = 350 mV

Total Jitter tJ200 ps RTERM = 50 Ω, CLOAD = 5 pF,

rise time = fall time = 500 ps at

480 Mbps (PRBS = 215 - 1)

Skew of Opposite

Transitions of the Same

Output

tSK(P) 20 ps RTERM = 50 Ω, CLOAD = 5 pF

Table 3.3 Electrical Specifications (continued)

VDD = 4.5 V to 5.5 V, VS = 2.9 V to 5.5 V, VPULLUP = 3V to 5.5V, T

A = -40 °C to 85 °C

all Typical values at VDD = VS = 5 V, TA = 27 °C unless otherwise noted.

CHARACTERISTIC SYMBOL MIN TYP MAX UNIT CONDITIONS

Programmable USB Port Power Controller with Charger Emulation

Datasheet

SMSC UCS1002 19 Revision 1.4 (07-16-13)

DATASHEET

Port Power Switch

Port Power Switch - DC Parameter

Over-voltage Lockout VS_OV 6V

On Resistance RON_PSW 55 65 mΩ4.75 V < VS < 5.25 V

VS Leakage Current ILEAK_VS 2.2 5 µA Sleep state

into VS pin

Back-voltage Protection

Threshold

VBV_TH 150 mV VBUS > VS

VS > VS_UVLO

Back-drive Current IBD_1 0 3 µA VDD < VDD_TH,

Any powered power pin to any

unpowered power pin. Current

out of unpowered pin.

IBD_2 0 2 µA VDD > VDD_TH,

Any powered power pin to any

unpowered power pin, except

for VDD to VBUS in Detect

power state and VS to VBUS in

Active power state. Current out

of unpowered pin.

Selectable Current Limits ILIM1 450 467 500 mA ILIM Resistor = 0 or 47 kΩ

(500 mA setting)

ILIM2 810 839 900 mA ILIM Resistor = 10 kΩ or 56 kΩ

(900 mA setting)

ILIM3 900 932 1000 mA ILIM Resistor = 12 kΩ or 68 kΩ

(1000 mA setting)

ILIM4 1080 1112 1200 mA ILIM Resistor = 15 kΩ or 82 kΩ

(1200 mA setting)

ILIM5 1350 1385 1500 mA ILIM Resistor = 18 kΩ or

100 kΩ

(1500 mA setting)

ILIM6 1620 1702 1800 mA ILIM Resistor = 22 kΩ or

120 kΩ

(1800 mA setting)

ILIM7 1800 1892 2000 mA ILIM Resistor = 27 kΩ or

150 kΩ

(2000 mA setting)

ILIM8 2250 2355 2500 mA ILIM Resistor = 33 kΩ or VDD

(2500 mA setting)

Pin Wake Time tPIN_WAKE 3ms

Table 3.3 Electrical Specifications (continued)

VDD = 4.5 V to 5.5 V, VS = 2.9 V to 5.5 V, VPULLUP = 3V to 5.5V, T

A = -40 °C to 85 °C

all Typical values at VDD = VS = 5 V, TA = 27 °C unless otherwise noted.

CHARACTERISTIC SYMBOL MIN TYP MAX UNIT CONDITIONS

Programmable USB Port Power Controller with Charger Emulation

Datasheet

Revision 1.4 (07-16-13) 20 SMSC UCS1002

DATASHEET

SMBus Wake Time tSMB_WAKE 4ms

Idle Sleep Time tIDLE_SLEEP 200 ms

Thermal Regulation Limit TREG 110 °C Die Temperature at which

current limit will be reduced

Thermal Regulation

Hysteresis

TREG_HYST 10 °C Hysteresis for tREG

functionality. Temperature must

drop by this value before ILIM

value restored to normal

operation

Thermal Shutdown

Threshold

TTSD 135 °C Die Temperature at which port

power switch will turn off

Thermal Shutdown

Hysteresis

TTSD_HYST 35 °C After shutdown due to TTSD

being reached, die temperature

drop required before port power

switch can be turned on again

Auto-recovery Test

Current

ITEST 190 mA Portable device attached,

VBUS = 0 V, Die temp < TTSD

Auto-recovery Test

Voltage

VTEST 750 mV Portable device attached,

VBUS = 0 V before application,

Die temp < TTSD

Programmable, 250 - 1000 mV,

default listed

Discharge Impedance RDISCHARGE 100 Ω

Port Power Switch - AC Parameters

Turn On Delay tON_PSW 0.75 ms PWR_EN active toggle to

switch on time, VBUS

discharge not active

Turn Off Time tOFF_PSW_INA 0.75 ms PWR_EN inactive toggle to

switch off time

CBUS = 120 μF

Turn Off Time tOFF_PSW_ERR 1 ms Over-current Error, VBUS Min

Error, or Discharge Error to

switch off

CBUS = 120 μF

Turn Off Time tOFF_PSW_ERR 100 ns TSD or Back-drive Error to

switch off

CBUS = 120 μF

VBUS Output Rise Time tR_BUS 1.1 ms Measured from 10% to 90% of

VBUS, CLOAD = 220 μF

ILIM = 1.0 A

Table 3.3 Electrical Specifications (continued)

VDD = 4.5 V to 5.5 V, VS = 2.9 V to 5.5 V, VPULLUP = 3V to 5.5V, T

A = -40 °C to 85 °C

all Typical values at VDD = VS = 5 V, TA = 27 °C unless otherwise noted.

CHARACTERISTIC SYMBOL MIN TYP MAX UNIT CONDITIONS

Programmable USB Port Power Controller with Charger Emulation

Datasheet

SMSC UCS1002 21 Revision 1.4 (07-16-13)

DATASHEET

Soft Turn on Rate ΔIBUS / Δt100 mA /

µs

Temperature Update

Time

tDC_TEMP 200 ms Programmable 200 - 1600 ms,

default listed

Short Circuit Response

Time

tSHORT_LIM 1.5 µs Time from detection of short to

current limit applied.

No CBUS applied

Short Circuit Detection

Time

tSHORT 6 ms Time from detection of short to

port power switch disconnect

and ALERT# pin assertion.

Latched Mode Cycle

Time

tUL 7 ms From PWR_EN edge transition

from inactive to active to begin

error recovery

Auto-recovery Mode

Cycle Time

tCYCLE 25 ms Time delay before error

condition check

Programmable 15-50 ms,

default listed

Auto-recovery Delay tRST 20 ms Portable device attached,

VBUS must be > VTEST after

this time

Programmable 10-25 ms,

default listed

Discharge Time tDISCHARGE 200 ms Amount of time discharge

resistor applied

Programmable 100-400 ms,

default listed

Port Power Switch Operation With Trip Mode Current Limiting

Region 2 Current Keep-

out

IBUS_R2MIN 0.1 A

Minimum VBUS Allowed

at Output

VBUS_MIN 2.0 V

Port Power Switch Operation With Constant Current Limiting (Variable Slope)

Region 2 Current Keep-

out

IBUS_R2MIN 1.5 A

Minimum VBUS Allowed

at Output

VBUS_MIN 2.0 V

Port Power Switch Operation With Custom Current Limiting

Region 2 Current Keep-

out

IBUS_R2MIN 0.1 A Programmable from 100 mA to

1.8 A. Default value listed.

Table 3.3 Electrical Specifications (continued)

VDD = 4.5 V to 5.5 V, VS = 2.9 V to 5.5 V, VPULLUP = 3V to 5.5V, T

A = -40 °C to 85 °C

all Typical values at VDD = VS = 5 V, TA = 27 °C unless otherwise noted.

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Minimum VBUS Allowed

at Output

VBUS_MIN 2.0 V Programmable from 1.5 V to

2.25 V. Default value listed.

Current Measurement - DC

Current Measurement

Range

IBUS_M 6.4 2500 mA Range

(see Note 3.3)

Reported Current

Measurement Resolution

ΔIBUS_M 9.76 mA 1 LSB

Current Measurement

Accuracy

±2 % ILIM not exceeded

Current Measurement - AC

Sampling Rate 500 µs

Charge Rationing - DC

Accumulated Current

Measurement Accuracy

±4.5 %

Charge Rationing - AC

Current Measurement

Update Time

tPCYCLE 1s

Attach / Removal Detection

VBUS Bypass - DC

On Resistance RON_BYP 50 Ω

Leakage Current ILEAK_BYP 3 µA Switch off

Current Limit IDET_CHG /

IBUS_BYP

2 mA VDD = 5 V and VBUS> 4.75 V

Attach / Removal Detection - DC

Attach Detection

Threshold

IDET_QUAL 800 µA Programmable 200-1000 µA,

default listed

Primary Removal

Detection Threshold

IREM_QUAL_ACT 700 µA

Programmable 100-900 µA,

default listed

Active power state

IREM_QUAL_DET 800 µA Programmable 200-1000 µA,

default listed

Detect power state

(see Section 8.4)

Table 3.3 Electrical Specifications (continued)

VDD = 4.5 V to 5.5 V, VS = 2.9 V to 5.5 V, VPULLUP = 3V to 5.5V, T

A = -40 °C to 85 °C

all Typical values at VDD = VS = 5 V, TA = 27 °C unless otherwise noted.

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Attach / Removal Detection - AC

Attach Detection Time tDET_QUAL 100 ms Time from Attach to A_DET#

assert .

Removal Detection Time tREM_QUAL 1000 ms

Allowed Charge Time tDET_CHARGE 800 ms CBUS = 500 µF max

Programmable 200-2000 ms,

default listed

Charger Emulation Profile

General Emulation - DC

Charging Current

Threshold

IBUS_CHG 9.76 mA default

Charging Current

Threshold Range

IBUS_CHG_RNG 9.76 155 mA Programmable, all typical

DP-DM Shunt Resistor

Value

RDCP_RES 200 ΩConnected between DPOUT

and DMOUT

0 V < DPOUT = DMOUT < 3V

Response Magnitude

(voltage divider option

min resistance range)

SX_RXMAG_

DVDR

93 200 kΩProgrammable, all mins

Resistor Ratio Range

(voltage divider option)

SX_RATIO 0.25 0.66 V / V Programmable, all typical

Resistor Ratio Accuracy

(voltage divider option)

SX_RATIO_

ACC

±0.5 % Average over range

Response Magnitude

(resistor option range)

SX_RXMAG_

RES

1.8 150 kΩProgrammable, all typical

Internal Resistor

Tolerance (resistor

option)

SX_RXMAG_

RES_ACC

±10 % Average over range

Response Magnitude

(voltage option range)

SX_RXMAG_

VOLT

0.4 2.2 V Programmable, all typical

Voltage Option Accuracy SX_RXMAG_

VOLT_ACC

±1 % No load

Average over range

Voltage Option Accuracy SX_RXMAG_

VOLT_ACC_

150

-6 % 150 µA load

Average over range

Voltage Option Accuracy SX_RXMAG_

VOLT_ACC_

250

-10 % 250 µA load

Average over range

Table 3.3 Electrical Specifications (continued)

VDD = 4.5 V to 5.5 V, VS = 2.9 V to 5.5 V, VPULLUP = 3V to 5.5V, T

A = -40 °C to 85 °C

all Typical values at VDD = VS = 5 V, TA = 27 °C unless otherwise noted.

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Note 3.2 For split supply systems using the Attach Detection feature, VS must not exceed VDD +

150 mV.

Note 3.3 The current measurement full scale range maximum value is 2.5 A. However, the

UCS1002 cannot report values above ILIM (if IBUS_R2MIN < ILIM) or above IBUS_R2MIN (if

IBUS_R2MIN > ILIM and ILIM < 1.5 A).

Voltage Option Output SX_RXMAG_

VOLT_BC

0.5 V DMOUT = 0.6 V

250 µA load

Response Magnitude

(zero volt option range)

SX_PUPD 10 150 µA SX_RXMAG_VOLT = 0

Programmable, all typical

Pull-down Current

Accuracy

SX_PUPD

_ACC_3p6

±5 % DPOUT or DMOUT = 3.6 V

Compliance voltage

Pull-down Current SX_PUPD

_ACC_BC

50 µA Setting = 100 µA

DPOUT or DMOUT = 0.15 V

Compliance voltage

Stimulus Voltage

Threshold Range

SX_TH 0.3 2.2 V Programmable, all typical

Stimulus Voltage

Accuracy

SX_TH_ ACC ±2 % Average over range

Stimulus Voltage

Accuracy

SX_TH_ACC_

0.25 V At SX_TH = 0.3 V

Stimulus Voltage

Hysteresis

SX_TH_HYST 40 mV Voltage falling

General Emulation - AC

Emulation Reset Time tEM_RESET 50 ms default

Emulation Reset Time

Range

tEM_RESET_

RNG

50 175 ms Programmable, all typical

Emulation Timeout

Range

tEM_ TIMEOUT 0.8 12.8 s Programmable, 0.8 s to 12.8 s,

all typical

Stimulus Delay, SX_TD

Range

tSTIM_DEL 0 100 ms Programmable, all typical

Emulation Delay tRES_EM 0.5 s Time from set impedance to

impedance appears on DP /

Table 3.3 Electrical Specifications (continued)

VDD = 4.5 V to 5.5 V, VS = 2.9 V to 5.5 V, VPULLUP = 3V to 5.5V, T

A = -40 °C to 85 °C

all Typical values at VDD = VS = 5 V, TA = 27 °C unless otherwise noted.

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Figure 3.1 USB Rise Time / Fall Time Measurement

Figure 3.2 Description of DC Terms

DPIN DPOUT

RCHG

VBUS

VTST

RCHG

ITST

DMIN

RCHG

VBUS

VTST

RCHG

ITST

DMOUT

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3.1 ESD & Transient Performance

APPLICATION NOTE: Depending on the level of ESD protection required by the application, external protection

devices may be required. The datasheet ESD levels were reached using external devices

and standard USB-A connectors; refer to the EVB schematic and reference design for

details.

Note 3.4 Operational Classification B indicates that during and immediately after an ESD event,

anomalous behavior may occur; however, it is non-damaging and the device is self-

recovering. All IEC testing is performed using an SMSC evaluation board.

Note 3.5 Operational Classification A indicates that during and immediately after an ESD event no

anomalous behavior will occur. All IEC testing is performed using an SMSC evaluation

board.

3.1.1 Human Body Model (HBM) Performance

HBM testing verifies the ability to withstand ESD strikes like those that occur during handling and

manufacturing and is done without power applied to the IC. To pass the test, the device must have no

change in operation or performance due to the event.

3.1.2 Charged Device Model (CDM) Performance

CDM testing verifies the ability to withstand ESD strikes like those that occur during handling and

assembly with pick and place style machinery and is done without power applied to the IC. To pass

the test, the device must have no change in operation or performance due to the event.

3.1.3 IEC61000-4-2 Performance

The IEC61000-4-2 ESD specification is an international standard that addresses system-level immunity

to ESD strikes while the end equipment is operational. These tests are performed while the device is

powered.

Table 3.4 ESD Ratings

ESD SPEC RATING OR VALUE

EN / IEC61000-4-2 (DPOUT, DMOUT pins) air gap,

Operational Classification B (see Note 3.4)

Level 4 (15 kV)

EN / IEC61000-4-2 (DPOUT, DMOUT pins) direct contact,

Operational Classification B (see Note 3.4)

Level 4 (8 kV)

EN / IEC61000-4-2 (VBUS, GND pins) air gap,

Operational Classification A (see Note 3.5)

Level 4 (15 kV)

EN / IEC61000-4-2 (VBUS, GND pins) direct contact,

Operational Classification A (see Note 3.5)

Level 4 (8 kV)

Human Body Model (JEDEC JESD22-A114) - All pins 8 kV

Charged Device Model (JEDEC JESD22-C101) - All pins 500 V

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Chapter 4 Communications

4.1 Operating Mode

The UCS1002 can operate in SMBus mode (see Section 4.2, "SMBus Operating Mode") or Stand-

alone mode (see Section 4.3, "Stand-alone Operating Mode"). The resistor on the COMM_SEL / ILIM

pin determines operating mode and the hardware-set ILIM setting, as shown in Ta b le 4 . 1. Unless

connected to GND or VDD, the resistors in Ta b l e 4 . 1 are pull-down resistors.

APPLICATION NOTE: If it is necessary to connect the COMM_SEL / ILIM pin to VDD via a pull-up resistor, it is

recommended that this resistor value not exceed 100 kΩ.

Table 4.1 UCS1002 Communication Mode and ILIM Selection

SELECTION RESISTOR ±5% ILIM SETTING COMMUNICATIONS MODE

GND 500 mA SMBus - see Section 4.2.1.2

10 kΩ pull-down 900 mA SMBus - see Section 4.2.1.2

12 kΩ pull-down 1000 mA SMBus - see Section 4.2.1.2

15 kΩ pull-down 1200 mA SMBus - see Section 4.2.1.2

18 kΩ pull-down 1500 mA SMBus - see Section 4.2.1.2

22 kΩ pull-down 1800 mA SMBus - see Section 4.2.1.2

27 kΩ pull-down 2000 mA SMBus - see Section 4.2.1.2

33 kΩ pull-down 2500 mA SMBus - see Section 4.2.1.2

47 kΩ pull-down 500 mA Stand-alone mode

56 kΩ pull-down 900 mA Stand-alone mode

68 kΩ pull-down 1000 mA Stand-alone mode

82 kΩ pull-down 1200 mA Stand-alone mode

100 kΩ pull-down 1500 mA Stand-alone mode

120 kΩ pull-down 1800 mA Stand-alone mode

150 kΩ pull-down 2000 mA Stand-alone mode

VDD

(If a pull-up resistor is used, its

value must not exceed 100 kΩ.)

2500 mA Stand-alone mode

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4.2 SMBus Operating Mode

When the COMM_SEL / ILIM pin is connected to directly to ground or though a pull-down resistor with

a value of 33kΩ or below as listed in Table 4.1, "UCS1002 Communication Mode and ILIM Selection",

the UCS1002 communicates via the SMBus or I2C communications protocols.

APPLICATION NOTE: Upon power-up, the UCS1002 will not respond to any SMBus communications for 5.5 ms.

After this time, full functionality is available.

APPLICATION NOTE: When in the Sleep state, the first SMBus read command sent to the UCS1002 device

address will wake it. Any data sent to the UCS1002 will be ignored and any data read from

the UCS1002 should be considered invalid. The UCS1002 will be fully functional 3 ms after

this first read command is sent. See Section 5.1.2.

4.2.1 System Management Bus

In SMBus mode, the UCS1002 communicates with a host controller, such as an SMSC SIO. The

SMBus is a two-wire serial communication protocol between a computer host and its peripheral

devices. A detailed timing diagram is shown in Figure 4.1. Stretching of the SMCLK signal is supported;

however, the UCS1002 will not stretch the clock signal.

4.2.1.1 SMBus Start Bit

The SMBus Start bit is defined as a transition of the SMBus data line from a logic ‘1’ state to a logic

‘0’ state while the SMBus clock line is in a logic ‘1’ state.

4.2.1.2 SMBus Address and RD / WR Bit

The SMBus Address Byte consists of the 7-bit client address followed by the RD / WR indicator bit. If

this RD / WR bit is a logic ‘0’, the SMBus host is writing data to the client device. If this RD / WR bit

is a logic ‘1’, the SMBus host is reading data from the client device.

The SMBus address is determined based on the resistor connected on the SEL pin as shown in

Table 4.2.

APPLICATION NOTE: If it is necessary to connect the SEL pin to VDD via a resistor, the pull-up resistor may be

any value up to 100 kΩ.

Figure 4.1 SMBus Timing Diagram

SMDATA

SMCLK

TBUF

PS S - Start Condition P - Stop Condition PS

THIGH

TLOW THD:STA TSU:STO

THD:STA THD:DAT

TSU:DAT TSU:STA

TFALL

TRISE

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4.2.1.3 SMBus Data Bytes

All SMBus data bytes are sent most significant bit first and composed of 8-bits of information.

4.2.1.4 SMBus ACK and NACK Bits

The SMBus client will acknowledge all data bytes that it receives. This is done by the client device

pulling the SMBus data line low after the 8th bit of each byte that is transmitted. This applies to both

the Write Byte and Block Write protocols.

The host will NACK (not acknowledge) the last data byte to be received from the client by holding the

SMBus data line high after the 8th data bit has been sent. For the Block Read protocol, the host will

ACK each data byte that it receives except the last data byte.

4.2.1.5 SMBus Stop Bit

The SMBus Stop bit is defined as a transition of the SMBus data line from a logic ‘0’ state to a logic

‘1’ state while the SMBus clock line is in a logic ‘1’ state. When the UCS1002 detects an SMBus Stop

Table 4.2 SEL Pin Decode

RESISTOR (±5%)

PWR_EN

POLARITY SMBUS ADDRESS

GND Active Low 1010_111(r/w)

10 kΩ pull-down Active Low 1010_110(r/w)

12 kΩ pull-down Active Low 1010_101(r/w)

15 kΩ pull-down Active Low 1010_100(r/w)

18 kΩ pull-down Active Low 0110_000(r/w)

22 kΩ pull-down Active Low 0110_001(r/w)

27 kΩ pull-down Active Low 0110_010(r/w)

33 kΩ pull-down Active Low 0110_011(r/w)

47 kΩ pull-down Active High 0110_011(r/w)

56 kΩ pull-down Active High 0110_010(r/w)

68 kΩ pull-down Active High 0110_001(r/w)

82 kΩ pull-down Active High 0110_000(r/w)

100 kΩ pull-down Active High 1010_100(r/w)

120 kΩ pull-down Active High 1010_101(r/w)

150 kΩ pull-down Active High 1010_110(r/w)

VDD

(If a pull-up resistor is used, its

value must not exceed 100 kΩ.)

Active High 1010_111(r/w)

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bit, and it has been communicating with the SMBus protocol, it will reset its client interface and prepare

to receive further communications.

4.2.1.6 SMBus Timeout and Idle Reset

The UCS1002 includes an SMBus timeout feature. If the clock is held at logic ‘0’ for tTIMEOUT

, the

device can timeout and reset the SMBus interface. The SMBus interface can also reset if both the

clock and data lines are held at a logic ‘1’ for tIDLE_RESET

. Communication is restored with a start

condition. This functionality defaults to disabled and can be enabled by clearing the DIS_TO bit in the

Emulation Configuration register (see Section 10.4.2, "Emulation Configuration - 16h").

4.2.2 SMBus and I2C Compatibility

The major differences between SMBus and I2C devices are highlighted here. For more information,

refer to the SMBus 2.0 and I2C specifications.

1. UCS1002 supports I2C fast mode at 400 kHz. This covers the SMBus max time of 100 kHz.

2. Minimum frequency for SMBus communications is 10 kHz.

3. The SMBus client protocol will reset if the clock is held at a logic ‘0’ for longer than 30 ms. This

timeout functionality is disabled by default in the UCS1002 and can be enabled by clearing the

DIS_TO bit. I2C does not have a timeout.

4. Except when operating in Sleep, the SMBus client protocol will reset if both the clock and data

lines are held at a logic ‘1’ for longer than 200 µs (idle condition). This function is disabled by

default in the UCS1002 and can be enabled by clearing the DIS_TO bit. I2C does not have an idle

condition.

5. I2C devices do not support the Alert Response Address functionality (which is optional for SMBus).

6. I2C devices support block read and write differently. I2C protocol allows for unlimited number of

bytes to be sent in either direction. The SMBus protocol requires that an additional data byte

indicating number of bytes to read / write is transmitted. The UCS1002 supports I2C formatting only.

4.2.3 SMBus Protocols

The UCS1002 is SMBus 2.0 compatible and supports Write Byte, Read Byte, Send Byte, and Receive

Byte as valid protocols as shown below.

All of the below protocols use the convention in Table 4 . 3 .

Table 4.3 Protocol Format

DATA SENT

TO DEVICE

DATA SENT TO

THE HOST

Data sent Data sent

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4.2.3.1 SMBus Write Byte

The Write Byte is used to write one byte of data to a specific register as shown in Table 4.4.

4.2.3.2 SMBus Read Byte

The Read Byte protocol is used to read one byte of data from the registers as shown in Table 4.5.

4.2.3.3 SMBus Send Byte

The Send Byte protocol is used to set the internal address register pointer to the correct address

location. No data is transferred during the Send Byte protocol as shown in Ta b l e 4. 6 .

4.2.3.4 SMBus Receive Byte

The Receive Byte protocol is used to read data from a register when the internal register address

pointer is known to be at the right location (e.g., set via Send Byte). This is used for consecutive reads

of the same register as shown in Tab l e 4 . 7.

4.2.4 I2C Protocols

The UCS1002 supports I2C Block Read and Block Write. The protocols listed below use the convention

in Ta b l e 4 . 3 .

Table 4.4 Write Byte Protocol

START

CLIENT

ADDRESS WR ACK

ADDRESS ACK

DATA ACK STOP

1 ->0 YYYY_YYY 0 0 XXh 0 XXh 0 0 -> 1

Table 4.5 Read Byte Protocol

START CLIENT

ADDRESS

WR ACK REGISTER

ADDRESS

ACK START CLIENT

ADDRESS

RD ACK REGISTER

DATA

NACK STOP

1->0 YYYY_YYY 0 0 XXh 0 1 ->0 YYYY_YYY 1 0 XXh 1 0 -> 1

Table 4.6 Send Byte Protocol

START

CLIENT

ADDRESS WR ACK

ADDRESS ACK STOP

1 -> 0 YYYY_YYY 0 0 XXh 0 0 -> 1

Table 4.7 Receive Byte Protocol

START

CLIENT

ADDRESS RD ACK REGISTER DATA NACK STOP

1 -> 0 YYYY_YYY 1 0 XXh 1 0 -> 1

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4.2.4.1 Block Write

The Block Write is used to write multiple data bytes to a group of contiguous registers as shown in

Table 4.8.

APPLICATION NOTE: When using the Block Write protocol, the internal address pointer will be automatically

incremented after every data byte is received. It will wrap from FFh to 00h.

4.2.4.2 Block Read

The Block Read is used to read multiple data bytes from a group of contiguous registers as shown in

Table 4.9.

APPLICATION NOTE: When using the Block Read protocol, the internal address pointer will be automatically

incremented after every data byte is received. It will wrap from FFh to 00h.

4.3 Stand-alone Operating Mode

Stand-alone mode allows the UCS1002 to operate without active SMBus / I2C communications. Stand-

alone mode can be enabled by connecting a pull-down resistor greater or equal to 47 kΩ on the

COMM_SEL / ILIM pin as shown in Table 4.1, "UCS1002 Communication Mode and ILIM Selection".

When the device is configured to operate in Stand-alone mode, the fault handling and Attach Detection

controls are determined via the LATCH and S0 pins as shown in Table 4.10.

APPLICATION NOTE: If it is necessary to connect the S0 or LATCH pins to VDD via a pull-up resistor, the pull-up

resistor value should be 100 kΩ in order to guarantee VIH specification. Likewise, if it is

necessary to connect the S0 or LATCH pins to GND via a pull-down resistor, the pull-down

resistor value should be 100 kΩ in order to guarantee VIL specification.

Table 4.8 Block Write Protocol

START

CLIENT

ADDRESS WR ACK

ADDRESS ACK

DATA ACK

1 ->0 YYYY_YYY 0 0 XXh 0 XXh 0

DATA ACK

DATA ACK . . .

DATA ACK STOP

XXh 0 XXh 0 . . . XXh 0 0 -> 1

Table 4.9 Block Read Protocol

START CLIENT

ADDRESS

WR ACK REGISTER

ADDRESS

ACK START CLIENT

ADDRESS

RD ACK REGISTER

DATA

1->0 YYYY_YYY 00 XXh 01 ->0YYYY_YYY 1 0 XXh

ACK REGISTER

DATA

ACK REGISTER

DATA

ACK REGISTER

DATA

ACK . . . REGISTER

DATA

NACK STOP

0 XXh 0 XXh 0 XXh 0 . . . XXh 1 0 -> 1

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In the Stand-alone operating mode, communications from and to the UCS1002 are limited to the

PWR_EN, EM_EN, M2, M1, ALERT#, and A_DET# pins.

Table 4.10 Stand-alone Fault and Attach Detection Selection

LATCH PIN S0 PIN COMMAND

Low Low No Attach Detection. Auto-recovery upon error detection.

Low High Attach Detection in the Detect power state. Auto-recovery upon error detection.

High Low No Attach Detection. Error states are Latched and require host to change

PWR_EN control to recover from Error state.

High High Attach Detection in the Detect power state. Error states are Latched and

require host to change PWR_EN control to recover from Error state.

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Chapter 5 General Description

The UCS1002 provides a single USB port power switch for precise control of up to 2.5 amperes

continuous current with over-current limit (OCL), dynamic thermal management, latch or auto-recovery

fault handling, selectable active low or high enable, under- and over-voltage lockout, and back-voltage

protection.

Split supply support for VBUS and VDD is an option for low power in system standby states.

In addition to power switching and current limiting, the UCS1002 provides automatic and configurable

charger emulation profiles to charge a wide variety of portable devices, including USB-IF BC1.2 (CDP

or DCP modes), YD/T-1591 (2009), most Apple and RIM portable devices, and many others.

The UCS1002 also provides current monitoring to allow intelligent management of system power and

charge rationing for controlled delivery of current regardless of the host power state. This is especially

important for battery operated applications that want to provide power and do not want to excessively

drain the battery, or that require power allocation depending on application activities.

Figure 5.1 shows a UCS1002 full-featured system configuration in which the UCS1002 provides a port

power switch and low power Attach Detection with wake-up signaling (wake on USB). The current limit

is established at power-up. It can be lowered if required after power-up via the SMBus / I2C. This

configuration also provides configurable USB data line charger emulation, programmable current

limiting (as determined by the accepted charger emulation profile), active current monitoring, and port

charge rationing.

Figure 5.1 UCS1002 Full-Featured System Configuration (SMBus Control)

UCS1002

ALERT#

3 V – 5.5 V

Device

DPOUT

DMOUT

5 V

VBUS1

VBUS2

VS1

VS2

A_DET#

5 V Host

CBUS

USB Host

3 V – 5.5 V

CIN

VDD

DPIN

DMIN

VDD

EM_EN

PWR_EN

SMDATA

SMCLK

SEL COMM_SEL / ILIM

GND

VDD

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Figure 5.2 shows a system configuration in which the UCS1002 provides a USB data switch, port

power switch, low power Attach Detection, and portable device Attach / Removal Detection signaling.

This configuration does not include configurable data line charger emulation, programmable current

limiting, or current monitoring and rationing.

Figure 5.3 shows a system configuration in which the UCS1002 provides a port power switch, low

power Attach Detection, and portable device attachment detected signaling. This configuration is useful

for applications that already provide USB BC1.2 and/or legacy data line handshaking on the USB data

lines, but still require port power switching and current limiting.

Figure 5.2 UCS1002 System Configuration (Charger Emulation, No SMBus, with USB Host)

UCS1002

LATCH

ALERT#

PWR_EN

3 V – 5.5 V

GND

Device

DPIN

DMIN

DPOUT

DMOUT

VDD

5 V

VBUS1

VBUS2

VS1

VS2

COMM_SEL / ILIM

3 V – 5.5 V

Auto-recovery

Upon Fault

Latch

Upon Fault

EM_EN

SEL

A_DET#

5 V Host

CBUS

USB Host

Disable

Detect State

Enable

Detect State

CIN

VDD

> 47k

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Figure 5.4 shows a system configuration in which the UCS1002 provides a port power switch, low

power Attach Detection, charger emulation (with no USB host), and portable device attachment

detected signaling. This configuration is useful for wall adapter type applications.

Figure 5.3 UCS1002 System Configuration (No SMBus, No Charger Emulation)

UCS1002

LATCH

ALERT#

PWR_EN

3 V – 5.5 V

GND

Device

DPIN

DMIN

DPOUT

DMOUT

VDD

5 V

VBUS1

VBUS2

VS1

VS2

COMM_SEL / ILIM

3 V – 5.5 V

Auto-recovery

Upon Fault

Latch

Upon Fault

EM_EN

SEL

A_DET#

5 V Host

CBUS

USB Host

(DP, DM)

Disable Detect

State

Enable Detect

State

CIN

VDD

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UCS1002 references design is available; contact your SMSC representative.

Figure 5.4 UCS1002 System Configuration (No SMBus, No USB Host, with Charger Emulation)

UCS1002

LATCH

ALERT#

PWR_EN

3 V – 5.5 V

GND

Device

DPIN

DMIN

DPOUT

DMOUT

VDD

5 V

VBUS1

VBUS2

VS1

VS2

COMM_SEL / ILIM

3 V – 5.5 V

Auto-recovery

Upon Fault

Latch

Upon Fault

EM_EN

SEL

A_DET#

5 V

CBUS

Disable Detect

State

Enable Detect

State

CIN

VDD

15 K

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5.1 UCS1002 Power States

The UCS1002 has the following power states.

Off - This power state is entered when the voltage at the VDD pin voltage is < VDD_TH. In this state

the device is considered “off”. The UCS1002 will not retain its digital states and register contents

nor respond to SMBus / I2C communications. The port power switch, bypass switch, and the high-

speed data switches will be off. See Section 5.1.1, "Off State Operation".

Sleep - This is the lowest power state available. While in this state, the UCS1002 will retain digital

functionality, respond to changes in emulation controls, and wake to respond to SMBus / I2C

communications. The high-speed switch and all other functionality will be disabled. See Section

5.1.2, "Sleep State Operation".

Detect - This is a lower current power state. In this state, the device is actively looking for a

portable device to be attached. The high-speed switch is disabled by default. While in this state,

the UCS1002 will retain the configuration and charge rationing data, but it will not monitor the bus

current. SMBus / I2C communications will be fully functional. See Section 5.1.3, "Detect State

Operation".

Error - This power state is entered when a fault condition exists. See Section 5.1.5, "Error State

Operation".

Active - This power state provides full functionality. While in this state, operations include activation

of the port power switch, USB data line handshaking / charger emulation, current limiting, and

charge rationing. See Section 5.1.4, "Active State Operation".

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Table 5.1 shows the settings for the various power states, except Off and Error. If VDD < VDD_TH, the

UCS1002 is in the Off state. To determine the mode of operation in the Active state, see Ta b l e 9 . 1 ,

"Active Mode Selection". For more information about configuring the UCS1002 to create single or dual

mode charger solutions, see SMSC application note 24.20“Using the UCS100x as a Single or Dual

Mode Charger.”

APPLICATION NOTE: Using configurations not listed in Table 5.1 is not recommended and may produce

undesirable results.

Note 5.1 In order to transition from Active state Data Pass-through mode into Sleep with these

settings, change the M1, M2, and EM_EN pins before changing the PWR_EN pin. See

Section 9.4, "Data Pass-through (No Charger Emulation)".

Note 5.2 If S0=’0’ and a portable device is not attached in DCE Cycle mode, the UCS1002 will be

cycling through charger emulation profiles (by default). There is no guarantee which

charger emulation profile will be applied first when a portable device attaches.

5.1.1 Off State Operation

The device will be in the off state if VDD is less than VDD_TH. When the UCS1002 is in the Off state,

it will do nothing, and all circuitry will be disabled. Digital register values are not stored and the device

will not respond to SMBus commands.

Table 5.1 Power States Control Settings

POWER

STATE VS PWR_EN S0

M1, M2,

EM_EN

PORTABLE

DEVICE

ATTACHED BEHAVIOR

Sleep X disabled 0 Not set to

Data

Pass-

through.

See

Note 5.1.

X All switches disabled. VBUS will be

near ground potential. The

UCS1002 wakes to respond to

SMBus communications.

X enabled 0 All = 0b X

Detect

(see Chapter 8,

Detect State)

X disabled 1 X X High-speed switch disabled (by

default). Port power switch disabled.

Host-controlled transition to Active

state (see Section 5.1.3.2, "Host-

Controlled Transition from Detect to

Active").

< VS_UVLO enabled 1 All <> 0b X

> VS_UVLO enabled 1 All <> 0b No High-speed switch disabled(by

default). Automatic transition to

Active state when conditions met

(see Section 5.1.3.1, "Automatic

Transition from Detect to Active").

Active

(see Chapter 9,

Active State)

> VS_UVLO enabled 0 All <> 0b X High-speed switch enabled /

disabled based on mode. Port power

switch is on at all times. Attach and

Removal Detection disabled. See

Note 5.2.

> VS_UVLO enabled 1 All <> 0b Yes Port power switch is on. Removal

Detection enabled.

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5.1.2 Sleep State Operation

When the UCS1002 is in the Sleep state, the device will be in its lowest power state. The high-speed

switch, bypass switch, and the port power switch will be disabled. The Attach and Removal Detection

feature will be disabled. VBUS will be near ground potential. The ALERT# pin will not be asserted. If

asserted prior to entering the Sleep state, the ALERT# pin will be released. The A_DET# pin will be

released. SMBus activity is limited to single byte read or write.

The first data byte read from the UCS1002 when it is in the Sleep state will wake it; however, the data

to be read will return all 0’s and should be considered invalid. This is a “dummy” read byte meant to

wake the UCS1002. Subsequent read or write bytes will be accepted normally. After the dummy read,

the UCS1002 will be in a higher power state (see Figure 5.6). After communication has not occurred

for tIDLE_SLEEP

, the UCS will return to Sleep.

Figure 5.5 shows timing diagrams for waking the UCS1002 via external pins. Figure 5.6 shows the

timing for waking the UCS1002 via SMBus.

Figure 5.5 Wake Timing via External Pins

M1 or M2

Port power switch closed

(Active state)

tPIN_WAKE

Wake with M1 or M2 to Active State Data Pass-through Mode

(PWR_EN enabled, S0 = ‘0’, EM_EN = ‘0’, VS > VS_UVLO)

Bypass switch closed

(Detect state)

tPIN_WAKE

Wake with S0

(VS > VS_UVLO, M1 & M2 & EM_EN not all ‘0’ and not set to Data Pass-through)

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5.1.3 Detect State Operation

When the UCS1002 is in the Detect state, the port power switch will be disabled. The high-speed

switch is also disabled by default. The VBUS output will be connected to the VDD voltage by a

secondary bypass switch (see Chapter 8, Detect State).

There is one non-recommended configuration which places the UCS1002 in the Detect state, but

VBUS will not be discharged and a portable device attachment will not be detected. For the

recommended configurations, see Table 5.1, "Power States Control Settings".

NOT RECOMMENDED: PWR_EN is enabled, S0 = ‘1’, and M1, M2, and EM_EN are all ‘0’.

There are two methods for transitioning from the Detect state to the Active state: automatic and host-

controlled.

5.1.3.1 Automatic Transition from Detect to Active

For the Detect state, set S0 to ‘1’, enable PWR_EN, set the EM_EN, M1, and M2 controls to the

desired Active mode (Table 9.1, "Active Mode Selection"), and supply VS > VS_UVLO. When a portable

device is attached and an Attach Detection event occurs, the UCS1002 will automatically transition to

the Active state and operate according to the selected Active mode.

5.1.3.2 Host-Controlled Transition from Detect to Active

For the Detect state, set S0 to ‘1’, set the EM_EN, M1, and M2 controls to the desired Active mode

(Table 9.1, "Active Mode Selection"), and configure one of the following: 1) disable PWR_EN and

supply VS, or 2) enable PWR_EN and don’t supply VS. When a portable device is attached and an

Attach Detection event occurs, the host must respond to transition to the Active state. Depending on

the control settings in the Detect state, this could entail 1) enabling PWR_EN or 2) supplying VS above

the threshold.

APPLICATION NOTE: If S0 is '1', PWR_EN is enabled, and VS is not present, the A_DET# pin will cycle if the

current draw exceeds the current capacity of the bypass switch.

5.1.3.3 State Change from Detect to Active

When conditions cause the UCS1002 to transition from the Detect state to the Active state, the

following occurs:

1. The Attach Detection feature will be disabled; the Removal Detection feature remains enabled,

unless S0 is changed to ‘0’.

Figure 5.6 Wake Via SMBus Read with S0 = ‘0’

0101_111

0A invalid dataN P

SMBus Read

A0001_0000 0101_111

0A valid data N P

0001_0000SS

tIDLE_SLEEP

Sleep Sleep

Dummy read returns invalid data

and places device in temporary

Active state

Read returns valid data

0101_111

1AS 0101_111

Power State temporary Active state

(not all functionality available)

tSMB_WAKE

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2. The bypass switch will be turned off.

3. The discharge switch will be turned on for tDISCHARGE.

4. The port power switch will be turned on.

5.1.4 Active State Operation

Every time that the UCS1002 enters the Active state and the port power switch is closed, it will enter

the mode as instructed by the host controller (see Chapter 9, Active State). The UCS1002 cannot be

in the Active state (and therefore, the port power switch cannot be turned on) if any of the following

conditions exist:

1. VS < VS_UVLO.

2. PWR_EN is disabled.

3. M1, M2, and EM_EN are all set to '0'.

4. S0 is set to ‘1’ and an Attach Detection event has not occurred.

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5.1.5 Error State Operation

The UCS1002 will enter the Error state from the Active state when any of the following events are

detected:

1. The maximum allowable internal die temperature (TTSD) has been exceeded (see Section 7.3.1.2).

2. An over-current condition has been detected (see Section 7.2.1).

3. An under-voltage condition on VBUS has been detected (see Section 5.2.5).

4. A back-drive condition has been detected (see Section 5.2.3).

5. A discharge error has been detected (see Section 7.4).

6. An over-voltage condition on the VS pins.

The UCS1002 will enter the Error state from the Detect state when a back-drive condition has been

detected or when the maximum allowable internal die temperature has been exceeded.

The UCS1002 will enter the Error state from the Sleep state when a back-drive condition has been

detected.

When the UCS1002 enters the Error state, the port power switch, the VBUS bypass switch, the high-

speed switch are turned off, and the ALERT# pin is asserted (by default). They will remain off while in

this power state. The UCS1002 will leave this state as determined by the fault handling selection (see

Section 7.6, "Fault Handling Mechanism").

When using the Latch fault handler and the user has re-activated the device by clearing the ERR bit

(see Section 10.3, "Status Registers"), or toggling the PWR_EN control, the UCS1002 will check that

all of the error conditions have been removed. If using Auto-recovery fault handler, after the tCYCLE

time period, the UCS1002 will check that all of the error conditions have been removed.

If all of the error conditions have been removed, the UCS1002 will return to the Active state or Detect

state, as applicable. Returning to the Active state will cause the UCS1002 to restart the selected mode

(see Section 9.2, "Active Mode Selection").

If the device is in the Error state and a Removal Detection event occurs, it will check the error

conditions and then return to the power state defined by the PWR_EN, M1, M2, EM_EN, and S0

controls.

5.2 Supply Voltages

5.2.1 VDD Supply Voltage

The UCS1002 requires 4.5 V to 5.5 V present on the VDD pin for core device functionality. Core device

functionality consists of maintaining register states, wake-up upon SMBus / I2C query, and Attach

Detection.

5.2.2 VS Source Voltage

VS can be a separate supply and can be greater than VDD to accommodate high current applications

in which current path resistances result in unacceptable voltage drops that may prevent optimal

charging of some portable devices.

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5.2.3 Back-voltage Detection

Whenever the following conditions are true, the port power switch will be disabled, the VBUS bypass

switch will be disabled, the high-speed data switch will be disabled, and a Back-voltage event will be

flagged. This will cause the UCS1002 to enter the Error power state (see Section 5.1.5, "Error State

Operation").

1. The VBUS voltage exceeds the VS voltage by VBV_TH and the port power switch is closed. The

port power switch will be opened immediately. If the condition lasts for longer than tMASK, then the

UCS1002 will enter the Error state. Otherwise, the port power switch will be turned on as soon as

the condition is removed.

2. The VBUS voltage exceeds the VDD voltage by VBV_TH and the VBUS bypass switch is closed.

The bypass switch will be opened immediately. If the condition lasts for longer than tMASK, then the

UCS1002 will enter the Error state. Otherwise, the bypass switch will be turned on as soon as the

condition is removed.

5.2.4 Back-drive Current Protection

If a portable device is attached that is self-powered, it may drive the VBUS port to its power supply

voltage level; however, the UCS1002 is designed such that leakage current from the VBUS pins to the

VDD or VS pins shall not exceed IBD_1 (if the VDD voltage is zero) or IBD_2 (if the VDD voltage exceeds

VDD_TH).

5.2.5 Under-voltage Lockout on VS

The UCS1002 requires a minimum voltage (VS_UVLO) be present on the VS pin for Active power state.

5.2.6 Over-voltage Detection and Lockout on VS

The UCS1002 port power switch will be disabled if the voltage on the VS pin exceeds a voltage

(VS_OV) for longer than the specified time (tMASK). This will cause the device to enter the Error state.

5.3 Discrete Input Pins

APPLICATION NOTE: If it is necessary to connect any of the control pins except the COMM_SEL / ILIM or SEL

pins via a resistor to VDD or GND, the resistor value should not exceed 100 kΩ in order to

meet the VIH and VIL specifications.

5.3.1 COMM_SEL / ILIM Input

The COMM_SEL / ILIM input determines the initial ILIM settings and the communications mode, as

shown in Table 4.1, "UCS1002 Communication Mode and ILIM Selection".

5.3.2 SEL Input

The SEL pin selects the polarity of the PWR_EN control. In addition, if the UCS1002 is not configured

to operate in Stand-alone mode, the SEL pin determines the SMBus address. See Table 4.2, "SEL Pin

Decode". The SEL pin state is latched upon device power-up and further changes will have no effect.

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5.3.3 M1, M2, and EM_EN Inputs

The M1, M2, and EM_EN input controls determine the Active mode and affect the power state (see

Table 5.1, "Power States Control Settings" and Table 9.1, "Active Mode Selection"). When these

controls are all set to ‘0’ and PWR_EN is enabled, the UCS1002 Attach and Removal Detection feature

is disabled. In SMBus mode, the M1, M2, and EM_EN pin states will be ignored by the UCS1002 if

the PIN_IGNORE configuration bit is set (see Section 10.4.3); otherwise, the M1_SET, M2_SET, and

EM_EN_SET configuration bits (see Section 10.4.3) are checked along with the pins.

5.3.4 PWR_EN Input

The PWR_EN control enables the port power switch to be turned on if conditions are met and affects

the power state (see Table 5.1, "Power States Control Settings"). The port power switch cannot be

closed if PWR_EN is disabled. However, if PWR_EN is enabled, the port power switch is not

necessarily closed (see Section 5.1.4, "Active State Operation"). Polarity is controlled by the SEL pin.

In SMBus mode, the PWR_EN pin state will be ignored by the UCS1002 if the PIN_IGNORE

configuration bit is set (see Section 10.4.3); otherwise, the PWR_EN_SET configuration bit (see

Section 10.4.3) is checked along with the pin.

5.3.5 Latch Input

The Latch input control determines the behavior of the fault handling mechanism (see Section 7.6,

"Fault Handling Mechanism").

When the UCS1002 is configured to operate in Stand-alone mode (see Section 4.3, "Stand-alone

Operating Mode"), the LATCH control is available exclusively via the LATCH pin (see Section

Table 4.10, "Stand-alone Fault and Attach Detection Selection"). When the UCS1002 is configured to

operate in SMBus mode, the LATCH control is available exclusively via the LATCH_SET configuration

bit (see Section 10.4.3, "Switch Configuration - 17h").

5.3.6 S0 Input

The S0 control enables the Attach and Removal Detection feature and affects the power state (see

Table 5.1, "Power States Control Settings"). When S0 is set to ‘1’, an Attach Detection event must

occur before the port power switch can be turned on. When S0 is set to ‘0’, the Attach and Removal

Detection feature is not enabled.

When the device is configured to operate in SMBus mode, (see Section 4.3, "Stand-alone Operating

Mode"), the S0 control is available exclusively via the S0_SET configuration bit (see Section 10.4.3,

"Switch Configuration - 17h"). Otherwise, the S0 control is available exclusively via the S0 pin since

the SMBus protocol will be disabled.

5.4 Discrete Output Pins

5.4.1 ALERT# and A_DET# Output Pins

The ALERT# pin is an active low open-drain interrupt to the host controller. The ALERT# pin is

asserted (by default - see ALERT_MASK in Section 10.4.1, "General Configuration - 15h") when an

error occurs (see Section 10.3.2, "Interrupt Status - 10h"). The ALERT# pin can also be asserted when

the LOW_CUR (portable device is pulling less current and may be finished charging) or TREG (thermal

regulation temperature exceeded) bits are set and linked. As well, when charge rationing is enabled,

the ALERT# pin is asserted by default when the current rationing threshold is reached (as determined

by RATION_BEH[1:0] - see Table 7.1, "Charge Rationing Behavior"). The ALERT# pin is released

when all conditions that may assert the ALERT# pin (such as an error condition, charge rationing, and

TREG and LOW_CHG if linked) have been removed or reset as necessary.

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The A_DET# pinprovides an active low open-drain output indication that a valid Attach Detection event

has occurred. It will remain asserted until the UCS1002 is placed into the Sleep state or a Removal

Detection event occurs. For wake on USB, the A_DET# pin assertion can be utilized by the system.

If the S0 control is ‘0’ and the UCS1002 is in the Active state, the A_DET# pin will be asserted

regardless if a portable device is attached or not. If S0 is '1', PWR_EN is enabled, and VS is not

present, the A_DET# pin will cycle if the current draw exceeds the current capacity of the bypass

switch.

5.4.2 Interrupt Blanking

The ALERT# and A_DET# pins will not be asserted for a specified time (up to tBLANK) after power-up.

Additionally, an error condition (except for the thermal shutdown) must be present for longer than a

specified time (tMASK) before the ALERT# pin is asserted.

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Chapter 6 USB High-speed Data Switch

6.1 USB High-speed Data Switch

The UCS1002 contains a series USB 2.0 compliant high-speed switch between the DPIN and DMIN

pins and between the DPOUT and DMOUT pins. This switch is designed for high-speed, low latency

functionality to allow USB 2.0 full-speed and high-speed communications with minimal interference.

Nominally, the switch is closed in the Active state, allowing uninterrupted USB communications

between the upstream host and the portable device. The switch is opened when:

1. The UCS1002 is actively emulating using any of the charger emulation profiles except CDP (by

default - see Section 10.4.5, "High-speed Switch Configuration - 25h").

2. The UCS1002 is operating as a dedicated charger unless the HSW_DCE configuration bit is set

(see Section 10.4.5).

3. The UCS1002 is in the Detect state (by default) or in the Sleep state.

APPLICATION NOTE: If the VDD voltage is less than VDD_TH, the high-speed data switch will be disabled and

opened.

6.1.1 USB-IF High-speed Compliance

The USB data switch will not significantly degrade the signal integrity through the device DP / DM pins

with USB high-speed communications.

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Chapter 7 USB Port Power Switch

7.1 USB Port Power Switch

To assure compliance to various charging specifications, the UCS1002 contains a USB port power

switch that supports two current limiting modes: trip and constant current (variable slope). The current

limit (ILIM) is pin selectable (and may be updated via the register set). The switch also includes soft

start circuitry and a separate short circuit current limit.

The port power switch is on in the Active state (except when VBUS is discharging).

7.2 Current Limiting

7.2.1 Current Limit Setting

The UCS1002 hardware set current limit, ILIM, can be one of eight values (see Table 4.1, "UCS1002

Communication Mode and ILIM Selection"). This resistor value is read once upon UCS1002 power-up.

The current limit can be changed via the SMBus / I2C after power-up; however, the programmed

current limit cannot exceed the hardware set current limit.

At power-up, the communication mode (Stand-alone or SMBus / I2C) and hardware current limit (ILIM)

are determined via the pull-down resistor (or pull-up resistor if connected to VDD) on the COMM_SEL

/ ILIM pin, as shown in Table 4.1.

7.2.2 Short Circuit Output Current Limiting

Short circuit current limiting occurs when the output current is above the selectable current limit (ILIMx).

This event will be detected and the current will immediately be limited (within tSHORT_LIM time). If the

condition remains, the port power switch will flag an Error condition and enter the Error state (see

Section 5.1.5, "Error State Operation").

7.2.3 Soft Start

When the PWR_EN control changes states to enable the port power switch, or an Attach Detection

event occurs in the Detect power state and the PWR_EN control is already enabled, the UCS1002

invokes a soft start routine for the duration of the VBUS rise time (tR_BUS). This soft start routine will

limit current flow from VS into VBUS while it is active. This circuitry will prevent current spikes due to

a step in the portable device current draw.

In the case when a portable device is attached while the PWR_EN pin is already enabled, if the bus

current exceeds ILIM, the UCS1002 current limiter will respond within a specified time (tSHORT_LIM)

and will operate normally at this point. The CBUS capacitor will deliver the extra current, if any, as

required by the load change.

7.2.4 Current Limiting Modes

The UCS1002 current limiting has two modes: trip and constant current (variable slope). Either mode

functions at all times when the port power switch is closed. The current limiting mode used depends

on the Active state mode (see Section 9.9, "Current Limit Mode Associations"). When operating in the

Detect power state (see Section 5.1.3), the current capacity at VBUS is limited to I

BUS_BYP as

described in Section 8.2, "VBUS Bypass Switch".

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7.2.4.1 Trip Mode

When using trip current limiting, the UCS1002 USB port power switch functions as a low resistance

switch and rapidly turns off if the current limit is exceeded. While operating using trip current limiting,

the VBUS output voltage will be held relatively constant (equal to the VS voltage minus the RON * IBUS

current) for all current values up to the ILIM.

If the current drawn by a portable device exceeds ILIM, the following occurs:

1. The port power switch will be turned off (trip action).

2. The UCS1002 will enter the Error state and assert the ALERT# pin.

3. The fault handling circuitry will then determine subsequent actions.

Trip current limiting is used by default when the UCS1002 is in Data Pass-through and Dedicated

Charger Emulation Cycle (except when the BC1.2 DCP charger emulation profile is accepted), and

when there’s no handshake.

APPLICATION NOTE: To avoid cycling in trip mode, set ILIM higher than the highest expected portable device

current draw.

Figure 7.1 shows operation of current limits in trip mode with the shaded area representing the USB

2.0 specified VBUS range. Dashed lines indicate the port power switch output will go to zero (e.g., trip)

when ILIM is exceeded. Note that operation at all possible values of ILIM are shown in Figure 7.1 for

illustrative purposes only; in actual operation only one ILIM can be active at any time.

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7.2.4.2 Constant Current Limiting (Variable Slope)

Constant current limiting is used when a portable device handshakes using the BC1.2 DCP charger

emulation profile and the current drawn is greater than ILIM (and ILIM < 1.5 A). It’s also used in BC1.2

CDP mode and during the DCE Cycle when a charger emulation profile is being applied and the

emulation timeout is active.

In CC mode, the port power switch allows the attached portable device to reduce VBUS output voltage

to less than the input VS voltage while maintaining current delivery. The V/I slope depends on the user

set ILIM value. This slope is held constant for a given ILIM value.

Figure 7.1 Trip Current Limiting Operation

0.5 1.0 1.5 2.0 2.5

5.25

4.75

IBUS (Amps)

VBUS (Volts)

Operating

Current

0.9 1.2

1.21.00.90.5 1.5 2.51.8 2.0

= ILIM’s

1.8

Power Switch Voltage and Current Output

go to Zero when ILIM is Exceeded

Trip action

(ILIM = 0.5 A)

Trip action

(ILIM = 2.5 A)

ILIM (Amps)

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Figure 7.2 shows operation of current limits while using CC mode. Unlike trip mode, once IBUS current

exceeds ILIM, operation continues at a reduced voltage and increased current. Note that the shaded

area representing the USB 2.0 specified VBUS range is now restricted to an upper current limit of

IBUS_R2MIN. Note that the UCS1002 will heat up along each load line as voltage decreases. If the

internal temperature exceeds the TREG or TTSD thresholds, the port power switch will open. Also note

that when the VBUS voltage is brought low enough (below VBUS_MIN), the port power switch will open.

7.3 Thermal Management and Voltage Protection

7.3.1 Thermal Management

The UCS1002 utilizes two-stage internal thermal management. The first is named dynamic thermal

management and the second is a fixed thermal shutdown.

Figure 7.2 Constant Current Limiting (Variable Slope) Operation

0.5 1.0 1.5 2.0 2.5

5.25

4.75

0.9 1.2

1.21.00.90.5 1.5

IBUS_R2MIN

1.8

1.8 2.0 2.5

IBUS (Amps)

VBUS (Volts)

ILIM (Amps)

= ILIM’s

Constant

resistance IBUS

operation line 1

(ILIM = 0.5 A)

Constant resistance

IBUS operation line 5

(ILIM = 1.5 A*)

CC Mode - Power switch current increases as

voltage decreases when ILIM is exceeded

following constant resistance lines

*1.5 A limit reduced by -3.5% internally

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7.3.1.1 Dynamic Thermal Management

For the first stage (active in both current limiting modes), referred to as dynamic thermal management,

the UCS1002 automatically adjusts port power switch limits and modes to lower power dissipation

when the thermal regulation temperature value is approached, as described below.

If the internal temperature exceeds the TREG value, the port power switch is opened, the current limit

(ILIM) will be lowered by one step and a timer is started (tDC_TEMP). When this timer expires, the port

power switch is closed and the internal temperature will be checked again. If it remains above the TREG

threshold, the UCS1002 will repeat this cycle (open port power switch and reduce the ILIM setting by

one step) until ILIM reaches its minimum value.

APPLICATION NOTE: If the temperature exceeds the TREG threshold while operating in the DCE Cycle mode after

a charger emulation profile has been accepted, the profile will be removed. The UCS1002

will not restart the DCE Cycle until one of the control inputs changes states to restart

emulation.

APPLICATION NOTE: The UCS1002 will not actively discharge VBUS as a result of the temperature exceeding

TREG; however, any load current provided by a portable device or other load will cause

VBUS to be discharged when the port power switch is opened, possibly resulting in an

attached portable device resetting.

If the UCS1002 is operating using constant current limiting (variable slope) and the ILIM setting has

been reduced to its minimum set point and the temperature is still above TREG

, the UCS1002 will

switch to operating using trip current limiting. This will be done by reducing the IBUS_R2MIN setting to

100 mA and restoring the ILIM setting to the value immediately below the programmed setting (e.g., if

the programmed ILIM is 1.8 A, the value will be set to 1.5 A). If the temperature continues to remain

above TREG

, the UCS1002 will continue this cycle (open the port power switch and reduce the ILIM

setting by one step).

If the UCS1002 internal temperature drops below TREG - TREG_HYST

, the UCS1002 will take action

based on the following:

1. If the current limit mode changed from CC mode to trip mode, then a timer is started. When this

timer expires, the UCS1002 will reset the port power switch operation to its original configuration

allowing it to operate using constant current limiting (variable slope).

2. If the current limit mode did not change from CC mode to trip mode, or was already operating in

trip mode, the UCS1002 will reset the port power switch operation to its original configuration.

If the UCS1002 is operating using trip current limiting and the ILIM setting has been reduced to its

minimum set point and the temperature is above TREG

, the port power switch will be closed and the

current limit will be held at its minimum setting until the temperature drops below TREG - TREG_HYST

7.3.1.2 Thermal Shutdown

The second stage thermal management consists of a hardware implemented thermal shutdown

corresponding to the maximum allowable internal die temperature (TTSD). If the internal temperature

exceeds this value, the port power switch will immediately be turned off until the temperature is below

TTSD - TTSD_HYST

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7.4 VBUS Discharge

The UCS1002 will discharge VBUS through an internal 100 Ω resistor when at least one of the following

conditions occurs:

The PWR_EN control is disabled (triggered on the inactive edge of the PWR_EN control).

A portable device Removal Detection event is flagged.

The VS voltage drops below a specified threshold (VS_UVLO) that causes the port power switch to

be disabled.

When commanded into the Sleep power state via the EM_EN, M1, and M2 controls.

Before each charger emulation profile is applied.

Upon recovery from the Error state.

When commanded via the SMBus (see Section 10.4, "Configuration Registers") in the Active state.

Any time that the port power switch is activated after the VBUS bypass switch has been on (i.e.,

whenever VBUS voltage transitions from being driven from VDD to being driven from VS, such as

going from Detect to Active power state).

Any time that the VBUS bypass switch is activated after the port power switch has been on (i.e.,

going from Active to Detect power state).

When the VBUS discharge circuitry is activated, at the end of the tDISCHARGE time, the UCS1002 will

confirm that VBUS was discharged. If the VBUS voltage is not below the VTEST level, a discharge error

will be flagged (by setting the DISCHARGE_ERR status bit) and the UCS1002 will enter the Error

state.

7.5 Battery Full

Delivery of bus current to a portable device can be rationed by the UCS1002. When this functionality

is enabled, the host system must provide the UCS1002 with an accumulated charge maximum limit

(in milliampere-hours). The charge rationing functionality works only in the Active power state. It

continuously monitors the current delivered as well as the time elapsed since the mode was activated

(or since the data was updated). This information is compiled to generate a charge-rationing number

that is checked against the host limit.

Once the programmed current-rationing limit has been reached, the UCS1002 will take action as

determined by the RATION_BEH bits as described in Table 7.1. Note that this does not cause the

device to enter the Error state.

Once the charge rationing circuitry has reached the programmed threshold, the UCS1002 will maintain

the desired behavior until charge rationing is reset. Once charge rationing has been reset or disabled,

the UCS1002 will recover as shown in Ta b l e 7. 2 .

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Table 7.1 Charge Rationing Behavior

RATION_BEH

[1:0]

BEHAVIOR ACTIONS TAKEN NOTES10

0 0 Report ALERT# pin asserted.

0 1 Report and

Disconnect

(default)

1. ALERT# pin asserted.

2. Charger emulation

profile removed.

3. Port power switch

disconnected.

The HSW will not be affected.

All bus monitoring is still active.

Changing the M1, M2, EM_EN, S0, and

PWR_EN controls will cause the device to

change power states as defined by the pin

combinations; however, the port power

switch will remain off until the rationing

circuitry is reset. Furthermore, the bypass

switch will not be turned on if enabled via

the S0 control.

1 0 Disconnect and go

to Sleep

1. Port power switch

disconnected.

2. Charger emulation

profile removed.

3. Device will enter the

Sleep state.

The HSW will be disabled.

All VBUS and VS monitoring will be

stopped.

Changing the M1, M2, EM_EN, S0, and

PWR_EN controls will have no effect on the

power state until the rationing circuitry is

reset.

1 1 Ignore Take no further action.

Table 7.2 Charge Rationing Reset Behavior

BEHAVIOR RESET ACTIONS

Report 1. Reset the Total Accumulated Charge registers.

2. Clear the RATION status bit.

3. Release the ALERT# pin.

Report and Disconnect 1. Reset the Total Accumulated Charge registers.

2. Clear the RATION status bit.

3. Release the ALERT# pin.

4. Check the M1, M2, EM_EN, S0, and PWR_EN controls and enter the indicated

power state if the controls changed (see Note 7.1).

Disconnect and go to

Sleep

1. Reset the Total Accumulated Charge registers.

2. Clear the RATION status bit.

3. Check the M1, M2, EM_EN, S0, and PWR_EN controls and enter the indicated

power state if the controls changed (see Note 7.1).

Ignore 1. Reset the Total Accumulated Charge registers.

2. Clear the RATION status bit.

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Note 7.1 Any time the charge rationing circuitry checks the pin conditions when changing rationing

behavior or resetting charge rationing, if the external pin conditions have changed, then

charger emulation will be restarted (provided emulation is enabled via the pin states). If

the pin conditions have not changed, the UCS1002 return to the previous power state as

if the rationing threshold had not been reached (e.g., it will not discharge VBUS or restart

emulation).

7.5.1 Charge Rationing Interactions

When charge rationing is active, regardless of the specified behavior, the UCS1002 will function

normally until the charge rationing threshold is reached. Note that charge rationing is only active when

the UCS1002 is in the Active state, and it does not automatically reset when a Removal or Attach

Detection event occurs. Charger emulation will start over if a Removal Detection event and Attach

Detection event occur while charge rationing is active and the charge rationing threshold has not been

reached. This allows charging of sequential portable devices while charge is being rationed, which

means that the accumulated power given to several portable devices will still be held to the stated

rationing limit.

Changing the charge rationing behavior will have no effect on the charge rationing data registers. If

the behavior is changed prior to reaching the charge rationing threshold, this change will occur and be

transparent to the user. When the charge rationing threshold is reached, the UCS1002 will take action

as shown in Ta b l e 7. 1 . If the behavior is changed after the charge rationing threshold has been

reached, the UCS1002 will immediately adopt the newly programmed behavior, clearing the ALERT#

pin and restoring switch operation respectively (see Table 7.3).

Table 7.3 Effects of Changing Rationing Behavior after Threshold Reached

BEHAVIOR NEW BEHAVIOR ACTIONS TAKEN

Ignore Report Assert ALERT# pin.

Report and

Disconnect

1. Assert ALERT# pin.

2. Remove charger emulation profile.

3. Open port power switch. See the “Report and Disconnect” entry in

Tab l e 7 . 1.

Disconnect and

go to Sleep

1. Remove charger emulation profile.

2. Open port power switch.

3. Enter the Sleep state. See the “Disconnect and go to Sleep” entry in

Tab l e 7 . 1.

Report Ignore Release ALERT# pin.

Report and

Disconnect

Open port power switch. See the “Report and Disconnect” entry in Tab l e 7 .1 .

Disconnect and

go to Sleep

1. Release the ALERT# pin.

2. Remove charger emulation profile.

3. Open the port power switch.

4. Enter the Sleep state. See the “Disconnect and go to Sleep” entry in

Tab l e 7 . 1.

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If the RATION_EN control is set to ‘0’ prior to reaching the charge rationing threshold, rationing will be

disabled and the Total Accumulated Charge registers will be cleared. If the RATION_EN control is set

to ‘0’ after the charge rationing threshold has been reached, the following will be done:

1. RATION status bit will be cleared.

2. The ALERT# pin will be released if asserted by the rationing circuitry and no other conditions are

present.

3. The M1, M2, EM_EN, S0, and PWR_EN controls are checked to determine the power state. See

Note 7.1.

APPLICATION NOTE: If the rationing behavior was set to “Report and Disconnect” when the charge rationing

threshold was reached and then the RATION_EN bit is cleared, the portable device may start

charging suboptimally because the charger emulation profile has been removed. Toggle the

PWR_EN control to restart charger emulation.

Setting the RATION_RST control to ‘1’ will automatically reset the Total Accumulated Charge registers

to 00_00h. If this is done prior to reaching the charge rationing threshold, the data will continue to be

accumulated restarting from 00_00h. If this is done after the charge rationing threshold is reached, the

UCS1002 will take action as shown in Ta b l e 7 .2 .

7.6 Fault Handling Mechanism

The UCS1002 has two modes for handling faults: Latch (latch-upon-fault) or Auto-recovery

(automatically attempt to restore the Active power state after a fault occurs). If the SMBus is actively

utilized, auto-recovery fault handling is the default error handler as determined by the LATCH_SET bit

(see Section 10.4.3, "Switch Configuration - 17h"). Otherwise, the fault handling mechanism used

depends on the state of the LATCH pin. Faults include over-current, over-voltage (on VS), under-

Report and

Disconnect

Ignore 1. Release the ALERT# pin.

2. Check the M1, M2, EM_EN, S0, and PWR_EN controls and enter the

indicated power state if the controls changed (see Note 7.1).

Report Check the M1, M2, EM_EN, S0, and PWR_EN controls and enter the

indicated power state if the controls changed (see Note 7.1).

Disconnect and

go to Sleep

1. Release the ALERT# pin.

2. Enter the Sleep state. See the “Disconnect and go to Sleep” entry in

Tab l e 7 . 1.

Disconnect

and go to

Sleep

Ignore Check the M1, M2, EM_EN, S0, and PWR_EN controls and enter the

indicated power state if the controls changed (see Note 7.1).

Report 1. Assert the ALERT# pin.

2. Check the M1, M2, EM_EN, S0, and PWR_EN controls and enter the

indicated power state if the controls changed (see Note 7.1).

Report and

Disconnect

1. Assert the ALERT# pin.

2. Check the M1, M2, EM_EN, S0, and PWR_EN controls to determine the

power state then enter that state except that the port power switch and

bypass switch will not be closed (see Note 7.1).

Table 7.3 Effects of Changing Rationing Behavior after Threshold Reached (continued)

BEHAVIOR NEW BEHAVIOR ACTIONS TAKEN

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voltage (on VBUS), back-voltage (VBUS to VS or VBUS to VDD), discharge error, and maximum

allowable internal die temperature (TTSD) exceeded (see Section 5.1.5, "Error State Operation").

7.6.1 Auto-recovery Fault Handling

When the LATCH control is low, auto-recovery fault handling is used. When an error condition is

detected, the UCS1002 will immediately enter the Error state and assert the ALERT# pin (see

Section 5.1.5). Independently from the host controller, the UCS1002 will wait a preset time (tCYCLE),

check error conditions (tTST), and restore Active operation if the error condition(s) no longer exist. If

all other conditions that may cause the ALERT# pin to be asserted have been removed, the ALERT#

pin will be released.

7.6.2 Latched Fault Handling

When the LATCH control is high, latch fault handling is used. When an error condition is detected, the

UCS1002 will enter the Error power state and assert the ALERT# pin. Upon command from the host

controller (by toggling the PWR_EN control from enabled to disabled or by clearing the ERR bit via

SMBus), the UCS1002 will check error conditions once and restore Active operation if error conditions

no longer exist. If an error condition still exists, the host controller is required to issue the command

again to check error conditions.

Figure 7.3 Error Recovery Timing (Short Circuit Example)

tRST

VBUS

IBUS

SHORT

applied.

ITST

tDISCHARG

ITST

VTEST

Short Detected. VBUS

discharged. Enter

Error state.

Check short

condition. Short

still present.

Return to Error

State.

Wait tCYCLE.Wait tCYCLE.Check short

condition. Short

removed.

Return to

normal

operation.

tCYCLE tCYCLE

tRST

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Chapter 8 Detect State

8.1 Device Attach / Removal Detection

The UCS1002 can detect the attachment and removal of a portable device on the USB port. Attach

and Removal Detection does not perform any charger emulation or qualification of the device. The

high-speed switch is “off” (by default) during the Detect power state.

8.2 VBUS Bypass Switch

The UCS1002 contains circuitry to provide VBUS current as shown in Figure 8.1. In the Detect state,

VDD is the voltage source; in the Active state, VS is the voltage source. The bypass switch and the

port power switch are never both on at the same time.

While the VBUS bypass switch is active, the current available to a portable device will be limited to

IBUS_BYP

, and the Attach Detection feature is active.

8.3 Attach Detection

The Attach Detection feature is only active in the Detect power state. When active, this feature

constantly monitors the current load on the VBUS pin. If the current drawn by a portable device is

greater than IDET_QUAL for longer than tDET_QUAL, an Attach Detection event occurs. This will cause

the A_DET# pin to assert low and the ADET_PIN and ATT status bits to be set.

Until the port power switch is enabled, the current available to a portable device will be limited to that

used to detect device attachment (IDET_QUAL). Once an Attach Detection event occurs, the UCS1002

will wait for the PWR_EN control to be enabled (if not already). When PWR_EN is enabled and VS is

above the threshold, the UCS1002 will activate the USB port power switch and operate in the selected

Active mode (see Chapter 9, Active State).

8.4 Removal Detection

The Removal Detection feature will be active in the Active and Detect power states if S0 = 1. This

feature monitors the current load on the VBUS pin. If this load drops to less than IREM_QUAL_DET for

longer than tREM_QUAL, a Removal Detection event is flagged.

When a Removal Detection event is flagged, the following will be done:

1. Disable the port power switch and the bypass switch.

Figure 8.1 Detect State VBUS Biasing

Port Power

Switch

VDD

VBUS

Bypass

Switch

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2. De-assert the A_DET# pinUCS1002 and set the REM status register bit.

3. Enable an internal discharging device that will discharge the VBUS line within tDISCHARGE.

4. Once the VBUS pin has been discharged, the device will return to the Detect state regardless of

the PWR_EN control state.

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Chapter 9 Active State

9.1 Active State Overview

The UCS1002 has the following modes of operation in the Active state: Data Pass-through, BC1.2

DCP, BC1.2 SDP, BC1.2 CDP, and Dedicated Charger Emulation Cycle. The current limiting mode

depends on the Active mode behavior (see Table 9.2, "Current Limit Mode Options").

9.2 Active Mode Selection

The Active mode selection is controlled by three controls: EM_EN, M1, and M2, as shown in Tab l e 9 . 1.

Note 9.1 BC1.2 SDP behaves the same as the Data Pass-through mode with the exception that it

is preceded by a VBUS discharge when the mode is entered per the BC1.2 specification.

9.3 BC1.2 Detection Renegotiation

The BC1.2 specification allows a charger to act as an SDP, CDP, or DCP and to change between these

roles. To force an attached portable device to repeat the charging detection procedure, VBUS must be

cycled. In compliance with this specification, the UCS1002 automatically cycles VBUS when switching

between the BC1.2 SDP, BC1.2 DCP, and BC1.2 CDP modes.

9.4 Data Pass-through (No Charger Emulation)

When commanded to Data Pass-through mode, UCS1002 will close its USB high-speed data switch

to allow USB communications between a portable device and host controller and will operate using trip

current limiting. No charger emulation profiles are applied in this mode. Data Pass-through mode will

persist until commanded otherwise by the M1, M2, and EM_EN controls.

APPLICATION NOTE: If it is desired that the Data Pass-through mode operates as a traditional / standard port

power switch, the S0 control should be set to ‘0’. When entering this mode, there is no

automatic VBUS discharge.

Table 9.1 Active Mode Selection

# M1 M2 EM_EN ACTIVE MODE

10 0 1 Dedicated Charger Emulation Cycle

20 1 0 Data Pass-through

30 1 1 BC1.2 DCP

41 0 0 BC1.2 SDP - See Note 9.1

51 0 1 Dedicated Charger Emulation Cycle

61 1 0 Data Pass-through

71 1 1 BC1.2 CDP

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APPLICATION NOTE: When the M1, M2, and EM_EN controls are set to ‘0’, ‘1’, ‘0’ or to ‘1’, ‘1’, ‘0’ respectively,

Data Pass-through mode will persist if the PWR_EN control is disabled; however, the

UCS1002 will draw more current. To leave Data Pass-through mode, the PWR_EN control

must be enabled before the M1, M2, and EM_EN controls are changed to the desired mode.

9.5 BC1.2 SDP (No Charger Emulation)

When commanded to BC1.2 SDP mode, UCS1002 will discharge VBUS, close its USB high-speed

data switch to allow USB communications between a portable device and host controller, and will

operate using trip current limiting. No charger emulation profiles are applied in this mode. BC1.2 SDP

mode will persist until commanded otherwise by the M1, M2, EM_EN, and PWR_EN controls.

APPLICATION NOTE: If it is desired that the BC1.2 SDP mode operates as a traditional / standard port power

switch, the S0 control should be set to ‘0’.

9.6 BC1.2 CDP

When BC1.2 CDP is selected as the Active mode, UCS1002 will discharge VBUS, close its USB high-

speed data switch (by default), and apply the BC1.2 CDP charger emulation profile which performs

handshaking per the specification. The combination of the UCS1002 CDP handshake along with a

standard USB host comprises a charging downstream port. In BC1.2 CDP mode, there is no emulation

timeout.

If the handshake is successful, the UCS1002 will operate using constant current limiting (variable

slope). If the handshake is not successful, the UCS1002 will leave the applied CDP profile in place,

leave the high-speed switch closed, enable constant current limiting, and persist in this condition until

commanded otherwise by the M1, M2, EM_EN, and PWR_EN controls.

The UCS1002 will respond per the BC1.2 specification to portable device initiated charger

renegotiation requests.

APPLICATION NOTE: BC1.2 compliance testing may require the S0 control to be set to ‘0’ (Attach and Removal

Detection feature disabled) while testing is in progress.

APPLICATION NOTE: When the UCS1002 is in BC1.2 CDP mode and the Attach and Removal Detection feature

is enabled, if a power thief, such as a USB light or fan, attaches but does not assert DP, a

Removal event will not occur when the portable device is removed. However, if a standard

USB device is subsequently attached, Removal Detection will again be fully functional. As

well, if PWR_EN is cycled or M1, M2, and / or EM_EN change state, a Removal event will

occur and Attach Detection will be reactivated.

9.6.1 BC1.2 CDP Charger Emulation Profile

The BC1.2 CDP charger emulation profile acts as described below.

APPLICATION NOTE: All CDP handshaking is performed with the high-speed switch closed.

1. VBUS voltage is applied.

2. Primary Detection - When the portable device drives a voltage between 0.4 V and 0.8 V onto the

DPOUT pin, the UCS1002 will drive 0.6 V onto the DMOUT pin within 20 ms.

3. When the portable device drives the DPOUT pin back to ‘0’, the UCS1002 will then drive the

DMOUT pin back to ‘0’ within 20 ms.

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4. Optional Secondary Detection - If the portable device then drives a voltage of 0.6 V (nominal) onto

the DMOUT pin, the UCS1002 will take no other action. This will cause the portable device to

observe a ‘0’ on the DPOUT pin and know that it is connected to a CDP.

9.7 BC1.2 DCP

When BC1.2 DCP is selected as the Active mode, UCS1002 will discharge VBUS and apply the BC1.2

DCP charger emulation profile per the specification. In BC1.2 DCP mode, the emulation timeout and

requirement for portable device current draw are automatically disabled. When the BC1.2 DCP charger

emulation profile is applied within the Dedicated Charger Emulation Cycle (see Section 9.11.1, "BC1.2

DCP Charger Emulation Profile Within DCE Cycle"), the timeout and current draw requirement are

enabled.

If the portable device is charging after the DCP charger emulation profile is applied, the UCS1002 will

leave in place the resistive short, leave the high-speed switch open, and enable constant current

limiting (variable slope).

APPLICATION NOTE: BC1.2 compliance testing may require the S0 control to be set to ‘0’ (Attach and Removal

Detection feature disabled) while testing is in progress.

9.7.1 BC1.2 DCP Charger Emulation Profile

The BC1.2 DCP charger emulation profile is described below.

1. VBUS voltage is applied. A resistor (RDCP_RES) is connected between the DPOUT and DMOUT

pins.

2. Primary Detection - If the portable device drives 0.6 V (nominal) onto the DPOUT pin, the UCS1002

will take no other action than to leave the resistor connected between DPOUT and DMOUT. This

will cause the portable device to see 0.6 V (nominal) on the DMOUT pin and know that it is

connected to a DCP.

3. Optional Secondary Detection - If the portable device drives 0.6 V (nominal) onto the DMOUT pin,

the UCS1002 will take no other action than to leave the resistor connected between DPOUT and

DMOUT. This will cause the portable device to see 0.6 V (nominal) on the DPOUT pin and know

that it is connected to a DCP.

9.8 Dedicated Charger

When commanded to Dedicated Charger Emulation Cycle mode, the UCS1002 enables an attached

portable device to enter its charging mode by applying specific charger emulation profiles in a

predefined sequence. Using these profiles, the UCS1002 is capable of generating and recognizing

several signal levels on the DPOUT and DMOUT pins. The preloaded charger emulation profiles

include ones compatible with BC1.2 DCP, YD/T-1591 (2009) and most Apple and RIM portable

devices. Other levels, sequences, and protocols are configurable via the SMBus / I2C.

When a charger emulation profile is applied, a programmable timer for the emulation profile is started.

When emulation timeout occurs, the UCS1002 checks the IBUS current against a programmable

threshold. If the current is above the threshold, the charger emulation profile is accepted and the

associated current limiting mode is applied. No active USB data communication is possible when

charging in this mode (by default - see Section 10.4.5, "High-speed Switch Configuration - 25h").

9.8.1 Emulation Reset

Prior to applying any of the charger emulation profiles, the UCS1002 will perform an emulation reset.

This involves the following:

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1. The UCS1002 resets the VBUS line by disconnecting the port power switch and connecting VBUS

to ground via an internal 100 Ω resistor for tDISCHARGE time. The port power switch will be held

open for a time equal to tEM_RESET at which point the port power switch will be closed and the

VBUS voltage applied.

2. The DPOUT and DMOUT pins will be pulled low using internal 15 kΩ pull-down resistors.

APPLICATION NOTE: To help prevent possible damage to a portable device, the DPOUT and DMOUT pins have

current limiting in place when the emulation profiles are applied.

9.8.2 Emulation Cycling

In Dedicated Charger Emulation Cycle mode, the charger emulation profiles (if enabled) will be applied

in the following order:

1. Legacy 1

2. BC1.2 DCP

3. Legacy 2

4. Legacy 3

5. Legacy 4

6. Legacy 5

7. Legacy 6

8. Legacy 7

9. Custom (disabled by default). If the CS1_FIRST configuration bit is set, then the Custom charger

emulation profile will be tested first and the order will proceed as given.

APPLICATION NOTE: If S0=’0’ and a portable device is not attached in DCE Cycle mode, the UCS1002 will be

cycling through charger emulation profiles (by default). There is no guarantee which charger

emulation profile will be applied first when a portable device attaches.

The UCS1002 will apply a charger emulation profile until one of the following exit conditions occurs:

1. Current greater than IBUS_CHG is detected flowing out of VBUS at the respective emulation timeout

time. In this case, the profile is assumed to be accepted and no other profiles will be applied.

2. The respective emulation timeout (tEM_TIMEOUT) time is reached without current that exceeds the

IBUS_CHG limit flowing out of VBUS (the emulation timeout is enabled by default, see Section

10.4.2, "Emulation Configuration - 16h" and Section 10.13.1, "Custom Emulation Configuration -

40h"). The profile is assumed to be rejected, and the UCS1002 will perform emulation reset and

apply the next profile, if there is one.

Emulation timeouts can be programmed for each charger emulation profile (see Section 10.11,

"Preloaded Emulation Timeout Configuration Registers" and Section 10.13.1, "Custom Emulation

Configuration - 40h").

9.8.3 DCE Cycle Retry

If none of the charger emulation profiles cause a charge current to be drawn, the UCS1002 will perform

emulation reset and cycle through the profiles again (if the EM_RETRY bit is set (default - see Section

10.4.2, "Emulation Configuration - 16h")). The UCS1002 will continue to cycle through the profiles so

as long as charging current is not drawn and the PWR_EN control is enabled. If the Emulation Retry

is not enabled, the UCS1002 will flag “no handshake” and end the DCE Cycle using trip current

limiting.

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9.9 Current Limit Mode Associations

The UCS1002 will close the port power switch and use the current limiting mode as shown in Ta b l e 9 . 2 .

As noted in the last three rows in Table 9.2, under those specific conditions with ILIM < 1.5 A, it is the

relationship of ILIM and IBUS_R2MIN that determines the current limiting mode. In these cases, the value

of IBUS_R2MIN is determined by CS_R2_IMIN[2:0] bits 4-2 in the Custom Current Limiting Behavior

Configuration register 51h.

9.10 No Handshake

In DCE Cycle mode with emulation retry disabled, a “no handshake” condition is flagged (the NO_HS

status bit stays set (see Section 10.3.4, "Profile Status 1 - 12h")) when the end of the DCE Cycle is

reached without a handshake and without drawing current.

All signatures / handshaking placed on the DPOUT and DMOUT pins are removed. The UCS1002 will

operate with the high-speed switch opened or closed as determined by the high-speed switch

configuration and will use trip or constant current limiting as determined by the IBUS_R2MIN setting

(CS_R2_IMIN[2:0] bits 4-2 in the Custom Current Limiting Behavior Configuration register 51h).

Table 9.2 Current Limit Mode Options

ACTIVE MODE

CURRENT LIMIT MODE

(SEE Section 10.14)

Data Pass-through Trip mode

BC1.2 DCP CC mode if ILIM < 1.5 A, otherwise, trip mode

BC1.2 SDP Trip mode

BC1.2 CDP CC mode if ILIM < 1.5 A, otherwise, trip mode

DCE CYCLE

During DCE Cycle when a charger

emulation profile is being applied and the

emulation timeout is active

CC mode if ILIM < 1.5 A, otherwise, trip mode

BC1.2 DCP charger emulation profile

accepted or the emulation timeout is

disabled

CC mode if ILIM < 1.5 A, otherwise, trip mode

Legacy 2 charger emulation profile

accepted or the emulation timeout is

disabled

CC mode if ILIM < 1.5 A, otherwise, trip mode

Legacy 1 or Legacy 3 - Legacy 7 charger

emulation profile accepted or the

emulation timeout is disabled

Trip mode if IBUS_R2MIN < ILIM or ILIM > 1.5 A (normal operation),

otherwise, CC mode (see Section 10.14.2)

Custom charger emulation profile

accepted or the emulation timeout is

disabled

Trip mode if IBUS_R2MIN < ILIM or ILIM > 1.5 A (normal operation),

otherwise, CC mode (see Section 10.14.2)

No handshake (DCE Cycle with

Emulation Retry not enabled)

Trip mode if IBUS_R2MIN < ILIM or ILIM > 1.5 A (normal operation),

otherwise, CC mode (see Section 10.14.2)

Programmable USB Port Power Controller with Charger Emulation

Datasheet

SMSC UCS1002 65 Revision 1.4 (07-16-13)

DATASHEET

Portable devices that can cause this are generally ones that pull up DPOUT to some voltage and leave

it there, or apply the wrong voltage.

9.11 Preloaded Charger Emulation Profiles

The following charger emulation profiles are resident to the UCS1002:

1. Legacy 1, 3, 4, and 6 - See Section 9.11.3

2. Legacy 2 - See Section 9.11.2

3. Legacy 5 - See Section 9.11.4

4. Legacy 7 - See Section 9.11.5

5. BC1.2 CDP - See Section 9.6.1

6. BC1.2 DCP - See Section 9.7.1

Additionally, the user may “build” a charger emulation profile by determining the voltage and resistance

characteristics that are placed on each of the DPOUT and DMOUT pins. See Section 9.12, "Custom

Charger Emulation Profile".

9.11.1 BC1.2 DCP Charger Emulation Profile Within DCE Cycle

When the BC1.2 DCP charger emulation profile (Section 9.7.1, "BC1.2 DCP Charger Emulation

Profile") is applied within the DCE Cycle (Dedicated Charger Emulation Cycle is selected as the Active

mode), the behavior after the profile is applied is different than Active mode BC1.2 DCP (BC1.2 DCP

in Ta b l e 9 . 1 ) because the tEM_TIMEOUT timer is enabled (by default) during the DCE Cycle.

During the DCE Cycle after the DCP charger emulation profile, the UCS1002 will perform one of the

following:

1. If the portable device is drawing more than IBUS_CHG current when the tEM_TIMEOUT timer expires,

the UCS1002 will flag that a BC1.2 DCP was detected. The UCS1002 will leave in place the

resistive short, leave the high-speed switch open, and then enable constant current limiting

(variable slope).

2. If the portable device does not draw more than IBUS_CHG current when the tEM_TIMEOUT timer

expires, the UCS1002 will stop applying the DCP charger emulation profile and proceed to the next

charger emulation profile in the DCE Cycle.

9.11.2 Legacy 2 Charger Emulation Profile

The Legacy 2 charger emulation profile does the following:

1. The UCS1002 will connect a resistor (RDCP_RES) between DPOUT and DMOUT.

2. VBUS is applied.

3. If the portable device draws more than IBUS_CHG current when the tEM_TIMEOUT timer expires

(enabled by default), the UCS1002 will accept that this is the correct charger emulation profile for

the attached portable device. Charging commences. The resistive short between the DPOUT and

DMOUT pins will be left in place. The UCS1002 will use constant current limiting.

4. If the portable device does not draw more than IBUS_CHG current when tEM_TIMEOUT timer expires,

the UCS1002 will stop the Legacy 2 charger emulation. This will cause resistive short between the

DPOUT and DMOUT pins to be removed. Emulation reset occurs, and the UCS1002 will initiate

the next charger emulation profile.

Programmable USB Port Power Controller with Charger Emulation

Datasheet

Revision 1.4 (07-16-13) 66 SMSC UCS1002

DATASHEET

9.11.3 Legacy 1, 3, 4, and 6 Charger Emulation Profiles

Legacy 1, 3, 4, and 6 charger emulation profiles follow the same pattern of operation although the

voltage that is applied on the DPOUT and DMOUT pins will vary. They do the following:

1. The UCS1002 will apply a voltage on the DPOUT pin using either a current-limited voltage source

or a voltage divider between VBUS and ground with the center tap on the DPOUT pin.

2. The UCS1002 will apply a possibly different voltage on the DMOUT pin using either a current-

limited voltage source or a voltage divider between VBUS and ground with the center tap on the

DMOUT pin.

3. VBUS voltage is applied.

4. If the portable device draws more than IBUS_CHG current when the tEM_TIMEOUT timer expires, the

UCS1002 will accept that the currently applied profile is the correct charger emulation profile for

the attached portable device. Charging commences. The voltages applied to the DPOUT and

DMOUT pins will remain in place (unless LEAVE_EMU_RESP is set to 0b). The UCS1002 will

begin operating in trip mode or CC mode as determined by the IBUS_R2MIN setting (see Section

10.14, "Current Limiting Behavior Configuration Registers").

5. If the portable device does not draw more than IBUS_CHG current when tEM_TIMEOUT timer expires,

the UCS1002 will stop the currently applied charger emulation profile. This will cause all voltages

put onto the DPOUT and DMOUT pins to be removed. Emulation reset occurs, and the UCS1002

will initiate the next charger emulation profile.

9.11.4 Legacy 5 Charger Emulation Profile

Legacy 5 charger emulation profile does the following:

1. The UCS1002 will apply 900 mV to both the DPOUT and the DMOUT pins.

2. VBUS voltage is applied.

3. If the portable device draws more than IBUS_CHG current when the tEM_TIMEOUT timer expires, the