Features Windowed for reprogrammability CMOS for optimum speed/power High speed 15-ns max set-up 10-ns clock te output Low power 330 mW (commercial) for 25 ns 660 mW (military) Programmable synchronous or asynchronous output enable On-chip edge-triggered registers e Programmable asynchronous register (INIT) EPROM technology, 100% programmable Slim, 300-mil, 24-pin plastic or hermetic DIP CY7C245A @ 5V +10% Vcc, commercial and mnilitary e TTL-compatible /O Direct replacement for bipolar PROMs e Capable of withstanding greater than 2001V static discharge Functional Description The CY7C245A is a high-performance 2048-word by 8-bit electrically program- mable read only memory packaged in a slim 300-mil plastic or hermetic DIP. The ceramic package may be equipped with an erasure window; when exposed to UV light the PROM is erased and can then be reprogrammed. The memory cells utilize proven EPROM floating-gate technology and byte-wide intelligent programming al- gorithms. Reprogrammable 2K x 8 Registered PROM The CY7C245A replaces bipolar devices and offers the advantages of lower power, reprogrammability, superior performance and high programming yield. The EPROM cell requires only 12.5V for the supervoltage, and low current require- ments allow gang programming. The EPROM cells allow each memory location tobe tested 100%, because each location is written into, erased, and repeatedly exer- cised prior to encapsulation. Each PROM is also tested for AC performance to guar- antee that after customer programming the product will meet AC specification limits. The CY7C245A has an asynchronous ini- tialize function (INIT). This function acts as a 2049th 8-bit word loaded into the on- chip register. It is user programmable with any desired word, or may be used as a PRESET or CLEAR function on the out- puts. INIT is triggered by a low level, not an edge. Logic Block Diagram iNT > | . Ao Le L 7 Ay 3 | 6 A an row FN] proGRaMMaBLe MULTIPLEXER i { | Aq ] ADDRESS nd ARRAY | | se Os A > Wa 8-BIT A | o EDGE- | an ADDRESS | <3 TRIGGERED Os As *] DECODER 24 REGISTER Ay 3 - Og Ag az ~ a HP o Ag m{ COLUMN q ADDRESS Vj Ato 0, q CP Oo PROGRAMMABLE E/Es Dal} = MULTIPLEXER ce i c C24ga1 Pin Configurations DIP Top View C245A-2 LCC/PLCC (Opaque only) Top View og LLTZL LZ 4 3 2,1, 282726 - 25 24 23 19: 12 1314 151617 18 SSBSSE So Os, C245A-3 Selection Guide Current (mA 7C245A15 7C245AL25 7C245AL35 | 7C245AL45an CY7C245A e CYPRESS (# SEMICONDUCTOR Maximum Ratings (Above which the useful life may be impaired. For user guidelines, Static Discharge Voltage .............-----+----- >2001V not tested.) (per MIL-STD-883, Method 3015) Storage Temperature .............---- 65C to +150C _ Latch-Up Current ...........--- serene >200 mA Paves Ape wan ceececereeens ~55Cto +125C | Operating Range Supply Voltage to Ground Potential Ambient (Pin 24 to Pin 12) .............- 0. eee 0.5V to +7.0V Range Temperature Vec DC Voltage Applied to Outputs Commercial 0C to +70C SV 410% DC pot lage sn, D3ovee erov [Aedes TT <soecro rasre [Sv sI0% | g DC Program Voltage (Pins 7, 18,20) .........000-0 0 13.0V Military = 55C to +125C SV +10% UV Erasure 0.0.00... cee cee eee eee eee 7258 Wsec/em? c Electrical Characteristics Over the Operating Range! 41 7C245A25 | 7C245AL25 7C245A35 | 7C245AL35 7C245A-15 | 7C245A45 | 7C245AL45 Parameter Description Test Conditions Min. | Max. | Min. | Max. | Min. | Max. | Unit Vou Output HIGH Voltage Vcc = Min., Ion = 4.0mA | 2.4 2.4 2.4 Vv Vin = Vin oF Vi VoL Output LOW Voltage Voc = Min, Io, = 16 mA 0.4 0.4 0.4 Vv Vin = Vin or Vit Vin Input HIGH Level Guaranteed Input Logical 2.0 | Vcc 2.0 | Veco | 2.0 | Vcc Vv HIGH Voltage for All Inputs Vit Input LOW Level Guaranteed Input Logical 0.8 08 0.8 Vv LOW Voltage for All Inputs Iyx Input Leakage Current GND < Vin < Vcc -10 | +10 | -10 | +10 | 10 | +10 |] pA Vep Input Clamp Diode Voltage Note 4 loz Output Leakage Current GND < Vo < Vor -10 | +10 | -10 | +10 | 10 | +10 |] pA Output Disabledl> los Output Short Circuit Current | Vcc = Max., Vour =0.0V'Ol | 20 | 90 | ~20 | -90 | -20 | -90 | mA Tec Power Supply Current Vcc = Max., Coml 120 90 60 mA Tour=0 mA Mil 120 120 Vpp Programming Supply Voltage 12 13 12 13 12 13 v Ipp Programming Supply Current 50 50 50 mA VIHP Input HIGH 3.0 3.0 3.0 Vv Programming Voltage VILP Input LOW 0.4 0.4 0.4 Vv Programming Voltage Capacitancel4] Parameter Description Test Conditions Max. Unit Cin Input Capacitance Ta = 25C, f = 1 MHz, 10 pF CouT Output Capacitance Voc = 5.0V 10 pF Notes: 1, Contact a Cypress representative for industrial temperature range 4. See the Introduction to CMOS PROMs section of the Cypress Data specifications. Book for general information on testing. 2. Ta is the instant on case temperature. 5. For devices using the synchronous enable, the device must be clocked 3. See the last page of this specification for Group A subgroup testing in- after applying these voltages to perform this measurement. formation. 6. For test purposes, not more than one output at a time should be shorted. Short circuit test duration should not exceed 30 seconds.-.. CYPRESS BF SEMICONDUCTOR CY7C245A AC Test Loads and Waveforms!>: 4] Ri 250Q R1 250 5V 5V ow ALL INPUT PULSES OUTPUT OUTPUT R2 Ra 50 pF I 1672 5 pF 1 3 1670 INCLUDING => tL INCLUDING + JIGAND ~ ~ JIG AND ~ ~ SCOPE SCOPE C245A-4 C245A-5 (a) Normal Load (b) High Z Load Equivalent to: THEVENIN EQUIVALENT 1002 OUTPUT o_~w-_-0 2.0V C245A-6 Switching Characteristics Over Operating Rangel> 4] 7C245A25 7C245A35 7TC245A45 7C245A-15 | 7C245AL25 | 7C245AL35 | 7C245AL45 Parameter Description Min. | Max. | Min. | Max. | Min. | Max. | Min. | Max. | Unit tsa Address Set-Up to Clock HIGH 1S 25 35 45 ns tHa Address Hold from Clock HIGH 0 0 0 0 ns tco Clock HIGH to Valid Output 10 12 15 25 ns tpwe Clock Pulse Width 10 15 20 20 ns tsEs Es Set-Up to Clock HIGH 10 12 15 15 ns tyes Es Hold from Clock HIGH 5 5 5 5 ns tbr Delay from INIT to Valid Output IS 20 20 35 ns try INIT Recovery to Clock HIGH 10 15 20 20 ns tpwi INIT Pulse Width 10 15 20 25 ns tcos Valid Output from Clock HIGHI7] 15 15 20 30 ns tuze Inactive Output from Clock HIGH! 15 15 20 30 ns tpoE Valid Output from E LOWS! 12 15 20 30 ns tyzE Inactive Output from E HIGHE! 15 15 20 30 ns Notes: 7. Applies only when the synchronous (Es) function is used. Operating Modes The CY7C245A is a CMOS electrically programmable read only memory organized as 2048 words x 8 bits and is a pin-for-pin re- placement for bipolar TTL fusible link PROMs. The CY7C245A incorporates a D-type, master-slave register on chip, reducing the cost and size of pipelined microprogrammed systems and applica- tions where accessed PROM data is stored temporarily in a regis- ter. Additional flexibility is provided with a programmable syn- chronous (Es) or asynchronous (E) output enable and asynchronous initialization (INIT). Upon power-up the state of the outputs will depend on the pro- grammed state of the enable function (Eg or E). Ifthe synchronous enable (Es) has been programmed, the register will be in the set condition causing the outputs (Og O7) to be in the OFF or high- impedance state. If the asynchronous enable (E) is being used, the outputs will come up in the OFF or high-impedance state only if the enable (E) input is ata HIGH logic level. Data is read by apply- ing the memory location to the address inputs (Ag Ajo) anda logic LOW to the enable input. The stored data is accessed and loaded into the master flip-flops of the data register during the ad- 8. Applies only when the asynchronous (E) function is used. dress set-up time. At the next LOW-to-HIGH transition of the clock (CP), data is transferred to the slave flip-flops, which drive the output buffers, and the accessed data will appear at the outputs (Og O7). If the asynchronous enable (E) is being used, the outputs may be disabled at any time by switching the enable to a logic HIGH, and may be returned to the active state by switching the enable to a log- ic LOW. If the synchronous enable (Es) is being used, the outputs will go to the OFFor high-impedance state upon the next positive clock edge after the synchronous enable input is switched to a HIGH level. If the synchronous enable pin is switched to a logic LOW, the subse- quent positive clock edge will return the output to the active state. Following a positive clock edge, the address and synchronous en- able inputs are free to change since no change in the output will oc- cur until the next LOW-to-HIGH transition of the clock. This unique feature allows the CY7C245A decoders and sense amplifi- ers to access the next location while previously addressed data re- mains stable on the outputs.= = =>. Sag CY7C245A Fa CYPRESS Ss SEMICONDUCTOR Operating Modes (continued) System timing is simplified in that the on-chip edge triggered regis- ter allows the PROM clock to be derived directly from the system clock without introducing race conditions. The on-chip register timing requirements are similar to those of discrete registers avail- able in the market. The CY7C245A has an asynchronous initialize input (INIT). The initialize function is useful during power-up and time-out se- quences and can facilitate implementation of other sophisticated functions such as a built-in jump start address. When activated, the initialize control input causes the contents of a user-pro- grammed 2049th 8-bit word to be loaded into the on-chip register. Switching Waveforms!) tHa Ao Ato tses | tHEs tsEs THES cP tpwe tpwe Op ~ O7 mI tb Fl tpwi Erasure Characteristics Wavelengths of light less than 4000 Angstroms begin to erase the 7C24SA. For this reason, an opaque label should be placed over the window if the PROM is exposed tosunlight or fluorescent light- ing for extended periods of time. The recommended dose for erasure is ultraviolet light with a wave- length of 2537 Angstroms for a minimum dose (UV intensity mul- tiplied by exposure time) of 25 Wsec/cm?. For an ultraviolet lamp with a 12 mW/cm? power rating the exposure time would be ap- proximately 35 minutes. The 7C245A needs to be within 1 inch of the lamp during erasure. Permanent damage may result if the PROM is exposed to high-intensity UV light for an extended peri- od of time. 7258 Wsec/cm? is the recommended maximum dosage. Programming Information Programming support is available from Cypress as well as from a number of third-party software vendors. For detailed pro- gramming information, includinga listing ofsoftware packages, please see the PROM Programming Information located at the end of this section. Programming algorithms can be obtained from any Cypress representative. Each bit is programmable and the initialize function can be used to load any desired combination of 1s and 0s into the register. In the unprogrammed state, activating INIT will generate a register CLEAR (all outputs LOW). If all the bits of the initialize word are programmed, activating INIT performs a register PRESET (all outputs HIGH). Applying a LOW to the INIT input causes an immediate load of the programmed initialize word into the master and slave flip-flops of the register, independent of all other inputs, including the clock (CP). The initialize data will appear at the device outputs after the outputs are enabled by bringing the asynchronous enable (E) LOW. tsa C245A-7 Bit Map Data Programmer Address RAM Data Decimal Hex Contents 0 0 Data 2047 TFF Data 2048 800 Init Byte 2049 801 Control Byte Control Byte 00 Asynchronous output enable (default state) 01 Synchronous output enable PROMs =|ry ro 8 Dp fgzs 2 4 3 2,1, 282726 ~ 25 O Figure 1. Programming Pinouts Zs CY7C245A BF BSc.c Table 1. Mode Selection Pin Function! Read or Output Disable Ayo Aq | Ag Ap Ay Ag cP E, Es INIT 07 - Oo Mode | Other Ai Ag | As | AoAy | Ap | PGM | VEY | Vpp | D7Dpo Read Aio- Ag | Ax | Ao-Ai | Ao | Va/Vin |] Vit Vin O07 Oo Output Disable Aig Aq | Ag A2~ At Ag x Vin Vin High Z Initialize Ajo Ag | Ag Ag Ay Ag x Vit Vin Init. Byte Program Aio- Ag | A3 | AzAj | Ao VILP Vrnp Vpp D7 ~ Do Program Verify Aio Ag | Az | Az- Ai | Ao Vinp ViILP Vpp O07 - Oo Program Inhibit A1o Aq | Ag Az? Ay Ag Viep Vine Vpp High Z Intelligent Program Aigo Ag | Ag Ag Ay Ago VILP Vinp Vpp D7 Do Program Synchronous Enable Aigo Ag | Vip | Ao - Ar | Vpp VILp Vine Vpp High Z Program Initialization Byte Aio Ag | Virp | Ao Ai | Vpp VILp VinP Vpp D7 - Do Blank Check Zeros Aio~ Aq | Ag Ag Ay Ag Viep Vitp Vpp Zeros Note: X = dont care but not to exceed Vcc +5%. DIP LCC/PLCC (Opaque Only) Top View Top View Ato Vpp NC DO; Dg C245A~9grease CY7C245A o SEMICONDUCTOR Typical DC and AC Characteristics NORMALIZED SUPPLY CURRENT NORMALIZED SUPPLY CURRENT w CLOCK TO OUTPUT TIME ys. SUPPLY VOLTAGE vs. AMBIENT TEMPERATURE s vs. Vec 1.6 1.2 F 1.6 5 a Qi14 K 5 1.4 a 814 3 N12 a 212 Z 2 10 8 c = a 4. a 5 1.0 & o 1.0 = 2 0. ost 4 Ta = 25C 8 N 08 ra La 1 = fmax 2 Ta = 25C a 06 | 08 Z 06 40 45 50 55 60 55 25 126 9 40 45 50 55 6.0 SUPPLY VOLTAGE (V) AMBIENT TEMPERATURE (C) SUPPLY VOLTAGE (V) w CLOCK TO OUTPUT TIME NORMALIZED SET-UP TIME NORMALIZED SET-UP TIME S ys, TEMPERATURE vs. SUPPLY VOLTAGE vs. TEMPERATURE F 16 1.2 16 2 14 F 1.0 P S14 3 5 bi 2 & 12 bi NN a 12 o Oo 08 SJ ON 9 ry 5 o 1.0 N = 10 a | | =< fa S os zo 2 o8 z . 9 Ta = 25C , =z 06 0.4 | 06 Q -55 25 125 40 45 50 55 60 ~ 55 25 125 AMBIENT TEMPERATURE (C) SUPPLY VOLTAGE (V) AMBIENT TEMPERATURE (C) NORMALIZED SUPPLY CURRENT TYPICAL ACCESS TIME CHANGE OUTPUT SINK CURRENT ys. CLOCK PERIOD vs. OUTPUT LOADING ys. OUTPUT VOLTAGE 1.02 30.0 @ 175 E 1.00 Voc = 5.5V 25.0 ae 150 Ta = 25C 2 2 0.98 a W425 2 20.0 a G 0.96 $ B 100 q ~ 15.0 x =z 0.94 < Zz 75 z 10.0 E Voc = 5.0V 6 0.92 a 2 50 Ta = 25C 2 Ta = 25C Ee 5. A 0.90 8 Voc = 4.5V 3 25 0.88 0.0 0 0 25 50 75 100 0 200 400 600 800 1000 00 10 20 30 40 CLOCK PERIOD (ns) CAPACITANCE (pF) OUTPUT VOLTAGE (V) C245A-10= Sey oes CY7C245A ! SEMICONDUCTOR Ordering Information! Speed (ns) Icc Ordering tsa tco (mA) Code Note: 10. Most of these products are available in industrial temperature range. Contact a Cypress representative for specifications and product avail- ability.S85 Fors CY7C245A = SEMICONDUCTOR MILITARY SPECIFICATIONS SMD Cross Reference Group A Subgroup Testing SMD Cypress toe Number Suffix Number DC Characteristics 5962-88735 OIKX | CY7C245A45KMB Parameter Subgroups V 33 5962-88735 O1LX CY7C245A45DMB on 5962-88735 013X | CY7C245A45LMB VoL 1, 2,3 5962-88735 O2KX | CY7C245A35KMB Vint 1, 2,3 Vi. 12,3 5962-88735 02LX | CY7C245A35DMB lx 1, 2,3 5962-88735 023X CY7C245A35LMB loz 1, 2,3 5962-88735 O3KX | CY7C245A-35KMB Icc 1, 2,3 5962-88735 03LX | CY7C245A35DMB . . ous 5962-88735 033X CY7C245A-25LMB Switching Characteristics 5962-88735 O4KX | CY7C245A25KMB Parameter Subgroups 5962-88735 04LX CY7C245A25DMB tsa 7, 8,9, 10, 11 THA 7,8, 9, 10, 11 5962-88735 043K CY7C245A25LMB tco 7, 8,9, 10, 11 5962-87529 O1KX | CY7C245A45TMB 5962-87529 O1LX CY7C245A45WMB 5962-87529 013X CY7C245A~45QOMB 5962-87529 O2KX | CY7C245A-35TMB 5962-87529 02LX CY7C245A35WMB 5962-87529 023% CY7C245A350MB 5962 ~89815 O1LX CY7C245A-35WMB 5962 ~89815 O1KX =| CY7C245A-35TMB 5962-89815 013X CY7C245A35QOMB 5962-89815 02LX CY7C245A-25WMB 5962-89815 O2KX CY7C245A-25TMB 5962-89815 023X CY7C245A~-25QMB 5962-89815 03LX CY7C245A18WMB 5962-89815 03KX | CY7C245A18TMB 5962-89815 033X CY7C245A18QMB Document #: 3800074F PROMs ol