PCA9557PWRG4 - Texas Instruments

1. General description

The PCA9557 is a silicon CMOS circuit which provides parallel input/output expansion for

SMBus and I2C-bus applications. The PCA9557 consists of an 8-bit input port register,

8-bit output port register, and an I2C-bus/SMBus interface. It has low current consumption

and a high-impedance open-drain output pin, IO0.

The system master can enable the PCA9557’s I/O as either input or output by writing to

the conﬁguration register. The system master can also invert the PCA9557 inputs by

writing to the active HIGH polarity inversion register. Finally, the system master can reset

the PCA9557 in the event of a time-out by asserting a LOW in the reset input.

The power-on reset puts the registers in their default state and initializes the

I2C-bus/SMBus state machine. The RESET pin causes the same reset/initialization to

occur without de-powering the part.

2. Features

nLower voltage, higher performance migration path for the PCA9556

n8 general purpose input/output expander/collector

nInput/output conﬁguration register

nActive HIGH polarity inversion register

nI2C-bus and SMBus interface logic

nInternal power-on reset

nNoise ﬁlter on SCL/SDA inputs

nActive LOW reset input

n3 address pins allowing up to 8 devices on the I2C-bus/SMBus

nHigh-impedance open-drain on IO0

nNo glitch on power-up

nPower-up with all channels conﬁgured as inputs

nLow standby current

nOperating power supply voltage range of 2.3 V to 5.5 V

n5 V tolerant inputs/outputs

n0 kHz to 400 kHz clock frequency

nESD protection exceeds 2000 V HBM per JESD22-A114, 150 V MM per

JESD22-A115 and 1000 V CDM per JESD22-C101

nLatch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA

nThree packages offered: SO16, TSSOP16, HVQFN16

PCA9557

8-bit I2C-bus and SMBus I/O port with reset

Rev. 06 — 11 June 2008 Product data sheet

Product data sheet Rev. 06 — 11 June 2008 2 of 26

NXP Semiconductors PCA9557

8-bit I2C-bus and SMBus I/O port with reset

3. Ordering information

3.1 Ordering options

4. Block diagram

Table 1. Ordering information

Type number Package

Name Description Version

PCA9557D SO16 plastic small outline package; 16 leads;

body width 3.9 mm SOT109-1

PCA9557PW TSSOP16 plastic thin shrink small outline package; 16 leads;

body width 4.4 mm SOT403-1

PCA9557BS HVQFN16 plastic thermal enhanced very thin quad ﬂat package;

no leads; 16 terminals; body 4 ×4×0.85 mm SOT629-1

Table 2. Ordering options

Type number Topside mark Temperature range

PCA9557D PCA9557D Tamb =−40 °C to +85 °C

PCA9557PW PCA9557 Tamb =−40 °C to +85 °C

PCA9557BS 9557 Tamb =−40 °C to +85 °C

Fig 1. Block diagram of PCA9557

PCA9557

POWER-ON

RESET

002aad275

I2C-BUS/SMBus

CONTROL

INPUT

FILTER

SCL

SDA

VDD

INPUT/

OUTPUT

PORTS

IO0

VSS

8-bit

write pulse

read pulse

IO2

IO4

IO6

IO1

IO3

IO5

IO7

RESET

Product data sheet Rev. 06 — 11 June 2008 3 of 26

NXP Semiconductors PCA9557

8-bit I2C-bus and SMBus I/O port with reset

On power-up or reset, all registers return to default values.

Fig 2. Simpliﬁed schematic of IO0

IO0

output port

configuration

CK Q

data from

shift register

write configuration

pulse

output port

write pulse

polarity inversion

data from

shift register

write polarity

pulse

input port

read pulse

input port

polarity inversion

002aad277

data from

shift register

VSS

ESD protection

diode

Product data sheet Rev. 06 — 11 June 2008 4 of 26

NXP Semiconductors PCA9557

8-bit I2C-bus and SMBus I/O port with reset

On power-up or reset, all registers return to default values.

Fig 3. Simpliﬁed schematic of IO1 to IO7

VDD

IO1 to IO7

output port

configuration

CK Q

data from

shift register

write configuration

pulse

output port

write pulse

polarity inversion

data from

shift register

write polarity

pulse

input port

read pulse

input port

polarity inversion

002aad278

data from

shift register

VSS

ESD protection

diode

ESD protection

diode

Product data sheet Rev. 06 — 11 June 2008 5 of 26

NXP Semiconductors PCA9557

8-bit I2C-bus and SMBus I/O port with reset

5. Pinning information

5.1 Pinning

5.2 Pin description

Fig 4. Pin conﬁguration for SO16 Fig 5. Pin conﬁguration for TSSOP16

Fig 6. Pin conﬁguration for HVQFN16

PCA9557D

SCL VDD

SDA RESET

A0 IO7

A1 IO6

A2 IO5

IO0 IO4

IO1 IO3

VSS IO2

002aad272

IO7

IO6

IO5

IO4

IO3

IO2

SCL

SDA

IO0

IO1

VSS

PCA9557PW

002aad273

15 VDD

RESET

002aad274

PCA9557BS

Transparent top view

IO0 IO4

A2 IO5

A1 IO6

A0 IO7

IO1

VSS

IO2

IO3

SDA

SCL

VDD

RESET

4 9

3 10

2 11

1 12

terminal 1

index area

Table 3. Pin description

Symbol Pin Description

SO16, TSSOP16 HVQFN16

SCL 1 15 serial clock line

SDA 2 16 serial data line

A0 3 1 address input 0

A1 4 2 address input 1

A2 5 3 address input 2

IO0 6 4 input/output 0 (open-drain)

IO1 7 5 input/output 1

Product data sheet Rev. 06 — 11 June 2008 6 of 26

NXP Semiconductors PCA9557

8-bit I2C-bus and SMBus I/O port with reset

[1] HVQFN16 package die supply ground is connected to both the VSS pin and the exposed center pad. The

VSS pin must be connected to the supply ground for proper device operation. For enhanced thermal,

electrical, and board-level performance, the exposed pad needs to be soldered to the board using a

corresponding thermal pad on the board, and for proper heat conduction through the board thermal vias

need to be incorporated in the PCB in the thermal pad region.

6. System diagram

VSS 86

[1] supply ground

IO2 9 7 input/output 2

IO3 10 8 input/output 3

IO4 11 9 input/output 4

IO5 12 10 input/output 5

IO6 13 11 input/output 6

IO7 14 12 input/output 7

RESET 15 13 active LOW reset input

VDD 16 14 supply voltage

Table 3. Pin description

…continued

Symbol Pin Description

SO16, TSSOP16 HVQFN16

Fig 7. System diagram

002aad276

1.1 kΩ

RESET

1.6 kΩ

SCL

1.6 kΩ

SDA

1.1 kΩ

A2 or

1.1 kΩ

A1 or

1.1 kΩ

A0 or

I2C-BUS/SMBus

INTERFACE

LOGIC

INPUT

PORT

POLARITY

INVERSION

CONFIG.

OUTPUT

PORT 1.1 kΩ

IO0

IO7

IO6

IO5

IO4

IO3

IO2

IO1

Product data sheet Rev. 06 — 11 June 2008 7 of 26

NXP Semiconductors PCA9557

8-bit I2C-bus and SMBus I/O port with reset

7. Functional description

Refer to Figure 1 “Block diagram of PCA9557”.

7.1 Device address

Following a START condition the bus master must output the address of the slave it is

accessing. The address of the PCA9557 is shown in Figure 8. To conserve power, no

internal pull-up resistors are incorporated on the hardware selectable address pins and

they must be pulled HIGH or LOW.

The last bit of the slave address deﬁnes the operation to be performed. When set to

logic 1 a read is selected, while a logic 0 selects a write operation.

7.2 Control register

Following the successful acknowledgement of the slave address, the bus master will send

a byte to the PCA9557, which will be stored in the control register. This register can be

written and read via the I2C-bus.

Fig 8. PCA9557 device address

002aad279

0 0 1 1 A2 A1 A0 R/W

fixed

slave address

programmable

Fig 9. Control register

Table 4. Register deﬁnition

D1 D0 Name Access Description

0 0 Register 0 read-only Input port register

0 1 Register 1 read/write Output port register

1 0 Register 2 read/write Polarity inversion register

1 1 Register 3 read/write Conﬁguration register

002aad280

0 0 0 0 0 0 D1 D0

76543210bit:

Product data sheet Rev. 06 — 11 June 2008 8 of 26

NXP Semiconductors PCA9557

8-bit I2C-bus and SMBus I/O port with reset

7.3 Register descriptions

7.3.1 Register 0 - Input port register

This register is a read-only port. It reﬂects the incoming logic levels of the pins, regardless

of whether the pin is deﬁned as an input or an output by the Conﬁguration register. Writes

to this register have no effect.

7.3.2 Register 1 - Output port register

This register reﬂects the outgoing logic levels of the pins deﬁned as outputs by the

Conﬁguration register. Bit values in this register have no effect on pins deﬁned as inputs.

In turn, reads from this register reﬂect the value that is in the ﬂip-ﬂop controlling the output

selection, not the actual pin value.

7.3.3 Register 2 - Polarity inversion register

This register enables polarity inversion of pins deﬁned as inputs by the Conﬁguration

polarity is inverted. If a bit in this register is cleared (written with logic 0), the

corresponding port pin’s original polarity is retained.

7.3.4 Register 3 - Conﬁguration register

This register conﬁgures the directions of the I/O pins. If a bit in this register is set, the

corresponding port pin is enabled as an input with high-impedance output driver. If a bit in

this register is cleared, the corresponding port pin is enabled as an output.

Table 5. Register 0 - Input port register bit allocation

Bit 76543210

Symbol I7 I6 I5 I4 I3 I2 I1 I0

Table 6. Register 1 - Output port register bit allocation

Bit 76543210

Symbol O7 O6 O5 O4 O3 O2 O1 O0

Default 00000000

Table 7. Register 2 - Polarity inversion register bit allocation

Bit 76543210

Symbol N7 N6 N5 N4 N3 N2 N1 N0

Default 11110000

Table 8. Register 3 - Conﬁguration register bit allocation

Bit 76543210

Symbol C7 C6 C5 C4 C3 C2 C1 C0

Default 11111111

Product data sheet Rev. 06 — 11 June 2008 9 of 26

NXP Semiconductors PCA9557

8-bit I2C-bus and SMBus I/O port with reset

7.4 Power-on reset

When power is applied to VDD, an internal Power-On Reset (POR) holds the PCA9557 in

a reset condition until VDD has reached VPOR. At that point, the reset condition is released

and the PCA9557 registers and I2C-bus/SMBus state machine will initialize to their default

states. Thereafter, VDD must be lowered below 0.2 V to reset the device.

7.5 RESET input

A reset can be accomplished by holding the RESET pin LOW for a minimum of tw(rst). The

PCA9557 registers and SMBus/I2C-bus state machine will be held in their default state

until the RESET input is once again HIGH. This input requires a pull-up resistor to VDD if

no active connection is used.

8. Characteristics of the I2C-bus

The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two

lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be

connected to a positive supply via a pull-up resistor when connected to the output stages

of a device. Data transfer may be initiated only when the bus is not busy.

8.1 Bit transfer

One data bit is transferred during each clock pulse. The data on the SDA line must remain

stable during the HIGH period of the clock pulse as changes in the data line at this time

will be interpreted as control signals (see Figure 10).

8.1.1 START and STOP conditions

Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW

transition of the data line while the clock is HIGH is deﬁned as the START condition (S). A

LOW-to-HIGH transition of the data line while the clock is HIGH is deﬁned as the STOP

condition (P) (see Figure 11).

Fig 10. Bit transfer

mba607

data line

stable;

data valid

change

of data

allowed

SDA

SCL

Product data sheet Rev. 06 — 11 June 2008 10 of 26

NXP Semiconductors PCA9557

8-bit I2C-bus and SMBus I/O port with reset

8.2 System conﬁguration

A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The

device that controls the message is the ‘master’ and the devices which are controlled by

the master are the ‘slaves’ (see Figure 12).

8.3 Acknowledge

The number of data bytes transferred between the START and the STOP conditions from

transmitter to receiver is not limited. Each byte of eight bits is followed by one

acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter,

whereas the master generates an extra acknowledge related clock pulse.

A slave receiver which is addressed must generate an acknowledge after the reception of

each byte. Also a master must generate an acknowledge after the reception of each byte

that has been clocked out of the slave transmitter. The device that acknowledges has to

pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable

LOW during the HIGH period of the acknowledge related clock pulse; set-up and hold

times must be taken into account.

A master receiver must signal an end of data to the transmitter by not generating an

acknowledge on the last byte that has been clocked out of the slave. In this event, the

transmitter must leave the data line HIGH to enable the master to generate a STOP

condition.

Fig 11. Deﬁnition of START and STOP conditions

mba608

SDA

SCL P

STOP condition

SDA

SCL

START condition

Fig 12. System conﬁguration

002aaa966

MASTER

TRANSMITTER/

RECEIVER

SLAVE

RECEIVER SLAVE

TRANSMITTER/

RECEIVER

MASTER

TRANSMITTER MASTER

TRANSMITTER/

RECEIVER

SDA

SCL

I2C-BUS

MULTIPLEXER

SLAVE

Product data sheet Rev. 06 — 11 June 2008 11 of 26

NXP Semiconductors PCA9557

8-bit I2C-bus and SMBus I/O port with reset

8.4 Bus transactions

Data is transmitted to the PCA9557 registers using Write Byte transfers (see Figure 14

and Figure 15). Data is read from the PCA9557 registers using Read and Receive Byte

transfers (see Figure 16 and Figure 17).

Fig 13. Acknowledgement on the I2C-bus

002aaa987

START

condition

9821

clock pulse for

acknowledgement

not acknowledge

acknowledge

data output

by transmitter

data output

by receiver

SCL from master

Fig 14. Write to output port register

0 AS

slave address

START condition R/W acknowledge

from slave

002aad281

00000010

command byte

acknowledge

from slave

12345678SCL 9

SDA DATA 1 A

write to port

data out from port

tv(Q)

acknowledge

from slave

DATA 1 VALID

data to port

0 1 1 A2 A1 A00 P

STOP

condition

Fig 15. Write to I/O conﬁguration or polarity inversion registers

0 AS

slave address

START condition R/W acknowledge

from slave

002aad282

0000011/00

command byte

acknowledge

from slave

12345678SCL 9

SDA DATA A

acknowledge

from slave

data to register

0 1 1 A2 A1 A00 P

STOP

condition

Product data sheet Rev. 06 — 11 June 2008 12 of 26

NXP Semiconductors PCA9557

8-bit I2C-bus and SMBus I/O port with reset

Fig 16. Read from register

0 1 1 A2 A1 A0 0 AS0

START condition R/W

acknowledge

from slave

002aad283

acknowledge

from slave

SDA

A P

acknowledge

from master

data from register

DATA (first byte)

slave address

STOP

condition

(repeated)

START condition

(cont.)

(cont.) 1 A

R/W

acknowledge

from slave

slave address

at this moment master-transmitter becomes master-receiver

and slave-receiver becomes slave-transmitter

no acknowledge

from master

data from register

DATA (last byte)

command byte

0 1 1 A2 A1 A00

Remark: This ﬁgure assumes the command byte has previously been programmed with 00h.

Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the last acknowledge

phase is valid (output mode). Input data is lost.

Fig 17. Read input port register

0 1 1 A2 A1 A0 1 AS0

START condition R/W acknowledge

from slave

002aad284

acknowledge

from master

SDA NA

read from

port

data into

port

th(D)

data from port

no acknowledge

from master

data from port

DATA 4

slave address

DATA 1

STOP

condition

DATA 2 DATA 3 DATA 4

tsu(D)

DATA 1

Product data sheet Rev. 06 — 11 June 2008 13 of 26

NXP Semiconductors PCA9557

8-bit I2C-bus and SMBus I/O port with reset

9. Application design-in information

9.1 Minimizing IDD when the I/Os are used to control LEDs

When the I/Os are used to control LEDs, they are normally connected to VDD through a

resistor as shown in Figure 18. Since the LED acts as a diode, when the LED is off the

I/O VI is about 1.2 V less than VDD. The supply current, IDD, increases as VI becomes

lower than VDD.

Designs needing to minimize current consumption, such as battery power applications,

should consider maintaining the I/O pins greater than or equal to VDD when the LED is off.

Figure 19 shows a high value resistor in parallel with the LED. Figure 20 shows VDD less

than the LED supply voltage by at least 1.2 V. Both of these methods maintain the I/O VI

at or above VDD and prevents additional supply current consumption when the LED is off.

Device address conﬁgured as 0011 100x for this example.

IO0, IO2, IO3 conﬁgured as outputs.

IO1, IO4, IO5 conﬁgured as inputs.

IO6, IO7 are not used.

Fig 18. Typical application

PCA9557

IO0

IO1

SCL

SDA

VDD

002aad285

SCL

SDA IO2

IO3

VDD

VSS

MASTER

CONTROLLER

VSS

VDD (5 V)

620 Ω

SUBSYSTEM 1

(e.g., temp. sensor)

INT

SUBSYSTEM 2

(e.g., counter)

RESET

controlled switch

(e.g., CBT device)

enable

RESETRESET

2 kΩ2 kΩ

SUBSYSTEM 3

(e.g., alarm system)

ALARM

IO4

IO5

VDD

IO6

IO7

100 kΩ

(× 5)

1.8 kΩ1.8 kΩ

Product data sheet Rev. 06 — 11 June 2008 14 of 26

NXP Semiconductors PCA9557

8-bit I2C-bus and SMBus I/O port with reset

10. Limiting values

Fig 19. High value resistor in parallel with

the LED Fig 20. Device supplied by a lower voltage

002aac660

LED

VDD

IOn

100 kΩ

VDD

002aac661

LED

VDD

IOn

3.3 V 5 V

Table 9. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

VDD supply voltage −0.5 +6 V

VIinput voltage VSS −0.5 5.5 V

IIinput current - ±20 mA

IIHL(max) maximum allowed input current

through protection diode (IO1 to IO7) VI≥VDD or VI≤VSS -±400 µA

VI/O voltage on an input/output pin I/O as an input, except IO0 VSS −0.5 5.5 V

IO0 as an input VSS −0.5 5.5 V

II/O input/output current IO0 as an input - +400 µA

-−20 mA

IO(IOn) output current on pin IOn - ±50 mA

IDD supply current - 85 mA

ISS ground supply current - 100 mA

Ptot total power dissipation - 200 mW

Tstg storage temperature −65 +150 °C

Tamb ambient temperature operating −40 +85 °C

Product data sheet Rev. 06 — 11 June 2008 15 of 26

NXP Semiconductors PCA9557

8-bit I2C-bus and SMBus I/O port with reset

11. Static characteristics

[1] VDD must be lowered to 0.2 V in order to reset part.

[2] The total amount sunk by all I/Os must be limited to 100 mA and 25 mA per bit.

[3] The total current sourced by all I/Os must be limited to 85 mA and 20 mA per bit.

Table 10. Static characteristics

= 2.3 V to 5.5 V; V

=0V; T

amb

−

C to +85

C; unless otherwise speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

Supplies

VDD supply voltage 2.3 - 5.5 V

IDD supply current operating mode; VDD = 5.5 V;

no load; fSCL = 100 kHz -1925µA

IstbL LOW-level standby current standby mode; VDD = 5.5 V;

no load; VI=V

SS; fSCL = 0 kHz;

I/O = inputs

- 0.25 1 µA

IstbH HIGH-level standby current standby mode; VDD = 5.5 V;

no load; VI=V

DD; fSCL = 0 kHz;

I/O = inputs

- 0.25 1 µA

∆Istb additional standby current standby mode; VDD = 5.5 V;

every LED I/O at VI= 4.3 V;

fSCL = 0 kHz

- 0.8 1 mA

VPOR power-on reset voltage no load; VI=V

DD or VSS [1] - 1.65 2.1 V

Input SCL; input/output SDA

VIL LOW-level input voltage −0.5 - +0.3VDD V

VIH HIGH-level input voltage 0.7VDD - 5.5 V

IOL LOW-level output current VOL = 0.4 V 3 - - mA

ILleakage current VI=V

DD or VSS −1- +1µA

Ciinput capacitance VI=V

SS - 6 10 pF

I/Os

VIL LOW-level input voltage −0.5 - +0.8 V

VIH HIGH-level input voltage 2.0 - 5.5 V

IOL LOW-level output current [2] 810- mA

IOH HIGH-level output current except pin IO0; VOH = 2.4 V [3] 4- - mA

pin IO0; VOH = 4.6 V - - 1 µA

pin IO0; VOH = 3.3 V - - 1 µA

ILI input leakage current VDD = 5.5 V; VI=V

SS --−100 µA

Ciinput capacitance - 3.7 5 pF

Cooutput capacitance - 3.7 5 pF

Select inputs A0, A1, A2 and RESET

VIL LOW-level input voltage −0.5 - +0.8 V

VIH HIGH-level input voltage 2.0 - 5.5 V

ILI input leakage current −1- +1µA

Product data sheet Rev. 06 — 11 June 2008 16 of 26

NXP Semiconductors PCA9557

8-bit I2C-bus and SMBus I/O port with reset

12. Dynamic characteristics

[1] tVD;ACK = time for acknowledgement signal from SCL LOW to SDA (out) LOW.

[2] tVD;DAT = minimum time for SDA data out to be valid following SCL LOW.

[3] Cb= total capacitance of one bus line in pF.

Table 11. Dynamic characteristics

Symbol Parameter Conditions Standard-mode

I2C-bus Fast-mode I2C-bus Unit

Min Max Min Max

fSCL SCL clock frequency 0 100 0 400 kHz

tBUF bus free time between a STOP and

START condition 4.7 - 1.3 - µs

tHD;STA hold time (repeated) START condition 4.0 - 0.6 - µs

tSU;STA set-up time for a repeated START

condition 4.7 - 0.6 - µs

tSU;STO set-up time for STOP condition 4.0 - 0.6 - µs

tHD;DAT data hold time 0 - 0 - ns

tVD;ACK data valid acknowledge time [1] - 1 - 0.9 µs

tVD;DAT data valid time [2] - 1 - 0.9 ms

tSU;DAT data set-up time 250 - 100 - ns

tLOW LOW period of the SCL clock 4.7 - 1.3 - µs

tHIGH HIGH period of the SCL clock 4.0 - 0.6 - µs

tffall time of both SDA and SCL signals - 300 20 + 0.1Cb[3] 300 ns

trrise time of both SDA and SCL signals - 1000 20 + 0.1Cb[3] 300 ns

tSP pulse width of spikes that must be

suppressed by the input ﬁlter - 50 - 50 ns

Port timing

tv(Q) data output valid time pin IO0 - 250 - 250 ns

pins IO1 to IO7 - 200 - 200 ns

tsu(D) data input set-up time 0 - 0 - ns

th(D) data input hold time 200 - 200 - ns

Reset timing

tw(rst) reset pulse width 6 - 6 - ns

trec(rst) reset recovery time 0 - 0 - ns

trst reset time 400 - 400 - ns

Product data sheet Rev. 06 — 11 June 2008 17 of 26

NXP Semiconductors PCA9557

8-bit I2C-bus and SMBus I/O port with reset

Fig 21. Deﬁnition of timing on the I2C-bus

tSP

tBUF

tHD;STA PP S

tLOW

tHD;DAT

tHIGH tSU;DAT tSU;STA

tHD;STA

tSU;STO

SDA

SCL

002aaa986

Fig 22. Deﬁnition of RESET timing

SDA

SCL

002aad289

trst

50 %

30 %

50 % 50 %

50 %

trec(rst) tw(rst)

RESET

IOn I/O configured

as inputs

START

trst

ACK or read cycle

Product data sheet Rev. 06 — 11 June 2008 18 of 26

NXP Semiconductors PCA9557

8-bit I2C-bus and SMBus I/O port with reset

13. Package outline

Fig 23. Package outline SOT109-1 (SO16)

detail X

vMA

(A )

pin 1 index

UNIT A

max. A1A2A3bpcD

(1) E(1) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

inches

1.75 0.25

0.10 1.45

1.25 0.25 0.49

0.36 0.25

0.19 10.0

9.8 4.0

3.8 1.27 6.2

5.8 0.7

0.6 0.7

0.3 8

0.25 0.1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

1.0

0.4

SOT109-1 99-12-27

03-02-19

076E07 MS-012

0.069 0.010

0.004 0.057

0.049 0.01 0.019

0.014 0.0100

0.0075 0.39

0.38 0.16

0.15 0.05

1.05

0.041

0.244

0.228 0.028

0.020 0.028

0.012

0.01

0.25

0.01 0.004

0.039

0.016

0 2.5 5 mm

scale

SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1

Product data sheet Rev. 06 — 11 June 2008 19 of 26

NXP Semiconductors PCA9557

8-bit I2C-bus and SMBus I/O port with reset

Fig 24. Package outline SOT403-1 (TSSOP16)

UNIT A1A2A3bpcD

(1) E(2) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.15

0.05 0.95

0.80 0.30

0.19 0.2

0.1 5.1

4.9 4.5

4.3 0.65 6.6

6.2 0.4

0.3 0.40

0.06 8

0.13 0.10.21

DIMENSIONS (mm are the original dimensions)

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

0.75

0.50

SOT403-1 MO-153 99-12-27

03-02-18

0.25

16 9

detail X

(A )

vMA

0 2.5 5 mm

scale

TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1

max.

1.1

pin 1 index

Product data sheet Rev. 06 — 11 June 2008 20 of 26

NXP Semiconductors PCA9557

8-bit I2C-bus and SMBus I/O port with reset

Fig 25. Package outline SOT629-1 (HVQFN16)

terminal 1

index area

0.651

A1Eh

UNIT ye

0.2

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 4.1

3.9

2.25

1.95

4.1

3.9 2.25

1.95

0.38

0.23

0.05

0.00 0.05 0.1

DIMENSIONS (mm are the original dimensions)

SOT629-1 MO-220 - - -- - -

0.75

0.50

0.1

0.05

0 2.5 5 mm

scale

SOT629-1

HVQFN16: plastic thermal enhanced very thin quad flat package; no leads;

16 terminals; body 4 x 4 x 0.85 mm

A(1)

max.

AA1c

detail X

y1C

16 13

01-08-08

02-10-22

terminal 1

index area

1/2 e

E(1)

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

D(1)

Product data sheet Rev. 06 — 11 June 2008 21 of 26

NXP Semiconductors PCA9557

8-bit I2C-bus and SMBus I/O port with reset

14. Handling information

Inputs and outputs are protected against electrostatic discharge in normal handling.

However, to be completely safe you must take normal precautions appropriate to handling

integrated circuits.

15. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note

AN10365 “Surface mount reﬂow

soldering description”

15.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for ﬁne pitch SMDs. Reﬂow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

15.2 Wave and reﬂow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

•Through-hole components

•Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reﬂow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature proﬁle. Leaded packages,

packages with solder balls, and leadless packages are all reﬂow solderable.

Key characteristics in both wave and reﬂow soldering are:

•Board speciﬁcations, including the board ﬁnish, solder masks and vias

•Package footprints, including solder thieves and orientation

•The moisture sensitivity level of the packages

•Package placement

•Inspection and repair

•Lead-free soldering versus SnPb soldering

15.3 Wave soldering

Key characteristics in wave soldering are:

Product data sheet Rev. 06 — 11 June 2008 22 of 26

NXP Semiconductors PCA9557

8-bit I2C-bus and SMBus I/O port with reset

•Process issues, such as application of adhesive and ﬂux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

•Solder bath speciﬁcations, including temperature and impurities

15.4 Reﬂow soldering

Key characteristics in reﬂow soldering are:

•Lead-free versus SnPb soldering; note that a lead-free reﬂow process usually leads to

higher minimum peak temperatures (see Figure 26) than a SnPb process, thus

reducing the process window

•Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

•Reﬂow temperature proﬁle; this proﬁle includes preheat, reﬂow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enough for the solder to make reliable solder joints (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classiﬁed in accordance with

Table 12 and 13

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reﬂow

soldering, see Figure 26.

Table 12. SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm3)

< 350 ≥ 350

< 2.5 235 220

≥ 2.5 220 220

Table 13. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm3)

< 350 350 to 2000 > 2000

< 1.6 260 260 260

1.6 to 2.5 260 250 245

> 2.5 250 245 245

Product data sheet Rev. 06 — 11 June 2008 23 of 26

NXP Semiconductors PCA9557

8-bit I2C-bus and SMBus I/O port with reset

For further information on temperature proﬁles, refer to Application Note

AN10365

“Surface mount reﬂow soldering description”

16. Abbreviations

MSL: Moisture Sensitivity Level

Fig 26. Temperature proﬁles for large and small components

001aac844

temperature

time

minimum peak temperature

= minimum soldering temperature

maximum peak temperature

= MSL limit, damage level

peak

temperature

Table 14. Abbreviations

Acronym Description

CBT Cross Bar Technology

CDM Charged-Device Model

CMOS Complementary Metal-Oxide Semiconductor

ESD ElectroStatic Discharge

HBM Human Body Model

I2C-bus Inter-Integrated Circuit bus

I/O Input/Output

LED Light-Emitting Diode

MM Machine Model

PCB Printed-Circuit Board

POR Power-On Reset

SMBus System Management Bus

Product data sheet Rev. 06 — 11 June 2008 24 of 26

NXP Semiconductors PCA9557

8-bit I2C-bus and SMBus I/O port with reset

17. Revision history

Table 15. Revision history

Document ID Release date Data sheet status Change notice Supersedes

PCA9557_6 20080611 Product data sheet - PCA9557_5

Modiﬁcations: •Section 2 “Features”, 17th bullet item: changed from “200 V MM” to “150 V MM”

•Table 11 “Dynamic characteristics”, sub-section “Reset timing”: changed Min value for tw(rst) from

“4 ns” to “6 ns” (for both Standard-mode and Fast-mode)

•Updated soldering information

PCA9557_5 20070912 Product data sheet - PCA9557_4

PCA9557_4

(9397 750 13336) 20041124 Product data sheet - PCA9557_3

PCA9557_3

(9397 750 10872) 20021213 Product data ECN 853-2308 29160

of 06 Nov 2002 PCA9557_2

PCA9557_2

(9397 750 09819) 20020513 Product data ECN 853-2308 28188

of 13 May 2002 PCA9557_1

PCA9557_1 20011212 Product data ECN 853-2308 27449

of 12 Dec 2001 -

Product data sheet Rev. 06 — 11 June 2008 25 of 26

NXP Semiconductors PCA9557

8-bit I2C-bus and SMBus I/O port with reset

18. Legal information

18.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Deﬁnitions”.

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

18.2 Deﬁnitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

18.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

18.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

I2C-bus — logo is a trademark of NXP B.V.

19. Contact information

For more information, please visit: http://www.nxp.com

For sales ofﬁce addresses, please send an email to: salesaddresses@nxp.com

Document status[1][2] Product status[3] Deﬁnition

Objective [short] data sheet Development This document contains data from the objective speciﬁcation for product development.

Preliminary [short] data sheet Qualiﬁcation This document contains data from the preliminary speciﬁcation.

Product [short] data sheet Production This document contains the product speciﬁcation.

NXP Semiconductors PCA9557

8-bit I2C-bus and SMBus I/O port with reset

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 11 June 2008

Document identifier: PCA9557

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

20. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2

3.1 Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 2

4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2

5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 5

5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5

6 System diagram . . . . . . . . . . . . . . . . . . . . . . . . . 6

7 Functional description . . . . . . . . . . . . . . . . . . . 7

7.1 Device address. . . . . . . . . . . . . . . . . . . . . . . . . 7

7.2 Control register. . . . . . . . . . . . . . . . . . . . . . . . . 7

7.3 Register descriptions . . . . . . . . . . . . . . . . . . . . 8

7.3.1 Register 0 - Input port register . . . . . . . . . . . . . 8

7.3.2 Register 1 - Output port register. . . . . . . . . . . . 8

7.3.3 Register 2 - Polarity inversion register . . . . . . . 8

7.3.4 Register 3 - Conﬁguration register . . . . . . . . . . 8

7.4 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 9

7.5 RESET input. . . . . . . . . . . . . . . . . . . . . . . . . . . 9

8 Characteristics of the I2C-bus. . . . . . . . . . . . . . 9

8.1 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

8.1.1 START and STOP conditions . . . . . . . . . . . . . . 9

8.2 System conﬁguration . . . . . . . . . . . . . . . . . . . 10

8.3 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 10

8.4 Bus transactions. . . . . . . . . . . . . . . . . . . . . . . 11

9 Application design-in information . . . . . . . . . 13

9.1 Minimizing IDD when the I/Os are used to

control LEDs. . . . . . . . . . . . . . . . . . . . . . . . . . 13

10 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 14

11 Static characteristics. . . . . . . . . . . . . . . . . . . . 15

12 Dynamic characteristics . . . . . . . . . . . . . . . . . 16

13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 18

14 Handling information. . . . . . . . . . . . . . . . . . . . 21

15 Soldering of SMD packages . . . . . . . . . . . . . . 21

15.1 Introduction to soldering . . . . . . . . . . . . . . . . . 21

15.2 Wave and reﬂow soldering . . . . . . . . . . . . . . . 21

15.3 Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 21

15.4 Reﬂow soldering. . . . . . . . . . . . . . . . . . . . . . . 22

16 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 23

17 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 24

18 Legal information. . . . . . . . . . . . . . . . . . . . . . . 25

18.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 25

18.2 Deﬁnitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

18.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 25

18.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 25

19 Contact information . . . . . . . . . . . . . . . . . . . . 25

20 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26