2015-2017 Microchip Technology Inc. DS00001854E-page 1
Highlights
• USB Hub Feature Controller IC with 4 USB 3.1
Gen 1 / USB 2.0 downstream ports
• USB-IF Battery Charger revision 1.2 support on
up & downstream ports (DCP, CDP, SDP)
•FlexConnect: Downstream port able to swap with
upstream port, allowing master capable devices
to control other devices on the hub
• USB to I2C/UART/SPI/GPIO bridge endpoint sup-
port
• USB Link Power Management (LPM) support
• Enhanced OEM configuration options available
through either OTP or SPI ROM
• Available in 64-pin (9 x 9 mm) VQFN lead-free,
RoHS compliant package
• Commercial and industrial grade temperature
support
• Configuration Straps: Predefined configuration of
system level functions including GPIOs
Target Applications
• Standalone USB Hubs
• Laptop Docks
• PC Motherboards
• PC Monitor Docks
• Multi-function USB 3.1 Gen 1 Peripherals
Key Benefits
• USB 3.1 Gen 1 compliant 5 Gbps, 480 Mbps,
12 Mbps and 1.5 Mbps operation
- 5 V tolerant USB 2.0 pins
- 1.32 V tolerant USB 3.1 Gen 1 pins
- Integrated termination & pull-up/pull-down resistors
• Supports per port battery charging of most popu-
lar battery powered devices
- USB-IF Battery Charging rev. 1.2 support
(DCP, CDP, SDP)
-Apple
portable product charger emulation
- Chinese YD/T 1591-2006 charger emulation
- Chinese YD/T 1591-2009 charger emulation
- European Union universal mobile charger support
- Support for Microchip USC100x family of battery
charging controllers
- Supports additional portable devices
• Smart port controller operation
- Firmware handling of companion port controllers
• On-chip microcontroller
- Manages I/Os, VBUS, and other signals
• 8 KB RAM, 64 KB ROM
• 8 KB One Time Programmable (OTP) ROM
- Includes on-chip charge pump
• Configuration programming via OTP ROM, SPI
ROM, or SMBus
•PortSwap
- Configurable differential intro-pair signal swapping
•PHYBoost
™
- Programmable USB transceiver drive strength for
recovering signal integrity
• VariSense™
- Programmable USB receiver sensitivity
• Compatible with Microsoft Windows 8, 7, XP,
Apple OS X 10.4+, and Linux hub drivers
• Optimized for low-power operation and
low thermal dissipation
• Package
- 64-pin VQFN (9 x 9 mm)
• Environmental
- 3 kV HBM JESD22-A114F ESD protection
- Commercial temperature range (0°C to +70°C)
- Industrial temperature range (-40°C to +85°C)
USB5734
4-Port SS/HS USB Controller Hub
USB5734
DS00001854E-page 2 2015-2017 Microchip Technology Inc.
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2015-2017 Microchip Technology Inc. DS00001854E-page 3
USB5734
1.0 Preface ............................................................................................................................................................................................ 4
2.0 Introduction ..................................................................................................................................................................................... 6
3.0 Pin Description and Configuration .................................................................................................................................................. 8
4.0 Device Connections ...................................................................................................................................................................... 26
5.0 Modes of Operation ...................................................................................................................................................................... 28
6.0 Device Configuration ..................................................................................................................................................................... 31
7.0 Device Interfaces .......................................................................................................................................................................... 33
8.0 Functional Descriptions ................................................................................................................................................................. 35
9.0 Operational Characteristics ........................................................................................................................................................... 41
10.0 Package Information ................................................................................................................................................................... 50
USB5734
DS00001854E-page 4 2015-2017 Microchip Technology Inc.
1.0 PREFACE
1.1 General Terms
TABLE 1-1: GENERAL TERMS
Term Description
ADC Analog-to-Digital Converter
Byte 8 bits
CDC Communication Device Class
CSR Control and Status Registers
DWORD 32 bits
EOP End of Packet
EP Endpoint
FIFO First In First Out buffer
FS Full-Speed
FSM Finite State Machine
GPIO General Purpose I/O
HS Hi-Speed
HSOS High Speed Over Sampling
Hub Feature Controller The Hub Feature Controller, sometimes called a Hub Controller for short is the internal
processor used to enable the unique features of the USB Controller Hub. This is not to
be confused with the USB Hub Controller that is used to communicate the hub status
back to the Host during a USB session.
I2CInter-Integrated Circuit
LS Low-Speed
lsb Least Significant Bit
LSB Least Significant Byte
msb Most Significant Bit
MSB Most Significant Byte
N/A Not Applicable
NC No Connect
OTP One Time Programmable
PCB Printed Circuit Board
PCS Physical Coding Sublayer
PHY Physical Layer
PLL Phase Lock Loop
RESERVED Refers to a reserved bit field or address. Unless otherwise noted, reserved bits must
always be zero for write operations. Unless otherwise noted, values are not guaran-
teed when reading reserved bits. Unless otherwise noted, do not read or write to
reserved addresses.
SDK Software Development Kit
SMBus System Management Bus
UUID Universally Unique IDentifier
WORD 16 bits
2015-2017 Microchip Technology Inc. DS00001854E-page 5
USB5734
1.2 Reference Documents
1. UNICODE UTF-16LE For String Descriptors USB Engineering Change Notice, December 29th, 2004, http://
www.usb.org
2. Universal Serial Bus Revisi on 3.1 Specification, http://www.usb.org
3. Battery Charging Specification, Revision 1.2, Dec. 07, 2010, http://www.usb.org
4. I2C-Bus Specification, Version 1.1, http://www.nxp.com
5. System Management Bus Specification, Version 1.0, http://smbus.org/specs
USB5734
DS00001854E-page 6 2015-2017 Microchip Technology Inc.
2.0 INTRODUCTION
2.1 General Description
The Microchip USB5734 hub is low-power, OEM configurable, USB 3.1 Gen 1 hub feature controller with 4 downstream
ports and advanced features for embedded USB applications. The USB5734 is fully compliant with the Universal Serial
Bus Revision 3.1 Specification and USB 2.0 Link Power Management Addendum. The USB5734 supports 5 Gbps
SuperSpeed (SS), 480 Mbps Hi-Speed (HS), 12 Mbps Full-Speed (FS), and 1.5 Mbps Low-Speed (LS) USB down-
stream devices on all enabled downstream ports.
The USB5734 supports the legacy USB speeds (HS/FS/LS) through a dedicated USB 2.0 hub feature controller that is
the culmination of five generations of Microchip hub feature controller design and experience with proven reliability,
interoperability, and device compatibility. The SuperSpeed hub feature controller operates in parallel with the USB 2.0
controller, decoupling the 5 Gbps SS data transfers from bottlenecks due to the slower USB 2.0 traffic.
The USB5734 enables OEMs to configure their system using “Configuration Straps.” These straps simplify the config-
uration process assigning default values to USB3.1 Gen 1 ports and GPIOs OEMs can disable ports, enable battery
charging and define GPIO functions as default assignments on power up removing the need for OTP or external SPI
ROM.
The USB5734 supports downstream battery charging. The USB5734 integrated battery charger detection circuitry sup-
ports the USB-IF Battery Charging (BC1.2) detection method and most Apple devices. The USB5734 provides the bat-
tery charging handshake and supports the following USB-IF BC1.2 charging profiles:
• DCP: Dedicated Charging Port (Power brick with no data)
• CDP: Charging Downstream Port (1.5A with data)
• SDP: Standard Downstream Port (0.5A with data)
• Custom profiles loaded via SMBus or OTP
The USB5734 provides an additional USB endpoint dedicated for use as a USB to I2C/UART/SPI/GPIO interface, allow-
ing external circuits or devices to be monitored, controlled, or configured via the USB interface. Additionally, the
USB5734 includes many powerful and unique features such as:
FlexConnect, which provides flexible connectivity options. One of the USB5734’s downstream ports can be reconfig-
ured to become the upstream port, allowing master capable devices to control other devices on the hub.
PortSwap, which adds per-port programmability to USB differential-pair pin locations. PortSwap allows direct alignment
of USB signals (D+/D-) to connectors to avoid uneven trace length or crossing of the USB differential signals on the
PCB.
PHYBoost, which provides programmable levels of Hi-Speed USB signal drive strength
in the downstream port transceivers. PHYBoost attempts to restore USB signal integrity
in a compromised system environment. The graphic on the right shows an example of
Hi-Speed USB eye diagrams before and after PHYBoost signal integrity restoration. in
a compromised system environment
VariSense, which controls the USB receiver sensitivity enabling programmable levels of USB signal receive sensitivity.
This capability allows operation in a sub-optimal system environment, such as when a captive USB cable is used.
The USB5734 can be configured for operation through internal default settings. Custom OEM configurations are sup-
ported through external SPI ROM or OTP ROM. All port control signal pins are under firmware control in order to allow
for maximum operational flexibility, and are available as GPIOs for customer specific use.
The USB5734 is available in commercial (0°C to +70°C) and industrial (-40°C to +85°C) temperature ranges. An internal
block diagram of the USB5734 is shown in Figure 2-1.
2015-2017 Microchip Technology Inc. DS00001854E-page 7
USB5734
FIGURE 2-1: INTERNAL BLOCK DIAGRAM
USB5734
DS00001854E-page 8 2015-2017 Microchip Technology Inc.
3.0 PIN DESCRIPTION AND CONFIGURATION
3.1 Pin Assignments
Note 1: Configuration straps are identified by an underlined symbol name. Signals that function as configurations
traps must be augmented with an external resistor when connected to a load. Refer to Section 3.4, "Config-
uration Straps and Programmable Functions" for additional information.
FIGURE 3-1: 64-VQFN PIN ASSIGNMENTS
Note: Exposed pad (VSS) on bottom of package must be connected to ground with a via field.
(Connect exposed pad to ground with a via field)
VSS
USB5734
64-VQFN
(Top View)
5
6
7
8
9
10
11
12
44
43
42
41
40
39
38
37
USB3DN_RXDM1
USB3DN_RXDP1
USB2DN_DP2/PRT_DIS_P2
USB2DN_DM2/PRT_DIS_M2
USB3DN_TXDP2
USB3DN_TXDM2
VDD12
USB3DN_RXDP2
PROG_FUNC4
SPI_CE_N/GPIO7/CFG_NON_REM
SPI_DO/UART_TX/GPIO5/I2C_SLV_CFG1
PRT_CTL1
PRT_CTL3
VDD12
SPI_CLK/UART_RX/GPIO4/I2C_SLV_CFG0
SPI_DI/GPIO9/CFG_BC_EN
3
4
13
14
36
35
46
45
VDD12
USB3DN_TXDM1
USB3DN_TXDP1
USB2DN_DM1/PRT_DIS_M1
VBUS_DET/GPIO16
PROG_FUNC3
PROG_FUNC2
PRT_CTL2
1
2
USB2DN_DP1/PRT_DIS_P1
CFG_STRAP
16
15
PROG_FUNC7
USB3DN_RXDM2 34
33 VDD33
PRT_CTL4/GANG_PWR
48
PROG_FUNC5
47
RESET_N
2015-2017 Microchip Technology Inc. DS00001854E-page 9
USB5734
Table 3-1 details the package pin assignments in table format.
TABLE 3-1: 64-VQFN PIN ASSIGNMENTS
Pin
Number Pin Name Pin
Number Pin Name
1CFG_STRAP 33 VDD33
2USB2DN_DP1/PRT_DIS_P1 34 PRT_CTL4/GANG_PWR
3USB2DN_DM1/PRT_DIS_M1 35 VDD12
4USB3DN_TXDP1 36 PRT_CTL3
5USB3DN_TXDM1 37 PRT_CTL2
6VDD12 38 PRT_CTL1
7USB3DN_RXDP1 39 PROG_FUNC2
8USB3DN_RXDM1 40 PROG_FUNC3
9USB2DN_DP2/PRT_DIS_P2 41 VBUS_DET/GPIO16
10 USB2DN_DM2/PRT_DIS_M2 42 SPI_CLK/UART_RX/GPIO4/I2C_SLV_CFG0
11 USB3DN_TXDP2 43 SPI_DO/UART_TX/GPIO5/I2C_SLV_CFG1
12 USB3DN_TXDM2 44 SPI_DI/GPIO9/CFG_BC_EN
13 VDD12 45 SPI_CE_N/GPIO7/CFG_NON_REM
14 USB3DN_RXDP2 46 PROG_FUNC4
15 USB3DN_RXDM2 47 PROG_FUNC5
16 PROG_FUNC7 48 RESET_N
17 VDD12 49 PROG_FUNC6
18 VDD33 50 PROG_FUNC1
19 USB2DN_DP3/PRT_DIS_P3 51 VDD12
20 USB2DN_DM3/PRT_DIS_M3 52 VDD33
21 USB3DN_TXDP3 53 USB2UP_DP
22 USB3DN_TXDM3 54 USB2UP_DM
23 VDD12 55 USB3UP_TXDP
24 USB3DN_RXDP3 56 USB3UP_TXDM
25 USB3DN_RXDM3 57 VDD12
26 USB2DN_DP4/PRT_DIS_P4 58 USB3UP_RXDP
27 USB2DN_DM4/PRT_DIS_M4 59 USB3UP_RXDM
28 USB3DN_TXDP4 60 ATEST
29 USB3DN_TXDM4 61 XTALO
30 VDD12 62 XTALI/CLK_IN
31 USB3DN_RXDP4 63 VDD33
32 USB3DN_RXDM4 64 RBIAS
USB5734
DS00001854E-page 10 2015-2017 Microchip Technology Inc.
3.2 Pin Descriptions
This section contains descriptions of the various USB5734 pins. This pin descriptions have been broken into functional
groups as follows:
•USB 3.1 Gen 1 Pin Descriptions
•USB 2.0 Pin Descriptions
•USB Port Control Pin Descriptions
•SPI/UART Pin Descriptions
•Programmable Function Pin Descriptions
•Miscellaneous Pin Descriptions
•Power and Ground Pin Descriptions
The “_N” symbol in the signal name indicates that the active, or asserted, state occurs when the signal is at a low voltage
level. For example, RESET_N indicates that the reset signal is active low. When “_N” is not present after the signal
name, the signal is asserted when at the high voltage level.
The terms assertion and negation are used exclusively. This is done to avoid confusion when working with a mixture of
“active low” and “Active high” signals. The term assert, or assertion, indicates that a signal is active, independent of
whether that level is represented by a high or low voltage. The term negate, or negation, indicates that a signal is inac-
tive.
Note: The buffer type for each signal is indicated in the “Buffer Type” column of the pin description tables. A
description of the buffer types is provided in Section 3.3, "Buffer Types," on page 15.
For additional information on configuration straps and configurable pins, refer to Section 3.4, "Configuration
Straps and Programmable Functions".
TABLE 3-2: USB 3.1 GEN 1 PIN DESCRIPTIONS
Num
Pins Symbol Buffer
Type Description
1USB3UP_TXDP IO-U USB 3.1 Gen 1 upstream SuperSpeed transmit data plus.
1USB3UP_TXDM IO-U USB 3.1 Gen 1 upstream SuperSpeed transmit data minus.
1USB3UP_RXDP IO-U USB 3.1 Gen 1 upstream SuperSpeed receive data plus.
1USB3UP_RXDM IO-U USB 3.1 Gen 1 upstream SuperSpeed receive data minus.
4USBDN_TXDP[4:1] IO-U USB 3.1 Gen 1 downstream ports 4-1 SuperSpeed transmit data plus.
4USBDN_TXDM[4:1] IO-U USB 3.1 Gen 1 downstream ports 4-1 SuperSpeed transmit data
minus.
4USBDN_RXDP[4:1] IO-U USB 3.1 Gen 1 downstream ports 4-1 SuperSpeed receive data plus.
4USBDN_RXDM[4:1] IO-U USB 3.1 Gen 1 downstream ports 4-1 SuperSpeed receive data
minus.
TABLE 3-3: USB 2.0 PIN DESCRIPTIONS
Num
Pins Symbol Buffer
Type Description
1USB2UP_DP IO-U USB 2.0 upstream data plus (D+).
1USB2UP_DM IO-U USB 2.0 upstream data minus (D-).
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USB5734
Note 2: Configuration strap values are latched on Power-On Reset (POR) and the rising edge of RESET_N (external
chip reset). Configuration straps are identified by an underlined symbol name. Signals that function as con-
figurations traps must be augmented with an external resistor when connected to a load. Refer to Section
3.4, "Configuration Straps and Programmable Functions" for additional information.
4
USB2DN_DP[4:1] IO-U USB 2.0 downstream ports 4-1 data plus (D+).
PRT_DIS_P[4:1] I
Port 4-1 D+ Disable Configuration Strap.
These configuration straps are used in conjunction with the corre-
sponding PRT_DIS_M[4:1] straps to disable the related port (4-1).
Refer to Section 3.4.2, "Port Disable Configuration (PRT_DIS_P[4:1] /
PRT_DIS_M[4:1])" for more information.
See Note 2.
4
USB2DN_DM[4:1] IO-U USB 2.0 downstream ports 4-1 data minus (D-).
PRT_DIS_M[4:1] I
Port 4-1 D- Disable Configuration Strap.
These configuration straps are used in conjunction with the corre-
sponding PRT_DIS_P[4:1] straps to disable the related port (4-1).
Refer to Section 3.4.2, "Port Disable Configuration (PRT_DIS_P[4:1] /
PRT_DIS_M[4:1])" for more information.
See Note 2.
1VBUS_DET IS
This signal detects the state of the upstream bus power.
When designing a detachable hub, this pin must be connected to the
VBUS power pin of the upstream USB port through a resistor divider
(50 k by 100 k) to provide 3.3 V.
For self-powered applications with a permanently attached host, this
pin must be connected to either 3.3 V or 5.0 V through a resistor
divider to provide 3.3 V.
In embedded applications, VBUS_DET may be controlled (toggled)
when the host desires to renegotiate a connection without requiring a
full reset of the device.
GPIO16 I/O6 General purpose input/output 16.
TABLE 3-4: USB PORT CONTROL PIN DESCRIPTIONS
Num
Pins Symbol Buffer
Type Description
1PRT_CTL1 I
(PU)
Port 1 Power Enable / Overcurrent Sense.
As an output, this signal is an active high control signal used to enable
power to the downstream port 1. As an input, this signal indicates an
overcurrent condition from an external current monitor on USB port 1.
1PRT_CTL2 I
(PU)
Port 2 Power Enable / Overcurrent Sense.
As an output, this signal is an active high control signal used to enable
power to the downstream port 2. As an input, this signal indicates an
overcurrent condition from an external current monitor on USB port 2.
TABLE 3-3: USB 2.0 PIN DESCRIPTIONS (CONTINUED)
Num
Pins Symbol Buffer
Type Description
USB5734
DS00001854E-page 12 2015-2017 Microchip Technology Inc.
1PRT_CTL3 I
(PU)
Port 3 Power Enable / Overcurrent Sense.
As an output, this signal is an active high control signal used to enable
power to the downstream port 3. As an input, this signal indicates an
overcurrent condition from an external current monitor on USB port 3.
1
PRT_CTL4 I
(PU)
Port 4 Power Enable / Overcurrent Sense.
As an output, this signal is an active high control signal used to enable
power to the downstream port 4. As an input, this signal indicates an
overcurrent condition from an external current monitor on USB port 4.
GANG_PWR I
(PU)
When pulled high enables gang mode. Gang power pin when used in
gang mode.
TABLE 3-5: SPI/UART PIN DESCRIPTIONS
Num
Pins Symbol Buffer
Type Description
1
SPI_CE_N O12 Active low SPI chip enable output.
GPIO7 I/O12 General purpose input/output 7.
CFG_NON_REM I
Non-Removable Port Configuration Strap.
This configuration strap is used to configure the number of non-
removable ports. Refer to Section 3.4.3, "Non-Removable Port Con-
figuration (CFG_NON_REM)" for more information.
See Note 3.
1
SPI_CLK O6 SPI clock output to the serial ROM, when configured for SPI opera-
tion.
UART_RX I UART receive pin, when configured for UART operation.
GPIO4 I/O6 General purpose input/output 4.
I2C_SLV_CFG0 I
I2C Slave 0 Configuration Strap.
This configuration strap is used to configure I2C controller 0. Refer to
Section 3.4.1, "SPI/SMBus/I2C/UART Configuration
(I2C_SLV_CFG[1:0])" for additional information.
1
SPI_DO O6 SPI data output, when configured for SPI operation.
UART_TX O12 UART transmit pin, when configured for UART operation.
GPIO5 I/O6 General purpose input/output 5.
I2C_SLV_CFG1 I
I2C Slave 1 Configuration Strap.
This configuration strap is used to configure I2C controller 1. Refer to
Section 3.4.1, "SPI/SMBus/I2C/UART Configuration
(I2C_SLV_CFG[1:0])" for additional information.
TABLE 3-4: USB PORT CONTROL PIN DESCRIPTIONS (CONTINUED)
Num
Pins Symbol Buffer
Type Description
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USB5734
Note 3: Configuration strap values are latched on Power-On Reset (POR) and the rising edge of RESET_N (external
chip reset). Configuration straps are identified by an underlined symbol name. Signals that function as con-
figurations traps must be augmented with an external resistor when connected to a load. Refer to Section
3.4, "Configuration Straps and Programmable Functions" for additional information.
Note 4: The PROG_FUNC2 buffer type is I/O6. The PROG_FUNC7 buffer type is I/O10. All other PROG_FUNCx
pins have a buffer type of I/O12.
Note 5: Configuration strap values are latched on Power-On Reset (POR) and the rising edge of RESET_N (external
chip reset). Configuration straps are identified by an underlined symbol name. Signals that function as con-
figurations traps must be augmented with an external resistor when connected to a load. Refer to Section
3.4, "Configuration Straps and Programmable Functions" for additional information.
1
SPI_DI IS SPI data input, when configured for SPI operation.
GPIO9 I/O12 General purpose input/output 9.
CFG_BC_EN I
Battery Charging Configuration Strap.
This configuration strap is used to enable battery charging. Refer to
Section 3.4.4, "Battery Charging Configuration (CFG_BC_EN)" for
more information.
See Note 3.
TABLE 3-6: PROGRAMMABLE FUNCTION PIN DESCRIPTIONS
Num
Pins Symbol Buffer
Type Description
7PROG_FUNC[7:1] Note 4
Programmable function pins 7-1.
The functions of these pins are configured via the CFG_STRAP pin.
Refer to Section 3.4.5, "Device Mode / PROG_FUNC[7:1] Configura-
tion (CFG_STRAP)" for additional information.
1CFG_STRAP I
Device Mode Configuration Strap.
This configuration strap is used to set the device mode. Refer to Sec-
tion 3.4.5, "Device Mode / PROG_FUNC[7:1] Configuration
(CFG_STRAP)" for more information.
See Note 5.
TABLE 3-5: SPI/UART PIN DESCRIPTIONS (CONTINUED)
Num
Pins Symbol Buffer
Type Description
USB5734
DS00001854E-page 14 2015-2017 Microchip Technology Inc.
TABLE 3-7: MISCELLANEOUS PIN DESCRIPTIONS
Num
Pins Symbol Buffer
Type Description
1RESET_N IS The RESET_N pin puts the device into Reset Mode, as the name of
the pin and function then align.
1
XTALI ICLK External 25 MHz crystal input
CLK_IN ICLK
External reference clock input.
The device may alternatively be driven by a single-ended clock oscil-
lator. When this method is used, XTALO should be left unconnected.
1XTALO OCLK External 25 MHz crystal output
1RBIAS AI A 12.0 k (+/- 1%) resistor is attached from ground to this pin to set
the transceiver’s internal bias settings.
1ATEST AI
Analog test pin.
This signal is used for test purposes and must always be connected to
ground.
TABLE 3-8: POWER AND GROUND PIN DESCRIPTIONS
Num
Pins Symbol Buffer
Type Description
4VDD33 P
+3.3 V power and internal regulator input
Refer to Section 4.1, "Power Connections" for power connection infor-
mation.
8VDD12 P
+1.2 V core power
Refer to Section 4.1, "Power Connections" for power connection infor-
mation.
Pad VSS P
Common ground.
This exposed pad must be connected to the ground plane with a via
array.
2015-2017 Microchip Technology Inc. DS00001854E-page 15
USB5734
3.3 Buffer Types
TABLE 3-9: BUFFER TYPES
Buffer Type Description
I Input
IS Schmitt-triggered input
O6 Output with 6 mA sink and 6 mA source
O10 Output with 10 mA sink and 10 mA source
O12 Output with 12 mA sink and 12 mA source
OD12 Open-drain output with 12 mA sink
PU 50 µA (typical) internal pull-up. Unless otherwise noted in the pin description, internal pull-
ups are always enabled.
Internal pull-up resistors prevent unconnected inputs from floating. Do not rely on internal
resistors to drive signals external to the device. When connected to a load that must be
pulled high, an external resistor must be added.
PD 50 µA (typical) internal pull-down. Unless otherwise noted in the pin description, internal
pull-downs are always enabled.
Internal pull-down resistors prevent unconnected inputs from floating. Do not rely on internal
resistors to drive signals external to the device. When connected to a load that must be
pulled low, an external resistor must be added.
IO-U Analog input/output as defined in USB specification
AI Analog input
ICLK Crystal oscillator input pin
OCLK Crystal oscillator output pin
P Power pin
Note: Refer to Section 9.5, "DC Specifications" for individual buffer DC electrical characteristics.
USB5734
DS00001854E-page 16 2015-2017 Microchip Technology Inc.
3.4 Configuration Straps and Programmable Functions
Configuration straps are multi-function pins that are used during Power-On Reset (POR) or external chip reset
(RESET_N) to determine the default configuration of a particular feature. The state of the signal is latched following de-
assertion of the reset. Configuration straps are identified by an underlined symbol name. This section details the various
device configuration straps and associated programmable pin functions.
3.4.1 SPI/SMBUS/I2C/UART CONFIGURATION (I2C_SLV_CFG[1:0])
The SPI/SMBus/I2C//UART pins can be configured into one of four functional modes:
• SPI Mode
• SMBus Slave Enable Mode
•I
2C Bridging Mode
•UART Mode
If 10 k pull-up resistors are detected on SPI_DO and SPI_CLK, the SPI/SMBus/I2C/UART pins are configured into
SMBus Slave Enable Mode. If a 10 k pull-down resistor is detected on SPI_DO, the SPI/SMBus/I2C/UART pins are
configured into UART Mode. If no pull-ups or pull-downs are detected on SPI_DO and SPI_CLK, the SPI/SMBus/I2C/
UART pins are first configured into SPI Mode. If no valid SPI ROM is detected, the SPI/SMBus/I2C/UART pins are con-
figured into I2C Bridging Mode. The strap settings for these supported modes are detailed in Ta ble 3 -1 0. The individual
pin function assignments for each mode are detailed in Table 3-11. For additional device connection information, refer
to Section 4.0, "Device Connections".
Note 6: In order to use the SPI interface, an SPI ROM containing a valid signature of 2DFU (device firmware
upgrade) beginning at address 0xFFFA must be present. Refer to Section 7.1, "SPI Master Interface" for
additional information.
Note 7: In order to use the SMBus slave interface, the SPI_DO and SPI_CLK pins must be configured for SMBus
Slave Enable Mode and CFG_STRAP must be configured to Configuration 1, 2, 3, or 6, which programs the
PROG_FUNC4 and PROG_FUNC5 pins as SMDAT and SMCLK, respectively. When in Configuration 4 or
5, the SMBus slave interface is not usable. Refer to Section 3.4.5, "Device Mode / PROG_FUNC[7:1] Con-
figuration (CFG_STRAP)" for additional information.
Note 8: In order to use the I2C Bridging interface, the SPI_DO and SPI_CLK pins must be configured for I2C Bridg-
ing Mode and CFG_STRAP must be configured to Configuration 1, 2, 3, or 6, which programs the PROG_-
FUNC4 and PROG_FUNC5 pins as SMDAT and SMCLK, respectively. When in Configuration 4 or 5, the
I2C Bridging interface is not usable. Additional hub register configuration is also required. Refer to Section
3.4.5, "Device Mode / PROG_FUNC[7:1] Configuration (CFG_STRAP)" and Section 7.3, "I2C Bridge Inter-
face" for additional information.
Note: The system designer must guarantee that configuration straps meet the timing requirements specified in
Section 9.6.2, "Power-On and Configuration Strap Timing," on page 45 and Section 9.6.3, "Reset and Con-
figuration Strap Timing," on page 46. If configuration straps are not at the correct voltage level prior to being
latched, the device may capture incorrect strap values.
Note: The following interfaces cannot be used simultaneously:
• UART and SMBus Slave
• UART and SPI
• SMBus Slave and I2C Bridging interface
TABLE 3-10: SPI/SMBUS/I2C/UART MODE CONFIGURATION SETTINGS
Pin SPI Mode
(Note 6)SMBus Slave Enable
Mode (Note 7)I2C Bridging
Mode (Note 8)UART
Mode
43
(SPI_DO)No pull-up/down 10 k pull-up No pull-up/down 10 k pull-down
42
(SPI_CLK)No pull-up/down 10 k pull-up No pull-up/down No pull-up/down
2015-2017 Microchip Technology Inc. DS00001854E-page 17
USB5734
3.4.2 PORT DISABLE CONFIGURATION (PRT_DIS_P[4:1] / PRT_DIS_M[4:1])
The PRT_DIS_P[4:1] and PRT_DIS_M[4:1] configuration straps are used in conjunction to disable the related port (4-1).
For PRT_DIS_Px (where x is the corresponding port 4-1):
0 = Port x D+ Enabled
1 = Port x D+ Disabled
For PRT_DIS_Mx (where x is the corresponding port 4-1):
0 = Port x D- Enabled
1 = Port x D- Disabled
3.4.3 NON-REMOVABLE PORT CONFIGURATION (CFG_NON_REM)
The CFG_NON_REM configuration strap is used to configure the non-removable port settings of the device to one of
five settings. These modes are selected by the configuration of an external resistor on the CFG_NON_REM pin. The
resistor options are a 200 kΩ pull-down, 200 kΩ pull-up, 10 kΩ pull-down, 10 kΩ pull-up, and 10 Ω pull-down, as shown
in Table 3-12.
TABLE 3-11: SPI/SMBUS/I2C/UART MODE PIN ASSIGNMENTS
Pin SPI
Mode SMBus Slave Enable
Mode I2C Bridging
Mode UART
Mode
45 SPI_CE_N CFG_NON_REM CFG_NON_REM CFG_NON_REM
44 SPI_DI CFG_BC_EN CFG_BC_EN CFG_BC_EN
43 SPI_DO I2C_SLV_CFG1 -UART_TX
42 SPI_CLK I2C_SLV_CFG0 - UART_RX
Note: Both PRT_DIS_Px and PRT_DIS_Mx (where x is the corresponding port) must be tied to 3.3 V to disable
the associated downstream port. Disabling the USB 2.0 port will also disable the corresponding USB 3.1
Gen 1 port.
TABLE 3-12: CFG_NON_REM RESISTOR ENCODING
CFG_NON_REM Resistor Value Setting
200 kΩ Pull-Down All ports removable
200 kΩ Pull-Up Port 1 non-removable
10 kΩ Pull-Down Port 1, 2 non-removable
10 kΩ Pull-Up Port 1, 2, 3, non-removable
10 Ω Pull-Down Port 1, 2, 3, 4 non-removable
USB5734
DS00001854E-page 18 2015-2017 Microchip Technology Inc.
3.4.4 BATTERY CHARGING CONFIGURATION (CFG_BC_EN)
The CFG_BC_EN configuration strap is used to configure the battery charging port settings of the device to one of five
settings. These modes are selected by the configuration of an external resistor on the CFG_BC_EN pin. The resistor
options are a 200 kΩ pull-down, 200 kΩ pull-up, 10 kΩ pull-down, 10 kΩ pull-up, and 10 Ω pull-down, as shown in
Table 3-13.
3.4.5 DEVICE MODE / PROG_FUNC[7:1] CONFIGURATION (CFG_STRAP)
The CFG_STRAP is used to configure the programmable function pins (PROG_FUNC[7:1]) into one of six modes.
These modes are selected by the configuration of an external resistor on the CFG_STRAP pin. The resistor options are
a 200 kΩ pull-down, 200 kΩ pull-up, 10 kΩ pull-down, 10 kΩ pull-up, 10 Ω pull-down, and 10 Ω pull-up, as shown in
Table 3-14. For details on each device mode, including pin assignments, refer to the following subsections.
TABLE 3-13: CFG_BC_EN RESISTOR ENCODING
CFG_BC_EN Resistor Value Setting
200 kΩ Pull-Down No battery charging
200 kΩ Pull-Up Port 1 battery charging
10 kΩ Pull-Down Port 1, 2 battery charging
10 kΩ Pull-Up Port 1, 2, 3, battery charging
10 Ω Pull-Down Port 1, 2, 3, 4 battery charging
TABLE 3-14: CFG_STRAP RESISTOR ENCODING
CFG_STRAP Resistor Value Mode
200 kΩ Pull-Down Configuration 1 - Mixed Mode
200 kΩ Pull-Up Configuration 2 - FlexConnect Mode
10 kΩ Pull-Down Configuration 3 - Speed Indicator Mode
10 kΩ Pull-Up Configuration 4 - GPIO Mode (Reserved)
10 Ω Pull-Down Configuration 5 - Battery Charging / Power Delivery Indicator Mode
10 Ω Pull-Up Configuration 6 - Full UART Mode
2015-2017 Microchip Technology Inc. DS00001854E-page 19
USB5734
3.4.5.1 Configuration 1 - Mixed Mode
When the CFG_STRAP is configured to this mode, the programmable function pins (PROG_FUNC[7:1]) are set to pro-
vide an SMBus/I2C interface, 3 GPIOs, and FlexConnect capabilities. Ta bl e 3- 15 details the PROG_FUNC[7:1] pin
assignments in this mode.
TABLE 3-15: CONFIGURATION 1 PROG_FUNC[7:1] FUNCTION ASSIGNMENT
Pin Function Buffer
Type Description
PROG_FUNC1 GPIO1 I/O12 General Purpose Input/Output 1
PROG_FUNC2 GPIO2 I/O6 General Purpose Input/Output 2
PROG_FUNC3 GPIO3 I/O12 General Purpose Input/Output 3
PROG_FUNC4 SMDAT OD12 SMBus/I2C Data
The SMBus/I2C interface acts as SMBus slave or I2C bridge
dependent on the device configuration. Refer to Section 3.4.1,
"SPI/SMBus/I2C/UART Configuration (I2C_SLV_CFG[1:0])".
PROG_FUNC5 SMCLK OD12 SMBus/I2C Clock
The SMBus/I2C interface acts as SMBus slave or I2C bridge
dependent on the device configuration. Refer to Section 3.4.1,
"SPI/SMBus/I2C/UART Configuration (I2C_SLV_CFG[1:0])".
PROG_FUNC6 FLEXCMD IS FlexConnect Control
0: Normal Operation (Port 0 upstream, Port 1 downstream)
1: Flex Operation (Port 1 upstream, Port 0 downstream)
Note: Refer to Section 8.2, "FlexConnect" for additional
information.
PROG_FUNC7 USB2_SUSP_IND O10 USB2.0 Suspend Indicator
USB2_SUSP_IND can be used as a sideband remote wakeup
signal for the host when in USB2.0 suspend.
Note: Refer to Section 8.5, "Remote Wakeup Indicator"
for additional information.
USB5734
DS00001854E-page 20 2015-2017 Microchip Technology Inc.
3.4.5.2 Configuration 2 - FlexConnect Mode
When the CFG_STRAP is configured to this mode, the programmable function pins (PROG_FUNC[7:1]) are set to pro-
vide FlexConnect, an SMBus/I2C interface, and other additional features. Table 3-16 details the PROG_FUNC[7:1] pin
assignments in this mode.
TABLE 3-16: CONFIGURATION 2 PROG_FUNC[7:1] FUNCTION ASSIGNMENT
Pin Function Buffer
Type Description
PROG_FUNC1 HOST_TYPE0 O12 Port 0 USB Hos t Type
Tri-state: No USB host detected on Port 0
0: USB 3.1 Gen 1 Host detected on Port 0
1: USB 2.0 or USB 1.1 Host detected on Port 0
A USB 2.0 Host is considered detected when the USB 2.0 hub
address register holds a non-zero value. A USB 3.1 Gen 1
Host is considered detected when the USB 3.1 Gen 1 hub
address register holds a non-zero value.
PROG_FUNC2 HOST_TYPE1 O6 Por t 1 USB Host Type
Tri-state: No USB host detected on Port 1
0: USB 3.1 Gen 1 Host detected on Port 1
1: USB 2.0 or USB 1.1 Host detected on Port 1
A USB 2.0 Host is considered detected when the USB 2.0 hub
address register holds a non-zero value. A USB 3.1 Gen 1
Host is considered detected when the USB 3.1 Gen 1 hub
address register holds a non-zero value.
PROG_FUNC3 FLEX_STATE_N O12 FlexConnect State Compliment Indicator
This signal reflects the inverse of the current state of FLEX-
CMD.
0: Flex Operation (Port 1 upstream, Port 0 downstream)
1: Normal Operation (Port 0 upstream, Port 1 downstream)
Note: Refer to Section 8.2, "FlexConnect" for additional
information.
PROG_FUNC4 SMDAT OD12 SMBus/I2C Data
The SMBus/I2C interface acts as SMBus slave or I2C bridge
dependent on the device configuration. Refer to Section 3.4.1,
"SPI/SMBus/I2C/UART Configuration (I2C_SLV_CFG[1:0])".
PROG_FUNC5 SMCLK OD12 SMBus/I2C Clock
The SMBus/I2C interface acts as SMBus slave or I2C bridge
dependent on the device configuration. Refer to Section 3.4.1,
"SPI/SMBus/I2C/UART Configuration (I2C_SLV_CFG[1:0])".
PROG_FUNC6 FLEXCMD IS FlexConnect Control
0: Normal Operation (Port 0 upstream, Port 1 downstream)
1: Flex Operation (Port 1 upstream, Port 0 downstream)
Note: Refer to the Section 8.2, "FlexConnect" for addi-
tional information.
PROG_FUNC7 FLEX_STATE O10 FlexConnect State Indicator
This signal reflects the current state of FLEXCMD.
0: Normal Operation (Port 0 upstream, Port 1 downstream)
1: Flex Operation (Port 1 upstream, Port 0 downstream)
Note: Refer to Section 8.2, "FlexConnect" for additional
information.
2015-2017 Microchip Technology Inc. DS00001854E-page 21
USB5734
3.4.5.3 Configuration 3 - Speed Indicator Mode
When the CFG_STRAP is configured to this mode, the programmable function pins (PROG_FUNC[7:1]) are set to indi-
cate speed status, host type, and provide an SMBus/I2C interface. Ta b l e 3 - 1 7 details the PROG_FUNC[7:1] pin assign-
ments in this mode.
TABLE 3-17: CONFIGURATION 3 PROG_FUNC[7:1] FUNCTION ASSIGNMENT
Pin Function Buffer
Type Description
PROG_FUNC1 SPEED_IND1 O12 Port 1 Sp ee d Indicator
Tri-state: Not connected
0: USB 2.0 / USB 1.1
1: USB 3.1 Gen 1
PROG_FUNC2 SPEED_IND2 O6 Port 2 Sp ee d Indicator
Tri-state: Not connected
0: USB 2.0 / USB 1.1
1: USB 3.1 Gen 1
PROG_FUNC3 SPEED_IND3 O12 Port 3 Sp ee d Indicator
Tri-state: Not connected
0: USB 2.0 / USB 1.1
1: USB 3.1 Gen 1
PROG_FUNC4 SMDAT OD12 SMBus/I2C Data
The SMBus/I2C interface acts as SMBus slave or I2C bridge
dependent on the device configuration. Refer to Section 3.4.1,
"SPI/SMBus/I2C/UART Configuration (I2C_SLV_CFG[1:0])".
PROG_FUNC5 SMCLK OD12 SMBus/I2C Clock
The SMBus/I2C interface acts as SMBus slave or I2C bridge
dependent on the device configuration. Refer to Section 3.4.1,
"SPI/SMBus/I2C/UART Configuration (I2C_SLV_CFG[1:0])".
PROG_FUNC6 SPEED_IND4 O12 Port 4 Sp ee d Indicator
Tri-state: Not connected
0: USB 2.0 / USB 1.1
1: USB 3.1 Gen 1
PROG_FUNC7 HOST_TYPE O10 Port 0 USB Hos t Type
Tri-state: No USB host detected on Port 0
0: USB 3.1 Gen 1 Host detected on Port 0
1: USB 2.0 or USB 1.1 Host detected on Port 0
A USB 2.0 Host is considered detected when the USB 2.0 hub
address register holds a non-zero value. A USB 3.1 Gen 1
Host is considered detected when the USB 3.1 Gen 1 hub
address register holds a non-zero value.
USB5734
DS00001854E-page 22 2015-2017 Microchip Technology Inc.
FIGURE 3-2: CONFIGURATION 3 PRO G_F UNC [7 :1 ] P IN CON NECT IO NS
PROG_FUNC1
3.3 V Rail
330
SPEED_IND1
PROG_FUNC2
PROG_FUNC3
PROG_FUNC4
MMBD914LT1G
Spee d L ED Indi ca t i on:
OFF – Port Not Connected
A – USB2.0/1.1 Connection
B – USB 3.1 Gen 1 Connection
PROG_FUNC5
PROG_FUNC6
PROG_FUNC7
330
SPEED_IND2
330
SPEED_IND3
330
SPEED_IND4
330
HOST_TYPE
SMDAT
SMCLK
AB
AB
AB
AB
AB
2015-2017 Microchip Technology Inc. DS00001854E-page 23
USB5734
3.4.5.4 Configuration 4 - GPIO Mode (Reserved)
When the CFG_STRAP is configured to this mode, the programmable function pins (PROG_FUNC[7:1]) are set to pro-
vide 7 general purpose I/Os that can be used for GPIO bridging. Table 3-18 details the PROG_FUNC[7:1] pin assign-
ments in this mode.
3.4.5.5 Configuration 5 - Battery Charging / Power Delivery Indicator Mode
When the CFG_STRAP is configured to this mode, the programmable function pins (PROG_FUNC[7:1]) are set to indi-
cate battery charging and 3 general purpose I/Os. Ta bl e 3-19 details the PROG_FUNC[7:1] pin assignments in this
mode.
TABLE 3-18: CONFIGURATION 4 PROG_FUNC[7:1] FUNCTION ASSIGNMENT
Pin Function Buffer
Type Description
PROG_FUNC1 GPIO1 I/O12 General Purpose Input/Output 1
PROG_FUNC2 GPIO2 I/O6 General Purpose Input/Output 2
PROG_FUNC3 GPIO3 I/O12 General Purpose Input/Output 3
PROG_FUNC4 GPIO6 I/O12 General Purpose Input/Output 4
PROG_FUNC5 GPIO8 I/O12 General Purpose Input/Output 5
PROG_FUNC6 GPIO10 I/O12 General Purpose Input/Output 6
PROG_FUNC7 GPIO11 I/O10 General Purpose Input/Output 7
TABLE 3-19: CONFIGURATION 5 PROG_FUNC[7:1] FUNCTION ASSIGNMENT
Pin Function Buffer
Type Description
PROG_FUNC1 BC_IND1 O12 Port 1 Battery Charging Indic a tor
Tri-state: Battery Charging not enabled
0: In BC 1.2 Mode
1: Battery Charging enabled
PROG_FUNC2 BC_IND2 O6 Port 2 Battery Charging Indic a tor
Tri-state: Battery Charging not enabled
0: In BC 1.2 Mode
1: Battery Charging enabled
PROG_FUNC3 BC_IND3 O12 Port 3 Battery Charging Indic a tor
Tri-state: Battery Charging not enabled
0: In BC 1.2 Mode
1: Battery Charging enabled
PROG_FUNC4 BC_IND4 O12 Port 4 Battery Charging Indic a tor
Tri-state: Battery Charging not enabled
0: In BC 1.2 Mode
1: Battery Charging enabled
PROG_FUNC5 GPIO8 I/O12 General Purpose Input/Output 8
PROG_FUNC6 GPIO10 I/O12 General Purpose Input/Output 10
PROG_FUNC7 GPIO11 I/O10 General Purpose Input/Output 11
USB5734
DS00001854E-page 24 2015-2017 Microchip Technology Inc.
FIGURE 3-3: CONFIGURATION 5 PRO G_F UNC [7 :1 ] P IN CON NECT IO NS
PROG_FUNC1
3.3 V Rail
330
BC_STATUS_1
PROG_FUNC2
PROG_FUNC3
PROG_FUNC4
MMBD914LT1G
BC LED Indication:
OFF – BC In not Enabled
A – BC Enabled
B – BC in 1.2 Mode
PROG_FUNC5
PROG_FUNC6
PROG_FUNC7
330
BC_STATUS_2
330
BC_STATUS_3
330
BC_STATUS_4
GPIO8
GPIO10
GPIO11
AB
AB
AB
AB
2015-2017 Microchip Technology Inc. DS00001854E-page 25
USB5734
3.4.5.6 Configuration 6 - Full UART Mode
When the CFG_STRAP is configured to this mode, the programmable function pins (PROG_FUNC[7:1]) are set for full
UART configuration and also provide an SMBus/I2C interface. In this mode the PROG_FUNCx pins are used in con-
junction with the UART_TX and UART_RX pins for a full UART interface. Table 3-20 details the PROG_FUNC[7:1] pin
assignments in this mode.
Note: When flow control is disabled, UART_nCTS, UART_nDCD, and UART_nDSR must not be left floating. In
this case, these pins should include external pull-downs to maintain UART communication in Full UART
Mode with no flow control.
TABLE 3-20: CONFIGURATION 6 PROG_FUNC[7:1] FUNCTION ASSIGNMENT
Pin Function Buffer
Type Description
PROG_FUNC1 UART_nRTS I/O12 UART Request To Send
PROG_FUNC2 UART_nCTS I/O6 UART Clear To Send
PROG_FUNC3 UART_nDCD I/O12 UART Data Carrier Detect
PROG_FUNC4 SMDAT OD12 SMBus/I2C Data
The SMBus/I2C interface acts as SMBus slave or I2C bridge
dependent on the device configuration. Refer to Section 3.4.1,
"SPI/SMBus/I2C/UART Configuration (I2C_SLV_CFG[1:0])".
PROG_FUNC5 SMCLK OD12 SMBus/I2C Clock
The SMBus/I2C interface acts as SMBus slave or I2C bridge
dependent on the device configuration. Refer to Section 3.4.1,
"SPI/SMBus/I2C/UART Configuration (I2C_SLV_CFG[1:0])".
PROG_FUNC6 UART_nDTR I/O12 UART Data Termina l Ready
PROG_FUNC7 UART_nDSR I/O10 UART Data Set Ready
USB5734
DS00001854E-page 26 2015-2017 Microchip Technology Inc.
4.0 DEVICE CONNECTIONS
4.1 Power Connections
Figure 4-1 illustrates the device power connections.
4.2 SPI ROM Connections
Figure 4-2 illustrates the device SPI ROM connections. Refer to Section 7.1, "SPI Master Interface," on page 33 for
additional information on this device interface.
FIGURE 4-1: POWER CONNECTIONS
FIGURE 4-2: SPI ROM CONNECTIONS
+3.3V
Supply
USB5734
3.3V Internal Logic
VDD33
(4x)
VSS
1.2V Internal Logic
+1.2V
Supply
VDD12
(8x)
USB5734
SPI_CE_N
SPI_CLK
SPI_DO
SPI_DI
SPI ROM
CE#
CLK
DO
DI
2015-2017 Microchip Technology Inc. DS00001854E-page 27
USB5734
4.3 SMBus Slave Connections
Figure 4-3 illustrates the device SMBus slave connections. Refer to Section 7.2, "SMBus Slave Interface," on page 33
for additional information on this device interface.
4.4 I2C Bridge Connections
Figure 4-4 illustrates the device I2C bridge connections. Refer to Section 7.3, "I2C Bridge Interface," on page 33 for
additional information on this device interface.
4.5 UART Bridge Connections
Figure 4-5 illustrates the device UART bridge connections. Refer to Section 7.4, "Two Pin Serial Port (UART) Interface,"
on page 34 for additional information on this device interface.
FIGURE 4-3: SMBUS SLAVE CONNECTIONS
FIGURE 4-4: I2C BRIDGE CONNECTIONS
FIGURE 4-5: UART BRIDGE CONNECTIONS
+3.3V
USB5734SMCLK
SMDAT
SMBus
Master
Clock
Data
10K
+3.3V
10K
+3.3V
10K
+3.3V
10K
I2C_SLV_CFG1
I2C_SLV_CFG0
+3.3V
USB5734SMCLK
SMDAT
I2C
Slave
Clock
Data
10K
+3.3V
10K
I2C_SLV_CFG1
I2C_SLV_CFG0
X
X
No
Connect
USB5734
UART_RX
UART_TX
UART
TX
RX
10K
USB5734
DS00001854E-page 28 2015-2017 Microchip Technology Inc.
5.0 MODES OF OPERATION
The device provides two main modes of operation: Standby Mode and Hub Mode. These modes are controlled via the
RESET_N pin, as shown in Tab l e 5- 1 .
The flowchart in Figure 5-1 details the modes of operation and details how the device traverses through the Hub Mode
stages (shown in bold). The remaining sub-sections provide more detail on each stage of operation.
TABLE 5-1: MODES OF OPERATION
RESET_N Input Summary
0 St andby Mode: This is the lowest power mode of the device. No functions are active
other than monitoring the RESET_N input. All port interfaces are high impedance and
the PLL is halted. Refer to Section 8.3.2, "External Chip Reset (RESET_N)" for addi-
tional information on RESET_N.
1 Hub (Normal) Mode: The device operates as a configurable USB hub with battery
charger detection. This mode has various sub-modes of operation, as detailed in
Figure 5-1. Power consumption is based on the number of active ports, their speed,
and amount of data received.
FIGURE 5-1: HUB MODE FLOWCHART
Combine OTP
Config Data
In SPI Mode &
Ext. SPI ROM
present?
YES
NO
Run From
External SPI ROM
Hub Connect
(Hub.Connect)
(SPI_INIT)
Normal operation
SMBus Host Present?
RESET_N deasserted
Modify Config
Based on Config
Straps
(CFG_RD)
Load Config from
Internal ROM
YES
NO
(STRAP)
UART Present? YES
NO
Perform SMBus/I2C
Initialization
SOC Done? YES
NO
(SOC_CFG) (CDC)
Expose CDC
Interface
(OTP_CFG)
2015-2017 Microchip Technology Inc. DS00001854E-page 29
USB5734
5.1 Boot Sequence
5.1.1 STANDBY MODE
If the RESET_N pin is asserted, the hub will be in Standby Mode. This mode provides a very low power state for maxi-
mum power efficiency when no signaling is required. This is the lowest power state. In Standby Mode all downstream
ports are disabled, the USB data pins are held in a high-impedance state, all transactions immediately terminate (no
states saved), all internal registers return to their default state, the PLL is halted, and core logic is powered down in order
to minimize power consumption. Because core logic is powered off, no configuration settings are retained in this mode
and must be re-initialized after RESET_N is negated high.
5.1.2 SPI INITIALIZATION STAGE (SPI_INIT)
The first stage, the initialization stage, occurs on the deassertion of RESET_N. In this stage, the internal logic is reset,
the PLL locks if a valid clock is supplied, and the configuration registers are initialized to their default state. The internal
firmware then checks for an external SPI ROM. The firmware looks for an external SPI flash device that contains a valid
signature of “2DFU” (device firmware upgrade) beginning at address 0xFFFA. If a valid signature is found, then the
external ROM is enabled and the code execution begins at address 0x0000 in the external SPI device. If a valid signa-
ture is not found, then execution continues from internal ROM (CFG_RD stage).
When using an external SPI ROM, a 1 Mbit, 60 MHz or faster ROM must be used. Both 1- and 2-bit SPI operation are
supported. For optimum throughput, a 2-bit SPI ROM is recommended. Both mode 0 and mode 3 SPI ROMs are also
supported.
If the system is not strapped for SPI Mode, code execution will continue from internal ROM (CFG_RD stage).
5.1.3 CONFIGURATION READ STAGE (CFG_RD)
In this stage, the internal firmware loads the default values from the internal ROM and then uses the configuration strap-
ping options to override the default values. Refer to Section 3.4, "Configuration Straps and Programmable Functions"
for information on usage of the various device configuration straps.
5.1.4 STRAP READ STAGE (STRAP)
In this stage, the firmware registers the configuration strap settings on the SPI_DO and SPI_CLK pins. Refer to Section
3.4.1, "SPI/SMBus/I2C/UART Configuration (I2C_SLV_CFG[1:0])" for information on configuring these straps. If config-
ured for SMBus Slave Mode, the next state will be SOC_CFG. If configured for UART Mode, the device will become a
UART bridging combination device and the next state will be CDC. If neither condition is met, the next state is
OTP_CFG.
5.1.5 SOC CONFIGURATION STAGE (SOC_CFG)
In this stage, the SOC can modify any of the default configuration settings specified in the integrated ROM, such as USB
device descriptors and port electrical settings.
There is no time limit on this mode. In this stage the firmware will wait indefinitely for the SMBus/I2C configuration. When
the SOC has completed configuring the device, it must write to register 0xFF to end the configuration.
5.1.6 CDC CONFIGURATION STAGE (CDC)
If the device is configured in UART Mode, (UART Bridge), the hub feature controller will identify itself as a CDC UART
device and move to the OTP_CFG. Refer to Section 3.4.1, "SPI/SMBus/I2C/UART Configuration (I2C_SLV_CFG[1:0])"
for information on configuring the UART Mode.
5.1.7 OTP CONFIGURATION STAGE (OTP_CFG)
Once the SOC has indicated that it is done with configuration, all configuration data is combined in this stage. The
default data, the SOC configuration data, and the OTP data are all combined in the firmware and the device is pro-
grammed.
After the device is fully configured, it will go idle and then into suspend if there is no VBUS or Hub.Connect present.
Once VBUS is present, and battery charging is enabled, the device will transition to the Battery Charger Detection
Stage. If VBUS is present, and battery charging is not enabled, the device will transition to the Connect stage.
USB5734
DS00001854E-page 30 2015-2017 Microchip Technology Inc.
5.1.8 HUB CONNECT STAGE (HUB.CONNECT)
Once the CHGDET stage is completed, the device enters the Hub Connect stage. USB connect can be initiated by
asserting the VBUS pin function high. The device will remain in the Hub Connect stage indefinitely until the VBUS pin
function is deasserted.
5.1.9 NORMAL MODE
Lastly, the hub enters Normal Mode of operation. In this stage full USB operation is supported under control of the USB
Host on the upstream port. The device will remain in the normal mode until the operating mode is changed by the sys-
tem.
If RESET_N is asserted low, then Standby Mode is entered. The device may then be placed into any of the designated
hub stages. Asserting a soft disconnect on the upstream port will cause the hub to return to the Hub.Connect stage until
the soft disconnect is negated.
2015-2017 Microchip Technology Inc. DS00001854E-page 31
USB5734
6.0 DEVICE CONFIGURATION
The device supports a large number of features (some mutually exclusive), and must be configured in order to correctly
function when attached to a USB host controller. The hub can be configured either internally or externally depending on
the implemented interface.
Microchip provides a comprehensive software programming tool, Pro-Touch, for configuring the USB5734 functions,
registers and OTP memory. All configuration is to be performed via the Pro-Touch programming tool. For additional infor-
mation on the Pro-Touch programming tool, refer to the Software Libraries within the Microchip USB5734 product page
at www.microchip.com/USB5734.
6.1 Customer Accessible Functions
The following USB or SMBus accessible functions are available to the customer via the Pro-Touch Programming Tool.
6.1.1 USB ACCESSIBLE FUNCTIONS
6.1.1.1 I2C Bridging Access over USB
Access to I2C devices is performed as a pass-through operation from the USB Host. The device firmware has no knowl-
edge of the operation of the attached I2C device. For more information, refer to the Microchip USB5734 product page
and SDK at www.microchip.com/USB5734.
6.1.1.2 SPI Access over USB
Access to an attached SPI device is performed as a pass-through operation from the USB Host. The device firmware
has no knowledge of the operation of the attached SPI device. For more information, refer to the Microchip USB5734
product page and SDK at www.microchip.com/USB5734.
6.1.1.3 UART Access over USB
Access to UART devices is performed as a pass-through operation from the USB Host. The device firmware has no
knowledge of the operation of the attached UART device. For more information, refer to the Microchip USB5734 product
page and SDK at www.microchip.com/USB5734.
6.1.1.4 OTP Access over USB
The OTP ROM in the device is accessible via the USB bus. All OTP parameters can be modified to the USB Host. The
OTP operates in Single Ended mode. For more information, refer to the Microchip USB5734 product page and SDK at
www.microchip.com/USB5734.
6.1.1.5 Battery Charging Access over USB
The Battery charging behavior of the device can be dynamically changed by the USB Host when something other than
the preprogrammed or OTP programmed behavior is desired. For more information, refer to the Microchip USB5734
product page and SDK at www.microchip.com/USB5734.
Note: Device configuration straps and programmable pins are detailed in Section 3.4, "Configuration Straps and
Programmable Functions," on page 16.
Refer to Section 7.0, "Device Interfaces" for detailed information on each device interface.
Note: For additional programming details, refer to the Pro-Touch programming tool.
Note: Refer to Section 7.3, "I2C Bridge Interface," on page 33 for additional information on the I2C interface.
Note: Refer to Section 7.1, "SPI Master Interface," on page 33 for additional information on the SPI.
Note: Refer to Section 7.4, "Two Pin Serial Port (UART) Interface," on page 34 for additional information on the
UART interface.
USB5734
DS00001854E-page 32 2015-2017 Microchip Technology Inc.
6.1.2 SMBUS ACCESSIBLE FUNCTIONS
OTP access and configuration of specific device functions are possible via the USB5734 SMBus. All OTP parameters
can be modified via the SMBus Host. The OTP can be programmed to operate in Single-Ended, Differential, Redundant,
or Differential Redundant mode, depending on the level of reliability required. For more information, refer to AN1903 -
“Configuration Options for the USB5734 and USB5744” application note at www.microchip.com/AN1903.
2015-2017 Microchip Technology Inc. DS00001854E-page 33
USB5734
7.0 DEVICE INTERFACES
The USB5734 provides multiple interfaces for configuration and external memory access. This section details the vari-
ous device interfaces and their usage:
•SPI Master Interface
•SMBus Slave Interface
•I2C Bridge Interface
•Two Pin Serial Port (UART) Interface
7.1 SPI Master Interface
The device is capable of code execution from an external SPI ROM. When configured for SPI Mode, on power up the
firmware looks for an external SPI flash device that contains a valid signature of 2DFU (device firmware upgrade) begin-
ning at address 0xFFFA. If a valid signature is found, then the external ROM is enabled and the code execution begins
at address 0x0000 in the external SPI device. If a valid signature is not found, then execution continues from internal
ROM.
7.2 SMBus Slave Interface
The device includes an integrated SMBus slave interface, which can be used to access internal device run time registers
or program the internal OTP memory. SMBus slave detection is accomplished by detection of pull-up resistors on both
the SMDAT and SMCLK signals. Refer to Section 3.4.1, "SPI/SMBus/I2C/UART Configuration (I2C_SLV_CFG[1:0])"
for additional information.
7.3 I2C Bridge Interface
The I2C Bridge interface implements a subset of the I2C Master Specification (Please refer to the Philips Semiconductor
Standard I2C-Bus Specification for details on I2C bus protocols). The I2C Bridge conforms to the Fast-Mode I2C Spec-
ification (400 kbit/s transfer rate and 7-bit addressing) for protocol and electrical compatibility. The device acts as the
master and generates the serial clock SCL, controls the bus access (determines which device acts as the transmitter
and which device acts as the receiver), and generates the START and STOP conditions. The I2C Bridge interface fre-
quency is configurable through the I2C Bridging commands. I2C Bridge frequencies are derived from the formula
626KHz/n, where n is any integer from 1 to 256. Refer to Section 3.4.1, "SPI/SMBus/I2C/UART Configuration
(I2C_SLV_CFG[1:0])" for additional information.
Note: For details on how to enable each interface, refer to Section 3.4.1, "SPI/SMBus/I2C/UART Configuration
(I2C_SLV_CFG[1:0])".
For information on device connections, refer to Section 4.0, "Device Connections". For information on
device configuration, refer to Section 6.0, "Device Configuration".
Microchip provides a comprehensive software programming tool, Pro-Touch, for configuring the USB5734
functions, registers and OTP memory. All configuration is to be performed via the Pro-Touch programming
tool. For additional information on the Pro-Touch programming tool, refer to Software Libraries within Micro-
chip USB5734 product page at www.microchip.com/USB5734.
Note: For SPI timing information, refer to Section 9.6.7, "SPI Timing".
Note: All device configuration must be performed via the Pro-Touch Programming Tool. For additional information
on the Pro-Touch programming tool, refer to Software Libraries within Microchip USB5734 product page at
www.microchip.com/USB5734.
USB5734
DS00001854E-page 34 2015-2017 Microchip Technology Inc.
7.4 Two Pin Serial Port (UART) Interface
The device incorporates a fully programmable, universal asynchronous receiver/transmitter (UART) that is functionally
compatible with the NS 16550AF, 16450, 16450 ACE registers and the 16C550A. The UART performs serial-to-parallel
conversion on received characters and parallel-to-serial conversion on transmit characters. Two sets of baud rates are
provided: 24 Mhz and 16 MHz. When the 24 Mhz source clock is selected, standard baud rates from 50 to 115.2 K are
available. When the source clock is 16 MHz, baud rates from 125 K to 1,000 K are available. The character options are
programmable for the transmission of data in word lengths of from five to eight, 1 start bit; 1, 1.5 or 2 stop bits; even,
odd, sticky or no parity; and prioritized interrupts. The UART contains a programmable baud rate generator that is capa-
ble of dividing the input clock or crystal by a number from 1 to 65535. The UART is also capable of supporting the MIDI
data rate.
7.4.1 TRANSMIT OPERATION
Transmission is initiated by writing the data to be sent to the TX Holding Register or TX FIFO (if enabled). The data is
then transferred to the TX Shift Register together with a start bit and parity and stop bits as determined by settings in
the Line Control Register. The bits to be transmitted are then shifted out of the TX Shift Register in the order Start bit,
Data bits (LSB first), Parity bit, Stop bit, using the output from the Baud Rate Generator (divided by 16) as the clock.
If enabled, a TX Holding Register Empty interrupt will be generated when the TX Holding Register or the TX FIFO (if
enabled) becomes empty.
When FIFOs are enabled (i.e. bit 0 of the FIFO Control Register is set), the UART can store up to 16 bytes of data for
transmission at a time. Transmission will continue until the TX FIFO is empty. The FIFO’s readiness to accept more data
is indicated by interrupt.
7.4.2 RECEIVE OPERATION
Data is sampled into the RX Shift Register using the Receive clock, divided by 16. The Receive clock is provided by the
Baud Rate Generator. A filter is used to remove spurious inputs that last for less than two periods of the Receive clock.
When the complete word has been clocked into the receiver, the data bits are transferred to the RX Buffer Register or
to the RX FIFO (if enabled) to be read by the CPU. (The first bit of the data to be received is placed in bit 0 of this reg-
ister.) The receiver also checks that the parity bit and stop bits are as specified by the Line Control Register.
If enabled, an RX Data Received interrupt will be generated when the data has been transferred to the RX Buffer Reg-
ister or, if FIFOs are enabled, when the RX Trigger Level has been reached. Interrupts can also be generated to signal
RX FIFO Character Timeout, incorrect parity, a missing stop bit (frame error) or other Line Status errors.
When FIFOs are enabled (i.e. bit 0 of the FIFO Control Register is set), the UART can store up to 16 bytes of received
data at a time. Depending on the selected RX Trigger Level, interrupt will go active to indicate that data is available when
the RX FIFO contains 1, 4, 8 or 14 bytes of data.
Note: Extensions to the I2C Specification are not supported.
All device configuration must be performed via the Pro-Touch Programming Tool. For additional information
on the Pro-Touch programming tool, contact your local sales representative.
2015-2017 Microchip Technology Inc. DS00001854E-page 35
USB5734
8.0 FUNCTIONAL DESCRIPTIONS
This section details various USB5734 functions, including:
•Downstream Battery Charging
•FlexConnect
•Resets
•Link Power Management (LPM)
•Remote Wakeup Indicator
•Port Control Interface
8.1 Downstream Battery Charging
The device can be configured by an OEM to have any of the downstream ports support battery charging. The hub’s role
in battery charging is to provide acknowledgment to a device’s query as to whether the hub system supports USB battery
charging. The hub silicon does not provide any current or power FETs or any additional circuitry to actually charge the
device. Those components must be provided externally by the OEM.
If the OEM provides an external supply capable of supplying current per the battery charging specification, the hub can
be configured to indicate the presence of such a supply from the device. This indication, via the PRT_CTL[4:1] pins, is
on a per port basis. For example, the OEM can configure two ports to support battery charging through high current
power FETs and leave the other two ports as standard USB ports.
For additional information, refer to the Microchip USB5734 Battery Charging application note on the Microchip.com
USB5734 product page at www.microchip.com/USB5734.
8.2 FlexConnect
This feature allows the upstream port to be swapped with downstream physical port 1. Only downstream port 1 can be
swapped physically. Using port remapping, any logical port (number assignment) can be swapped with the upstream
port (non-physical).
FlexConnect is enabled/disabled via the FLEXCONNECT control bit in the Connect Configuration register (address
0x318E). The FLEXCONNECT configuration bit switches the port. This bit can be controlled via the I2C interface or via
the FLEXCMD pin (PROG_FUNC6 in configurations 1 or 2). Toggling of FLEXCMD will cause an interrupt to the device
firmware. The firmware will then change the port direction based on the input value. Refer to Section 3.4.5, "Device
Mode / PROG_FUNC[7:1] Configuration (CFG_STRAP)" for additional information.
For additional information, refer to the Microchip USB5734 FlexConnect application note on the Microchip.com
USB5734 product page.
FIGURE 8-1: BATTERY CHARGING EXTERNAL POWER SUPPLY
SOC
VBUS[n]
PRT_CTL[n]
INT
SCL
SDA
Microchip
Hub
DC Power
USB5734
DS00001854E-page 36 2015-2017 Microchip Technology Inc.
8.3 Resets
The device includes the following chip-level reset sources:
•Power-On Reset (POR)
•External Chip Reset (RESET_N)
•USB Bus Reset
8.3.1 POWER-ON RESET (POR)
A power-on reset occurs whenever power is initially supplied to the device, or if power is removed and reapplied to the
device. A timer within the device will assert the internal reset per the specifications listed in Section 9.6.2, "Power-On
and Configuration Strap Timing," on page 45.
8.3.2 EXTERNAL CHIP RESET (RESET_N)
A valid hardware reset is defined as assertion of RESET_N, after all power supplies are within operating range, per the
specifications in Section 9.6.3, "Reset and Configuration Strap Timing," on page 46. While reset is asserted, the device
(and its associated external circuitry) enters Standby Mode and consumes minimal current.
Assertion of RESET_N causes the following:
1. The PHY is disabled and the differential pairs will be in a high-impedance state.
2. All transactions immediately terminate; no states are saved.
3. All internal registers return to the default state.
4. The external crystal oscillator is halted.
5. The PLL is halted.
8.3.3 USB BUS RESET
In response to the upstream port signaling a reset to the device, the device performs the following:
1. Sets default address to 0.
2. Sets configuration to Unconfigured.
3. Moves device from suspended to active (if suspended).
4. Complies with the USB Specification for behavior after completion of a reset sequence.
The host then configures the device in accordance with the USB Specification.
8.4 Link Power Management (LPM)
The device supports the L0 (On), L1 (Sleep), and L2 (Suspend) link power management states. These supported LPM
states offer low transitional latencies in the tens of microseconds versus the much longer latencies of the traditional USB
suspend/resume in the tens of milliseconds. The supported LPM states are detailed in Table 8-1.
Note: All power supplies must have reached the operating levels mandated in Section 9.2, "Operating Condi-
tions**," on page 41, prior to (or coincident with) the assertion of RESET_N.
Note: The device does not propagate the upstream USB reset to downstream devices.
TABLE 8-1: LPM STATE DEFINITIONS
State Description Entry/Exit Time to L0
L2 Suspend Entry: ~3 ms
Exit: ~2 ms (from start of RESUME)
L1 Sleep Entry: <10 us
Exit: <50 us
L0 Fully Enabled (On) -
2015-2017 Microchip Technology Inc. DS00001854E-page 37
USB5734
8.5 Remote Wakeup Indicator
The remote wakeup indicator feature uses USB2_SUSP_IND as a side band signal to wake up the host when in USB2.0
suspend. This feature is enabled and disabled via the HUB_RESUME_INHIBIT configuration bit in the hub configuration
space register CFG3. The only way to control the bit is by configuration EEPROM, SMBus or internal ROM default set-
ting. The state is only modified during a power on reset, or hardware reset. No dynamic reconfiguring of this capability
is possible.
When HUB_RESUME_INHIBIT = ‘0’, Normal Resume Behavior per the USB 2.0 specification
When HUB_RESUME_INHIBIT = ‘1’, Modified Resume Behavior is enabled
For additional information, refer to the Microchip USB5734 Suspend Indicator application note on the Microchip.com
USB5734 product page.
8.6 Port Control Interface
Port power and over-current sense share the same pin (PRT_CTLx) for each port. These functions can be controlled
directly from the USB hub, or via the processor. Additionally, smart port controllers can be controlled via the I2C inter-
face.
The device can be configured into the following port control modes:
• Ganged Mode
• Combined Mode
Port connection in various modes are detailed in the following subsections.
8.6.1 PORT CONNECTION IN GANGED MODE
In this mode, one pin (GANG_PWR) is used to control port power and over-current sensing.
8.6.2 PORT CONNECTION IN COMBINED MODE
8.6.2.1 Port Power Control using USB Power Switch
When operating in combined mode, the device will have one port power control and over-current sense pin for each
downstream port. When disabling port power, the driver will actively drive a '0'. To avoid unnecessary power dissipation,
the pull-up resistor will be disabled at that time. When port power is enabled, it will disable the output driver and enable
the pull-up resistor, making it an open drain output. If there is an over-current situation, the USB Power Switch will assert
the open drain OCS signal. The Schmidt trigger input will recognize that as a low. The open drain output does not inter-
fere. The over-current sense filter handles the transient conditions such as low voltage while the device is powering up.
Note: The USB2_SUSP_IND signal only indicates the USB2.0 state.
FIGURE 8-2: PORT POWER CONTROL WITH USB POWER SWITCH
USB Power
Switch
50k
PRTPWR
EN
OCS
OCS
Pull-Up Enable
5V
USB
Device
FILTER
PRT_CTLx
USB5734
DS00001854E-page 38 2015-2017 Microchip Technology Inc.
When the port is enabled, the PRT_CTLx pin input is constantly sampled. Overcurrent events can be detected in one
of two ways:
• Single, continuous low pulse (consecutive low samples over tocs_single), as shown in Figure 8-3.
• Two short low pulses within a rolling window (two groupings of 1 or more low samples over tocs_double), as shown
in Figure 8-4.
8.6.2.2 Port Power Control using Poly Fuse
When using the device with a poly fuse, there is no need for an output power control. To maintain consistency, the same
circuit will be used. A single port power control and over-current sense for each downstream port is still used from the
Hub's perspective. When disabling port power, the driver will actively drive a '0'. This will have no effect as the external
diode will isolate pin from the load. When port power is enabled, it will disable the output driver and enable the pull-up
resistor. This means that the pull-up resistor is providing 3.3 volts to the anode of the diode. If there is an over-current
situation, the poly fuse will open. This will cause the cathode of the diode to go to 0 volts. The anode of the diode will
be at 0.7 volts, and the Schmidt trigger input will register this as a low resulting in an over-current detection. The open
drain output does not interfere.
FIGURE 8-3: SINGLE LOW PULSE OVERCURRENT DETECTION
FIGURE 8-4: DOUBLE LOW PULSE OVERCURRENT DETECTION
TABLE 8-2: OVERCURRENT PULSE TIMING
Symbol Description Min Max Units
tocs_single single low pulse assertion time 5 - ms
tocs_double double low pulse window - 20 ms
Note: The USB 2.0 and USB 3.1 Gen 1 bPwrOn2PwrGood descriptors must be set to 0 when using poly-fuse
mode. Refer to Microchip application note AN1903 “Configuration Options for the USB5734 and USB5744”
for details on how to change these values.
PRT_CTLx IS VIL
tocs_single
PRT_CTLx IS VIL
tocs_double
2015-2017 Microchip Technology Inc. DS00001854E-page 39
USB5734
8.6.2.3 Port Power Control with Single Poly Fuse and Multiple Loads
Many customers use a single poly fuse to power all their devices. For the ganged situation, all power control pins must
be tied together.
FIGURE 8-5: PORT POWER CONTROL USING A POLY FUSE
FIGURE 8-6: PORT POWER CONTROL WITH GANGED CONTROL WITH POLY FUSE
PRT_CTLx
50k
PRTPWR
OCS
USB
Device
Pull-Up Enable
5V
Poly Fuse
FILTER
Pull-Up Enable
USB
Device
Poly Fuse
5V
Pull-Up Enable
Pull-Up Enable
50k
50k
50k
PRTPWR
OCS
USB
Device
USB
Device
PRT_CTLx
PRT_CTLy
PRT_CTLz
USB5734
DS00001854E-page 40 2015-2017 Microchip Technology Inc.
8.6.3 PORT CONTROLLER CONNECTION EXAMPLE
FIGURE 8-7: USB5734 WITH 4 GENERIC PORT POWER CONTROLLERS (2 BC ENABLED)
Note: The CFG_BC_EN configuration strap must be properly configured to enable battery charging on the appro-
priate ports. For example, in the application shown in Figure 8-7, CFG_BC_EN must be connected to an
external 10 kΩ pull-down resistor to enable battery charging on Ports 1 and 2. For more information on the
CFG_BC_EN configuration strap, refer to Section 3.4.4, "Battery Charging Configuration (CFG_BC_EN)".
USB5734
Port 1
Connector
Generic Port
Power Controller
POWER
(High Current)
(BC Enabled)
OCS
D+
D-
VBUS
D+
D-
Port 2
Connector
Generic Port
Power Controller
POWER
(High Current)
(BC Enabled)
OCS
D+
D-
VBUS
D+
D-
PRT_CTL2
PRT_CTL1
Port 3
Connector
Generic Port
Power Controller
POWER
OCS
D+
D-
VBUS
D+
D-
PRT_CTL3
Port 4
Connector
Generic Port
Power Controller
POWER
OCS
D+
D-
VBUS
D+
D-
PRT_CTL4
2015-2017 Microchip Technology Inc. DS00001854E-page 41
USB5734
9.0 OPERATIONAL CHARACTERISTICS
9.1 Absolute Maximum Ratings*
+1.2 V Supply Voltage (VDD12) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to +1.32 V
+3.3 V Supply Voltage (VDD33) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to +4.6 V
Positive voltage on input signal pins, with respect to ground (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.6 V
Negative voltage on input signal pins, with respect to ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V
Positive voltage on XTALI/CLK_IN, with respect to ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+3.63 V
Positive voltage on USB DP/DM signal pins, with respect to ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+6.0 V
Positive voltage on USB 3.1 Gen 1 USB3UP_xxxx and USB3DN_xxxx signal pins, with respect to ground . . . . .1.32 V
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55oC to +150oC
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +125oC
Lead Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Refer to JEDEC Spec. J-STD-020
HBM ESD Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 kV
Note 1: When powering this device from laboratory or system power supplies, it is important that the absolute max-
imum ratings not be exceeded or device failure can result. Some power supplies exhibit voltage spikes on
their outputs when AC power is switched on or off. In addition, voltage transients on the AC power line may
appear on the DC output. If this possibility exists, it is suggested to use a clamp circuit.
Note 2: This rating does not apply to the following pins: All USB DM/DP pins, XTAL1/CLK_IN, and XTALO
*Stresses exceeding those listed in this section could cause permanent damage to the device. This is a stress rating
only. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Functional
operation of the device at any condition exceeding those indicated in Section 9.2, "Operating Conditions**", Section 9.5,
"DC Specifications", or any other applicable section of this specification is not implied.
9.2 Operating Conditions**
+1.2 V Supply Voltage (VDD12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1.08 V to +1.32 V
+3.3 V Supply Voltage (VDD33) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +3.0 V to +3.6 V
Input Signal Pins Voltage (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +3.6 V
XTALI/CLK_IN Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +3.6 V
USB 2.0 DP/DM Signal Pins Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +5.5 V
USB 3.1 Gen 1 USB3UP_xxxx and USB3DN_xxxx Signal Pins Voltage . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +1.32 V
Ambient Operating Temperature in Still Air (TA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Note 3
+1.2 V Supply Voltage Rise Time (TRT in Figure 9-1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400 µs
+3.3 V Supply Voltage Rise Time (TRT in Figure 9-1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400 µs
Note 3: 0oC to +70oC for commercial version, -40oC to +85oC for industrial version.
**Proper operation of the device is guaranteed only within the ranges specified in this section.
Note: Do not drive input signals without power supplied to the device.
USB5734
DS00001854E-page 42 2015-2017 Microchip Technology Inc.
9.3 Package Thermal Specifications
FIGURE 9-1: SUPPLY RISE TIME MODEL
TABLE 9-1: PACKAGE THERMAL PARAMETERS
Symbol °C/W Velocity (Meters/s)
JA
25 0
22 1
JT
0.2 0
0.3 1
JC
2.5 0
2.5 1
Note: Thermal parameters are measured or estimated for devices in a multi-layer 2S2P PCB per JESDN51.
TABLE 9-2: MAXIMUM POWER DISSIP A TION
Parameter Value Units
PD(max) 1400 mW
t10%
10%
90%
Voltage TRT
t90% Time
100%
3.3 V
VSS
VDD33
90%
100%
1.2 V
VDD12
2015-2017 Microchip Technology Inc. DS00001854E-page 43
USB5734
9.4 Power Consumption
This section details the power consumption of the device as measured during various modes of operation. Power dis-
sipation is determined by temperature, supply voltage, and external source/sink requirements.
TABLE 9-3: DEVICE POWER CONSUMPTION
Typical (mA) Typical Power
VDD33 VDD12 (mW)
Reset 0.8 1.8 4.8
No VBUS 2.0 5.0 12.6
Global Suspend 2.0 5.2 12.9
4 FS Ports 39 35 170
4 HS Ports 53 42 222
4 SS Ports 55 683 1001
4 SS/HS Ports 93 688 1132
USB5734
DS00001854E-page 44 2015-2017 Microchip Technology Inc.
9.5 DC Specifications
Note 4: The PROG_FUNC3 pin has a Schmitt trigger hysteresis minimum of 10 mV and a maximum of 60 mV.
Note 5: XTALI can optionally be driven from a 25 MHz singled-ended clock oscillator.
Note 6: Refer to the USB 3.1 Gen 1 Specification for USB DC electrical characteristics.
TABLE 9-4: I/O DC ELECTRICAL CHARACTERISTICS
Parameter Symbol Min Typical Max Units Notes
I Type Input Buffer
Low Input Level
High Input Level
VIL
VIH 2.1
0.9 V
V
IS Type Input Buffer
Low Input Level
High Input Level
Schmitt Trigger Hysteresis
(VIHT - VILT)
VIL
VIH
VHYS
1.9
920
0.9
40
V
V
mV Note 4
O6 Type Output Buffer
Low Output Level
High Output Level
VOL
VOH VDD33-0.4
0.4 V
V
IOL = 6 mA
IOH = -6 mA
O10 Type Output Buffer
Low Output Level
High Output Level
VOL
VOH VDD33-0.4
0.4 V
V
IOL = 10 mA
IOH = -10 mA
O12 Type Output Buffer
Low Output Level
High Output Level
VOL
VOH VDD33-0.4
0.4 V
V
IOL = 12 mA
IOH = -12 mA
OD12 Type Output Buffer
Low Output Level VOL 0.4 V IOL = 12 mA
ICLK Type I nput Buffer
(XTALI Input)
Low Input Level
High Input Level
VIL
VIH 0.85
0.50
VDD33
V
V
Note 5
IO-U Type Buffer
(See Note 6)Note 6
2015-2017 Microchip Technology Inc. DS00001854E-page 45
USB5734
9.6 AC Specifications
This section details the various AC timing specifications of the device.
9.6.1 POWER SUPPLY AND RESET_N SEQUENCE TIMING
Figure 9-2 illustrates the recommended power supply sequencing and timing for the device. VDD33 should rise after or
at the same rate as VDD12. Similarly, RESET_N and/or VBUS_DET should rise after or at the same rate as VDD33.
VBUS_DET and RESET_N do not have any other timing dependencies.
9.6.2 POWER-ON AND CONFIGURATION STRAP TIMING
Figure 9-3 illustrates the configuration strap valid timing requirements in relation to power-on, for applications where
RESET_N is not used at power-on. In order for valid configuration strap values to be read at power-on, the following
timing requirements must be met. The operational levels (Vopp) for the external power supplies are detailed in Section
9.2, "Operating Conditions**," on page 41.
Device configuration straps are also latched as a result of RESET_N assertion. Refer to Section 9.6.3, "Reset and Con-
figuration Strap Timing" for additional details.
FIGURE 9-2: POWER SUPPLY AND RESET_N SEQUENCE TIMING
TABLE 9-5: POWER SUPPLY AND RESET_N SEQUENCE TIMING
Symbol Description Min Typ Max Units
tVDD33 VDD12 to VDD33 rise time 0 ms
treset VDD33 to RESET_N/VBUS_DET rise time 0 ms
FIGURE 9-3: POWER-ON CONFIGURA TI ON STRAP VALID TIMING
TABLE 9-6: POWER-ON CONFIGURATION STRAP LATCHING TIMING
Symbol Description Min Typ Max Units
tcsh Configuration strap hold after external power supplies at opera-
tional levels
1ms
VDD12
VDD33
RESET_N/
VBUS_DET
All External
Power Supplies
Vopp
Configuration
Straps
tcsh
USB5734
DS00001854E-page 46 2015-2017 Microchip Technology Inc.
9.6.3 RESET AND CONFIGURATION STRAP TIMING
Figure 9-4 illustrates the RESET_N pin timing requirements and its relation to the configuration strap pins. Assertion of
RESET_N is not a requirement. However, if used, it must be asserted for the minimum period specified. Refer to Section
8.3, "Resets" for additional information on resets. Refer to Section 3.4, "Configuration Straps and Programmable Func-
tions" for additional information on configuration straps.
9.6.4 USB TIMING
All device USB signals conform to the voltage, power, and timing characteristics/specifications as set forth in the Uni-
versal Serial Bus Specification. Please refer to the Universal Serial Bus Revisio n 3.1 Specification, available at http://
www.usb.org/developers/docs.
9.6.5 I2C TIMING
All device I2C signals conform to the 400KHz Fast Mode (Fm) voltage, power, and timing characteristics/specifications
as set forth in the I2C-Bus Specification. Please refer to the I2C-Bus Specification, available at http://www.nxp.com/doc-
uments/user_manual/UM10204.pdf.
9.6.6 SMBUS TIMING
All device SMBus signals conform to the voltage, power, and timing characteristics/specifications as set forth in the Sys-
tem Management Bus Specification. Please refer to the System Management Bus Specification, Version 1.0, available
at http://smbus.org/specs.
FIGURE 9-4: RESET_N CONFIGURATION STRAP TIMING
TABLE 9-7: RESET_N CONFIGURATION STRAP TIMING
Symbol Description Min Typ Max Units
trstia RESET_N input assertion time 5 s
tcsh Configuration strap pins hold after RESET_N deassertion 1 ms
Note: The clock input must be stable prior to RESET_N deassertion.
Configuration strap latching and output drive timings shown assume that the Power-On reset has finished
first otherwise the timings in Section 9.6.2, "Power-On and Configuration Strap Timing" apply.
RESET_N
Configuration
Straps
trstia
tcsh
2015-2017 Microchip Technology Inc. DS00001854E-page 47
USB5734
9.6.7 SPI TIMING
This section specifies the SPI timing requirements for the device.
FIGURE 9-5: SPI TIMING
TABLE 9-8: SPI TIMING (30 MHZ OPERATION)
Symbol Description Min Typ Max Units
tfc Clock frequency 30 MHz
tceh Chip enable (SPI_CE_EN) high time 100 ns
tclq Clock to input data 13 ns
tdh Input data hold time 0 ns
tos Output setup time 5 ns
toh Output hold time 5 ns
tov Clock to output valid 4 ns
tcel Chip enable (SPI_CE_EN) low to first clock 12 ns
tceh Last clock to chip enable (SPI_CE_EN) high 12 ns
TABLE 9-9: SPI TIMING (60 MHZ OPERATION)
Symbol Description Min Typ Max Units
tfc Clock frequency 60 MHz
tceh Chip enable (SPI_CE_EN) high time 50 ns
tclq Clock to input data 9 ns
tdh Input data hold time 0 ns
tos Output setup time 5 ns
toh Output hold time 5 ns
tov Clock to output valid 4 ns
tcel Chip enable (SPI_CE_EN) low to first clock 12 ns
tceh Last clock to chip enable (SPI_CE_EN) high 12 ns
SPI_CLK
SPI_DI
SPI_DO
SPI_CE_N
tcel tfc
tclq
tceh
tdh
toh
tos tov toh
USB5734
DS00001854E-page 48 2015-2017 Microchip Technology Inc.
9.7 Clock Specifications
The device can accept either a 25MHz crystal or a 25MHz single-ended clock oscillator (±50ppm) input. If the single-
ended clock oscillator method is implemented, XTALO should be left unconnected and XTALI/CLK_IN should be
driven with a nominal 0-3.3V clock signal. The input clock duty cycle is 40% minimum, 50% typical and 60% maximum.
It is recommended that a crystal utilizing matching parallel load capacitors be used for the crystal input/output signals
(XTALI/XTALO). The following circuit design (Figure 9-6) and specifications (Ta b le 9- 1 0 ) are required to ensure proper
operation.
9.7.1 CRYSTAL SPECIFICATIONS
It is recommended that a crystal utilizing matching parallel load capacitors be used for the crystal input/output signals
(XTALI/XTALO). Refer to Table 9-10 for the recommended crystal specifications.
Note 7: Frequency Deviation Over Time is also referred to as Aging.
FIGURE 9-6: 25MHZ CRYSTAL CIRCUIT
TABLE 9-10: CRYSTAL SPECIFICATIONS
Parameter Symbol Min Nom Max Units Notes
Crystal Cut AT, typ
Crystal Oscillation Mode Fundamental Mode
Crystal Calibration Mode Parallel Resonant Mode
Frequency Ffund - 25.000 - MHz
Frequency Tolerance @ 25oCF
tol - - ±50 PPM Note 7
Frequency Stability Over Temp Ftemp - - ±50 PPM Note 7
Frequency Deviation Over Time Fage - ±3 to 5 - PPM
Total Allowable PPM Budget - - ±100 PPM Note 8
Shunt Capacitance CO- 7 typ - pF
Load Capacitance CL- 20 typ - pF
Drive Level PW100 - - uW
Equivalent Series Resistance R1--50Ω
Operating Temperature Range Note 8 -Note 9 oC
XTALI/CLK_IN Pin Capacitance - 3 typ - pF Note 10
XTALO Pin Capacitance - 3 typ - pF Note 10
USB5734
XTALO
XTALI
Y1
C1C2
2015-2017 Microchip Technology Inc. DS00001854E-page 49
USB5734
Note 8: 0 °C for commercial version, -40 °C for industrial version.
Note 9: +70 °C for commercial version, +85 °C for industrial version.
Note 10: This number includes the pad, the bond wire and the lead frame. PCB capacitance is not included in this
value. The XTALI/CLK_IN pin, XTALO pin and PCB capacitance values are required to accurately calcu-
late the value of the two external load capacitors. These two external load capacitors determine the accu-
racy of the 25.000 MHz frequency.
9.7.2 EXTERNAL REFERENCE CLOCK (CLK_IN)
When using an external reference clock, the following input clock specifications are suggested:
•25MHz
• 50% duty cycle ±10%, ±100 ppm
• Jitter < 100 ps RMS
USB5734
DS00001854E-page 50 2015-2017 Microchip Technology Inc.
10.0 PACKAGE INFORMATION
10.1 Package Marking Information
*Standard device marking consists of Microchip part number, year code, week code and traceability code.
For device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office.
For QTP devices, any special marking adders are included in QTP price.
Legend: iTemperature range designator (Blank = commercial, i = industrial)
R Product revision
nnn Internal code
e3 Pb-free JEDEC® designator for Matte Tin (Sn)
V Plant of assembly
COO Country of origin
YY Year code (last two digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Note: In the event the full Microchip part number cannot be marked on one line, it
will be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
64-VQFN (9x9 mm)
PIN 1 USB5734i
Rnnn e3
VCOO
YYWWNNN
e3
2015-2017 Microchip Technology Inc. DS00001854E-page 51
USB5734
10.2 Package Drawings
Note: For the most current package drawings, see the Microchip Packaging Specification at:
http://www.microchip.com/packaging.
FIGURE 10-1: 64-VQFN PACKAGE (DRAWING)
USB5734
DS00001854E-page 52 2015-2017 Microchip Technology Inc.
FIGURE 10-2: 64-VQFN PACKAGE (DIMENSIONS)
2015-2017 Microchip Technology Inc. DS00001854E-page 53
USB5734
FIGURE 10-3: 64-VQFN LAND PATTERN
USB5734
DS00001854E-page 54 2015-2017 Microchip Technology Inc.
APPENDIX A: DATA SHEET REVISION HISTORY
TABLE A-1: REVISION HISTORY
Revision Level & Date Section/Figure/Entry Correction
DS00001854E(02-10-17) Tabl e 3 - 1 Removed errant duplicate pin assignment
table.
Tabl e 3 - 11 Corrected I2C_SLV_CFG0/1 ordering.
DS00001854D (06-06-16) Section 10.0, Package Information Added top marking information and land pat-
tern drawing.
All Updated “SQFN” references to “VQFN”.
Name change only.
Section 8.6.2.1, Port Power Control
using USB Power Switch
Added additional information on overcurrent
detection methods.
Section 9.6.1, Power Supply and
RESET_N Sequence Timing
Added Power Supply and RESET_N
Sequence Timing section.
Section 9.6.5, I2C Timing “100kHz Standard Mode (Sm)” updated to
“400kHz Fast Mode (Fm)”, since the device
supports up to 400kHz I2C operation.
DS00001854C (06-22-15) All Updated “USB 3.0” references to “USB 3.1
Gen 1” throughout the document
Updated USB specification references
Misc. typos
DS00001854B (04-16-15) Features Changed Environmental feature bullet from
“4kV HBM JESD22-A114F ESD protection”
to
“3kV HBM JESD22-A114F ESD protection”
Section 9.2, Operating Conditions** Changed XTALI/CLK_IN Voltage to -0.3V to
+3.6V
Table 9-10, "Crystal Specifications" Total Allowable PPM budget changed to
100pm, removed notes under table regarding
“Frequency Tolerance” and “Frequency and
Transmitter Clock Frequency”
Section 9.7.2, External Reference
Clock (CLK_IN)
Changed +-350ppm t +-100 ppm
Figure 3-1, "64-VQFN Pin Assign-
ments", Table 3-1, "64-VQFN Pin
Assignments"
Modified pin 32 from “PRT_CTL4/
GANG_PWR” to “PRT_CTL4/GANG_PWR”
Table 3-4, "USB Port Control Pin
Descriptions"
Revised description of Pin 1, GANG_PWR
Table 1-1, "General Terms" and
throughout document
Replaced the term Hub Controller with Hub
Feature Controller, added definition in Tab l e 1 -
1, "General Terms".
Section 6.1.2, SMBus Accessible
Functions
Added web link to AN1903
Removed PortMap feature throughout docu-
ment.
Table 3-7, "Miscellaneous Pin
Descriptions"
Modified RESET_N pin description
Section 8.4, Link Power Management
(LPM)
Removed “per the USB 3.0 Specification” from
the first sentence. Removed last sentence
“For additional information, refer to the USB
3.0 Specification.”
2015-2017 Microchip Technology Inc. DS00001854E-page 55
USB5734
Table 9-2, "MAXIMUM Power Dissipa-
tion"
Added Ta b l e 9-2 .
Section 9.7, "Clock
Specifications",Figure 9-6, Table 9-10,
"Crystal Specifications"
Updated these sections.
Section 9.7.2, External Reference
Clock (CLK_IN)
Oscillator changed from “35MHz” to “25 MHz”
Section 9.6.7, SPI Timing Removed SPI interface configure note
Section 9.1, Absolute Maximum Rat-
ings*
Added “Positive voltage on USB 3.0 USB3UP-
_xxxx and USB3DN_xxxx signal pins, with
respect to ground...1.32 V
Changed XTALI positive voltage from 2.1V to
3.63V.
Changed “USB 3.0 DP/DM Signal Pins Volt-
age” to “USB 3.0 USB3UP_xxxx and
USB3DN_xxxx Signal Pins Voltage”
Section 8.6.2, "Port Connection in
Combined Mode," on page 37
Added note under Section 8.6.2
Product Identification System on page
58
Updated ordering information
Section 9.1, "Absolute Maximum Rat-
ings*," on page 41
Updated +1.2V supply voltage absolute max
value. Added HBM ESD performance specifi-
cation.
Table 9-1, “Package Thermal Parame-
ters,” on page 42
Added package thermal parameters.
Worldwide Sales and Service Updated Worldwide Sales Listing
Table 9-4, “I/O DC Electrical Charac-
teristics,” on page 44
Updated I buffer type high input level max.
Added IS buffer type Schmitt trigger hystere-
sis values and note for PROG_FUNC3 pin.
Cover, All Updated document title to “4-Port SS/HS Con-
troller Hub”
Removed PortMap references.
Removed sentence: ”These circuits are used
to detect the attachment and type of a USB
charger and provide an interrupt output to indi-
cate charger information is available to be
read from the device’s status registers via the
serial interface.“
FIGURE 3-1: 64-VQFN Pin Assign-
ments on page 8
Added configuration strap note under figure.
Table 3-6, “Programmable Function
Pin Descriptions,” on page 13,
Tabl e 3 - 1 5 , Ta b le 3 - 1 6 , Table 3-17,
Tabl e 3 - 1 8 , Ta b le 3 - 1 9 , Table 3-20
Added note to PROG_FUNC[7:1] buffer type
column, which indicates the following: “The
PROG_FUNC2 buffer type is I/O6. The
PROG_FUNC7 buffer type is I/O10. All other
PROG_FUNCx pins have a buffer type of I/
O12.”
Tabl e 3 - 1 5 , Ta b le 3 - 1 6 , Table 3-17,
Tabl e 3 - 1 8 , Ta b le 3 - 1 9 , Table 3-20
Updated PROG_FUNC2 and PROG_FUNC7
buffer type definitions to reflect O6 and O10
outputs, respectively.
Table 3-9, “Buffer Types,” on page 15,
Table 9-4, “I/O DC Electrical Charac-
teristics,” on page 44
Added O10 buffer type
TABLE A-1: REVISION HISTORY (CONTINUED)
Revision Level & Date Section/Figure/Entry Correction
USB5734
DS00001854E-page 56 2015-2017 Microchip Technology Inc.
Table 3-15, “Configuration 1 PROG_-
FUNC[7:1] Function Assignment,” on
page 19
Updated PROG_FUNC7 name in Configura-
tion 1 - Mixed Mode from SUSP_IND to
USB2_SUSP_IND and clarified description.
Section 3.4.5.6, "Configuration 6 - Full
UART Mode," on page 25
Added note: “When flow control is disabled,
UART_nCTS, UART_nDCD, and
UART_nDSR must not be left floating. In this
case, these pins should include external pull-
downs to maintain UART communication in
Full UART Mode with no flow control.”
Section 8.2, "FlexConnect," on
page 35
Updated second paragraph to clarify proper
FLEXCONNECT operation.
Section 8.5, "Remote Wakeup Indica-
tor," on page 37
Updated SUSP_IND to USB2_SUSP_IND
and clarified the function is for USB2.0 only.
DS00001854A (12-15-14) All Initial Release
TABLE A-1: REVISION HISTORY (CONTINUED)
Revision Level & Date Section/Figure/Entry Correction
2015-2017 Microchip Technology Inc. DS00001854E-page 57
USB5734
THE MICROCHIP WEB SITE
Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make
files and information easily available to customers. Accessible by using your favorite Internet browser, the web site con-
tains the following information:
•Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s
guides and hardware support documents, latest software releases and archived software
•General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion
groups, Microchip consultant program member listing
•Business of Mic r oc hi p – Product selector and ordering guides, latest Microchip press releases, listing of semi-
nars and events, listings of Microchip sales offices, distributors and factory representatives
CUSTOMER CHANGE NOTIFICATION SERVICE
Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive
e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or
development tool of interest.
To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notifi-
cation” and follow the registration instructions.
CUSTOMER SUPPORT
Users of Microchip products can receive assistance through several channels:
• Distributor or Representative
• Local Sales Office
• Field Application Engineer (FAE)
• Technical Support
Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales
offices are also available to help customers. A listing of sales offices and locations is included in the back of this docu-
ment.
Technical support is available through the web site at: http://www.microchip.com/support
USB5734
DS00001854E-page 58 2015-2017 Microchip Technology Inc.
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Device: USB5734
Tape and Reel
Option: Blank = Standard packaging (tray)
T = Tape and Reel (Note 1)
Temperature
Range: Blank = 0C to +70C (Commercial)
I= -40C to +85C (Industrial)
Package: MR = 64-pin VQFN
Examples:
a) USB5734/MR
Tray, Commercial temp., 64-pin VQFN
b) USB5734-I/MR
Tray, Industrial temp., 64-pin VQFN
c) USB5734T-I/MR
Tape & reel, Industrial temp., 64-pin VQFN
d) USB5734T/MR
Tape & reel, Commercial temp., 64-pin VQFN
Note 1: Tape and Reel identifier only appears in
the catalog part number description. This
identifier is used for ordering purposes and
is not printed on the device package.
Check with your Microchip Sales Office for
package availability with the Tape and Reel
option.
PART NO.
Device Tape & Reel
/
Temperature
Range
XX
[X] [-X]
Package
Option
2015-2017 Microchip Technology Inc. DS00001854E-page 59
USB5734
Information contained in this publication regarding device applications and the like is provided only for your convenience and may be super-
seded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REP-
RESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE,
MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Micro-
chip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold
harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or
otherwise, under any Microchip intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, AnyRate, AVR, AVR logo, AVR Freaks, BeaconThings, BitCloud, CryptoMemory, CryptoRF,
dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KEELOQ, KEELOQ logo, Kleer, LANCheck, LINK MD, maXStylus, maXTouch, MediaLB, megaAVR,
MOST, MOST logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip Designer, QTouch, RightTouch, SAM-BA, SpyNIC,
SST, SST Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and
other countries.
ClockWorks, The Embedded Control Solutions Company, EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS, mTouch, Precision
Edge, and Quiet-Wire are registered trademarks of Microchip Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo, CodeGuard,
CryptoAuthentication, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN,
EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, Mindi, MiWi, motorBench,
MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit,
PICtail, PureSilicon, QMatrix, RightTouch logo, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher,
SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.
Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other
countries.
All other trademarks mentioned herein are property of their respective companies.
© 2015-2017, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.
ISBN: 9781522413721
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, micro perip hera ls, nonvolat ile memor y and
analog products . I n additio n, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
QUALITYMANAGEMENTS
YSTEM
CERTIFIEDBYDNV
== ISO/TS16949==
2015-2017 Microchip Technology Inc. DS00001854E-page 60
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Tel: 86-756-3210040
Fax: 86-756-3210049
India - Bangalore
Tel: 91-80-3090-4444
Fax: 91-80-3090-4123
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
India - Pune
Tel: 91-20-3019-1500
Japan - Osaka
Tel: 81-6-6152-7160
Fax: 81-6-6152-9310
Japan - Tokyo
Tel: 81-3-6880- 3770
Fax: 81-3-6880-3771
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
Taiwan - Hsin Chu
Tel: 886-3-5778-366
Fax: 886-3-5770-955
Taiwan - Kaohsiung
Tel: 886-7-213-7830
Taiwan - Taipei
Tel: 886-2-2508-8600
Fax: 886-2-2508-0102
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
EUROPE
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
Finland - Espoo
Tel: 358-9-4520-820
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
France - Saint Cloud
Tel: 33-1-30-60-70-00
Germany - Garching
Tel: 49-8931-9700
Germany - Haan
Tel: 49-2129-3766400
Germany - Heilbronn
Tel: 49-7131-67-3636
Germany - Karlsruhe
Tel: 49-721-625370
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Germany - Rosenheim
Tel: 49-8031-354-560
Israel - Ra’anana
Tel: 972-9-744-7705
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Italy - Padova
Tel: 39-049-7625286
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Norway - Trondheim
Tel: 47-7289-7561
Poland - Warsaw
Tel: 48-22-3325737
Romania - Bucharest
Tel: 40-21-407-87-50
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
Sweden - Gothenberg
Tel: 46-31-704-60-40
Sweden - Stockholm
Tel: 46-8-5090-4654
UK - Wokingham
Tel: 44-118-921-5800
Fax: 44-118-921-5820
Worldwide Sales and Service
11/07/16
