ASM1233D-L-5 - ON Semiconductor L.L.C.

August, 2011 − Rev. 3

1Publication Order Number:

ASM1233D/D

ASM1233D, ASM1233D-L,

ASM1233M

Low Power, 5 V/3.3 V,

mP Reset, Active LOW,

Open-Drain Output

Description

The ASM1233D−L/1233D/1233M are voltage supervisors with

low−power, 5/3.3 V mP Reset, with an active LOW, open−drain output.

Maximum supply current over temperature is 15 mA for 3.3 V devices

and 20 mA for 5 V devices.

The ASM1233D−L/1233D/1233M generates an active LOW reset

signal whenever the monitored supply is out of tolerance. A precision

reference and comparator circuit monitors power supply (VCC) level.

The tolerances are 5%, 10% and 15%. When an out−of−tolerance

condition is detected, an internal power−fail signal is generated which

forces an active LOW reset signal. After VCC returns to an

in−tolerance condition, the reset signal remains active for 350 ms to

allow the power supply and system microprocessor to stabilize.

The ASM1233D−L/1233D/1233M is designed with an open drain

output stage and operates over the extended industrial temperature

range. These devices are available in compact SOT−223, SO−8 and

TO−92 packages.

Other low power products in this family include ASM1810/11/12/

15/16/17.

Features

•Low Supply Current

•15 mA Maximum (≤ 3.6 V), 20 mA Maximum (5.5 V)

•Automatically Restarts a Microprocessor after Power Failure

•350 ms Reset Delay after VCC Returns to an In−tolerance Condition

•Active LOW Power−up Reset, 5 kW Internal Pull−up

•Precision Temperature−compensated Voltage Reference and

Comparator

•Eliminates External Components

•Low−cost SOT−223/SO−8/TO−92 Packages

•Operating Temperature: −40°C to +85°C

Applications

•Set−top Boxes

•Cellular Phones

•PDAs

•Energy Management Systems

•Embedded Control Systems

•Printers

•Single Board Computers

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PIN CONFIGURATIONS

See detailed ordering and shipping information in the package

dimensions section on page 9 of this data sheet.

ORDERING INFORMATION

SOIC−8

8 LEAD

CASE 751BD

RESET

VCC

GND

ASM1233M

SO−8

(Top View)

TO−92

ASM1233M

SOT−223

4 LEAD

CASE 318E

TO−92

3 LEAD

CASE 29−11

SOT−223

(Top View)

ASM1233D−L

ASM1233D

GND

RESET

VCC

GND 1

GND

RESET

VCC

GND

RESET

VCC

123 123 123

TO−92

ASM1233D−L

ASM1233D

(Top View)

ASM1233D, ASM1233D−L, ASM1233M

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Figure 1. Typical Operating Circuit

Figure 2. Block Diagram

ASM1233D, ASM1233D−L, ASM1233M

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Table 1. PIN DESCRIPTION

Pin #

Pin Name Description

TO−92

ASM1233D−L

ASM1233D

TO−92

ASM1233M SO−8 SOT−223

1 3 4 1,4 GND Ground.

2 1 1 2 RESET Active LOW reset output.

3 2 2 3 VCC Power supply input.

3, 5, 6, 7 & 8 NC No connection.

Table 2. ABSOLUTE MAXIMUM RATINGS

Parameter Min Max Unit

Voltage on VCC (Note 1) −0.5 7 V

Voltage on RESET (Note 1) −0.5 VCC + 0.5 V

Operating Temperature Range −40 +85 °C

Soldering Temperature (for 10 sec) +260 °C

Storage Temperature −55 +125 °C

ESD rating HBM 2 KV

MM 200 V

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

1. Voltages are measured with respect to ground.

ASM1233D, ASM1233D−L, ASM1233M

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Table 3. DC ELECTRICAL CHARACTERISTICS (Unless otherwise noted, VCC = 5 V ±10% and specifications are over the

operating temperature range of −40°C to +85°C. All voltages are referenced to ground.) (Note 2)

Parameter Symbol Conditions Min Typ Max Unit

Supply Voltage VCC 1.2 5.5 V

Output Voltage VOL RESET asserted 0.4 V

VOH IOUT < 500 mAVCC−0.5 V VCC−0.1 V

Output Current IOL Output = 0.4 V 8 mA

Operating Current ICC VCC < 5.5 V, RESET output open 8 20 mA

VCC ≤ 3.6 V, RESET output open 6 15

VCC Trip Point VCCTP ASM1233D−LZ−5 2.98 3.06 3.15 V

ASM1233D−LZ−10 2.8 2.88 2.97

ASM1233D−LZ−15 2.64 2.72 2.8

ASM1233DZ−5 4.5 4.625 4.74

ASM1233DZ−10 4.25 4.375 4.49

ASM1233DZ−15 4.0 4.125 4.24

ASM1233M−5 4.25 4.375 4.49

ASM1233M−55 4.5 4.625 4.75

ASM1233M−3 2.64 2.72 2.8

Voltage High Trip Level VHTL ASM1233D, ASM1233MS−5,

ASM1233MS−55

4.75 V

ASM1233MS−3 3.14

ASM1233D−L 3.06

Voltage Low Trip Level VLTL ASM1233D, ASM1233MS−5,

ASM1233MS−55

4.00 V

ASM1233MS−3 2.48

ASM1233D−L 2.3

Internal Pull−up Resistor RP3.5 5.0 7.5 kW

Output Capacitance COUT 10 pF

VCC Detect to

RESET Low

tRPD 2 10 ms

VCC Detect to

RESET High

tRPU ASM1233D−L, ASM1233M 200 350 500 ms

ASM1233D 250 350 450

VCC Slew Rate

(VHTL − VLTL)

tF300 ms

VCC Slew Rate

(VLTL − VHTL)

tR0 ns

2. A 1 kW resistor may be required in some applications for proper operation of the microprocessor reset control circuit.

ASM1233D, ASM1233D−L, ASM1233M

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Table 4. FAMILY SELECTION GUIDE

Part # RESET Voltage (V) RESET Time (ms) Output Stage RESET Polarity

ASM1810 4.620, 4.370, 4.120 150 Push−Pull LOW

ASM1811 4.620, 4.350, 4.130 150 Open−Drain LOW

ASM1812 4.620, 4.350, 4.130 150 Push−Pull HIGH

ASM1815 3.060, 2.880, 2.550 150 Push−Pull LOW

ASM1816 3.060, 2.880, 2.550 150 Open−Drain LOW

ASM1817 3.060, 2.880, 2.550 150 Push−Pull HIGH

ASM1233D 4.625, 4.375, 4.125 350 Open−Drain LOW

ASM1233M 4.625, 4.375, 2.720 350 Open−Drain LOW

ASM1233D−L3.060, 2.880, 2.720 350 Open−Drain LOW

Application Information

Operation − Power Monitor

The ASM1233D−L/1233D/1233M detects out−of−

tolerance Power supply conditions. It resets a processor

during powerup, Power−down and generates a reset to the

system Processor when the monitored power supply voltage

is below the reset threshold. When an out−of−tolerance VCC

voltage is detected, the RESET signal is asserted. On

power−up, RESET is kept active (LOW) for approximately

350 ms after the power supply voltage has reached the

selected tolerance. This allows the power supply and

microprocessor to stabilize before RESET is released.

Figure 3. Timing Diagram: Power−Up Figure 4. Timing Diagram: Power−Down

ASM1233D, ASM1233D−L, ASM1233M

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PACKAGE DIMENSIONS

SOT−223 (TO−261)

CASE 318E−04

ISSUE N

123

0.08 (0003)

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: INCH.

1.5

0.059 ǒmm

inchesǓ

SCALE 6:1

3.8

0.15

2.0

0.079

6.3

0.248

2.3

0.091

2.3

0.091

2.0

0.079

SOLDERING FOOTPRINT

DIM

MIN NOM MAX MIN

MILLIMETERS

1.50 1.63 1.75 0.060

INCHES

A1 0.02 0.06 0.10 0.001

b0.60 0.75 0.89 0.024

b1 2.90 3.06 3.20 0.115

c0.24 0.29 0.35 0.009

D6.30 6.50 6.70 0.249

E3.30 3.50 3.70 0.130

e2.20 2.30 2.40 0.087

0.85 0.94 1.05 0.033

0.064 0.068

0.002 0.004

0.030 0.035

0.121 0.126

0.012 0.014

0.256 0.263

0.138 0.145

0.091 0.094

0.037 0.041

NOM MAX

L1 1.50 1.75 2.00 0.060

6.70 7.00 7.30 0.264

0.069 0.078

0.276 0.287

− −

0°10°0°10°

L0.20 −−− −−− 0.008 −−− −−−

ASM1233D, ASM1233D−L, ASM1233M

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PACKAGE DIMENSIONS

TO−92 (TO−226)

CASE 29−11

ISSUE AM

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. CONTOUR OF PACKAGE BEYOND DIMENSION R

IS UNCONTROLLED.

4. LEAD DIMENSION IS UNCONTROLLED IN P AND

BEYOND DIMENSION K MINIMUM.

SECTION X−X

SEATING

PLANE DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A0.175 0.205 4.45 5.20

B0.170 0.210 4.32 5.33

C0.125 0.165 3.18 4.19

D0.016 0.021 0.407 0.533

G0.045 0.055 1.15 1.39

H0.095 0.105 2.42 2.66

J0.015 0.020 0.39 0.50

K0.500 --- 12.70 ---

L0.250 --- 6.35 ---

N0.080 0.105 2.04 2.66

P--- 0.100 --- 2.54

R0.115 --- 2.93 ---

V0.135 --- 3.43 ---

STRAIGHT LEAD

BULK PACK

ASM1233D, ASM1233D−L, ASM1233M

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PACKAGE DIMENSIONS

SOIC 8, 150 mils

CASE 751BD−01

ISSUE O

E1 E

PIN # 1

IDENTIFICATION

TOP VIEW

SIDE VIEW END VIEW

Notes:

(1) All dimensions are in millimeters. Angles in degrees.

(2) Complies with JEDEC MS-012.

SYMBOL MIN NOM MAX

0º 8º

0.10

0.33

0.19

0.25

4.80

5.80

3.80

1.27 BSC

1.75

0.25

0.51

0.25

0.50

5.00

6.20

4.00

L0.40 1.27

1.35

ASM1233D, ASM1233D−L, ASM1233M

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Table 5. ORDERING INFORMATION

Part Number

RESET

Output

Voltage

RESET

Tolerance

RESET

Time

Open

Drain

Output

RESET

Polarity Package Package Marking

TIN − LEAD DEVICES

ASM1233D−L−5

(ASM1233A−5)

3.06 5% 350 ms ♦LOW 3L TO−92 ASM1233D−L−5

ASM1233D−L−10

(ASM1233A−10)

2.88 10% 350 ms ♦LOW 3L TO−92 ASM1233D−L−10

ASM1233D−L−15

(ASM1233A−15)

2.72 15% 350 ms ♦LOW 3L TO−92 ASM1233D−L−15

ASM1233D−LZ−5

(ASM1233AZ−5)

3.06 5% 350 ms ♦LOW 4L SOT−223 RVLL

ASM1233D−LZ−10

(ASM1233AZ−10)

2.88 10% 350 ms ♦LOW 4L SOT−223 RWLL

ASM1233D−LZ−15

(ASM1233AZ−15)

2.72 15% 350 ms ♦LOW 4L SOT−223 RXLL

ASM1233D−5 4.625 5% 350 ms ♦LOW 3L TO−92 ASM1233D−5

ASM1233D−10 4.375 10% 350 ms ♦LOW 3L TO−92 ASM1233D−10

ASM1233D−15 4.125 15% 350 ms ♦LOW 3L TO−92 ASM1233D−15

ASM1233DZ−5 4.625 5% 350 ms ♦LOW 4L SOT−223 RSLL

ASM1233DZ−10 4.375 10% 350 ms ♦LOW 4L SOT−223 RTLL

ASM1233DZ−15 4.125 15% 350 ms ♦LOW 4L SOT−223 RULL

ASM1233M−55 4.625 5% 350 ms ♦LOW 3L TO−92 ASM1233M−55

ASM1233M−5 4.375 10% 350 ms ♦LOW 3L TO−92 ASM1233M−5

ASM1233M−3 2.72 15% 350 ms ♦LOW 3L TO−92 ASM1233M−3

ASM1233MS−55 4.625 5% 350 ms ♦LOW 8L SOIC ASM1233MS−55

ASM1233MS−5 4.38 10% 350 ms ♦LOW 8L SOIC ASM1233MS−5

ASM1233MS−3 2.72 15% 350 ms ♦LOW 8L SOIC ASM1233MS−3

LEAD FREE DEVICES

ASM1233D−L−5F 3.06 5% 350 ms ♦LOW 3L TO−92 ASM1233D−L−5F

ASM1233D−L−10F 2.88 10% 350 ms ♦LOW 3L TO−92 ASM1233D−L−10F

ASM1233D−L−15F 2.72 15% 350 ms ♦LOW 3L TO−92 ASM1233D−L−15F

ASM1233D−LZ−5F 3.06 5% 350 ms ♦LOW 4L SOT−223 KVLL

ASM1233D−LZ−10F 2.88 10% 350 ms ♦LOW 4L SOT−223 KWLL

ASM1233D−LZ−15F 2.72 15% 350 ms ♦LOW 4L SOT−223 KXLL

ASM1233D−5F 4.625 5% 350 ms ♦LOW 3L TO−92 ASM1233D−5F

ASM1233D−10F 4.375 10% 350 ms ♦LOW 3L TO−92 ASM1233D−10F

ASM1233D−15F 4.125 15% 350 ms ♦LOW 3L TO−92 ASM1233D−15F

ASM1233DZ−5F 4.625 5% 350 ms ♦LOW 4L SOT−223 KSLL

ASM1233DZ−10F 4.375 10% 350 ms ♦LOW 4L SOT−223 KTLL

ASM1233DZ−15F 4.125 15% 350 ms ♦LOW 4L SOT−223 KULL

ASM1233M−5F 4.375 5% 350 ms ♦LOW 3L TO−92 ASM1233M−5F

ASM1233M−55F 4.625 10% 350 ms ♦LOW 3L TO−92 ASM1233M−55F

ASM1233M−3F 2.72 15% 350 ms ♦LOW 3L TO−92 ASM1233M−3F

ASM1233MS−5F 4.38 5% 350 ms ♦LOW 8L SOIC ASM1233MS−5F

ASM1233MS−55F 4.625 10% 350 ms ♦LOW 8L SOIC ASM1233MS−55F

ASM1233MS−3F 2.72 15% 350 ms ♦LOW 8L SOIC ASM1233MS−3F

ASM1233D, ASM1233D−L, ASM1233M

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ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should

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ASM1233D/D

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