Data Sheet January 1997 T7296 DS3/STS-1/E3 Integrated Line Transmitter Features Fully integrated transmit interface for DS3, STS-1, or E3 applications Integrated pulse shaping circuit Intended for systems which must comply with AT&T CB119, ITU-T G.703, and ITU-T G.824, Bellcore TR-NWT-000499, ANSI T1.404 Built-in B3ZS/HDB3 encoder and decoder Remote and local loopback functions Single 5 V power supply Applications Interface for SONET, DS3, and E3 network equipment Digital cross connect systems CSU/DSU equipment PCM test equipment Fiber-optic terminals Multiplexers Description The T7296 is a fully integrated PCM line-driver IC intended for DS3 (44.736 Mbits/s), SONET STS-1 (51.84 Mbits/s), or E3 (34.368 Mbits/s) applications. The IC is designed to complement the T7295-6 DS3/ SONET STS-1 or T7295-1 E3 Integrated Line Receivers. The T7296 converts input clock and dualrail unipolar data into AMI pulses according to AT&T Technical Advisory No. 34 or ITU-T G.703 recommendations. The device provides B3ZS (DS3) or HDB3 (E3) encoding functions for data to be transmitted to the line. A complementary decoder circuit is also included in the T7296 for decoding received signals from an external line receiver. Both encoder and decoder functions can be disabled independently with external control pins. In the receive direction, coding errors and bipolar violations are detected and flagged at an output pin. On-chip pulse shaper circuitry eliminates the need for external components for line equalization to meet the cross connect template (DSX-3 and STSX-1). For system-level trouble shooting and testing, both transmit and receive loopbacks are possible with the builtin loopback circuit. The T7296 is manufactured in a BiCMOS technology and is packaged in 28-pin, plastic DIP and SOJ packages. The device requires a single 5 V power supply and dissipates a maximum power of 700 mW. T7296 DS3/STS-1/E3 Integrated Line Transmitter Data Sheet January 1997 Description (continued) VDDD VDDA GNDD GNDA ICT TAOS TXLEV ENCODIS TPDATA AMP1 TTIP AMP2 TRING PULSE SHAPER B3ZS/HDB3 ENCODER TNDATA TCLK DECODIS RNEG DMO LOOPBACK MUX RNRZ B3ZS/HDB3 DECODER DRIVER MONITOR MRING MTIP RPOS RCLK RCLKO RPDATA RNDATA BPV DS3, STS-1/E3 LLOOP RLOOP 5-2140(C)r.5 Figure 1. Block Diagram Pin Information RCLK 1 28 RNDATA RLOOP 2 27 RPDATA LLOOP 3 26 ICT DS3, STS-1/E3 4 25 TXLEV TAOS 5 24 VDDA VDDD 6 23 TTIP TPDATA 7 22 TRING TNDATA 8 21 GNDA TCLK T7296 9 20 MTIP GNDD 10 19 MRING ENCODIS 11 18 DMO DECODIS 12 17 RCLKO BPV 13 16 RPOS RNRZ 14 15 RNEG 5-2141(C)r.4 Figure 2. Pin Diagram 2 Lucent Technologies Inc. Data Sheet January 1997 T7296 DS3/STS-1/E3 Integrated Line Transmitter Pin Information (continued) Table 1. Pin Descriptions Pin 1 2 Symbol RCLK RLOOP 3 LLOOP 4 DS3, STS-1/E3 5 TAOS 6 7 VDDD TPDATA 8 TNDATA 9 10 11 TCLK GNDD ENCODIS 12 13 DECODIS BPV 14 RNRZ 15 16 17 18 RNEG RPOS RCLKO DMO 19 MRING 20 MTIP 21 22 GNDA TRING 23 TTIP 24 VDDA Type Name/Function I Receive Clock Input. Input sampling clock for RPDATA and RNDATA. I Remote Loopback. A high on this pin causes RPDATA and RNDATA to be transmitted to the line using RCLK. Setting LLOOP and RLOOP high simultaneously is not permitted. I Local Loopback. A high on this pin causes TPDATA and TNDATA to pass through the encoder and output at RPOS and RNEG, respectively. Setting LLOOP and RLOOP high simultaneously is not permitted. I DS3, STS-1, or E3 Select. A high on this pin selects DS3 or STS-1 operation and sets the encoder and decoder in B3ZS mode. A low selects E3 operation and sets the encoder and decoder in HDB3 mode. I Transmit All 1s Select. A high on this pin causes a continuous AMI all-1s pattern to be transmitted to the line. The frequency is determined by TCLK. -- 5 V Digital Supply (5%). For all logic circuitry. I Transmit Positive Data. TPDATA is sampled on the falling edge of TCLK. Pins 7 and 8 can be tied together for binary input signals. I Transmit Negative Data. TNDATA is sampled on the falling edge of TCLK. Pins 7 and 8 can be tied together for binary input signals. I Transmit Clock for TPDATA and TNDATA. -- Digital Ground. For all logic circuitry. I Encoder Disable. A high on this pin disables B3ZS or HDB3 encoding functions, unless overridden by a TAOS request. Set ENCODIS high if TPDATA and TNDATA are already encoded. I Decoder Disable. A high on this pin disables B3ZS or HDB3 decoding functions. O Bipolar Violation Output. This pin goes high for one bit period when a bipolar violation or a coding error not corresponding to the appropriate coding rule is detected in the RPDATA/RNDATA signals. O Receive Binary Data. The signal on this pin is the ORed-output of RPOS and RNEG. O Receive Negative Data. This signal is the decoded version of RNDATA.* O Receive Positive Data. This signal is the decoded version of RPDATA.* O Receive Clock Output. This signal is the inverted version of RCLK. O Driver Monitor Output. If no transmitted AMI signal is present on MTIP and MRING for 128 32 TCLK clock periods, DMO goes high until the next AMI signal is detected. Iu Monitor Ring Input. AMI signal from TRING can be connected to this pin for line driver failure detection. Internally pulled high. u I Monitor Tip Input. AMI signal from TTIP can be connected to this pin for line driver failure detection. Internally pulled high. -- Analog Ground. For analog circuitry. O Transmit Ring Output. Transmit AMI signal is driven to the line via a 1:1 transformer from this pin. O Transmit Tip Output. Transmit AMI signal is driven to the line via a 1:1 transformer from this pin. -- 5 V Analog Supply (5%). For analog circuitry. * If a bipolar violation occurs, RPOS and RNEG can correspond to decoded versions of RPDATA and RNDATA, respectively. If DECODIS is high, RPOS and RNEG always track RPDATA and RNDATA, respectively. Note: Pins with the Iu designation have an internal pull-up. Lucent Technologies Inc. 3 T7296 DS3/STS-1/E3 Integrated Line Transmitter Data Sheet January 1997 Pin Information (continued) Table 1. Pin Descriptions (continued) Pin 25 Symbol TXLEV 26 ICT 27 RPDATA 28 RNDATA Type Name/Function I Transmit Level Select. The output signal amplitude at TTIP and TRING can be varied by setting this pin high or low. When the cable length is greater than 120 ft., TXLEV should be set high. When it is below 120 ft., it should be set low. This pin is active only when the DS3, STS-1/E3 input (pin 4) is set high (DS3, STS-1 mode). Iu In-Circuit Testing (Active-Low). A low at this pin causes all digital and analog outputs to go into a high-impedance state to allow for in-circuit testing. Internally pulled high. I Receive Positive Data. NRZ input data to the decoder block. Sampled on the falling edge of RCLK. I Receive Negative Data. NRZ input data to the decoder block. Sampled on falling edge of RCLK. * If a bipolar violation occurs, RPOS and RNEG can correspond to decoded versions of RPDATA and RNDATA respectively. If DECODIS is high, RPOS and RNEG always track RPDATA and RNDATA, respectively. Note: Pins with the Iu designation have an internal pull-up. Overview T7295-6 RIN 0.01 F 728A CABLE 75 SHIELD BEAD* 1 RCLK RNDATA 28 2 RLOOP RPDATA 27 3 LLOOP 4 DS3,STS-1/E3 5 TAOS +5 V FROM SYSTEM 0.1 F 6 VDDD 36 ICT 26 TXLEV 25 T1 VDDA 24 TTIP 23 7 TPDATA TRING 22 8 TNDATA GNDA 21 9 TCLK MTIP 20 10 GNDD MRING 19 11 ENCODIS DMO 18 12 DECODIS RCLKO 17 13 BPV RPOS 16 14 RNRZ RNEG 15 728A CABLE 0.1 F 36 TO SYSTEM 5-2142(C)r.8 * Shield bead is the FairRite 2643000101 or equivalent. Output transformer Pulse Engineering PE-65966 (through-hole) or PE-65967 (surface mount) or equivalent. FairRite is a registered trademark of FairRite Products Corporation. Pulse Engineering is a registered trademark of Pulse Engineering, Inc. Note: Lucent Technologies does not endorse the use of or assume liability for the use of any bead or transformer. Figure 3. T7296 Application DS3 Mode, Less Than 120 Feet of Cable 4 Lucent Technologies Inc. Data Sheet January 1997 T7296 DS3/STS-1/E3 Integrated Line Transmitter Overview (continued) B3ZS/HDB3 Decoder System Description The decoder block is included to perform B3ZS or HDB3 decoding as determined by the state of the DS3, STS-1/E3 pin. In the B3ZS format, the decoder detects both B0V and 00V codes and replaces them with 000 data. If HDB3 decoding is selected by setting the DS3, STS-1/E3 pin low, the B00V and 000V codes are detected and replaced with the 0000 code. In both cases, bipolar violation and coding errors that do not conform to the coding scheme are detected and indicated at the BPV output pin. B3ZS/HDB3 Encoder Data to be transmitted is input to the encoder block to be encoded either in B3ZS or HDB3 as determined by the state of the DS3, STS-1/E3 pin. Input data format can be unipolar or binary. For binary signals, TPDATA and TNDATA need to be connected together externally. The line code used for DS3 is B3ZS. In this mode, each block of three consecutive zeros is removed and replaced by one of two codes that contain bipolar violations. These replacement codes are B0V and 00V, where B indicates a pulse conforming with the bipolar rule, and V represents a pulse violating the rule. The choice of these codes is made such that an odd number of B pulses will be transmitted between consecutive bipolar violation (BPV) pulses. For E3 format, the line code is HDB3. The encoding rule of HDB3 is similar to B3ZS except that the number of consecutive zeros is increased to four before a code replacement can take place. The replacement codes in this case are 000V and B00V. STS-1 operation is achieved by placing the part in the DS3 mode and using 51.84 MHz clocks. Logic operation for STS-1 is the same for DS3. Decoder Disable For testing purposes and in applications where the decoder needs to be bypassed, the decoder can be disabled by setting DECODIS high. In this mode, all bipolar violation pulses are indicated at the BPV pin. Bipolar Violation Detection The BPV pin goes high for one bit period when a code error or a bipolar violation not corresponding to the appropriate coding rule is detected on the RPDATA/ RNDATA signal. The violation pulse is always removed from the decoder outputs RPOS/RNEG when DECODIS is set low. Pulse Shaper Transmit All 1s Select Setting RLOOP high causes received RPDATA and RNDATA to be transmitted to the line through TTIP and TRING. The data rate is determined by RCLK. In this mode, TPDATA and TNDATA are ignored. The pulse shaper circuit uses a combination of filters and slew-rate control techniques to preshape the pulse to be transmitted to the line. The amplitude of the transmit pulse can be adjusted by using the TXLEV (transmit level) pin. When the distance to the cross connect exceeds 120 ft., TXLEV should be set high. When the distance is less than 120 ft., TXLEV should be set low. Setting TXLEV high enables the transmitter to send out a nominal 1.0 V peak pulse. Setting TXLEV low enables the transmitter to send out a nominal 850 mV peak pulse. The state of the TXLEV pin has no effect on E3 operation. Local Loopback Driver Monitor Setting LLOOP high causes TPDATA and TNDATA to go through both the encoder and the decoder. In this mode, the signals transmitted on RCLKO, RPOS, and RNEG correspond to those received on TCLK, TPDATA, and TNDATA, respectively. TPDATA and TNDATA are transmitted to the line unless overridden by a TAOS request. Setting both RLOOP and LLOOP high simultaneously is not permitted. Using TTIP and TRING as inputs, the driver monitor detects driver failure by monitoring the activities at MTIP and MRING. If no signal is detected on these pins for 128 32 TCLK cycles, DMO is set high until the next AMI signal is detected. Setting TAOS high causes continuous AMI encoded 1s to be transmitted to the line. In this mode, input TPDATA and TNDATA are ignored. If remote loopback (RLOOP) is set high, any TAOS request is ignored. Remote Loopback Lucent Technologies Inc. 5 T7296 DS3/STS-1/E3 Integrated Line Transmitter Data Sheet January 1997 DS3 Signal Requirements at the DSX For DS3 operation, pulse characteristics are specified at the DSX-3, which is an interconnection and test point referred to as the cross connect. The cross connect exists at the point where the transmitted signal reaches the distribution frame jack. The T7296 can transmit through 450 ft. of 728A cable to the DSX-3 in DS3 mode. Table 2 lists the signal requirements. Currently, two isolated pulse template requirements exist: the ANSI TI.404 pulse template (see Table 3 and Figure 4) and the Bellcore TR-NWT-000499 pulse template (see Table 4 and Figure 5). The pulse transmitted by the T7296 meets these templates. Table 2. DSX-3 Interconnection Specification Parameter Line Rate Line Code Test Load Pulse Shape Power Levels Specification 44.736 Mbits/s 20 ppm. Bipolar with three-0 substitution (B3ZS). 75 5%. An isolated pulse must fit the template in Figure 4 or Figure 5.* The pulse amplitude may be scaled by a constant factor to fit the template. The pulse amplitude must be between 0.36 V pk and 0.85 V pk, measured at the center of the pulse. For an all-1s transmitted pattern, the power at 22.368 MHz 0.002 MHz must be -1.8 dBm to +5.7 dBm, and the power at 44.736 MHz 0.002 MHz must be -21.8 dBm to -14.3 dBm. * The pulse template in G.703 is shown in Figure 5 and specified in Table 4. The proposed G.703 further states that the voltage in a time slot containing a zero must not exceed 5% of the peak pulse amplitude, except for the residue of preceding pulses. The power levels specified by the proposed G.703 are identical except that the power is to be measured in 3 kHz bands. The all-1s pattern must be a pure all-1s signal, without framing or other control bits. Table 3. DSX-3 Pulse Template Boundaries for ANSI TI.404 (See Figure 4.) Lower Curve Upper Curve Time Equation Time Equation T -0.36 -0.03 T -0.68 +0.03 T 0.5 1 + sin --- 1 + ----------- 0- 0.03 2 0.18 -0.36 T +0.36 +0.36 T -0.03 -0.68 T +0.36 T 0.5 1 + sin --- 1 + ----------- ++ 0.03 2 0.34 +0.36 T 0.05 + 0.407e-1.84[T - 0.36] 1.2 NORMALIZED AMPLITUDES 1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -1.0 -0.5 0 0.5 1.0 1.5 TIME SLOTS--NORMALIZED TO PEAK LOCATION 5-1242(C)r.4 Figure 4. DSX-3 Isolated Pulse Template for ANSI T1.404 6 Lucent Technologies Inc. Data Sheet January 1997 T7296 DS3/STS-1/E3 Integrated Line Transmitter DS3 Signal Requirements at the DSX (continued) Table 4. DSX-3 Pulse Template Boundaries for Bellcore TR-NWT-000499 (See Figure 5.) Lower Curve Upper Curve Time Equation Time Equation -0.85 T -0.36 -0.03 -0.85 T -0.68 +0.03 T 0.5 1 + sin --- 1 + ----------- 0- 0.03 2 0.18 -0.36 T +0.36 +0.36 T +1.4 T 0.5 1 + sin --- 1 + ----------- 0+ 0.03 2 0.34 -0.68 T +0.36 +0.36 T +1.4 -0.03 0.08 + 0.407e-1.84[T - 0.36] 1.2 NORMALIZED AMPLITUDES 1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -1.0 -0.5 0 0.5 1.0 1.5 TIME SLOTS--NORMALIZED TO PEAK LOCATION 5-3755(C).a Figure 5. DSX-3 Isolated Pulse Template for Bellcore TR-NWT-000499 Lucent Technologies Inc. 7 T7296 DS3/STS-1/E3 Integrated Line Transmitter Data Sheet January 1997 STS-1 Signal Requirements at the STSX-1 For STS-1 operation, pulse characteristics are specified at the STSX-1, which is an interconnection and test point referred to as the cross connect. The cross connect exists at the point where the transmitted signal reaches the distribution frame jack. The T7296 can transmit through 450 ft. of 728A cable to the STSX-1 in STS-1 mode. An isolated pulse template is specified per ANSI T1.102 standards (see Figure 6). The pulse transmitted by the T7296 meets this template. Table 5. STSX-1 Interconnection Specification Parameter Line Rate Line Code Test Load Power Levels Specification 51.84 Mbits/s. Bipolar with three-0 substitution (B3ZS). 75 5%. A wide-band power level measurement at the STSX-1 interface using a low-pass filter with a 3 dB cutoff frequency of at least 200 MHz is within -2.7 dBm and 4.7 dBm. Table 6. Pulse Template Boundaries for ANSI T1.102 (See Figure 6.) Lower Curve Upper Curve Time Equation Time Equation -0.85 T -0.38 -0.03 -0.85 T -0.68 +0.03 -0.38 T +0.36 T 0.5 1 + sin --- 1 + ----------- 0- 0.03 2 0.18 +0.36 T +1.4 -0.03 -0.68 T +0.26 T 0.5 1 + sin --- 1 + ----------- ++ 0.03 2 0.34 +0.26 T +1.4 0.1 + 0.61e-2.4[T - 0.26] 1.2 NORMALIZED AMPLITUDES 1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -1.0 -0.5 0 0.5 1.0 1.5 TIME SLOTS--NORMALIZED TO PEAK LOCATION 5-3755(C)r.1 Figure 6. STSX-1 Isolated Pulse Template for ANSI T1.102 8 Lucent Technologies Inc. Data Sheet January 1997 T7296 DS3/STS-1/E3 Integrated Line Transmitter E3 Signal Requirements For E3 operation, pulse characteristics are defined below. Table 6 lists the signal requirements, and Figure 7 illustrates the isolated pulse template requirements as specified in the ITU-T recommendation G.703. The pulse transmitted by the T7296 meets this template. Table 7. E3 Pulse Specifications Parameter Pulse Shape (nominally rectangular) Value All marks of a valid signal must conform with the mask (see Figure 7), regardless of the sign. Test Load Impedance 75 resistive. Nominal Peak Voltage of a Mark (pulse) 1.0 V. Peak Voltage of a Space (no pulse) 0 V 0.1 V. Nominal Pulse Width 14.55 ns. Ratio of the Amplitudes of Positive and Negative Pulses 0.95 to 1.05. at the Center of a Pulse Interval Ratio of the Widths of Positive and Negative Pulses at 0.95 to 1.05. Nominal Half-Amplitude 17 ns (14.55 + 2.45) V 0.2 1.0 0.1 8.65 ns (14.55 - 5.90) 0.1 0.2 NOMINAL PULSE 14.55 ns 0.5 12.1 ns (14.55 - 2.45) 24.5 ns (14.55 + 9.95) 0.1 0.1 0 0.1 0.1 0.2 29.1 ns (14.55 + 14.55) 5-2638(C)r.5 Figure 7. Isolated E3 Pulse Template for G.703 Standards Lucent Technologies Inc. 9 T7296 DS3/STS-1/E3 Integrated Line Transmitter Data Sheet January 1997 Absolute Maximum Ratings Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability. Parameter Power Supply Storage Temperature Power Dissipation Plastic SOJ Package Power Dissipation Plastic DIP Package Input Voltage (any pin) Input Current (any pin) Symbol VDD Tstg Pdiss Pdiss -- -- Min -0.5 -65 -- -- -0.5 -- Max 6.5 150 725 1 VDD + 0.5 10 Unit V C mW W V mA Handling Precautions Although protection circuitry has been designed into this device, proper precautions should be taken to avoid exposure to electrostatic discharge (ESD) during handling and mounting. Lucent Technologies Microelectronics Group employs a human-body model (HBM) and a charged-device model (CDM) for ESD-susceptibility testing and protection design evaluation. ESD voltage thresholds are dependent on the circuit parameters used to define the model. No industry-wide standard has been adopted for the CDM. A standard HBM (resistance = 1500 , capacitance = 100 pF) is widely accepted and can be used for comparison. The HBM ESD threshold presented here was obtained by using these circuit parameters: HBM ESD Threshold Device Voltage T7296 >2000 V Electrical Characteristics Test conditions: VDD = 5 V 5%, TA = -40 C to +85 C, unless otherwise specified. Table 8. dc Electrical Characteristics Parameter dc Supply Voltage Supply Current* Input Low Voltage Input High Voltage Output Low Voltage: Iout -4.0 mA Output High Voltage: Iout 3.0 mA Input Leakage Current (all pins except MRING, MTIP, and ICT) Input Leakage Current (MRING, MTIP, and ICT pins at 0 V) Input Capacitance Load Capacitance Symbol VDDD, VDDA -- VIL VIH VOL Min 4.75 -- 0 0.7VDDD GNDD Typ 5 -- -- -- -- Max Unit 5.25 V 133 mA 0.5 V VDDD V 0.4 V VOH VDDD - 0.5 -- VDDD V IL IL CI CL -- -50 -- -- -- -- -- -- 10 -150 10 10 A A pF pF * Supply current is measured with transmitter sending an all-1s AMI signal and with transmit level (TXLEV) set high. 10 Lucent Technologies Inc. Data Sheet January 1997 T7296 DS3/STS-1/E3 Integrated Line Transmitter Timing Characteristics Test conditions: VDD = 5 V 5%, TA = -40 C to +85 C unless otherwise specified. All timing characteristics are measured with 10 pF loading. Table 9. Timing Specifications Symbol -- -- tR tF tTSU tTHO tTDY -- tR tF tRSU tRHO tR tF tRDY Parameter TCLK Clock Duty Cycle (DS3/STS-1) TCLK Clock Duty Cycle (E3) TCLK Clock Rise Time (10% to 90%) TCLK Clock Fall Time (90% to 10%) Setup Time: TPDATA/TNDATA to TCLK Falling Hold Time: TCLK Falling to TPDATA/TNDATA Propagation Delay: TCLK Rising to TTIP/TRING* RCLK Clock Duty Cycle RCLK Clock Rise Time (10% to 90%) RCLK Clock Fall Time (90% to 10%) Setup Time: RPDATA/RNDATA to RCLK Falling Hold Time: RCLK Falling to RPDATA/RNDATA RCLKO Clock Rise Time (10% to 90%) RCLKO Clock Fall Time (90% to 10%) Propagation Delay: RCLKO Rising to RPOS/RNEG/RNRZ Min 45 47 -- -- 4.0 5.0 0.6 45 -- -- 4.0 5.0 -- -- -- Typ 50 50 -- -- -- -- -- 50 -- -- -- -- -- -- -- Max 55 53 4.0 4.0 -- -- 14 55 4.0 4.0 -- -- 4.0 4.0 4.0 Unit % % ns ns ns ns ns % ns ns ns ns ns ns ns * When the encoder is enabled, a handling delay of four and a half TCLK clock cycles for B3ZS and five and a half clock cycles for HDB3 always exists between TPDATA/TNDATA and TTIP/TRING. The handling delay is reduced to two clock cycles when the encoder is disabled. When the decoder is enabled, a handling delay of six and a half RCLK clock cycles always exists between RPDATA/RNDATA and RPOS/ RNEG/RNRZ. The handling delay is reduced to one and a half RCLK clock cycles when the decoder is disabled. tR tF TCLK tTSU tTHO TPDATA OR TNDATA tTDY TTIP OR TRING 5-3587(C)r.1 Figure 8. Transmit System-Side Timing Diagram tR tF RCLK tRSU tRHO RPDATA OR RNDATA 5-3588(C)r.1 Figure 9. Receive Line-Side Timing Diagram Lucent Technologies Inc. 11 T7296 DS3/STS-1/E3 Integrated Line Transmitter Data Sheet January 1997 Timing Characteristics (continued) tR tF RCLKO tRDY RPOS/RNEG OR RNRZ 5-3589(C)r.1 Figure 10. Receive System-Side Timing Diagram 0 1 0 0 V 0 1 0 0 0 1 0 V 0 1 1 0 0 0 1 1 0 0 0 0 1 RPDATA RNDATA RPOS RNEG RNRZ 1 0 0 0 0 1 BPV BPV CORRESPONDING TO CODING RULE BPV NOT CORRESPONDING TO CODING RULE CODING ERROR 5-3590(C)r.1 Note: The delay from RPDATA/RNDATA to RPOS/RNEG/RNRZ is not shown in this figure. Figure 11. Example of Bipolar Violations for B3ZS Mode 12 Lucent Technologies Inc. Data Sheet January 1997 T7296 DS3/STS-1/E3 Integrated Line Transmitter Outline Diagrams 28-Pin, Plastic DIP Dimensions are in millimeters. L N B 1 W PIN #1 IDENTIFIER ZONE H SEATING PLANE 0.38 MIN 2.54 TYP 0.023 MAX 5-4410.R1 Number of Pins (N) Maximum Length (L) Maximum Width Without Leads (B) Package Dimensions (DIP) Maximum Width Including Leads (W) Maximum Height Above Board (H) 28 37.34 13.97 15.49 5.59 Lucent Technologies Inc. 13 T7296 DS3/STS-1/E3 Integrated Line Transmitter Data Sheet January 1997 Outline Diagrams (continued) 28-Pin, Plastic SOJ Dimensions are in millimeters. L N B 1 PIN #1 IDENTIFIER ZONE W H SEATING PLANE 0.10 1.27 TYP 0.020 MAX 0.64 MIN 5-4413.R1 Number of Pins (N) Maximum Length (L) Maximum Width Without Leads (B) Package Dimensions (SOJ) Maximum Width Including Leads (W) Maximum Height Above Board (H) 28 18.03 7.62 8.81 3.18 Ordering Information 14 Device Code Package Temperature Comcode (Ordering Number) T - 7296 - - - EL 28-Pin, Plastic SOJ -40 C to +85 C 106932056 T - 7296 - - - PL 20-Pin, Plastic DIP -40 C to +85 C 106932064 Lucent Technologies Inc. Data Sheet January 1997 T7296 DS3/STS-1/E3 Integrated Line Transmitter Standards Documentation ITU-T Telecommunication technical standards and reference documentation may be obtained from the following sources: International Telecommunication UnionTelecommunication Sector ANSI (U.S.A.): American National Standards Institute (ANSI) 11 West 42nd Street New York, NY 10036 Tel: 212-642-4900 FAX: 212-302-1286 AT&T Publications: AT&T Customer Information Center (CIC) Place des Nations CH 1211 Geneve 20, Switzerland Tel: 41-22-730-5285 FAX: 41-22-730-5991 TTC (Japan): TTC Standard Publishing Group of the Telecommunications Technology Committee 2nd Floor, Hamamatsucho - Suzuki Building, 1 2-11, Hamamatsu-cho, Minato-ku, Tokyo Tel: 81-3-3432-1551 FAX: 81-3-3432-1553 Tel: 800-432-6600 FAX: 800-566-9568 (in U.S.A.) 317-322-6484 (outside U.S.A.) Bellcore (U.S.A.): Bellcore Customer Service 8 Corporate Place Piscataway, NJ 08854 Tel: 800-521-CORE (in U.S.A.) Tel: 908-699-5800 FAX: 908-336-2559 Lucent Technologies Inc. 15 For additional information, contact your Microelectronics Group Account Manager or the following: INTERNET: http://www.lucent.com/micro U.S.A.: Microelectronics Group, Lucent Technologies Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18103 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106), e-mail docmaster@micro.lucent.com ASIA PACIFIC: Microelectronics Group, Lucent Technologies Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256 Tel. (65) 778 8833, FAX (65) 777 7495 JAPAN: Microelectronics Group, Lucent Technologies Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700 For data requests in Europe: MICROELECTRONICS GROUP DATALINE: Tel. (44) 1734 324 299, FAX (44) 1734 328 148 For technical inquiries in Europe: CENTRAL EUROPE: (49) 89 95086 0 (Munich), NORTHERN EUROPE: (44) 1344 865 900 (Bracknell UK), FRANCE: (33) 1 41 45 77 00 (Paris), SOUTHERN EUROPE: (39) 2 6601 1800 (Milan) or (34) 1 807 1700 (Madrid) Lucent Technologies Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. No rights under any patent accompany the sale of any such product(s) or information. Copyright (c) 1997 Lucent Technologies Inc. All Rights Reserved Printed in U.S.A. January 1997 DS97-039TIC (Replaces DS94-060TCOM) Printed On Recycled Paper