STM32H745xI/G Dual 32-bit Arm(R) Cortex(R)-M7 up to 480MHz and -M4 MCUs, up to 2MB Flash, 1MB RAM, 46 com. and analog interfaces, SMPS Datasheet - production data Features FBGA Dual core * 32-bit Arm(R) Cortex(R)-M7 core with doubleprecision FPU and L1 cache: 16 Kbytes of data and 16 Kbytes of instruction cache; frequency up to 480 MHz, MPU, 1027 DMIPS/ 2.14 DMIPS/MHz (Dhrystone 2.1), and DSP instructions (R) (R) * 32-bit Arm 32-bit Cortex -M4 core with FPU, Adaptive real-time accelerator (ART AcceleratorTM) for internal Flash memory and external memories, frequency up to 240 MHz, MPU, 300 DMIPS/1.25 DMIPS /MHz (Dhrystone 2.1), and DSP instructions LQFP144 (20x20 mm) LQFP176 (24x24 mm) LQFP208 (28x28 mm) TFBGA240+25 (14x14 mm) FBGA UFBGA176+25 (10x10 mm) Reset and power management * 3 separate power domains which can be independently clock-gated or switched off: - D1: high-performance capabilities - D2: communication peripherals and timers - D3: reset/clock control/power management * 1.62 to 3.6 V application supply and I/Os Memories * Up to 2 Mbytes of Flash memory with readwhile-write support * 1 Mbyte of RAM: 192 Kbytes of TCM RAM (inc. 64 Kbytes of ITCM RAM + 128 Kbytes of DTCM RAM for time critical routines), 864 Kbytes of user SRAM, and 4 Kbytes of SRAM in Backup domain * Dual mode Quad-SPI memory interface running up to 133 MHz * Flexible external memory controller with up to 32-bit data bus: SRAM, PSRAM, SDRAM/LPSDR SDRAM, NOR/NAND Flash memory clocked up to 125 MHz in Synchronous mode * POR, PDR, PVD and BOR * Dedicated USB power embedding a 3.3 V internal regulator to supply the internal PHYs * Embedded regulator (LDO) to supply the digital circuitry * High power-efficiency SMPS step-down converter regulator to directly supply VCORE and/or external circuitry * Voltage scaling in Run and Stop mode (6 configurable ranges) * Backup regulator (~0.9 V) * Voltage reference for analog peripheral/VREF+ * 1.2 to 3.6 V VBAT supply * CRC calculation unit * Low-power modes: Sleep, Stop, Standby and VBAT supporting battery charging Security Low-power consumption * ROP, PC-ROP, active tamper * VBAT battery operating mode with charging capability General-purpose input/outputs * Up to 168 I/O ports with interrupt capability May 2019 This is information on a product in full production. * CPU and domain power state monitoring pins * 2.95 A in Standby mode (Backup SRAM OFF, RTC/LSE ON) DS12923 Rev 1 1/252 www.st.com STM32H745xI/G Clock management * 2x operational amplifiers (7.3 MHz bandwidth) * Internal oscillators: 64 MHz HSI, 48 MHz HSI48, 4 MHz CSI, 32 kHz LSI * 1x digital filters for sigma delta modulator (DFSDM) with 8 channels/4 filters * External oscillators: 4-48 MHz HSE, 32.768 kHz LSE Graphics * 3x PLLs (1 for the system clock, 2 for kernel clocks) with Fractional mode * LCD-TFT controller up to XGA resolution Interconnect matrix * Hardware JPEG Codec * 3 bus matrices (1 AXI and 2 AHB) * Bridges (5x AHB2-APB, 2x AXI2-AHB) * Chrom-ART graphical hardware AcceleratorTM (DMA2D) to reduce CPU load Up to 22 timers and watchdogs * 1x high-resolution timer (2.1 ns max resolution) 4 DMA controllers to unload the CPU * 1x high-speed master direct memory access controller (MDMA) with linked list support * 2x dual-port DMAs with FIFO * 2x 32-bit timers with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input (up to 240 MHz) * 1x basic DMA with request router capabilities * 2x 16-bit advanced motor control timers (up to 240 MHz) Up to 35 communication peripherals * 10x 16-bit general-purpose timers (up to 240 MHz) * 4x I2Cs FM+ interfaces (SMBus/PMBus) * 4x USARTs/4x UARTs (ISO7816 interface, LIN, IrDA, up to 12.5 Mbit/s) and 1x LPUART * 5x 16-bit low-power timers (up to 240 MHz) * 6x SPIs, 3 with muxed duplex I2S audio class accuracy via internal audio PLL or external clock, 1x I2S in LP domain (up to 150 MHz) * 2x SysTick timers * 4x SAIs (serial audio interface) * 4x watchdogs (independent and window) * RTC with sub-second accuracy and hardware calendar * SPDIFRX interface Debug mode * SWPMI single-wire protocol master I/F * SWD & JTAG interfaces * MDIO Slave interface * 4-Kbyte Embedded Trace Buffer * 2x SD/SDIO/MMC interfaces (up to 125 MHz) * 2x CAN controllers: 2 with CAN FD, 1 with time-triggered CAN (TT-CAN) * 2x USB OTG interfaces (1FS, 1HS/FS) crystalless solution with LPM and BCD * Ethernet MAC interface with DMA controller * HDMI-CEC * 8- to 14-bit camera interface (up to 80 MHz) * 3x ADCs with 16-bit max. resolution (up to 36 channels, up to 3.6 MSPS) * 2x 12-bit D/A converters (1 MHz) 96-bit unique ID Optional support of extended temperature range up to 125 C (specific part numbers) All packages are ECOPACK(R)2 compliant Table 1. Device summary 11 analog peripherals * 1x temperature sensor True random number generators (3 oscillators each) Reference STM32H745xI STM32H745ZI, STM32H745II, STM32H745BI, STM32H745XI STM32H745xG STM32H745ZG, STM32H745IG, STM32H745BG, STM32H745XG * 2x ultra-low-power comparators 2/252 Part number DS12923 Rev 1 STM32H745xI/G Contents Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.1 Dual Arm(R) Cortex(R) cores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.1.1 Arm(R) Cortex(R)-M7 with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.1.2 Arm(R) Cortex(R)-M4 with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.2 Memory protection unit (MPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.3 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.3.1 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.3.2 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.3.3 ARTTM accelerator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.4 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.5 Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.5.1 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.5.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.5.3 Voltage regulator (SMPS step-down converter and LDO) . . . . . . . . . . . 28 3.5.4 SMPS step-down converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.6 Low-power strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.7 Reset and clock controller (RCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.7.1 Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.7.2 System reset sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.8 General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.9 Bus-interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.10 DMA controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.11 Chrom-ART AcceleratorTM (DMA2D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.12 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . 34 3.13 Extended interrupt and event controller (EXTI) . . . . . . . . . . . . . . . . . . . . 34 3.14 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 34 3.15 Flexible memory controller (FMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.16 Quad-SPI memory interface (QUADSPI) . . . . . . . . . . . . . . . . . . . . . . . . . 35 DS12923 Rev 1 3/252 6 Contents 4/252 STM32H745xI/G 3.17 Analog-to-digital converters (ADCs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.18 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.19 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.20 Digital-to-analog converters (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.21 Ultra-low-power comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.22 Operational amplifiers (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.23 Digital filter for sigma-delta modulators (DFSDM) . . . . . . . . . . . . . . . . . . 38 3.24 Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.25 LCD-TFT controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.26 JPEG Codec (JPEG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.27 Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.28 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.28.1 High-resolution timer (HRTIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.28.2 Advanced-control timers (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.28.3 General-purpose timers (TIMx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.28.4 Basic timers TIM6 and TIM7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.28.5 Low-power timers (LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5) . . . . 44 3.28.6 Independent watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.28.7 Window watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.28.8 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.29 Real-time clock (RTC), backup SRAM and backup registers . . . . . . . . . . 45 3.30 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.31 Universal synchronous/asynchronous receiver transmitter (USART) . . . 46 3.32 Low-power universal asynchronous receiver transmitter (LPUART) . . . . 47 3.33 Serial peripheral interface (SPI)/inter- integrated sound interfaces (I2S) . 48 3.34 Serial audio interfaces (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.35 SPDIFRX Receiver Interface (SPDIFRX) . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.36 Single wire protocol master interface (SWPMI) . . . . . . . . . . . . . . . . . . . . 49 3.37 Management Data Input/Output (MDIO) slaves . . . . . . . . . . . . . . . . . . . . 50 3.38 SD/SDIO/MMC card host interfaces (SDMMC) . . . . . . . . . . . . . . . . . . . . 50 3.39 Controller area network (FDCAN1, FDCAN2) . . . . . . . . . . . . . . . . . . . . . 50 3.40 Universal serial bus on-the-go high-speed (OTG_HS) . . . . . . . . . . . . . . . 51 3.41 Ethernet MAC interface with dedicated DMA controller (ETH) . . . . . . . . . 51 DS12923 Rev 1 STM32H745xI/G Contents 3.42 High-definition multimedia interface (HDMI) - consumer electronics control (CEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.43 Debug infrastructure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 4 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 5 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . 107 6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 6.3.2 VCAP external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 6.3.3 SMPS step-down converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 6.3.4 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . 114 6.3.5 Embedded reset and power control block characteristics . . . . . . . . . . 115 6.3.6 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 6.3.7 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 6.3.8 Wakeup time from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . 137 6.3.9 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 138 6.3.10 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 142 6.3.11 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 6.3.12 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 6.3.13 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 6.3.14 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 150 6.3.15 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 6.3.16 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 6.3.17 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 6.3.18 FMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 DS12923 Rev 1 5/252 6 Contents 7 STM32H745xI/G 6.3.19 Quad-SPI interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 6.3.20 Delay block (DLYB) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 6.3.21 16-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 6.3.22 DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 6.3.23 Voltage reference buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . 197 6.3.24 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 6.3.25 Temperature and VBAT monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 6.3.26 Voltage booster for analog switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 6.3.27 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 6.3.28 Operational amplifier characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 201 6.3.29 Digital filter for Sigma-Delta Modulators (DFSDM) characteristics . . . 203 6.3.30 Camera interface (DCMI) timing specifications . . . . . . . . . . . . . . . . . . 206 6.3.31 LCD-TFT controller (LTDC) characteristics . . . . . . . . . . . . . . . . . . . . . 207 6.3.32 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 6.3.33 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 7.1 LQFP144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 7.2 LQFP176 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 7.3 LQFP208 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 7.4 UFBGA176+25 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 7.5 TFBGA240+25 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 7.6 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 7.6.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 8 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 6/252 DS12923 Rev 1 STM32H745xI/G List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 STM32H745xI/G features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 System vs domain low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 DFSDM implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 USART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 STM32H745xI/G pin/ball definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Port A alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Port B alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Port C alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Port D alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Port E alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Port F alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Port G alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Port H alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Port I alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Port J alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Port K alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Supply voltage and maximum frequency configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 111 VCAP operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Characteristics of SMPS step-down converter external components . . . . . . . . . . . . . . . . 113 SMPS step-down converter characteristics for external usage . . . . . . . . . . . . . . . . . . . . 114 Operating conditions at power-up / power-down (regulator ON) . . . . . . . . . . . . . . . . . . . 114 Reset and power control block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Typical and maximum current consumption in Run mode, code with data processing running from ITCM for Cortex-M7 core, and Flash memory for Cortex-M4 (ART accelerator ON), LDO regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Typical and maximum current consumption in Run mode, code with data processing running from ITCM for Arm Cortex-M7 and Flash memory for Arm Cortex-M4, ART accelerator ON, SMPS regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Typical and maximum current consumption in Run mode, code with data processing running from Flash memory, both cores running, cache ON, ART accelerator ON, LDO regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Typical and maximum current consumption in Run mode, code with data processing running from Flash memory, both cores running, cache OFF, ART accelerator OFF, LDO regulator ON. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Typical and maximum current consumption in Run mode, code with data processing running from ITCM, only Arm Cortex-M7 running, LDO regulator ON . . . . . . . . . . . . . . . 120 Typical and maximum current consumption in Run mode, code with data processing running from ITCM, only Arm Cortex-M7 running, SMPS regulator. . . . . . . . . . . . . . . . . 121 Typical and maximum current consumption in Run mode, code with data processing DS12923 Rev 1 7/252 10 List of tables Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. 8/252 STM32H745xI/G running from Flash memory, only Arm Cortex-M7 running, cache ON, LDO regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Typical and maximum current consumption in Run mode, code with data processing running from Flash memory, only Arm Cortex-M7 running, cache OFF, LDO regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Typical and maximum current consumption batch acquisition mode, LDO regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Typical and maximum current consumption in Run mode, code with data processing running from Flash memory, only Arm Cortex-M4 running, ART accelerator ON, LDO regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Typical and maximum current consumption in Run mode, code with data processing running from Flash bank 2, only Arm Cortex-M4 running, ART accelerator ON, SMPS regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Typical and maximum current consumption in Stop, LDO regulator ON . . . . . . . . . . . . . 124 Typical and maximum current consumption in Stop, SMPS regulator . . . . . . . . . . . . . . . 125 Typical and maximum current consumption in Sleep mode, LDO regulator ON . . . . . . . 126 Typical and maximum current consumption in Sleep mode, SMPS regulator . . . . . . . . . 126 Typical and maximum current consumption in Standby . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Typical and maximum current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . 127 Peripheral current consumption in Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 4-48 MHz HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 HSI48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 CSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 PLL characteristics (wide VCO frequency range) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 PLL characteristics (medium VCO frequency range) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Flash memory programming (single bank configuration nDBANK=1) . . . . . . . . . . . . . . . 147 Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Output voltage characteristics for all I/Os except PC13, PC14, PC15 and PI8 . . . . . . . . 154 Output voltage characteristics for PC13, PC14, PC15 and PI8 . . . . . . . . . . . . . . . . . . . . 155 Output timing characteristics (HSLV OFF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 Output timing characteristics (HSLV ON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . 161 Asynchronous non-multiplexed SRAM/PSRAM/NOR read-NWAIT timings . . . . . . . . . . . 161 Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 163 Asynchronous non-multiplexed SRAM/PSRAM/NOR write-NWAIT timings. . . . . . . . . . . 163 Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 165 Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 165 Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 166 DS12923 Rev 1 STM32H745xI/G Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88. Table 89. Table 90. Table 91. Table 92. Table 93. Table 94. Table 95. Table 96. Table 97. Table 98. Table 99. Table 100. Table 101. Table 102. Table 103. Table 104. Table 105. Table 106. Table 107. Table 108. Table 109. Table 110. Table 111. Table 112. Table 113. Table 114. Table 115. Table 116. Table 117. Table 118. Table 119. Table 120. Table 121. Table 122. Table 123. Table 124. Table 125. Table 126. Table 127. Table 128. Table 129. Table 130. Table 131. Table 132. Table 133. List of tables Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 166 Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 172 Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 177 SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 LPSDR SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 SDRAM Write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 LPSDR SDRAM Write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 QUADSPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 QUADSPI characteristics in DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 Delay Block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 Minimum sampling time vs RAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 DAC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 VREFBUF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 VBAT charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 Temperature monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 Voltage booster for analog switch characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 COMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 Operational amplifier characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 DFSDM measured timing 1.62-3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 DCMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 LTDC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 Minimum i2c_ker_ck frequency in all I2C modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 USART characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 I2S dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 MDIO Slave timing parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 Dynamics characteristics: SD / MMC characteristics, VDD=2.7 to 3.6 V . . . . . . . . . . . . . 221 Dynamics characteristics: eMMC characteristics VDD=1.71V to 1.9V . . . . . . . . . . . . . . . 222 Dynamics characteristics: USB ULPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 Dynamics characteristics: Ethernet MAC signals for SMI . . . . . . . . . . . . . . . . . . . . . . . . 225 Dynamics characteristics: Ethernet MAC signals for RMII . . . . . . . . . . . . . . . . . . . . . . . . 226 Dynamics characteristics: Ethernet MAC signals for MII . . . . . . . . . . . . . . . . . . . . . . . . . 226 Dynamics JTAG characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 Dynamics SWD characteristics: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 LQFP144 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 LQFP176 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 LQFP208 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 UFBGA176+25 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 UFBGA176+25 recommended PCB design rules (0.65 mm pitch BGA) . . . . . . . . . . . . . 243 DS12923 Rev 1 9/252 10 List of tables Table 134. Table 135. Table 136. Table 137. 10/252 STM32H745xI/G TFBG240+25 ball package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 TFBGA240+25 recommended PCB design rules (0.8 mm pitch) . . . . . . . . . . . . . . . . . . . 247 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 DS12923 Rev 1 STM32H745xI/G List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. STM32H745xI/G block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 TFBGA240+25 ball assignment differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 ARTTM accelerator schematic and environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Power-up/power-down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 STM32H745xI/G bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 LQFP176 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 UFBGA176+25 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 LQFP208 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 TFBGA240+25 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 External capacitor CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 External components for SMPS step-down converter . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Typical SMPS efficiency (%) vs load current (A) in Run mode at TJ = 30 C. . . . . . . . . . 128 Typical SMPS efficiency (%) vs load current (A) in Run mode at TJ = TJmax . . . . . . . . 128 Typical SMPS efficiency (%) vs load current (A) in low-power mode at TJ = 30 C . . . . . 129 Typical SMPS efficiency (%) vs load current (A) in low-power mode at TJ = TJmax . . . 130 High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 VIL/VIH for all I/Os except BOOT0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 160 Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 162 Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 164 Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 171 Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 176 NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 177 SDRAM read access waveforms (CL = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 SDRAM write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 Quad-SPI timing diagram - SDR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 Quad-SPI timing diagram - DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 ADC accuracy characteristics (12-bit resolution) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . 192 Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . 192 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 Channel transceiver timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 DCMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 DS12923 Rev 1 11/252 12 List of figures Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. Figure 64. Figure 65. Figure 66. Figure 67. Figure 68. Figure 69. Figure 70. Figure 71. Figure 72. Figure 73. Figure 74. Figure 75. Figure 76. Figure 77. Figure 78. Figure 79. Figure 80. Figure 81. Figure 82. Figure 83. Figure 84. 12/252 STM32H745xI/G LCD-TFT horizontal timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 LCD-TFT vertical timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 USART timing diagram in Master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 USART timing diagram in Slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 MDIO Slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 ULPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 Ethernet SMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 Ethernet RMII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 Ethernet MII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 JTAG timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 SWD timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 LQFP144 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 LQFP144 package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 LQFP144 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 LQFP176 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 LQFP176 package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 LQFP176 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 LQFP208 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 LQFP208 package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 LQFP208 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 UFBGA176+25 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 UFBGA176+25 package recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 UFBGA176+25 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 TFBGA240+25 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 TFBGA240+25 package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 TFBGA240+25 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . 247 DS12923 Rev 1 STM32H745xI/G 1 Introduction Introduction This document provides information on STM32H745xI/G microcontrollers, such as description, functional overview, pin assignment and definition, electrical characteristics, packaging, and ordering information. This document should be read in conjunction with the STM32H745xI/G reference manual (RM0399), available from the STMicroelectronics website www.st.com. For information on the Arm(R)(a) Cortex(R)-M7 core and Arm(R) Cortex(R)-M4 core, please refer to the Cortex(R)-M7 Technical Reference Manual, available from the http://www.arm.com website. a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere. DS12923 Rev 1 13/252 54 Description 2 STM32H745xI/G Description STM32H745xI/G devices are based on the high-performance Arm(R) Cortex(R)-M7 and Cortex(R)-M4 32-bit RISC cores. The Cortex(R)-M7 core operates at up to 480 MHz and the Cortex(R)-M4 core at up to 240 MHz. Both cores feature a floating point unit (FPU) which supports Arm(R) single- and double-precision (Cortex(R)-M7 core) operations and conversions (IEEE 754 compliant), including a full set of DSP instructions and a memory protection unit (MPU) to enhance application security. STM32H745xI/G devices incorporate high-speed embedded memories with a dual-bank Flash memory of up to 2 Mbytes, up to 1 Mbyte of RAM (including 192 Kbytes of TCM RAM, up to 864 Kbytes of user SRAM and 4 Kbytes of backup SRAM), as well as an extensive range of enhanced I/Os and peripherals connected to APB buses, AHB buses, 2x32-bit multi-AHB bus matrix and a multi layer AXI interconnect supporting internal and external memory access. All the devices offer three ADCs, two DACs, two ultra-low power comparators, a low-power RTC, a high-resolution timer, 12 general-purpose 16-bit timers, two PWM timers for motor control, five low-power timers, a true random number generator (RNG). The devices support four digital filters for external sigma-delta modulators (DFSDM). They also feature standard and advanced communication interfaces. * * Standard peripherals - Four I2Cs - Four USARTs, four UARTs and one LPUART - Six SPIs, three I2Ss in Half-duplex mode. To achieve audio class accuracy, the I2S peripherals can be clocked by a dedicated internal audio PLL or by an external clock to allow synchronization. - Four SAI serial audio interfaces - One SPDIFRX interface - One SWPMI (Single Wire Protocol Master Interface) - Management Data Input/Output (MDIO) slaves - Two SDMMC interfaces - A USB OTG full-speed and a USB OTG high-speed interface with full-speed capability (with the ULPI) - One FDCAN plus one TT-FDCAN interface - An Ethernet interface - Chrom-ART AcceleratorTM - HDMI-CEC Advanced peripherals including - A flexible memory control (FMC) interface - A Quad-SPI Flash memory interface - A camera interface for CMOS sensors - An LCD-TFT display controller - A JPEG hardware compressor/decompressor Refer to Table 2: STM32H745xI/G features and peripheral counts for the list of peripherals available on each part number. 14/252 DS12923 Rev 1 STM32H745xI/G Description STM32H745xI/G devices operate in the -40 to +85 C temperature range from a 1.62 to 3.6 V power supply. The supply voltage can drop down to 1.62 V by using an external power supervisor (see Section 3.5.2: Power supply supervisor) and connecting the PDR_ON pin to VSS. Otherwise the supply voltage must stay above 1.71 V with the embedded power voltage detector enabled. Dedicated supply inputs for USB (OTG_FS and OTG_HS) are available on all packages to allow a greater power supply choice. A comprehensive set of power-saving modes allows the design of low-power applications. STM32H745xI/G devices are offered in 5 packages ranging from 144 pins to 240 pins/balls. The set of included peripherals changes with the device chosen. These features make STM32H745xI/G microcontrollers suitable for a wide range of applications: * Motor drive and application control * Medical equipment * Industrial applications: PLC, inverters, circuit breakers * Printers, and scanners * Alarm systems, video intercom, and HVAC * Home audio appliances * Mobile applications, Internet of Things * Wearable devices: smart watches. Figure 1 shows the device block diagram. DS12923 Rev 1 15/252 54 Description STM32H745xI/G SRAM1 (D2 domain) 128 SRAM2 (D2 domain) 128 SRAM3 (D2 domain) 32 SRAM4 (D3 domain) 64 ITCM RAM (instruction) 64 DTCM RAM (data) 128 Backup SRAM (Kbytes) 4 FMC Yes 148 168 97 Yes Ethernet Yes Highresolution 1 Generalpurpose 10 Advancedcontrol (PWM) 2 Basic 2 Low-power 5 Wakeup pins Tamper pins 16/252 119/128 Quad-SPI Timers STM32H745II STM32H745ZI STM32H745XG 512 97 4 2 148 168 2 x 1 Mbyte SRAM mapped onto AXI bus General-purpose input/outputs STM32H745XI TCM RAM in Kbytes 2 x 512 Kbytes STM32H745BI Flash memory in Kbytes SRAM in Kbytes STM32H745BG STM32H745IG Peripherals STM32H745ZG Table 2. STM32H745xI/G features and peripheral counts 6 3 DS12923 Rev 1 119/128 4 2 6 3 STM32H745xI/G Description STM32H745XI STM32H745II 4 9 23 6/3(1) SPI / I I2C 4 USART/ UART/ LPUART 4/4 /1 SAI 4 SPDIFRX 4 inputs SWPMI Yes MDIO Yes SDMMC 2 FDCAN/TTFDCAN 1/1 USB OTG_FS Yes USB OTG_HS Yes Ethernet and camera interface Yes LCD-TFT Yes JPEG Codec Yes Chrom-ART AcceleratorTM (DMA2D) Yes 16-bit ADCs Number of Direct channels Number of Fast channels Number of Slow channels 2 9 21 Yes 2S Communicati on interfaces STM32H745BI Random number generator STM32H745ZI STM32H745XG STM32H745BG Peripherals STM32H745IG STM32H745ZG Table 2. STM32H745xI/G features and peripheral counts (continued) 3 2 6 15 2 9 17 4 9 23 2 9 21 4 9 23 2 6 15 12-bit DAC Number of channels Yes 2 Comparators 2 Operational amplifiers 2 DFSDM Yes DS12923 Rev 1 2 9 17 4 9 23 17/252 54 Description STM32H745xI/G STM32H745XI STM32H745BI STM32H745II STM32H745ZI STM32H745XG STM32H745BG STM32H745IG Peripherals STM32H745ZG Table 2. STM32H745xI/G features and peripheral counts (continued) 480 MHz(2) 400 MHz(3) Maximum CPU frequency 300 MHz(4) Operating voltage Operating temperatures Extended operating temperatures 1.62 to 3.6 V(5) Ambient temperature -40 up to +85 C(6) Junction temperature -40 to + 125 C Ambient temperature -40 to + 125 C(4)(7) Junction temperature -40 to + 140 C(8) Package LQFP LQFP UFBGA LQFP TFBGA LQFP 144 176 176+25 208 240+25 144 LQFP UFBGA LQFP TFBGA 176 176+25 208 240+25 1. The SPI1, SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either the SPI mode or the I2S audio mode. 2. The product junction temperature must be kept within the -40 to +105 C range. 3. The product junction temperature must be kept within the -40 to +125 C range. 4. Up to 300 MHz for STM32H745xxx3 sales types (extended industrial temperature range). 5. VDD/VDDA can drop down to 1.62 V by using an external power supervisor (see Section 3.5.2: Power supply supervisor) and connecting PDR_ON pin to VSS. Otherwise the supply voltage must stay above 1.71 V with the embedded power voltage detector enabled. 6. Using appropriate cooling methods to guarantee that the maximum junction temperature (125 C) is not exceeded, the maximum ambient temperature (85C) can be exceeded. 7. The product junction temperature must be kept within the -40 to +140 C range. 8. It is mandatory to use the SMPS step-down converter when the maximum junction temperature is higher than 125 C. 18/252 DS12923 Rev 1 STM32H745xI/G Description Figure 1. STM32H745xI/G block diagram MII / RMII To APB1-2 peripherals MDIO as AF AHB1 Up to 1 MB FLASH Up to 1 MB FLASH 16 Streams FIFO CHROM-ART (DMA2D) FIFO LCD-TFT FIFO JPEG FMC FMC_signals Quad-SPI CLK, CS,D[7:0] AXI/AHB34 (200MHz) RNG SRAM1 SRAM2 SRAM3 128 KB 128 KB 32 KB ADC1 Up to 20 analog inputs common to ADC1 & 2 ADC2 AHB/APB 32b TIM6 16b 16b TIM7 16b 16b SWPMI FIFO 32b 16b ART (instruction cache) 16b AHB ART (200MHz) TIM2 4 channels, ETR as AF TIM3 4 channels, ETR as AF TIM4 4 channels, ETR as AF TIM5 4 channels TIM12 2 channels as AF TIM13 1 channel as AF TIM14 16b 1 channel as AF smcard AHB2 (200MHz) Delay block DMA/ FIFO 32-bit AHB BUS-MATRIX AHB/APB SDMMC1 DMA/ FIFO FIFO DMA DMA Mux1 512 KB AXI SRAM AHBS PHY PHY ETHER SDMMC2 OTG_HS OTG_FS MAC AHB1 (200MHz) D-Cache 16KB (200MHz) 8 Stream 8 Stream FIFOs FIFOs D- SIBus Bus Bus AHB2 (200MHz) I-Cache 16KB WWDG1 SDMMC_D[7:0],SDMMC_D[7:3,1]Dir SDMMC_D0dir, SDMMC_D2dir CMD, CMDdir, CK, Ckin, CKio as AF AXIM ETM MDMA LCD_R[7:0], LCD_G[7:0], LCD_B[7:0], LCD_HSYNC, LCD_VSYNC, LCD_DE, LCD_CLK AXI/AHB12 (200MHz) AHB4 (200MHz) Arm Cortex M7 AHBP DMA2 AHB ART(200MHz) TRACECK TRACED[3:0] JTAG/SW DMA1 Arm Cortex M4 64-bit AXI BUS-MATRIX JTDO/SWD, JTDO JTRST, JTDI, JTCK/SWCLK DTCM 64KB AHB3 DTCM 64KB ITCM 64KB DP, DM, STP, SDMMC_ NXT,ULPI:CK DP, DM, ID, D[7:0], VBUS , D[7:0], DIR, CMD, CK as AF ID, VBUS USART2 irDA smcard RX, TX as AF RX, TX as AF UART7 RX, TX as AF UART8 RX, TX as AF SPI/I2S1 16b APB1 100 MHz (max) A P B 10 MHz 3 IWDG2 DAP 16b MOSI, MISO, SCK, NSS/SDO, SDI, CK, WS, MCK, as AF I2C2/SMBUS I2C3/SMBUS MDIOS SCL, SDA, SMBAL as AF SCL, SDA, SMBAL as AF SCL, SDA, SMBAL as AF MDC, MDIO FDCAN1 FDCAN2 TX, RX TX, RX CRS 64 KB SRAM SPDIFRX1 4 KB BKP RAM IN[1:4] as AF HDMI-CEC CEC as AF DAC1&2 HSEM TIM8/PWM MOSI, MISO, SCK, NSS/SDO, SDI, CK, WS, MCK, as AF SPI3/I2S3 I2C1/SMBUS RAM I/F 32-bit AHB BUS-MATRIX IWDG1 smcard irDA USART6 smcard irDA USART1 TIM1/PWM BDMA SPI2/I2S2 FIFO MOSI, MISO, SCK, NSS / SDO, SDI, CK, WS, MCK, as AF AHB4 DMA Mux2 10 KB SRAM TIM15 SPI4 4 compl. chan. (TIM1_CH1[1:4]N), 4 chan. (TIM1_CH1[1:4]ETR, BKIN as AF 4 compl. chan.(TIM8_CH1[1:4]N), 4 chan. (TIM8_CH1[1:4], ETR, BKIN as AF APB2 100 MHz (max) TIM16 MOSI, MISO, SCK, NSS as AF RX, TX, SCK, CTS, RTS as AF RX, TX, SCK CTS, RTS as AF UART5 Digital filter SPI5 TIM17 AHB4 SAI1 AHB4 SD, SCK, FS, MCLK, D[3:1], CK[2:1] as AF AHB4 (200MHz) SAI2 RX, TX, SCK, CTS, RTS as AF UART4 AHB4 SAI3 2 compl. chan.(TIM15_CH1[1:2]N), 2 chan. (TIM_CH15[1:2], BKIN as AF irDA DFSDM1 SD, SCK, FS, MCLK as AF MOSI, MISO, SCK, NSS as AF AHB/APB HRTIM1 SD, SCK, FS, MCLK as AF 1 compl. chan.(TIM17_CH1N), 1 chan. (TIM17_CH1, BKIN as AF 1 compl. chan.(TIM16_CH1N), 1 chan. (TIM16_CH1, BKIN as AF USART3 DCMI AHB4 HRTIM1_CH[A..E]x HRTIM1_FLT[5:1], HRTIM1_FLT[5:1]_in, SYSFLT DFSDM1_CKOUT, DFSDM1_DATAIN[0:7], DFSDM1_CKIN[0:7] FIFO FIFO FIFO HSYNC, VSYNC, PUIXCLK, D[13:0] RX, TX, SCK, CTS, RTS as AF LPTIM1 CRC DAC1_OUT, DAC2_OUT as AF 16b LPTIM1_IN1, LPTIM1_IN2, LPTIM1_OUT as AF @VSW LPTIM4_OUT as AF RX, TX, CK, CTS, RTS as AF LS XTAL 32 kHz COMP1&2 LPTIM4 MISO, MOSI, SCK, NSS as AF AHB/APB Voltage regulator 3.3 to 1.2V SMPS step-down converter SAI4 LPTIM5 LPTIM3_OUT as AF VDD12 POWER MANAGEMENT PWRCTRL GPIO PORTK LPTIM5_OUT as AF SCL, SDA, SMBAL as AF RCC Reset & control LPTIM3 I2C4 SPI6 RTC Backup registers @VDD VREF SYSCFG EXTI WKUP CSI RC48 4 MHz CSI 48 MHz HSI48 RC HSI 64 MHz HSI RC LSI 32 KHz LSI RC PLL1+PLL2+PLL3 LS PK[7:0] SD, SCK, FS, MCLK, PDM_DI/CK[4:1] as AF COMPx_INP, COMPx_INM, COMPx_OUT as AF Tem. sensor GPIO PORTA.. J WWDG2 @VDD33 APB4 100 MHz (max) PA..J[15:0] AHB4 VDDREF_ADC ADC3 APB4 100 100MHz MHz(max) (max) APB4 Up to 17 analog inputs common to ADC1 and 2 AHB4 (200MHz) OPAMP1&2 AWU OPAMPx_VINM OPAMPx_VINP OPAMPx_VOUT as AF VDD = 1.62 to 3.6V VDD33USB = 3.0 to 3.6V VSS VCAP VDDMMC33 = 1.8 to 3.6V VDDSMPS, VSSSMPS VLXSMP, VFBSMPS, OSC32_IN OSC32_OUT RTC_TS RTC_TAMP[1:3] RTC_OUT RTC_REFIN VBAT = 1.2 to 3.6 V @VDD XTAL OSC 4- 48 MHz OSC_IN OSC_OUT IWDG1 LPUART1 IWDG2 LPTIM2_OUT as AF LPTIM2 @VDD POR reset Int SUPPLY SUPERVISION POR/PDR/BOR PVD VDDA, VSSA NRESET WKUP[5:0] MSv43754V13 DS12923 Rev 1 19/252 54 Description STM32H745xI/G Compatibility throughout the family STM32H745xI/G devices are not pin-to-pin compatible with STM32H7x3 devices (single core line): * The TFBGA240+25 ballout is compatible with STM32H7x3 devices, except for a few I/O balls as shown in Figure 2. * LQFP208 and LQFP176 pinouts, as well as UFBGA176+25 ballout are not compatible with STM32H7x3 devices. Figure 2. TFBGA240+25 ball assignment differences 1 A VSS 2 3 4 5 6 7 8 9 10 11 12 PK5 PG10 PG9 PD5 PI6 PI5 PI4 PB5 VDDLDO VCAP 13 14 15 16 17 PD4 PC10 PA15 PI1 PI0 VSS B VBAT VSS PI7 PE1 PB6 VSS PB4 PK4 PG11 PJ15 PD6 PD3 PC11 PA14 PI2 PH15 PH14 C PC15OSC32_ OUT PC14OSC32_ IN PE2 PE0 PB7 PB3 PK6 PK3 PG12 VSS PD7 PC12 VSS PI3 PA13 VSS VDDLDO PE4 PE3 PB9 PB8 PG15 PK7 PG14 PG13 PJ14 PJ12 PD2 PD0 PA10 PA9 PH13 VCAP PI9 PC13 PI8 PE6 VDD PDR _ON BOOT0 VDD PJ13 VDD PD1 PC8 PC9 PA8 PA12 PA11 PI10 PI11 VDD PC7 PC6 PG8 PG7 VDD33 USB PF1 PF0 VDD VSS VSS VSS VSS VSS VDD PG5 PG6 VSS VDD50 USB D PE5 E F G PF2 H PI12 PI14 PF3 VDD VSS VSS VSS VSS VSS VDD PG4 PG3 PG2 PK2 J PH1PH0OSC_ OSC_IN OUT VSS PF5 PF4 VSS VSS VSS VSS VSS VDD PK0 PK1 VSS VSS K NRST PF6 PF7 PF8 VDD VSS VSS VSS VSS VSS VDD PJ11 VSS NC NC VSS VSS VSS VSS VSS VDD PJ10 VSS NC NC VDD PJ9 VSS NC NC NC PI13 L VDDA PC0 PF10 PF9 VDD M VREF+ PC1 PC2 PC3 VDD N VREF- PH2 PA2 PA1 PA0 PJ0 VDD VDD PE10 VDD VDD VDD PJ8 PJ7 PJ6 VSS P VSSA PH3 PH4 PH5 PI15 PJ1 PF13 PF14 PE9 PE11 PB10 PB11 PH10 PH11 PD15 PD14 VDD R PC2_C PC3_C PA6 VSS PA7 PB2 PF12 VSS PF15 PE12 PE15 PJ5 PH9 PH12 PD11 PD12 PD13 T PA0_C PA1_C PA5 PC4 PB1 PJ2 PF11 PG0 PE8 PE13 PH6 VSS PH8 PB12 PB15 PD10 PD9 U VSS PA3 PA4 PC5 PB0 PJ3 PJ4 PG1 PE7 PE14 VCAP VDDLDO PH7 PB13 PB14 PD8 VSS STM32H7x5 VLX SMPS STM32H7x3 PI9 VDD VSS SMPS SMPS NC PI9 NC NC VFB PF2 PF2 SMPS NC MSv48801V2 1. The balls highlighted in gray correspond to different signals on STM32H745xI/G and STM32H7x3 devices. 20/252 DS12923 Rev 1 STM32H745xI/G Functional overview 3 Functional overview 3.1 Dual Arm(R) Cortex(R) cores The industrial STM32H745xI/G devices embed two Arm(R) cores, a Cortex(R)-M7 and a Cortex(R)-M4. The Cortex(R)-M4 offers optimal performance for real-time applications while the Cortex(R)-M7 core can execute high-performance tasks in parallel. The two cores belong to separate power domains. This allows designing gradual highpower efficiency solutions in combination with the low-power modes already available on all STM32 microcontrollers. 3.1.1 Arm(R) Cortex(R)-M7 with FPU The Arm(R) Cortex(R)-M7 with double-precision FPU processor is the latest generation of Arm processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and optimized power consumption, while delivering outstanding computational performance and low interrupt latency. The Cortex(R)-M7 processor is a highly efficient high-performance featuring: * Six-stage dual-issue pipeline * Dynamic branch prediction * Harvard architecture with L1 caches (16 Kbytes of I-cache and 16 Kbytes of D-cache) * 64-bit AXI interface * 64-bit ITCM interface * 2x32-bit DTCM interfaces The following memory interfaces are supported: * Separate Instruction and Data buses (Harvard Architecture) to optimize CPU latency * Tightly Coupled Memory (TCM) interface designed for fast and deterministic SRAM accesses * AXI Bus interface to optimize Burst transfers * Dedicated low-latency AHB-Lite peripheral bus (AHBP) to connect to peripherals. The processor supports a set of DSP instructions which allow efficient signal processing and complex algorithm execution. It also supports single and double precision FPU (floating point unit) speeds up software development by using metalanguage development tools, while avoiding saturation. Figure 1 shows the general block diagram of the STM32H745xI/G family. Note: Cortex(R)-M7 with FPU core is binary compatible with the Cortex(R)-M4 core. DS12923 Rev 1 21/252 54 Functional overview 3.1.2 STM32H745xI/G Arm(R) Cortex(R)-M4 with FPU The Arm(R) Cortex(R)-M4 processor is a high-performance embedded processor which supports DSP instructions. It was developed to provide an optimized power consumption MCU, while delivering outstanding computational performance and low interrupt latency. The Arm(R) Cortex(R)-M4 processor is a highly efficient MCU featuring: * 3-stage pipeline with branch prediction * Harvard architecture * 32-bit System (S-BUS) interface * 32-bit I-BUS interface * 32-bit D-BUS interface The Arm(R) Cortex(R)-M4 processor also features a dedicated hardware adaptive real-time accelerator (ART AcceleratorTM). This is an instruction cache memory composed of sixtyfour 256-bit lines, a 256-bit cache buffer connected to the 64-bit AXI interface and a 32-bit interface for non-cacheable accesses. 3.2 Memory protection unit (MPU) The devices feature two memory protection units. Each MPU manages the CPU access rights and the attributes of the system resources. It has to be programmed and enabled before use. Its main purposes are to prevent an untrusted user program to accidentally corrupt data used by the OS and/or by a privileged task, but also to protect data processes or read-protect memory regions. The MPU defines access rules for privileged accesses and user program accesses. It allows defining up to 16 protected regions that can in turn be divided into up to 8 independent subregions, where region address, size, and attributes can be configured. The protection area ranges from 32 bytes to 4 Gbytes of addressable memory. When an unauthorized access is performed, a memory management exception is generated. 22/252 DS12923 Rev 1 STM32H745xI/G Functional overview 3.3 Memories 3.3.1 Embedded Flash memory The STM32H745xI/G devices embed up to 2 Mbytes of Flash memory that can be used for storing programs and data. The Flash memory is organized as 266-bit Flash words memory that can be used for storing both code and data constants. Each word consists of: * One Flash word (8 words, 32 bytes or 256 bits) * 10 ECC bits. The Flash memory is divided into two independent banks. Each bank is organized as follows: 3.3.2 * A user Flash memory block of 512 Kbytes (STM32H7xxxG) or 1-Mbyte (STM32H7xxxI) containing eight user sectors of 128 Kbytes (4 K Flash memory words) * 128 Kbytes of System Flash memory from which the device can boot * 2 Kbytes (64 Flash words) of user option bytes for user configuration Embedded SRAM All devices feature around 1 Mbyte of RAM with hardware ECC. The RAM is divided as follows: * 512 Kbytes of AXI-SRAM mapped onto AXI bus on D1 domain. * SRAM1 mapped on D2 domain: 128 Kbytes * SRAM2 mapped on D2 domain: 128 Kbytes * SRAM3 mapped on D2 domain: 32 Kbytes * SRAM4 mapped on D3 domain: 64 Kbytes * 4 Kbytes of backup SRAM The content of this area is protected against possible unwanted write accesses, and is retained in Standby or VBAT mode. * RAM mapped to TCM interface (ITCM and DTCM): Both ITCM and DTCM RAMs are 0 wait state memories. They can be accessed either from the Arm(R) Cortex(R)-M7 CPU or the MDMA (even in Sleep mode) through a specific AHB slave of the Cortex(R)-M7(AHBS): - 64 Kbytes of ITCM-RAM (instruction RAM) This RAM is connected to ITCM 64-bit interface designed for execution of critical real-times routines by the Cortex(R)-M7. - 128 Kbytes of DTCM-RAM (2x 64-Kbyte DTCM-RAMs on 2x32-bit DTCM ports) The DTCM-RAM could be used for critical real-time data, such as interrupt service routines or stack/heap memory. Both DTCM-RAMs can be used in parallel (for load/store operations) thanks to the Cortex(R)-M7 dual issue capability. The MDMA can be used to load code or data in ITCM or DTCM RAMs. DS12923 Rev 1 23/252 54 Functional overview STM32H745xI/G Error code correction (ECC) Over the product lifetime, and/or due to external events such as radiations, invalid bits in memories may occur. They can be detected and corrected by ECC. This is an expected behavior that has to be managed at final-application software level in order to ensure data integrity through ECC algorithms implementation. SRAM data are protected by ECC: * 7 ECC bits are added per 32-bit word. * 8 ECC bits are added per 64-bit word for AXI-SRAM and ITCM-RAM. The ECC mechanism is based on the SECDED algorithm. It supports single-error correction and double-error detection. 3.3.3 ARTTM accelerator The ARTTM (adaptive real-time) accelerator block speeds up instruction fetch accesses of the Cortex(R)-M4 core from D1-domain internal memories (Flash memory bank 1, Flash memory bank 2, AXI SRAM) and from D1-domain external memories attached via QuadSPI controller and Flexible memory controller (FMC). The ARTTM accelerator is a 256-bit cache line using 64-bit WRAP4 accesses from the 64-bit AXI D1 domain. The acceleration is achieved by loading selected code into an embedded cache and making it instantly available to Cortex(R)-M4 core, thus avoiding latency due to memory wait states. Figure 3. shows the block schematic and the environment of the ART accelerator. 24/252 DS12923 Rev 1 STM32H745xI/G Functional overview Figure 3. ARTTM accelerator schematic and environment AHB from D2 domain D1 domain ART accelerator Non-cacheable access path AHB switch Cacheable access path control Detect of write to cacheable page Cache Cache buffer noncacheable access instruction fetch cache cache hit miss 1 x 256-bit Cache memory 64 x 256-bit Cache memory Cache manager 64 x 256-bit cache refill AHB access AXI access Flash bank 1 Legend Flash bank 2 Control 32-bit bus AXI SRAM 64-bit bus QSPI Bus multiplexer AXI AHB Master interface FMC Slave interface 64-bit AXI bus matrix MSv39757V2 3.4 Boot modes By default, the boot codes are executed simultaneously by both cores. However, by programming the appropriate Flash user option byte, it is possible to boot from one core while clock-gating the other core. At startup, the boot memory space is selected by the BOOT pin and BOOT_ADDx option bytes, allowing to program any boot memory address from 0x0000 0000 to 0x3FFF FFFF which includes: * All Flash address space * Flash memory and SRAMs (except for ITCM /DTCM RAMs which cannot be accessed by the Cortex(R)-M4 core) DS12923 Rev 1 25/252 54 Functional overview STM32H745xI/G The bootloader is located in non-user System memory. It is used to reprogram the Flash memory through a serial interface (USART, I2C, SPI, USB-DFU). Refer to STM32 microcontroller System memory Boot mode application note (AN2606) for details. 3.5 Power supply management 3.5.1 Power supply scheme STM32H745xI/G power supply voltages are the following: * VDD = 1.62 to 3.6 V: external power supply for I/Os, provided externally through VDD pins. * VDDLDO = 1.62 to 3.6 V: supply voltage for the internal regulator supplying VCORE * VDDA = 1.62 to 3.6 V: external analog power supplies for ADC, DAC, COMP and OPAMP. * VDD33USB and VDD50USB: VDD50USB can be supplied through the USB cable to generate the VDD33USB via the USB internal regulator. This allows supporting a VDD supply different from 3.3 V. The USB regulator can be bypassed to supply directly VDD33USB if VDD = 3.3 V. * VBAT = 1.2 to 3.6 V: power supply for the VSW domain when VDD is not present. * VCAP: VCORE supply voltage, which values depend on voltage scaling (1.0 V, 1.1 V, 1.2 V or 1.35 V). They are configured through VOS bits in PWR_D3CR register and ODEN bit in the SYSCFG_PWRCR register. The VCORE domain is split into the following power domains that can be independently switch off. * - D1 domain containing some peripherals and the Cortex(R)-M7 core. - D2 domain containing a large part of the peripherals and the Cortex(R)-M4 core. - D3 domain containing some peripherals and the system control. VDDSMPS= 1.62 V to 3.6 V: SMPS step-down converter power supply VDDSMPS must be kept at the same voltage level as VDD. * VLXSMPS = SMPS step-down converter output coupled to an inductor. * VFBSMPS = VCORE, 1.8 V or 2.5 V external SMPS step-down converter feedback voltage sense input. During power-up and power-down phases, the following power sequence requirements must be respected (see Figure 4): * When VDD is below 1 V, other power supplies (VDDA, VDD33USB, VDD50USB) must remain below VDD + 300 mV. * When VDD is above 1 V, all power supplies are independent (except for VDDSMPS, which must remain at the same level as VDD). During the power-down phase, VDD can temporarily become lower than other supplies only if the energy provided to the microcontroller remains below 1 mJ. This allows external decoupling capacitors to be discharged with different time constants during the power-down transient phase. 26/252 DS12923 Rev 1 STM32H745xI/G Functional overview Figure 4. Power-up/power-down sequence V 3.6 VDDX(1) VDD VBOR0 1 0.3 Power-on Invalid supply area Operating mode VDDX < VDD + 300 mV Power-down VDDX independent from VDD time MSv47490V1 1. VDDx refers to any power supply among VDDA, VDD33USB, VDD50USB. 2. VDD and VDDSMPS must be wired together into order to follow the same voltage sequence. 3.5.2 Power supply supervisor The devices have an integrated power-on reset (POR)/ power-down reset (PDR) circuitry coupled with a Brownout reset (BOR) circuitry: * Power-on reset (POR) The POR supervisor monitors VDD power supply and compares it to a fixed threshold. The devices remain in Reset mode when VDD is below this threshold, * Power-down reset (PDR) The PDR supervisor monitors VDD power supply. A reset is generated when VDD drops below a fixed threshold. The PDR supervisor can be enabled/disabled through PDR_ON pin. * Brownout reset (BOR) The BOR supervisor monitors VDD power supply. Three BOR thresholds (from 2.1 to 2.7 V) can be configured through option bytes. A reset is generated when VDD drops below this threshold. DS12923 Rev 1 27/252 54 Functional overview 3.5.3 STM32H745xI/G Voltage regulator (SMPS step-down converter and LDO) The same voltage regulator supplies the 3 power domains (D1, D2 and D3). D1 and D2 can be independently switched off. Voltage regulator output can be adjusted according to application needs through 6 power supply levels: * Note: Run mode (VOS0 to VOS3) - Scale 0: boosted performance (available only with LDO regulator) - Scale 1: high performance - Scale 2: medium performance and consumption - Scale 3: optimized performance and low-power consumption For STM32H745xxx3 sales types (industrial temperature range) the voltage regulator output can be set only to VOS2 or VOS3 in Run mode (VOS0 and VOS1 are not available for industrial temperature range). * Stop mode (SVOS3 to SVOS5) - Scale 3: peripheral with wakeup from Stop mode capabilities (UART, SPI, I2C, LPTIM) are operational - Scale 4 and 5 where the peripheral with wakeup from Stop mode is disabled The peripheral functionality is disabled but wakeup from Stop mode is possible through GPIO or asynchronous interrupt. 3.5.4 SMPS step-down converter The built-in SMPS step-down converter is a highly power-efficient DC/DC non-linear switching regulator that provides lower power consumption than a conventional voltage regulator (LDO). 28/252 DS12923 Rev 1 STM32H745xI/G Functional overview The SMPS step-down converter can be used for the following purposes: * * Direct supply of the VCORE domain - the SMPS step-down converter operating modes follow the device system operating modes (Run, Stop, Standby). - the SMPS step-down converter output voltage are set according to the selected VOS and SVOS bits (voltage scaling) Delivery of an intermediate voltage level to supply the internal voltage regulator (LDO) - SMPS step-down converter operating modes When the SDEXTHP bit is equal to 0 in the PWR_CR3 register, the SMPS stepdown converter follows the device system operating modes (Run, Stop and Standby). When the SDEXTHP bit is equal to 1 in PWR_CR3, the SMPS step-down converter is forced to High-performance mode and does not follow the device system operating modes (Run, Stop and Standby). - * 3.6 The SMPS step-down converter output equals 1.8 V or 2.5 V according to the selected SD level Delivery of an external supply - The SMPS step-down converter is forced to High-performance mode (provided SDEXTHP bit is equal to 1 in PWR_CR3) - The SMPS step-down converter output equals 1.8 V or 2.5 V according to the selected SD level Low-power strategy There are several ways to reduce power consumption on STM32H745xI/G: * Select the SMPS step-down converter as VCORE supply voltage source, as it allows to enhance power efficiency. * Select the adequate voltage scaling * Decrease the dynamic power consumption by slowing down the system clocks even in Run mode, and by individually clock gating the peripherals that are not used. * Save power consumption when one or both CPUs are idle, by selecting among the available low-power mode according to the user application needs. This allows achieving the best compromise between short startup time, low-power consumption, as well as available wakeup sources. The devices feature several low-power modes: * CSleep (CPU clock stopped) * CStop (CPU sub-system clock stopped) * DStop (Domain bus matrix clock stopped) * Stop (System clock stopped) * DStandby (Domain powered down) * Standby (System powered down) CSleep and CStop low-power modes are entered by the MCU when executing the WFI (Wait for Interrupt) or WFE (Wait for Event) instructions, or when the SLEEPONEXIT bit of the Cortex(R)-Mx core is set after returning from an interrupt service routine. DS12923 Rev 1 29/252 54 Functional overview STM32H745xI/G A domain can enter low-power mode (DStop or DStandby) when the processor, its subsystem and the peripherals allocated in the domain enter low-power mode. For instance D1 or D2 domain enters DStop/DStandby mode when the CPU of the domain is in CStop mode AND the other CPU has no peripheral allocated in that domain, or if it is in CStop mode too. D3 domain can enter DStop/DStandby mode if both core subsystems do not have active peripherals in D3 domain, and D3 is not forced in Run mode. If part of the domain is not in low-power mode, the domain remains in the current mode. Finally the system can enter Stop or Standby when all EXTI wakeup sources are cleared and the power domains are in DStop or DStandby mode. The clock system can be re-initialize by a master CPU (either the Cortex(R)-M4 or -M7) after exiting Stop mode while the slave CPU is held in low-power mode. Once the master CPU has re-initialized the system, the slave CPU can receive a wakeup interrupt and proceed with the interrupt service routine. Table 3. System vs domain low-power mode D1 domain power mode System power mode Run 3.7 D2 domain power mode DRun/DStop/DStandby DRun/DStop/DStandby D3 domain power mode DRun Stop DStop/DStandby DStop/DStandby DStop Standby DStandby DStandby DStandby Reset and clock controller (RCC) The clock and reset controller is located in D3 domain. The RCC manages the generation of all the clocks, as well as the clock gating and the control of the system and peripheral resets. It provides a high flexibility in the choice of clock sources and allows to apply clock ratios to improve the power consumption. In addition, on some communication peripherals that are capable to work with two different clock domains (either a bus interface clock or a kernel peripheral clock), the system frequency can be changed without modifying the baudrate. 3.7.1 Clock management The devices embed four internal oscillators, two oscillators with external crystal or resonator, two internal oscillators with fast startup time and three PLLs. The RCC receives the following clock source inputs: * * 30/252 Internal oscillators: - 64 MHz HSI clock - 48 MHz RC oscillator - 4 MHz CSI clock - 32 kHz LSI clock External oscillators: - HSE clock: 4-50 MHz (generated from an external source) or 4-48 MHz(generated from a crystal/ceramic resonator) - LSE clock: 32.768 kHz DS12923 Rev 1 STM32H745xI/G Functional overview The RCC provides three PLLs: one for system clock, two for kernel clocks. The system starts on the HSI clock. The user application can then select the clock configuration. 3.7.2 System reset sources Power-on reset initializes all registers while system reset reinitializes the system except for the debug, part of the RCC and power controller status registers, as well as the backup power domain. A system reset is generated in the following cases: 3.8 * Power-on reset (pwr_por_rst) * Brownout reset * Low level on NRST pin (external reset) * Independent watchdog 1 (from D1 domain) * Independent watchdog 2 (from D2 domain) * Window watchdog 1 (from D1 domain) * Window watchdog 2 (from D2 domain) * Software reset * Low-power mode security reset * Exit from Standby General-purpose input/outputs (GPIOs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain, with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high-current-capable and have speed selection to better manage internal noise, power consumption and electromagnetic emission. After reset, all GPIOs (except debug pins) are in Analog mode to reduce power consumption (refer to GPIOs register reset values in the device reference manual). The I/O configuration can be locked if needed by following a specific sequence in order to avoid spurious writing to the I/Os registers. 3.9 Bus-interconnect matrix The devices feature an AXI bus matrix, two AHB bus matrices and bus bridges that allow interconnecting bus masters with bus slaves (see Figure 5). DS12923 Rev 1 31/252 54 AHBS 7 ITCM 64 Kbyte LTDC D1-to-D2 AHB USBHS2 I-bus DMA2D Ethernet SDMMC2 USBHS1 MAC S-bus MDMA DMA1_MEM SDMMC1 DMA2 DMA2_MEM DMA1 DMA2_PERIPH DTCM 128 Kbyte AHBP AXIM I$ D$ 16KB 16KB CPU Cortex-M4 DMA1_PERIPH Cortex-M7 D-bus CPU ART Functional overview 32/252 Figure 5. STM32H745xI/G bus matrix SRAM1 128 Kbyte APB3 4 AHB3 SRAM2 128 Kbyte SRAM3 32 Kbyte Flash A Up to 1 Mbyte 5 DS12923 Rev 1 AHB1 Flash B Up to 1 Mbyte AHB2 AXI SRAM 512 Kbyte APB1 QSPI APB2 FMC 1 64-bit AXI bus matrix D1 domain 32-bit AHB bus matrix D2 domain 2 D2-to-D1 AHB D2-to-D3 AHB BDMA D1-to-D3 AHB 3 32-bit bus TCM AHB AXI APB 64-bit bus Master interface Bus multiplexer Slave interface 6 AHB4 APB4 SRAM4 64 Kbyte 32-bit AHB bus matrix D3 domain Backup SRAM 4 Kbyte MSv39740V3 STM32H745xI/G Legend STM32H745xI/G 3.10 Functional overview DMA controllers The devices feature four DMA instances to unload CPU activity: * A master direct memory access (MDMA) The MDMA is a high-speed DMA controller, which is in charge of all types of memory transfers (peripheral to memory, memory to memory, memory to peripheral), without any CPU action. It features a master AXI interface and a dedicated AHB interface to access Cortex(R)-M7 TCM memories. The MDMA is located in D1 domain. It is able to interface with the other DMA controllers located in D2 domain to extend the standard DMA capabilities, or can manage peripheral DMA requests directly. Each of the 16 channels can perform single block transfers, repeated block transfers and linked list transfers. * Two dual-port DMAs (DMA1, DMA2) located in D2 domain, with FIFO and request router capabilities. * One basic DMA (BDMA) located in D3 domain, with request router capabilities. The DMA request router could be considered as an extension of the DMA controller. It routes the DMA peripheral requests to the DMA controller itself. This allowing managing the DMA requests with a high flexibility, maximizing the number of DMA requests that run concurrently, as well as generating DMA requests from peripheral output trigger or DMA event. 3.11 Chrom-ART AcceleratorTM (DMA2D) The Chrom-Art AcceleratorTM (DMA2D) is a graphical accelerator which offers advanced bit blitting, row data copy and pixel format conversion. It supports the following functions: * Rectangle filling with a fixed color * Rectangle copy * Rectangle copy with pixel format conversion * Rectangle composition with blending and pixel format conversion Various image format coding are supported, from indirect 4bpp color mode up to 32bpp direct color. It embeds dedicated memory to store color lookup tables. The DMA2D also supports block based YCbCr to handle JPEG decoder output. An interrupt can be generated when an operation is complete or at a programmed watermark. All the operations are fully automatized and are running independently from the CPU or the DMAs. DS12923 Rev 1 33/252 54 Functional overview 3.12 STM32H745xI/G Nested vectored interrupt controller (NVIC) Both Cortex(R)-M7 (CPU1) and Cortex(R)-M4 (CPU2) cores have their own nested vector interrupt controller (respectively NVIC1 and NVIC2). Each NVIC instance is able to manage 16 priority levels, and handle up to 150 maskable interrupt channels plus the 16 interrupt lines of the Cortex(R)-M7 with FPU core. * Closely coupled NVIC gives low-latency interrupt processing * Interrupt entry vector table address passed directly to the core * Allows early processing of interrupts * Processing of late arriving, higher-priority interrupts * Support tail chaining * Processor context automatically saved on interrupt entry, and restored on interrupt exit with no instruction overhead This hardware block provides flexible interrupt management features with minimum interrupt latency. 3.13 Extended interrupt and event controller (EXTI) The EXTI controller performs interrupt and event management. In addition, it can wake up the processors, power domains and/or D3 domain from Stop mode. The EXTI handles up to 89 independent event/interrupt lines split as 28 configurable events and 61 direct events (including two interrupt lines for inter-core management). Configurable events have dedicated pending flags, active edge selection, and software trigger capable. Direct events provide interrupts or events from peripherals having a status flag. 3.14 Cyclic redundancy check calculation unit (CRC) The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a programmable polynomial. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location. 34/252 DS12923 Rev 1 STM32H745xI/G 3.15 Functional overview Flexible memory controller (FMC) The FMC controller main features are the following: * Interface with static-memory mapped devices including: 3.16 - Static random access memory (SRAM) - NOR Flash memory/OneNAND Flash memory - PSRAM (4 memory banks) - NAND Flash memory with ECC hardware to check up to 8 Kbytes of data * Interface with synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) memories * 8-,16-,32-bit data bus width * Independent Chip Select control for each memory bank * Independent configuration for each memory bank * Write FIFO * Read FIFO for SDRAM controller * The maximum FMC_CLK/FMC_SDCLK frequency for synchronous accesses is the FMC kernel clock divided by 2. Quad-SPI memory interface (QUADSPI) All devices embed a Quad-SPI memory interface, which is a specialized communication interface targeting Single, Dual or Quad-SPI Flash memories. It supports both single and double datarate operations. It can operate in any of the following modes: * Direct mode through registers * External Flash status register polling mode * Memory mapped mode. Up to 256 Mbytes of external Flash memory can be mapped, and 8-, 16- and 32-bit data accesses are supported as well as code execution. The opcode and the frame format are fully programmable. 3.17 Analog-to-digital converters (ADCs) The STM32H745xI/G devices embed three analog-to-digital converters, which resolution can be configured to 16, 14, 12, 10 or 8 bits. Each ADC shares up to 20 external channels, performing conversions in the Single-shot or Scan mode. In Scan mode, automatic conversion is performed on a selected group of analog inputs. Additional logic functions embedded in the ADC interface allow: * Simultaneous sample and hold * Interleaved sample and hold The ADC can be served by the DMA controller, thus allowing to automatically transfer ADC converted values to a destination location without any software action. DS12923 Rev 1 35/252 54 Functional overview STM32H745xI/G In addition, an analog watchdog feature can accurately monitor the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds. To synchronize A/D conversion and timers, the ADCs could be triggered by any of TIM1, TIM2, TIM3, TIM4, TIM6, TIM8, TIM15, HRTIM1 and LPTIM1 timer. 3.18 Temperature sensor STM32H745xI/G devices embed a temperature sensor that generates a voltage (VTS) that varies linearly with the temperature. This temperature sensor is internally connected to ADC3_IN18. The conversion range is between 1.7 V and 3.6 V. It can measure the device junction temperature ranging from - 40 up to +140 C. The temperature sensor have a good linearity, but it has to be calibrated to obtain a good overall accuracy of the temperature measurement. As the temperature sensor offset varies from chip to chip due to process variation, the uncalibrated internal temperature sensor is suitable for applications that detect temperature changes only. To improve the accuracy of the temperature sensor measurement, each device is individually factory-calibrated by ST. The temperature sensor factory calibration data are stored by ST in the System memory area, which is accessible in Read-only mode. 3.19 VBAT operation The VBAT power domain contains the RTC, the backup registers and the backup SRAM. To optimize battery duration, this power domain is supplied by VDD when available or by the voltage applied on VBAT pin (when VDD supply is not present). VBAT power is switched when the PDR detects that VDD dropped below the PDR level. The voltage on the VBAT pin could be provided by an external battery, a supercapacitor or directly by VDD, in which case, the VBAT mode is not functional. VBAT operation is activated when VDD is not present. The VBAT pin supplies the RTC, the backup registers and the backup SRAM. Note: When the microcontroller is supplied from VBAT, external interrupts and RTC alarm/events do not exit it from VBAT operation. When PDR_ON pin is connected to VSS (Internal Reset OFF), the VBAT functionality is no more available and VBAT pin should be connected to VDD. 36/252 DS12923 Rev 1 STM32H745xI/G 3.20 Functional overview Digital-to-analog converters (DAC) The two 12-bit buffered DAC channels can be used to convert two digital signals into two analog voltage signal outputs. This dual digital Interface supports the following features: * two DAC converters: one for each output channel * 8-bit or 12-bit monotonic output * left or right data alignment in 12-bit mode * synchronized update capability * noise-wave generation * triangular-wave generation * dual DAC channel independent or simultaneous conversions * DMA capability for each channel including DMA underrun error detection * external triggers for conversion * input voltage reference VREF+ or internal VREFBUF reference. The DAC channels are triggered through the timer update outputs that are also connected to different DMA streams. 3.21 Ultra-low-power comparators (COMP) STM32H745xI/G devices embed two rail-to-rail comparators (COMP1 and COMP2). They feature programmable reference voltage (internal or external), hysteresis and speed (low speed for low-power) as well as selectable output polarity. The reference voltage can be one of the following: * An external I/O * A DAC output channel * An internal reference voltage or submultiple (1/4, 1/2, 3/4). All comparators can wake up from Stop mode, generate interrupts and breaks for the timers, and be combined into a window comparator. 3.22 Operational amplifiers (OPAMP) STM32H745xI/G devices embed two rail-to-rail operational amplifiers (OPAMP1 and OPAMP2) with external or internal follower routing and PGA capability. The operational amplifier main features are: * PGA with a non-inverting gain ranging of 2, 4, 8 or 16 or inverting gain ranging of -1, -3, -7 or -15 * One positive input connected to DAC * Output connected to internal ADC * Low input bias current down to 1 nA * Low input offset voltage down to 1.5 mV * Gain bandwidth up to 7.3 MHz DS12923 Rev 1 37/252 54 Functional overview STM32H745xI/G The devices embeds two operational amplifiers (OPAMP1 and OPAMP2) with two inputs and one output each. These three I/Os can be connected to the external pins, thus enabling any type of external interconnections. The operational amplifiers can be configured internally as a follower, as an amplifier with a non-inverting gain ranging from 2 to 16 or with inverting gain ranging from -1 to -15. 3.23 Digital filter for sigma-delta modulators (DFSDM) The devices embed one DFSDM with 4 digital filters modules and 8 external input serial channels (transceivers) or alternately 8 internal parallel inputs support. The DFSDM peripheral is dedicated to interface the external modulators to microcontroller and then to perform digital filtering of the received data streams (which represent analog value on modulators inputs). DFSDM can also interface PDM (Pulse Density Modulation) microphones and perform PDM to PCM conversion and filtering in hardware. DFSDM features optional parallel data stream inputs from internal ADC peripherals or microcontroller memory (through DMA/CPU transfers into DFSDM). DFSDM transceivers support several serial interface formats (to support various modulators). DFSDM digital filter modules perform digital processing according user selected filter parameters with up to 24-bit final ADC resolution. The DFSDM peripheral supports: * * 8 multiplexed input digital serial channels: - configurable SPI interface to connect various SD modulator(s) - configurable Manchester coded 1 wire interface support - PDM (Pulse Density Modulation) microphone input support - maximum input clock frequency up to 20 MHz (10 MHz for Manchester coding) - clock output for SD modulator(s): 0..20 MHz alternative inputs from 8 internal digital parallel channels (up to 16 bit input resolution): - * - Sincx filter: filter order/type (1..5), oversampling ratio (up to 1..1024) - integrator: oversampling ratio (1..256) * up to 24-bit output data resolution, signed output data format * automatic data offset correction (offset stored in register by user) * continuous or single conversion * start-of-conversion triggered by: * 38/252 internal sources: ADC data or memory data streams (DMA) 4 digital filter modules with adjustable digital signal processing: - software trigger - internal timers - external events - start-of-conversion synchronously with first digital filter module (DFSDM0) analog watchdog feature: - low value and high value data threshold registers - dedicated configurable Sincx digital filter (order = 1..3, oversampling ratio = 1..32) - input from final output data or from selected input digital serial channels - continuous monitoring independently from standard conversion DS12923 Rev 1 STM32H745xI/G * Functional overview short circuit detector to detect saturated analog input values (bottom and top range): - up to 8-bit counter to detect 1..256 consecutive 0's or 1's on serial data stream - monitoring continuously each input serial channel * break signal generation on analog watchdog event or on short circuit detector event * extremes detector: - storage of minimum and maximum values of final conversion data - refreshed by software * DMA capability to read the final conversion data * interrupts: end of conversion, overrun, analog watchdog, short circuit, input serial channel clock absence * "regular" or "injected" conversions: - "regular" conversions can be requested at any time or even in Continuous mode without having any impact on the timing of "injected" conversions - "injected" conversions for precise timing and with high conversion priority Table 4. DFSDM implementation DFSDM features 3.24 DFSDM1 Number of filters 4 Number of input transceivers/channels 8 Internal ADC parallel input X Number of external triggers 16 Regular channel information in identification register X Digital camera interface (DCMI) The devices embed a camera interface that can connect with camera modules and CMOS sensors through an 8-bit to 14-bit parallel interface, to receive video data. The camera interface can achieve a data transfer rate up to 105 Mbyte/s using a 60 MHz pixel clock. It features: * Programmable polarity for the input pixel clock and synchronization signals * Parallel data communication can be 8-, 10-, 12- or 14-bit * Supports 8-bit progressive video monochrome or raw bayer format, YCbCr 4:2:2 progressive video, RGB 565 progressive video or compressed data (like JPEG) * Supports Continuous mode or Snapshot (a single frame) mode * Capability to automatically crop the image DS12923 Rev 1 39/252 54 Functional overview 3.25 STM32H745xI/G LCD-TFT controller The LCD-TFT display controller provides a 24-bit parallel digital RGB (Red, Green, Blue) and delivers all signals to interface directly to a broad range of LCD and TFT panels up to XGA (1024x768) resolution with the following features: 3.26 * 2 display layers with dedicated FIFO (64x64-bit) * Color Look-Up table (CLUT) up to 256 colors (256x24-bit) per layer * Up to 8 input color formats selectable per layer * Flexible blending between two layers using alpha value (per pixel or constant) * Flexible programmable parameters for each layer * Color keying (transparency color) * Up to 4 programmable interrupt events * AXI master interface with burst of 16 words JPEG Codec (JPEG) The JPEG Codec can encode and decode a JPEG stream as defined in the ISO/IEC 109181 specification. It provides an fast and simple hardware compressor and decompressor of JPEG images with full management of JPEG headers. The JPEG codec main features are as follows: 3.27 * 8-bit/channel pixel depths * Single clock per pixel encoding and decoding * Support for JPEG header generation and parsing * Up to four programmable quantization tables * Fully programmable Huffman tables (two AC and two DC) * Fully programmable minimum coded unit (MCU) * Encode/decode support (non simultaneous) * Single clock Huffman coding and decoding * Two-channel interface: Pixel/Compress In, Pixel/Compressed Out * Support for single greyscale component * Ability to enable/disable header processing * Fully synchronous design * Configuration for High-speed decode mode Random number generator (RNG) All devices embed an RNG that delivers 32-bit random numbers generated by an integrated analog circuit. 3.28 Timers and watchdogs The devices include one high-resolution timer, two advanced-control timers, ten generalpurpose timers, two basic timers, five low-power timers, two watchdogs and a SysTick timer. 40/252 DS12923 Rev 1 STM32H745xI/G Functional overview All timer counters can be frozen in Debug mode. Table 5 compares the features of the advanced-control, general-purpose and basic timers. Table 5. Timer feature comparison Timer type Timer Highresolution HRTIM1 timer Advanced -control TIM1, TIM8 TIM2, TIM5 TIM3, TIM4 TIM12 DMA Capture/ Counter Counter Prescaler request compare resolution type factor generation channels TIM15 TIM16, TIM17 Max interface clock (MHz) Max timer clock (MHz) (1)(2) /1 /2 /4 (x2 x4 x8 x16 x32, with DLL) Yes 10 Yes 480(2) 480 16-bit Any Up, integer Down, between 1 Up/down and 65536 Yes 4 Yes 120 240 32-bit Any Up, integer Down, between 1 Up/down and 65536 Yes 4 No 120 240 16-bit Any Up, integer Down, between 1 Up/down and 65536 Yes 4 No 120 240 16-bit Up Any integer between 1 and 65536 No 2 No 120 240 Up Any integer between 1 and 65536 No 1 No 120 240 Up Any integer between 1 and 65536 Yes 2 1 120 240 Up Any integer between 1 and 65536 Yes 1 1 120 240 16-bit Up General purpose TIM13, TIM14 Complementary output 16-bit 16-bit 16-bit DS12923 Rev 1 41/252 54 Functional overview STM32H745xI/G Table 5. Timer feature comparison (continued) Timer type Timer DMA Capture/ Counter Counter Prescaler request compare resolution type factor generation channels Basic TIM6, TIM7 16-bit Up Any integer between 1 and 65536 Lowpower timer LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5 16-bit Up 1, 2, 4, 8, 16, 32, 64, 128 Complementary output Max interface clock (MHz) Max timer clock (MHz) (1)(2) Yes 0 No 120 240 No 0 No 120 240 1. The maximum timer clock is up to 480 MHz depending on TIMPRE bit in the RCC_CFGR register and D2PRE1/2 bits in RCC_D2CFGR register. 2. On STM32H745xxx3 sales types (extended industrial temperature range), the maximum clock frequency is 300 MHz for the high-resolution timer and 150 MHz for the other timers. 3.28.1 High-resolution timer (HRTIM1) The high-resolution timer (HRTIM1) allows generating digital signals with high-accuracy timings, such as PWM or phase-shifted pulses. It consists of 6 timers, 1 master and 5 slaves, totaling 10 high-resolution outputs, which can be coupled by pairs for deadtime insertion. It also features 5 fault inputs for protection purposes and 10 inputs to handle external events such as current limitation, zero voltage or zero current switching. The HRTIM1 timer is made of a digital kernel clocked at 480 MHz(a) The high-resolution is available on the 10 outputs in all operating modes: variable duty cycle, variable frequency, and constant ON time. The slave timers can be combined to control multiswitch complex converters or operate independently to manage multiple independent converters. The waveforms are defined by a combination of user-defined timings and external events such as analog or digital feedbacks signals. HRTIM1 timer includes options for blanking and filtering out spurious events or faults. It also offers specific modes and features to offload the CPU: DMA requests, Burst mode controller, Push-pull and Resonant mode. It supports many topologies including LLC, Full bridge phase shifted, buck or boost converters, either in voltage or current mode, as well as lighting application (fluorescent or LED). It can also be used as a general purpose timer, for instance to achieve high-resolution PWM-emulated DAC. a. Up to 300 MHz for STM32H745xxx3 sales types (extended industrial temperature range). 42/252 DS12923 Rev 1 STM32H745xI/G 3.28.2 Functional overview Advanced-control timers (TIM1, TIM8) The advanced-control timers (TIM1, TIM8) can be seen as three-phase PWM generators multiplexed on 6 channels. They have complementary PWM outputs with programmable inserted dead times. They can also be considered as complete general-purpose timers. Their 4 independent channels can be used for: * Input capture * Output compare * PWM generation (Edge- or Center-aligned modes) * One-pulse mode output If configured as standard 16-bit timers, they have the same features as the general-purpose TIMx timers. If configured as 16-bit PWM generators, they have full modulation capability (0100%). The advanced-control timer can work together with the TIMx timers via the Timer Link feature for synchronization or event chaining. TIM1 and TIM8 support independent DMA request generation. 3.28.3 General-purpose timers (TIMx) There are ten synchronizable general-purpose timers embedded in the STM32H745xI/G devices (see Table 5 for differences). * TIM2, TIM3, TIM4, TIM5 The devices include 4 full-featured general-purpose timers: TIM2, TIM3, TIM4 and TIM5. TIM2 and TIM5 are based on a 32-bit auto-reload up/downcounter and a 16-bit prescaler while TIM3 and TIM4 are based on a 16-bit auto-reload up/downcounter and a 16-bit prescaler. All timers feature 4 independent channels for input capture/output compare, PWM or One-pulse mode output. This gives up to 16 input capture/output compare/PWMs on the largest packages. TIM2, TIM3, TIM4 and TIM5 general-purpose timers can work together, or with the other general-purpose timers and the advanced-control timers TIM1 and TIM8 via the Timer Link feature for synchronization or event chaining. Any of these general-purpose timers can be used to generate PWM outputs. TIM2, TIM3, TIM4, TIM5 all have independent DMA request generation. They are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 4 hall-effect sensors. * TIM12, TIM13, TIM14, TIM15, TIM16, TIM17 These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler. TIM13, TIM14, TIM16 and TIM17 feature one independent channel, whereas TIM12 and TIM15 have two independent channels for input capture/output compare, PWM or One-pulse mode output. They can be synchronized with the TIM2, TIM3, TIM4, TIM5 full-featured general-purpose timers or used as simple timebases. DS12923 Rev 1 43/252 54 Functional overview 3.28.4 STM32H745xI/G Basic timers TIM6 and TIM7 These timers are mainly used for DAC trigger and waveform generation. They can also be used as a generic 16-bit time base. TIM6 and TIM7 support independent DMA request generation. 3.28.5 Low-power timers (LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5) The low-power timers have an independent clock and is running also in Stop mode if it is clocked by LSE, LSI or an external clock. It is able to wakeup the devices from Stop mode. This low-power timer supports the following features: 3.28.6 * 16-bit up counter with 16-bit autoreload register * 16-bit compare register * Configurable output: pulse, PWM * Continuous / One-shot mode * Selectable software / hardware input trigger * Selectable clock source: * Internal clock source: LSE, LSI, HSI or APB clock * External clock source over LPTIM input (working even with no internal clock source running, used by the Pulse Counter Application) * Programmable digital glitch filter * Encoder mode Independent watchdogs There are two independent watchdogs, one per domain. Each independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 32 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. It is hardware- or software-configurable through the option bytes. 3.28.7 Window watchdogs There are two window watchdogs, one per domain. Each window watchdog is based on a 7bit downcounter that can be set as free-running. It can be used as a watchdog to reset the device or each respective domain (configurable in the RCC register), when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in Debug mode. 3.28.8 SysTick timer The devices feature two SysTick timers, one per CPU. These timers are dedicated to realtime operating systems, but could also be used as a standard downcounter. It features: 44/252 * A 24-bit downcounter * Autoreload capability * Maskable system interrupt generation when the counter reaches 0 * Programmable clock source. DS12923 Rev 1 STM32H745xI/G 3.29 Functional overview Real-time clock (RTC), backup SRAM and backup registers The RTC is an independent BCD timer/counter. It supports the following features: * Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date, month, year, in BCD (binary-coded decimal) format. * Automatic correction for 28, 29 (leap year), 30, and 31 days of the month. * Two programmable alarms. * On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to synchronize it with a master clock. * Reference clock detection: a more precise second source clock (50 or 60 Hz) can be used to enhance the calendar precision. * Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal inaccuracy. * Three anti-tamper detection pins with programmable filter. * Timestamp feature which can be used to save the calendar content. This function can be triggered by an event on the timestamp pin, or by a tamper event, or by a switch to VBAT mode. * 17-bit auto-reload wakeup timer (WUT) for periodic events with programmable resolution and period. The RTC and the 32 backup registers are supplied through a switch that takes power either from the VDD supply when present or from the VBAT pin. The backup registers are 32-bit registers used to store 128 bytes of user application data when VDD power is not present. They are not reset by a system or power reset, or when the device wakes up from Standby mode. The RTC clock sources can be: * A 32.768 kHz external crystal (LSE) * An external resonator or oscillator (LSE) * The internal low-power RC oscillator (LSI, with typical frequency of 32 kHz) * The high-speed external clock (HSE) divided by 32. The RTC is functional in VBAT mode and in all low-power modes when it is clocked by the LSE. When clocked by the LSI, the RTC is not functional in VBAT mode, but is functional in all low-power modes. All RTC events (Alarm, Wakeup Timer, Timestamp or Tamper) can generate an interrupt and wakeup the device from the low-power modes. DS12923 Rev 1 45/252 54 Functional overview 3.30 STM32H745xI/G Inter-integrated circuit interface (I2C) STM32H745xI/G devices embed four I2C interfaces. The I2C bus interface handles communications between the microcontroller and the serial I2C bus. It controls all I2C bus-specific sequencing, protocol, arbitration and timing. The I2C peripheral supports: * * 3.31 I2C-bus specification and user manual rev. 5 compatibility: - Slave and Master modes, multimaster capability - Standard-mode (Sm), with a bitrate up to 100 kbit/s - Fast-mode (Fm), with a bitrate up to 400 kbit/s - Fast-mode Plus (Fm+), with a bitrate up to 1 Mbit/s and 20 mA output drive I/Os - 7-bit and 10-bit addressing mode, multiple 7-bit slave addresses - Programmable setup and hold times - Optional clock stretching System Management Bus (SMBus) specification rev 2.0 compatibility: - Hardware PEC (Packet Error Checking) generation and verification with ACK control - Address resolution protocol (ARP) support - SMBus alert * Power System Management Protocol (PMBusTM) specification rev 1.1 compatibility * Independent clock: a choice of independent clock sources allowing the I2C communication speed to be independent from the PCLK reprogramming. * Wakeup from Stop mode on address match * Programmable analog and digital noise filters * 1-byte buffer with DMA capability Universal synchronous/asynchronous receiver transmitter (USART) STM32H745xI/G devices have four embedded universal synchronous receiver transmitters (USART1, USART2, USART3 and USART6) and four universal asynchronous receiver transmitters (UART4, UART5, UART7 and UART8). Refer to Table 6 for a summary of USARTx and UARTx features. These interfaces provide asynchronous communication, IrDA SIR ENDEC support, multiprocessor communication mode, single-wire Half-duplex communication mode and have LIN Master/Slave capability. They provide hardware management of the CTS and RTS signals, and RS485 Driver Enable. They are able to communicate at speeds of up to 12.5 Mbit/s. USART1, USART2, USART3 and USART6 also provide Smartcard mode (ISO 7816 compliant) and SPI-like communication capability. The USARTs embed a Transmit FIFO (TXFIFO) and a Receive FIFO (RXFIFO). FIFO mode is enabled by software and is disabled by default. 46/252 DS12923 Rev 1 STM32H745xI/G Functional overview All USART have a clock domain independent from the CPU clock, allowing the USARTx to wake up the MCU from Stop mode.The wakeup from Stop mode is programmable and can be done on: * Start bit detection * Any received data frame * A specific programmed data frame * Specific TXFIFO/RXFIFO status when FIFO mode is enabled. All USART interfaces can be served by the DMA controller. Table 6. USART features USART modes/features(1) USART1/2/3/6 UART4/5/7/8 Hardware flow control for modem X X Continuous communication using DMA X X Multiprocessor communication X X Synchronous mode (Master/Slave) X - Smartcard mode X - Single-wire Half-duplex communication X X IrDA SIR ENDEC block X X LIN mode X X Dual clock domain and wakeup from low power mode X X Receiver timeout interrupt X X Modbus communication X X Auto baud rate detection X X Driver Enable X X USART data length 7, 8 and 9 bits Tx/Rx FIFO X Tx/Rx FIFO size X 16 1. X = supported. 3.32 Low-power universal asynchronous receiver transmitter (LPUART) The device embeds one Low-Power UART (LPUART1). The LPUART supports asynchronous serial communication with minimum power consumption. It supports half duplex single wire communication and modem operations (CTS/RTS). It allows multiprocessor communication. The LPUARTs embed a Transmit FIFO (TXFIFO) and a Receive FIFO (RXFIFO). FIFO mode is enabled by software and is disabled by default. DS12923 Rev 1 47/252 54 Functional overview STM32H745xI/G The LPUART has a clock domain independent from the CPU clock, and can wakeup the system from Stop mode. The wakeup from Stop mode are programmable and can be done on: * Start bit detection * Any received data frame * A specific programmed data frame * Specific TXFIFO/RXFIFO status when FIFO mode is enabled. Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to 9600 baud. Therefore, even in Stop mode, the LPUART can wait for an incoming frame while having an extremely low energy consumption. Higher speed clock can be used to reach higher baudrates. LPUART interface can be served by the DMA controller. 3.33 Serial peripheral interface (SPI)/inter- integrated sound interfaces (I2S) The devices feature up to six SPIs (SPI2S1, SPI2S2, SPI2S3, SPI4, SPI5 and SPI6) that allow communicating up to 150 Mbits/s in Master and Slave modes, in Half-duplex, Fullduplex and Simplex modes. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable from 4 to 16 bits. All SPI interfaces support NSS pulse mode, TI mode, Hardware CRC calculation and 8x 8-bit embedded Rx and Tx FIFOs with DMA capability. Three standard I2S interfaces (multiplexed with SPI1, SPI2 and SPI3) are available. They can be operated in Master or Slave mode, in Simplex communication modes, and can be configured to operate with a 16-/32-bit resolution as an input or output channel. Audio sampling frequencies from 8 kHz up to 192 kHz are supported. When either or both of the I2S interfaces is/are configured in Master mode, the master clock can be output to the external DAC/CODEC at 256 times the sampling frequency. All I2S interfaces support 16x 8bit embedded Rx and Tx FIFOs with DMA capability. 3.34 Serial audio interfaces (SAI) The devices embed 4 SAIs (SAI1, SAI2, SAI3 and SAI4) that allow designing many stereo or mono audio protocols such as I2S, LSB or MSB-justified, PCM/DSP, TDM or AC'97. An SPDIF output is available when the audio block is configured as a transmitter. To bring this level of flexibility and reconfigurability, the SAI contains two independent audio sub-blocks. Each block has it own clock generator and I/O line controller. Audio sampling frequencies up to 192 kHz are supported. In addition, up to 8 microphones can be supported thanks to an embedded PDM interface. The SAI can work in master or slave configuration. The audio sub-blocks can be either receiver or transmitter and can work synchronously or asynchronously (with respect to the other one). The SAI can be connected with other SAIs to work synchronously. 48/252 DS12923 Rev 1 STM32H745xI/G 3.35 Functional overview SPDIFRX Receiver Interface (SPDIFRX) The SPDIFRX peripheral is designed to receive an S/PDIF flow compliant with IEC-60958 and IEC-61937. These standards support simple stereo streams up to high sample rate, and compressed multi-channel surround sound, such as those defined by Dolby or DTS (up to 5.1). The main SPDIFRX features are the following: * Up to 4 inputs available * Automatic symbol rate detection * Maximum symbol rate: 12.288 MHz * Stereo stream from 32 to 192 kHz supported * Supports Audio IEC-60958 and IEC-61937, consumer applications * Parity bit management * Communication using DMA for audio samples * Communication using DMA for control and user channel information * Interrupt capabilities The SPDIFRX receiver provides all the necessary features to detect the symbol rate, and decode the incoming data stream. The user can select the wanted SPDIF input, and when a valid signal will be available, the SPDIFRX will re-sample the incoming signal, decode the Manchester stream, recognize frames, sub-frames and blocks elements. It delivers to the CPU decoded data, and associated status flags. The SPDIFRX also offers a signal named spdif_frame_sync, which toggles at the S/PDIF sub-frame rate that will be used to compute the exact sample rate for clock drift algorithms. 3.36 Single wire protocol master interface (SWPMI) The Single wire protocol master interface (SWPMI) is the master interface corresponding to the Contactless Frontend (CLF) defined in the ETSI TS 102 613 technical specification. The main features are: * Full-duplex communication mode * automatic SWP bus state management (active, suspend, resume) * configurable bitrate up to 2 Mbit/s * automatic SOF, EOF and CRC handling SWPMI can be served by the DMA controller. DS12923 Rev 1 49/252 54 Functional overview 3.37 STM32H745xI/G Management Data Input/Output (MDIO) slaves The devices embed an MDIO slave interface it includes the following features: * - 32 x 16-bit firmware read/write, MDIO read-only output data registers - 32 x 16-bit firmware read-only, MDIO write-only input data registers * Configurable slave (port) address * Independently maskable interrupts/events: * 3.38 32 MDIO Registers addresses, each of which is managed using separate input and output data registers: - MDIO Register write - MDIO Register read - MDIO protocol error Able to operate in and wake up from Stop mode SD/SDIO/MMC card host interfaces (SDMMC) Two SDMMC host interfaces are available. They support MultiMediaCard System Specification Version 4.51 in three different databus modes: 1 bit (default), 4 bits and 8 bits. Both interfaces support the SD memory card specifications version 4.1. and the SDIO card specification version 4.0. in two different databus modes: 1 bit (default) and 4 bits. Each SDMMC host interface supports only one SD/SDIO/MMC card at any one time and a stack of MMC Version 4.51 or previous. The SDMMC host interface embeds a dedicated DMA controller allowing high-speed transfers between the interface and the SRAM. 3.39 Controller area network (FDCAN1, FDCAN2) The controller area network (CAN) subsystem consists of two CAN modules, a shared message RAM memory and a clock calibration unit. Both CAN modules (FDCAN1 and FDCAN2) are compliant with ISO 11898-1 (CAN protocol specification version 2.0 part A, B) and CAN FD protocol specification version 1.0. FDCAN1 supports time triggered CAN (TT-FDCAN) specified in ISO 11898-4, including event synchronized time-triggered communication, global system time, and clock drift compensation. The FDCAN1 contains additional registers, specific to the time triggered feature. The CAN FD option can be used together with event-triggered and time-triggered CAN communication. A 10-Kbyte message RAM memory implements filters, receive FIFOs, receive buffers, transmit event FIFOs, transmit buffers (and triggers for TT-FDCAN). This message RAM is shared between the two FDCAN1 and FDCAN2 modules. The common clock calibration unit is optional. It can be used to generate a calibrated clock for both FDCAN1 and FDCAN2 from the HSI internal RC oscillator and the PLL, by evaluating CAN messages received by the FDCAN1. 50/252 DS12923 Rev 1 STM32H745xI/G 3.40 Functional overview Universal serial bus on-the-go high-speed (OTG_HS) The devices embed two USB OTG high-speed (up to 480 Mbit/s) device/host/OTG peripheral. OTG-HS1 supports both full-speed and high-speed operations, while OTG-HS2 supports only full-speed operations. They both integrate the transceivers for full-speed operation (12 Mbit/s) and are able to operate from the internal HSI48 oscillator. OTG-HS1 features a UTMI low-pin interface (ULPI) for high-speed operation (480 Mbit/s). When using the USB OTG-HS1 in HS mode, an external PHY device connected to the ULPI is required. The USB OTG HS peripherals are compliant with the USB 2.0 specification and with the OTG 2.0 specification. They have software-configurable endpoint setting and supports suspend/resume. The USB OTG controllers require a dedicated 48 MHz clock that is generated by a PLL connected to the HSE oscillator. The main features are: * Combined Rx and Tx FIFO size of 4 Kbytes with dynamic FIFO sizing * Supports the session request protocol (SRP) and host negotiation protocol (HNP) * 9 bidirectional endpoints (including EP0) * 16 host channels with periodic OUT support * Software configurable to OTG1.3 and OTG2.0 modes of operation * USB 2.0 LPM (Link Power Management) support * Battery Charging Specification Revision 1.2 support * Internal FS OTG PHY support * External HS or HS OTG operation supporting ULPI in SDR mode (OTG_HS1 only) The OTG PHY is connected to the microcontroller ULPI port through 12 signals. It can be clocked using the 60 MHz output. 3.41 * Internal USB DMA * HNP/SNP/IP inside (no need for any external resistor) * For OTG/Host modes, a power switch is needed in case bus-powered devices are connected Ethernet MAC interface with dedicated DMA controller (ETH) The devices provide an IEEE-802.3-2002-compliant media access controller (MAC) for ethernet LAN communications through an industry-standard medium-independent interface (MII) or a reduced medium-independent interface (RMII). The microcontroller requires an external physical interface device (PHY) to connect to the physical LAN bus (twisted-pair, fiber, etc.). The PHY is connected to the device MII port using 17 signals for MII or 9 signals for RMII, and can be clocked using the 25 MHz (MII) from the microcontroller. DS12923 Rev 1 51/252 54 Functional overview STM32H745xI/G The devices include the following features: 3.42 * Supports 10 and 100 Mbit/s rates * Dedicated DMA controller allowing high-speed transfers between the dedicated SRAM and the descriptors * Tagged MAC frame support (VLAN support) * Half-duplex (CSMA/CD) and full-duplex operation * MAC control sublayer (control frames) support * 32-bit CRC generation and removal * Several address filtering modes for physical and multicast address (multicast and group addresses) * 32-bit status code for each transmitted or received frame * Internal FIFOs to buffer transmit and receive frames. The transmit FIFO and the receive FIFO are both 2 Kbytes. * Supports hardware PTP (precision time protocol) in accordance with IEEE 1588 2008 (PTP V2) with the time stamp comparator connected to the TIM2 input * Triggers interrupt when system time becomes greater than target time High-definition multimedia interface (HDMI) - consumer electronics control (CEC) The devices embed a HDMI-CEC controller that provides hardware support for the Consumer Electronics Control (CEC) protocol (Supplement 1 to the HDMI standard). This protocol provides high-level control functions between all audiovisual products in an environment. It is specified to operate at low speeds with minimum processing and memory overhead. It has a clock domain independent from the CPU clock, allowing the HDMI-CEC controller to wakeup the MCU from Stop mode on data reception. 3.43 Debug infrastructure The devices offer a comprehensive set of debug and trace features on both cores to support software development and system integration. * Breakpoint debugging * Code execution tracing * Software instrumentation * JTAG debug port * Serial-wire debug port * Trigger input and output * Serial-wire trace port * Trace port * Arm(R) CoreSightTM debug and trace components The debug can be controlled via a JTAG/Serial-wire debug access port, using industry standard debugging tools. The debug infrastructure allows debugging one core at a time, or both cores in parallel. The trace port performs data capture for logging and analysis. 52/252 DS12923 Rev 1 STM32H745xI/G Functional overview A 4-Kbyte embedded trace FIFO (ETF) allows recording data and sending them to any com port. In Trace mode, the trace is transferred by DMA to system RAM or to a high-speed interface (such as SPI or USB). It can even be monitored by a software running on one of the cores. Unlike hardware FIFO mode, this mode is invasive since it uses system resources which are shared by the processors. DS12923 Rev 1 53/252 54 Memory mapping 4 STM32H745xI/G Memory mapping Refer to the product line reference manual for details on the memory mapping as well as the boundary addresses for all peripherals. 54/252 DS12923 Rev 1 STM32H745xI/G 5 Pin descriptions Pin descriptions PC10 PC11 PC12 PD0 PD1 PD2 PD3 PD4 PD5 VSS VDD PD6 PD7 PG9 PG10 PG11 PG12 PG13 PG14 VSS VDD PB3 PB4 PB5 PB6 PB7 BOOT0 PB8 PB9 PE0 PE1 VCAP VSS PDR_ON VDDLDO 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 VDD Figure 6. LQFP144 pinout PA15 PA14 VDD VDDLDO VSS VCAP PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 VDD VDD33USB VDD50USB VSS PG8 PG7 PG6 PD15 PD14 PD13 PD12 PD11 VSS VDD PD10 PD9 PD8 PB15 PB14 PB13 PB12 VDD VDDLDO VSS VCAP PB11 PB10 PE15 PE14 PE13 PE12 PE11 PE10 PE9 PE8 PE7 VDD VSS PF15 PF14 PF11 PB2 PB1 PB0 PC5 PC4 PA7 PA6 PA5 PA4 VDD VSS PA3 PA2 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 144-pins 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 PA0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 PA1 PE2 PE3 PE4 PE5 PE6 VSS VDD VBAT PC13 PC14-OSC32_IN PC15-OSC32_OUT VSS VDD VSSSMPS VLXSMPS VDDSMPS VFBSMPS VSS VDD PF6 PF7 PF8 PF9 PF10 PH0-OSC_IN PH1-OSC_OUT NRST PC0 PC1 PC2_C PC3_C VDD VSS VSSA VREF+ VDDA MSv43750V3 DS12923 Rev 1 55/252 104 Pin descriptions STM32H745xI/G PE2 PE3 PE4 PE5 PE6 VSS VDD VBAT PC13 PC14-OSC32_IN PC15-OSC32_OUT VSS VDD VSSSMPS VLXSMPS VDDSMPS VFBSMPS PF0 PF1 PF2 PF3 PF4 PF5 VSS VDD PF6 PF7 PF8 PF9 PF10 PH0-OSC_IN PH1-OSC_OUT NRST PC0 PC1 PC2_C PC3_C VSSA VREF+ VDDA PA0 PA1 PA2 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 176-pins 134 133 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 VDD VDDLDO PDR_ON VSS VCAP PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PG15 VDD VSS PG14 PG13 PG12 PG11 PG10 PG9 VDD VSS PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14 VSS VDD VDDLDO VSS VCAP Figure 7. LQFP176 pinout 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 PA13 PA12 PA11 PA10 PA9 PA8 VDD PC9 PC8 PC7 PC6 VDD33USB VDD50USB VSS PG8 PG7 PG6 PG5 PG4 VDD VSS PG3 PG2 PK2 PK1 PK0 VSS VDD PJ11 PJ10 PJ9 PJ8 VSS VDD PD15 PD14 PD13 PD12 PD11 VSS VDD PD10 PD9 PD8 VSS PA3 VSS NC PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PF11 PF12 PF13 PF14 PF15 PG0 VSS VDD PG1 PE7 PE8 PE9 VSS VDD PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VCAP VSS VDDLDO VSS VDD PB12 PB13 PB14 PB15 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 MSv43751V3 1. The above figure shows the package top view. 56/252 DS12923 Rev 1 STM32H745xI/G Pin descriptions Figure 8. UFBGA176+25 ballout 1 2 3 4 5 6 7 8 9 10 11 VCAP PB6 PB3 PG11 PG9 PD3 PD1 PA15 12 13 14 PA14 VDD LDO 15 VCAP VSS PA8 PA12 A VSS PB8 VDD LDO B PE4 PE3 PB9 PE0 PB7 PB4 PG13 PD7 PD5 PD2 PC12 PH14 C PC13 VSS PE2 PE1 BOOT0 PB5 PG14 PG10 PD4 PD0 PC11 PC10 PH13 PA10 PA11 D PC15OSC32 _OUT PC14OSC32_ IN PE5 PDR_ ON VDD VSS PG15 PG12 PD6 VSS VDD PH15 PA9 PC8 PC7 E VSS VBAT PE6 VDD VDD PC9 PC6 VDD50 USB F VLX SMPS VSS SMPS PF1 PF0 VSS VSS VSS VSS VSS VSS VDD33 USB PG6 PG5 G VDD SMPS VFB SMPS PF2 VDD VSS VSS VSS VSS VSS PG8 PG7 PG4 PG2 H PF6 PF4 PF5 PF3 VSS VSS VSS VSS VSS VDD PG3 PD14 PD13 J PH0OSC_IN PF8 PF7 PF9 VSS VSS VSS VSS VSS PD15 PD11 VSS PD12 K PH1OSC_ OUT VSS PF10 VDD VSS VSS VSS VSS VSS VSS PD9 PB15 PB14 L NRST PC0 PC1 VREF- VDD PD10 PD8 PB13 M PC2 PC3 VREF+ VDDA VDD VSS PC5 PB1 VDD VSS PH7 PE14 PH11 PH9 PB12 N PC2_C PC3_C VSSA PH2 PA3 PA7 PF11 PE8 PG1 PF15 PF13 PB10 PH8 PH10 PH12 PA1 PA1_C PH4 PA4 PA5 PB2 PG0 PE7 PB11 PF12 PE12 PE13 PE15 PH6 PA2 PA0_C PH3 PH5 PC4 PA6 PB0 PE10 PF14 PE9 PE11 VCAP VDD LDO VSS P R PA0 VSS PA13 MSv43752V4 1. The above figure shows the package top view. DS12923 Rev 1 57/252 104 Pin descriptions STM32H745xI/G PH14 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 VDD VSS PI7 PI6 PI5 PI4 VDDLDO PDR_ON VSS VCAP PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PG15 VDD VSS PG14 PG13 PG12 PG11 PG10 PG9 VDD VSS PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14 PI3 PI2 PI1 VDD VSS PI0 PH15 Figure 9. LQFP208 pinout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 208-pins 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 PH13 VDD VDDLDO VSS VCAP PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 VDD33USB VDD50USB VSS PG8 PG7 PG6 PG5 PG4 VDD VSS PG3 PG2 PK2 PK1 PK0 VSS VDD PJ11 PJ10 PJ9 PJ8 VSS VDD PJ7 PJ6 PD15 PD14 VDD VSS PD13 PD12 PD11 VSS VDD PD10 PD9 PD8 PH5 PA3 VSS VDD PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PI15 PF11 PF12 PF13 PF14 PF15 PG0 VSS VDD PG1 PE7 PE8 PE9 VSS VDD PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VCAP VSS VDDLDO PH6 PH7 PH8 PH9 PH10 PH11 PH12 VSS VDD PB12 PB13 PB14 PB15 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 PE2 PE3 PE4 PE5 PE6 VSS VDD VBAT PI8 PC13 PC14-OSC32_IN PC15-OSC32_OUT PI9 PI10 PI11 VSS VDD VSSSMPS VLXSMPS VDDSMPS VFBSMPS PF0 PF1 PF2 PF3 PF4 PF5 VSS VDD PF6 PF7 PF8 PF9 PF10 PH0-OSC_IN PH1-OSC_OUT NRST PC0 PC1 PC2_C PC3_C VSSA VREF+ VDDA PA0 PA1 PA2 PH2 VDD VSS PH3 PH4 MSv43753V3 1. The above figure shows the package top view. 58/252 DS12923 Rev 1 STM32H745xI/G Pin descriptions Figure 10. TFBGA240+25 ballout A B C 1 2 3 4 VSS PI6 PI5 VBAT VSS PC15PC14OSC32_ OSC32 OUT _IN 5 6 7 8 9 10 11 12 13 14 15 16 17 PI4 PB5 VDD LDO VCAP PK5 PG10 PG9 PD5 PD4 PC10 PA15 PI1 PI0 VSS PI7 PE1 PB6 VSS PB4 PK4 PG11 PJ15 PD6 PD3 PC11 PA14 PI2 PH15 PH14 PE2 PE0 PB7 PB3 PK6 PK3 PG12 VSS PD7 PC12 VSS PI3 PA13 VSS VDD LDO D PE5 PE4 PE3 PB9 PB8 PG15 PK7 PG14 PG13 PJ14 PJ12 PD2 PD0 PA10 PA9 PH13 VCAP E VLX SMPS PI9 PC13 PI8 PE6 VDD PDR _ON BOOT0 VDD PJ13 VDD PD1 PC8 PC9 PA8 PA12 PA11 F VDD SMPS VSS SMPS PI10 PI11 VDD PC7 PC6 PG8 PG7 VDD 33USB G PF2 VFB SMPS PF1 PF0 VDD VSS VSS VSS VSS VSS VDD PG5 PG6 VSS VDD 50USB H PI12 PI13 PI14 PF3 VDD VSS VSS VSS VSS VSS VDD PG4 PG3 PG2 PK2 J PH1OSC_ OUT PH0OSC _IN VSS PF5 PF4 VSS VSS VSS VSS VSS VDD PK0 PK1 VSS VSS K NRST PF6 PF7 PF8 VDD VSS VSS VSS VSS VSS VDD PJ11 VSS NC NC L VDDA PC0 PF10 PF9 VDD VSS VSS VSS VSS VSS VDD PJ10 VSS NC NC M VREF+ PC1 PC2 PC3 VDD VDD PJ9 VSS NC NC N VREF- PH2 PA2 PA1 PA0 PJ0 VDD VDD PE10 VDD VDD VDD PJ8 PJ7 PJ6 VSS NC P VSSA PH3 PH4 PH5 PI15 PJ1 PF13 PF14 PE9 PE11 PB10 PB11 PH10 PH11 PD15 PD14 VDD R PC2_C PC3_C PA6 VSS PA7 PB2 PF12 VSS PF15 PE12 PE15 PJ5 PH9 PH12 PD11 PD12 PD13 T PA0_C PA1_C PA5 PC4 PB1 PJ2 PF11 PG0 PE8 PE13 PH6 VSS PH8 PB12 PB15 PD10 PD9 U VSS PA3 PA4 PC5 PB0 PJ3 PJ4 PG1 PE7 PE14 VCAP VDD LDO PH7 PB13 PB14 PD8 VSS MSv43744V3 1. The above figure shows the package top view. DS12923 Rev 1 59/252 104 Pin descriptions STM32H745xI/G Table 7. Legend/abbreviations used in the pinout table Name Pin name Pin type Abbreviation Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name S Supply pin I Input only pin I/O Input / output pin ANA Analog-only Input FT 5 V tolerant I/O TT 3.3 V tolerant I/O B Dedicated BOOT0 pin RST I/O structure Notes Pin functions 60/252 Definition Bidirectional reset pin with embedded weak pull-up resistor Option for TT and FT I/Os _f I2C FM+ option _a analog option (supplied by VDDA) _u USB option (supplied by VDD33USB) _h High-speed low-voltage I/O Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset. Alternate functions Functions selected through GPIOx_AFR registers Additional functions Functions directly selected/enabled through peripheral registers DS12923 Rev 1 STM32H745xI/G Pin descriptions Table 8. STM32H745xI/G pin/ball definition 2 3 4 C3 B2 B1 D3 2 3 4 1 2 3 4 C3 D3 D2 D1 PE2 PE3 PE4 PE5 I/O structure Pin type TFBGA240+25 LQFP208 LQFP176 1 Pin name (function after reset) I/O FT_ h I/O FT_ h I/O I/O Notes 1 UFBGA176+25 LQFP144 Pin/ball name Alternate functions Additional functions - TRACECLK, SAI1_CK1, SPI4_SCK, SAI1_MCLK_A, SAI4_MCLK_A, QUADSPI_BK1_IO2, SAI4_CK1, ETH_MII_TXD3, FMC_A23, EVENTOUT - - TRACED0, TIM15_BKIN, SAI1_SD_B, SAI4_SD_B, FMC_A19, EVENTOUT - - TRACED1, SAI1_D2, DFSDM1_DATIN3, TIM15_CH1N, SPI4_NSS, SAI1_FS_A, SAI4_FS_A, SAI4_D2, FMC_A20, DCMI_D4, LCD_B0, EVENTOUT - - TRACED2, SAI1_CK2, DFSDM1_CKIN3, TIM15_CH1, SPI4_MISO, SAI1_SCK_A, SAI4_SCK_A, SAI4_CK2, FMC_A21, DCMI_D6, LCD_G0, EVENTOUT - - FT_ h FT_ h 5 E3 5 5 E5 PE6 I/O FT_ h - TRACED3, TIM1_BKIN2, SAI1_D1, TIM15_CH2, SPI4_MOSI, SAI1_SD_A, SAI4_SD_A, SAI4_D1, SAI2_MCLK_B, TIM1_BKIN2_COMP12, FMC_A22, DCMI_D7, LCD_G1, EVENTOUT 6 A1 6 6 A1 VSS S - - - - 7 D5 7 7 - VDD S - - - - 8 E2 8 8 B1 VBAT S - - - - - A15 - - B2 VSS S - - - - DS12923 Rev 1 61/252 104 Pin descriptions STM32H745xI/G Table 8. STM32H745xI/G pin/ball definition (continued) LQFP144 UFBGA176+25 LQFP176 LQFP208 TFBGA240+25 Pin name (function after reset) Pin type I/O structure Notes Pin/ball name Alternate functions - - - 9 E4 PI8 I/O FT - EVENTOUT RTC_TAMP2/WK UP3 9 C1 9 10 E3 PC13 I/O FT - EVENTOUT RTC_TAMP1/RTC _TS/WKUP2 - C2 - - - VSS S - - - - I/O FT - EVENTOUT OSC32_IN I/O FT - EVENTOUT OSC32_OUT I/O FT_ h - UART4_RX, FDCAN1_RX, FMC_D30, LCD_VSYNC, EVENTOUT - - FDCAN1_RXFD_MODE, ETH_MII_RX_ER, FMC_D31, LCD_HSYNC, EVENTOUT - 10 D2 10 11 C2 PC14OSC32_IN (OSC32_IN) Additional functions (1) 11 - D1 - 11 - 12 13 C1 E2 PC15OSC32_OUT (OSC32_ OUT)(1) PI9 - - - 14 F3 PI10 I/O FT_ h - - - 15 F4 PI11 I/O FT - LCD_G6, OTG_HS_ULPI_DIR, EVENTOUT WKUP4 12 D10 12 16 A17 VSS S - - - - 13 D11 13 17 E6 VDD S - - - - 14 F2 14 18 F2 VSSSMPS S - - - - 15 F1 15 19 E1 VLXSMPS S - - - - 16 G1 16 20 F1 VDDSMPS S - - - - 17 G2 17 21 G2 VFBSMPS S - - - - - F4 18 22 G4 PF0 I/O FT_f - I2C2_SDA, FMC_A0, EVENTOUT - - F3 19 23 G3 PF1 I/O FT_f - I2C2_SCL, FMC_A1, EVENTOUT - - G3 20 24 G1 PF2 I/O FT - I2C2_SMBA, FMC_A2, EVENTOUT - 62/252 DS12923 Rev 1 STM32H745xI/G Pin descriptions Table 8. STM32H745xI/G pin/ball definition (continued) LQFP144 UFBGA176+25 LQFP176 LQFP208 TFBGA240+25 Pin name (function after reset) Pin type I/O structure Notes Pin/ball name Alternate functions - - - - H1 PI12 I/O FT - LCD_HSYNC, EVENTOUT - - - - - H2 PI13 I/O FT - LCD_VSYNC, EVENTOUT - - - - - H3 PI14 I/O FT_ h - LCD_CLK, EVENTOUT - - H4 21 25 H4 PF3 I/O FT_ ha - FMC_A3, EVENTOUT ADC3_INP5 - H2 22 26 J5 PF4 I/O FT_ ha - FMC_A4, EVENTOUT ADC3_INN5, ADC3_INP9 - H3 23 27 J4 PF5 I/O FT_ ha - FMC_A5, EVENTOUT ADC3_INP4 18 E1 24 28 C10 VSS S - - - - 19 E4 25 29 E9 VDD S - - - - - TIM16_CH1, SPI5_NSS, SAI1_SD_B, UART7_RX, SAI4_SD_B, QUADSPI_BK1_IO3, EVENTOUT ADC3_INN4, ADC3_INP8 - TIM17_CH1, SPI5_SCK, SAI1_MCLK_B, UART7_TX, SAI4_MCLK_B, QUADSPI_BK1_IO2, EVENTOUT ADC3_INP3 - TIM16_CH1N, SPI5_MISO, SAI1_SCK_B, UART7_RTS/UART7_DE , SAI4_SCK_B, TIM13_CH1, QUADSPI_BK1_IO0, EVENTOUT ADC3_INN3, ADC3_INP7 - TIM17_CH1N, SPI5_MOSI, SAI1_FS_B, UART7_CTS, SAI4_FS_B, TIM14_CH1, QUADSPI_BK1_IO1, EVENTOUT ADC3_INP2 20 21 22 23 H1 J3 J2 J4 26 27 28 29 30 31 32 33 K2 K3 K4 L4 PF6 PF7 PF8 PF9 I/O I/O I/O I/O FT_ ha FT_ ha FT_ ha FT_ ha DS12923 Rev 1 Additional functions 63/252 104 Pin descriptions STM32H745xI/G Table 8. STM32H745xI/G pin/ball definition (continued) PF10 I/O 25 J1 31 35 J2 PH0OSC_IN (PH0) I/O FT - EVENTOUT OSC_IN 26 K1 32 36 J1 PH1OSC_OUT (PH1) I/O FT - EVENTOUT OSC_OUT 27 L1 33 37 K1 NRST I/O RST - - - - DFSDM1_CKIN0, DFSDM1_DATIN4, SAI2_FS_B, OTG_HS_ULPI_STP, FMC_SDNWE, LCD_R5, EVENTOUT ADC123_INP10 - TRACED0, SAI1_D1, DFSDM1_DATIN0, DFSDM1_CKIN4, SPI2_MOSI/I2S2_SDO, SAI1_SD_A, SAI4_SD_A, SDMMC2_CK, SAI4_D1, ETH_MDC, MDIOS_MDC, EVENTOUT ADC123_INN10, ADC123_INP11, RTC_TAMP3/WK UP5 28 L2 34 38 L2 Pin name (function after reset) PC0 I/O Notes I/O structure L3 TFBGA240+25 34 LQFP208 30 LQFP176 K3 UFBGA176+25 24 FT_ ha LQFP144 Pin type Pin/ball name Alternate functions - TIM16_BKIN, SAI1_D3, QUADSPI_CLK, SAI4_D3, DCMI_D11, LCD_DE, EVENTOUT FT_ a 29 L3 35 39 M2 PC1 I/O FT_ ha - M1 - - M3(2) PC2 I/O FT_ a - 40(3) R1(2) PC2_C ANA TT_ a - - M4(2) PC3 I/O FT_ a - 41(3) R2(2) PC3_C ANA TT_ a - 30(3) N1(3) 36(3) - M2 - 31(3) N2(3) 37(3) 64/252 DS12923 Rev 1 Additional functions ADC3_INN2, ADC3_INP6 C1DSLEEP, DFSDM1_CKIN1, SPI2_MISO/I2S2_SDI, DFSDM1_CKOUT, OTG_HS_ULPI_DIR, ETH_MII_TXD2, FMC_SDNE0, EVENTOUT ADC123_INN11, ADC123_INP12 C1SLEEP, DFSDM1_DATIN1, SPI2_MOSI/I2S2_SDO, OTG_HS_ULPI_NXT, ETH_MII_TX_CLK, FMC_SDCKE0, EVENTOUT ADC12_INN12, ADC12_INP13 ADC3_INN1, ADC3_INP0 ADC3_INP1 STM32H745xI/G Pin descriptions Table 8. STM32H745xI/G pin/ball definition (continued) LQFP144 UFBGA176+25 LQFP176 LQFP208 TFBGA240+25 Pin name (function after reset) Pin type I/O structure Notes Pin/ball name Alternate functions 32 E12 - - E11 VDD S - - - - 33 F6 - - C13 VSS S - - - - 34 N3 38 42 P1 VSSA S - - - - - L4 - - N1 VREF- S - - - - 35 M3 39 43 M1 VREF+ S - - - - 36 M4 40 44 L1 VDDA S - - - - 37 P1 41 45 N5(2) PA0 I/O FT_ a - ADC1_INP16, WKUP0 - R3 - - T1(2) PA0_C ANA TT_ a - TIM2_CH1/TIM2_ETR, TIM5_CH1, TIM8_ETR, TIM15_BKIN, USART2_CTS/USART2_ NSS, UART4_TX, SDMMC2_CMD, SAI2_SD_B, ETH_MII_CRS, EVENTOUT 38 P2 42 46 N4(2) PA1 I/O FT_ ha - - P3 - - T2(2) PA1_C ANA TT_ a - 39 R2 43 47 N3 PA2 I/O FT_ a TIM2_CH2, TIM5_CH2, LPTIM3_OUT, TIM15_CH1N, USART2_RTS/USART2_ DE, UART4_RX, QUADSPI_BK1_IO3, SAI2_MCLK_B, ETH_MII_RX_CLK/ETH_ RMII_REF_CLK, LCD_R2, EVENTOUT ADC12_INN1, ADC12_INP0 ADC1_INN16, ADC1_INP17 ADC12_INP1 - TIM2_CH3, TIM5_CH3, LPTIM4_OUT, TIM15_CH1, USART2_TX, SAI2_SCK_B, ETH_MDIO, MDIOS_MDIO, LCD_R1, EVENTOUT ADC12_INP14, WKUP1 ADC3_INP13 - - N4 - 48 N2 PH2 I/O FT_ ha - LPTIM1_IN2, QUADSPI_BK2_IO0, SAI2_SCK_B, ETH_MII_CRS, FMC_SDCKE0, LCD_R0, EVENTOUT - G4 44 49 F5 VDD S - - - DS12923 Rev 1 Additional functions 65/252 104 Pin descriptions STM32H745xI/G Table 8. STM32H745xI/G pin/ball definition (continued) LQFP208 TFBGA240+25 F7 45 50 C16 VSS S Notes LQFP176 - I/O structure UFBGA176+25 Pin name (function after reset) Pin type LQFP144 Pin/ball name Alternate functions Additional functions - - - - ADC3_INN13, ADC3_INP14 - R4 - 51 P2 PH3 I/O FT_ ha - QUADSPI_BK2_IO1, SAI2_MCLK_B, ETH_MII_COL, FMC_SDNE0, LCD_R1, EVENTOUT - P4 - 52 P3 PH4 I/O FT_f a - I2C2_SCL, LCD_G5, OTG_HS_ULPI_NXT, LCD_G4, EVENTOUT ADC3_INN14, ADC3_INP15 - R5 - 53 P4 PH5 I/O FT_f a - I2C2_SDA, SPI5_NSS, FMC_SDNWE, EVENTOUT ADC3_INN15, ADC3_INP16 ADC12_INP15 40 N5 46 54 U2 PA3 I/O FT_ ha - TIM2_CH4, TIM5_CH4, LPTIM5_OUT, TIM15_CH2, USART2_RX, LCD_B2, OTG_HS_ULPI_D0, ETH_MII_COL, LCD_B5, EVENTOUT 41 F8 47 55 - VSS S - - - - 42 H12 48 56 G5 VDD S - - - - - D1PWREN, TIM5_ETR, SPI1_NSS/I2S1_WS, SPI3_NSS/I2S3_WS, USART2_CK, SPI6_NSS, OTG_HS_SOF, DCMI_HSYNC, LCD_VSYNC, EVENTOUT ADC12_INP18, DAC1_OUT1 - D2PWREN, TIM2_CH1/TIM2_ETR, TIM8_CH1N, SPI1_SCK/I2S1_CK, SPI6_SCK, OTG_HS_ULPI_CK, LCD_R4, EVENTOUT ADC12_INN18, ADC12_INP19, DAC1_OUT2 43 44 66/252 P5 P6 49 50 57 58 U3 T3 PA4 PA5 I/O I/O TT_ a TT_ ha DS12923 Rev 1 STM32H745xI/G Pin descriptions Table 8. STM32H745xI/G pin/ball definition (continued) 46 47 R7 N6 R6 52 53 59 60 61 R3 R5 T4 PA6 PA7 PC4 I/O I/O I/O I/O structure Pin type TFBGA240+25 LQFP208 LQFP176 51 Pin name (function after reset) Notes 45 UFBGA176+25 LQFP144 Pin/ball name Alternate functions Additional functions - TIM1_BKIN, TIM3_CH1, TIM8_BKIN, SPI1_MISO/I2S1_SDI, SPI6_MISO, TIM13_CH1, TIM8_BKIN_COMP12, MDIOS_MDC, TIM1_BKIN_COMP12, DCMI_PIXCLK, LCD_G2, EVENTOUT ADC12_INP3 - TIM1_CH1N, TIM3_CH2, TIM8_CH1N, SPI1_MOSI/I2S1_SDO, SPI6_MOSI, TIM14_CH1, ETH_MII_RX_DV/ETH_R MII_CRS_DV, FMC_SDNWE, EVENTOUT ADC12_INN3, ADC12_INP7, OPAMP1_VINM - C2DSLEEP, DFSDM1_CKIN2, I2S1_MCK, SPDIFRX1_IN3, ETH_MII_RXD0/ETH_R MII_RXD0, FMC_SDNE0, EVENTOUT ADC12_INP4, OPAMP1_VOUT, COMP1_INM ADC12_INN4, ADC12_INP8, OPAMP1_VINM FT_ a TT_ a TT_ a 48 M7 54 62 U4 PC5 I/O TT_ a - C2SLEEP, SAI1_D3, DFSDM1_DATIN2, SPDIFRX1_IN4, SAI4_D3, ETH_MII_RXD1/ETH_R MII_RXD1, FMC_SDCKE0, COMP1_OUT, EVENTOUT - K4 - - G13 VDD S - - - - - F9 - - R4 VSS S - - - - DS12923 Rev 1 67/252 104 Pin descriptions STM32H745xI/G Table 8. STM32H745xI/G pin/ball definition (continued) 50 R8 M8 56 63 64 U5 T5 PB0 PB1 I/O I/O I/O structure Pin type TFBGA240+25 LQFP208 LQFP176 55 Pin name (function after reset) Notes 49 UFBGA176+25 LQFP144 Pin/ball name Alternate functions Additional functions - TIM1_CH2N, TIM3_CH3, TIM8_CH2N, DFSDM1_CKOUT, UART4_CTS, LCD_R3, OTG_HS_ULPI_D1, ETH_MII_RXD2, LCD_G1, EVENTOUT ADC12_INN5, ADC12_INP9, OPAMP1_VINP, COMP1_INP - TIM1_CH3N, TIM3_CH4, TIM8_CH3N, DFSDM1_DATIN1, LCD_R6, OTG_HS_ULPI_D2, ETH_MII_RXD3, LCD_G0, EVENTOUT ADC12_INP5, COMP1_INM COMP1_INP FT_ a TT_ u 51 P7 57 65 R6 PB2 I/O FT_ ha - RTC_OUT, SAI1_D1, DFSDM1_CKIN1, SAI1_SD_A, SPI3_MOSI/I2S3_SDO, SAI4_SD_A, QUADSPI_CLK, SAI4_D1, EVENTOUT - - - 66 P5 PI15 I/O FT - LCD_G2, LCD_R0, EVENTOUT - - - - - N6 PJ0 I/O FT - LCD_R7, LCD_R1, EVENTOUT - - - - - P6 PJ1 I/O FT - LCD_R2, EVENTOUT - - - - - T6 PJ2 I/O FT - LCD_R3, EVENTOUT - - - - - U6 PJ3 I/O FT - LCD_R4, EVENTOUT - - - - - U7 PJ4 I/O FT - LCD_R5, EVENTOUT - 52 N7 58 67 T7 PF11 I/O FT_ a - SPI5_MOSI, SAI2_SD_B, FMC_SDNRAS, DCMI_D12, EVENTOUT ADC1_INP2 - P11 59 68 R7 PF12 I/O FT_ ha - FMC_A6, EVENTOUT ADC1_INN2, ADC1_INP6 - F10 - - J3 VSS S - - - - - L12 - - H5 VDD S - - - - - N11 60 69 P7 PF13 I/O FT_ ha - DFSDM1_DATIN6, I2C4_SMBA, FMC_A7, EVENTOUT ADC2_INP2 68/252 DS12923 Rev 1 STM32H745xI/G Pin descriptions Table 8. STM32H745xI/G pin/ball definition (continued) LQFP144 UFBGA176+25 LQFP176 LQFP208 TFBGA240+25 Pin name (function after reset) Pin type I/O structure Notes Pin/ball name Alternate functions 53 R10 61 70 P8 PF14 I/O FT_f ha - DFSDM1_CKIN6, I2C4_SCL, FMC_A8, EVENTOUT ADC2_INN2, ADC2_INP6 54 N10 62 71 R9 PF15 I/O FT_f h - I2C4_SDA, FMC_A9, EVENTOUT - - P8 63 72 T8 PG0 I/O FT_ h - FMC_A10, EVENTOUT - 55 F12 64 73 J16 VSS S - - - - 56 M5 65 74 H13 VDD S - - - - - N9 66 75 U8 PG1 I/O TT_ h - FMC_A11, EVENTOUT OPAMP2_VINM - TIM1_ETR, DFSDM1_DATIN2, UART7_RX, QUADSPI_BK2_IO0, FMC_D4/FMC_DA4, EVENTOUT OPAMP2_VOUT, COMP2_INM - TIM1_CH1N, DFSDM1_CKIN2, UART7_TX, QUADSPI_BK2_IO1, FMC_D5/FMC_DA5, COMP2_OUT, EVENTOUT OPAMP2_VINM OPAMP2_VINP, COMP2_INP 57 58 P9 N8 67 68 76 77 U9 T9 PE7 PE8 I/O I/O TT_ ha TT_ ha Additional functions 59 R11 69 78 P9 PE9 I/O TT_ ha - TIM1_CH1, DFSDM1_CKOUT, UART7_RTS/UART7_DE , QUADSPI_BK2_IO2, FMC_D6/FMC_DA6, EVENTOUT - G6 70 79 J17 VSS S - - - - - M9 71 80 J13 VDD S - - - - - TIM1_CH2N, DFSDM1_DATIN4, UART7_CTS, QUADSPI_BK2_IO3, FMC_D7/FMC_DA7, EVENTOUT COMP2_INM 60 R9 72 81 N9 PE10 I/O FT_ ha DS12923 Rev 1 69/252 104 Pin descriptions STM32H745xI/G Table 8. STM32H745xI/G pin/ball definition (continued) 62 R12 P12 74 82 83 P10 R10 PE11 PE12 I/O I/O I/O structure Pin type TFBGA240+25 LQFP208 LQFP176 73 Pin name (function after reset) Notes 61 UFBGA176+25 LQFP144 Pin/ball name Alternate functions Additional functions - TIM1_CH2, DFSDM1_CKIN4, SPI4_NSS, SAI2_SD_B, FMC_D8/FMC_DA8, LCD_G3, EVENTOUT COMP2_INP - TIM1_CH3N, DFSDM1_DATIN5, SPI4_SCK, SAI2_SCK_B, FMC_D9/FMC_DA9, COMP1_OUT, LCD_B4, EVENTOUT - - FT_ ha FT_ h 63 P13 75 84 T10 PE13 I/O FT_ h - TIM1_CH3, DFSDM1_CKIN5, SPI4_MISO, SAI2_FS_B, FMC_D10/FMC_DA10, COMP2_OUT, LCD_DE, EVENTOUT - G7 - - T12 VSS S - - - - - - - - K13 VDD S - - - - I/O FT_ h - TIM1_CH4, SPI4_MOSI, SAI2_MCLK_B, FMC_D11/FMC_DA11, LCD_CLK, EVENTOUT - - TIM1_BKIN, FMC_D12/FMC_DA12, TIM1_BKIN_COMP12/C OMP_TIM1_BKIN, LCD_R7, EVENTOUT - - TIM2_CH3, HRTIM_SCOUT, LPTIM2_IN1, I2C2_SCL, SPI2_SCK/I2S2_CK, DFSDM1_DATIN7, USART3_TX, QUADSPI_BK1_NCS, OTG_HS_ULPI_D3, ETH_MII_RX_ER, LCD_G4, EVENTOUT - 64 65 66 70/252 M12 P14 N12 76 77 78 85 86 87 U10 R11 P11 PE14 PE15 PB10 I/O I/O FT_ h FT_f DS12923 Rev 1 STM32H745xI/G Pin descriptions Table 8. STM32H745xI/G pin/ball definition (continued) P10 79 88 P12 PB11 I/O FT_f - 68 R13 80 89 U11 VCAP S - - - - 69 M10 81 90 - VSS S - - - - 70 R14 82 91 U12 VDDLDO S - - - - 71 - - - L13 VDD S - - - - - - - - R12 PJ5 I/O FT - LCD_R6, EVENTOUT - - TIM12_CH1, I2C2_SMBA, SPI5_SCK, ETH_MII_RXD2, FMC_SDNE1, DCMI_D8, EVENTOUT - - I2C3_SCL, SPI5_MISO, ETH_MII_RXD3, FMC_SDCKE1, DCMI_D9, EVENTOUT - - - - P15 M11 - - LQFP208 67 TIM2_CH4, HRTIM_SCIN, LPTIM2_ETR, I2C2_SDA, DFSDM1_CKIN7, USART3_RX, OTG_HS_ULPI_D4, ETH_MII_TX_EN/ETH_R MII_TX_EN, LCD_G5, EVENTOUT LQFP176 Alternate functions LQFP144 Notes I/O structure Pin name (function after reset) Pin type TFBGA240+25 UFBGA176+25 Pin/ball name 92 93 T11 U13 PH6 PH7 I/O FT I/O FT_f a - TIM5_ETR, I2C3_SDA, FMC_D16, DCMI_HSYNC, LCD_R2, EVENTOUT Additional functions - - N13 - 94 T13 PH8 I/O FT_f ha - G9 - - - VSS S - - - - - - - - M13 VDD S - - - - - TIM12_CH2, I2C3_SMBA, FMC_D17, DCMI_D0, LCD_R3, EVENTOUT - - TIM5_CH1, I2C4_SMBA, FMC_D18, DCMI_D1, LCD_R4, EVENTOUT - - M14 - 95 R13 PH9 I/O FT_ h - N14 - 96 P13 PH10 I/O FT_ h DS12923 Rev 1 71/252 104 Pin descriptions STM32H745xI/G Table 8. STM32H745xI/G pin/ball definition (continued) LQFP144 UFBGA176+25 LQFP176 LQFP208 TFBGA240+25 Pin name (function after reset) Pin type I/O structure Notes Pin/ball name Alternate functions - M13 - 97 P14 PH11 I/O FT_f h - TIM5_CH2, I2C4_SCL, FMC_D19, DCMI_D2, LCD_R5, EVENTOUT - - N15 - 98 R14 PH12 I/O FT_f h - TIM5_CH3, I2C4_SDA, FMC_D20, DCMI_D3, LCD_R6, EVENTOUT - - G10 83 99 N16 VSS S - - - - - - 84 100 - VDD S - - - - - TIM1_BKIN, I2C2_SMBA, SPI2_NSS/I2S2_WS, DFSDM1_DATIN1, USART3_CK, FDCAN2_RX, OTG_HS_ULPI_D5, ETH_MII_TXD0/ETH_R MII_TXD0, OTG_HS_ID, TIM1_BKIN_COMP12, UART5_RX, EVENTOUT - - TIM1_CH1N, LPTIM2_OUT, SPI2_SCK/I2S2_CK, DFSDM1_CKIN1, USART3_CTS/USART3_ NSS, FDCAN2_TX, OTG_HS_ULPI_D6, ETH_MII_TXD1/ETH_R MII_TXD1, UART5_TX, EVENTOUT OTG_HS_VBUS - TIM1_CH2N, TIM12_CH1, TIM8_CH2N, USART1_TX, SPI2_MISO/I2S2_SDI, DFSDM1_DATIN2, USART3_RTS/USART3_ DE, UART4_RTS/UART4_DE , SDMMC2_D0, OTG_HS_DM, EVENTOUT - 72 73 74 72/252 M15 L15 K15 85 86 87 101 102 103 T14 U14 U15 PB12 PB13 PB14 I/O I/O I/O FT_ u FT_ u FT_ u DS12923 Rev 1 Additional functions STM32H745xI/G Pin descriptions Table 8. STM32H745xI/G pin/ball definition (continued) 76 77 K14 L14 K13 89 90 104 105 106 T15 U16 T17 PB15 PD8 PD9 I/O I/O I/O I/O structure Pin type TFBGA240+25 LQFP208 LQFP176 88 Pin name (function after reset) Notes 75 UFBGA176+25 LQFP144 Pin/ball name Alternate functions Additional functions - RTC_REFIN, TIM1_CH3N, TIM12_CH2, TIM8_CH3N, USART1_RX, SPI2_MOSI/I2S2_SDO, DFSDM1_CKIN2, UART4_CTS, SDMMC2_D1, OTG_HS_DP, EVENTOUT - - DFSDM1_CKIN3, SAI3_SCK_B, USART3_TX, SPDIFRX1_IN2, FMC_D13/FMC_DA13, EVENTOUT - - DFSDM1_DATIN3, SAI3_SD_B, USART3_RX, FDCAN2_RXFD_MODE, FMC_D14/FMC_DA14, EVENTOUT - - FT_ u FT_ h FT_ h 78 L13 91 107 T16 PD10 I/O FT_ h - DFSDM1_CKOUT, SAI3_FS_B, USART3_CK, FDCAN2_TXFD_MODE, FMC_D15/FMC_DA15, LCD_B3, EVENTOUT 79 - 92 108 N12 VDD S - - - - 80 H6 93 109 U17 VSS S - - - - - LPTIM2_IN2, I2C4_SMBA, USART3_CTS/USART3_ NSS, QUADSPI_BK1_IO0, SAI2_SD_A, FMC_A16, EVENTOUT - 81 J13 94 110 R15 PD11 I/O FT_ h DS12923 Rev 1 73/252 104 Pin descriptions STM32H745xI/G Table 8. STM32H745xI/G pin/ball definition (continued) J15 111 R16 PD12 I/O I/O structure Pin type TFBGA240+25 LQFP208 LQFP176 95 Pin name (function after reset) Notes 82 UFBGA176+25 LQFP144 Pin/ball name Alternate functions Additional functions - LPTIM1_IN1, TIM4_CH1, LPTIM2_IN1, I2C4_SCL, USART3_RTS/USART3_ DE, QUADSPI_BK1_IO1, SAI2_FS_A, FMC_A17, EVENTOUT - - FT_f h 83 H15 96 112 R17 PD13 I/O FT_f h - LPTIM1_OUT, TIM4_CH2, I2C4_SDA, QUADSPI_BK1_IO3, SAI2_SCK_A, FMC_A18, EVENTOUT - R1 - 113 - VSS S - - - - - - - 114 N11 VDD S - - - - - TIM4_CH3, SAI3_MCLK_B, UART8_CTS, FMC_D0/FMC_DA0, EVENTOUT - - 84 H14 97 115 P16 PD14 I/O FT_ h 85 J12 98 116 P15 PD15 I/O FT_ h - TIM4_CH4, SAI3_MCLK_A, UART8_RTS/UART8_DE , FMC_D1/FMC_DA1, EVENTOUT - - - 117 N15 PJ6 I/O FT - TIM8_CH2, LCD_R7, EVENTOUT - - - - 118 N14 PJ7 I/O FT - TRGIN, TIM8_CH2N, LCD_G0, EVENTOUT - - - 99 119 N10 VDD S - - - - - D6 100 120 R8 VSS S - - - - - - 101 121 N13 PJ8 I/O FT - TIM1_CH3N, TIM8_CH1, UART8_TX, LCD_G1, EVENTOUT - - - 102 122 M14 PJ9 I/O FT - TIM1_CH3, TIM8_CH1N, UART8_RX, LCD_G2, EVENTOUT - - - 103 123 L14 PJ10 I/O FT - TIM1_CH2N, TIM8_CH2, SPI5_MOSI, LCD_G3, EVENTOUT - 74/252 DS12923 Rev 1 STM32H745xI/G Pin descriptions Table 8. STM32H745xI/G pin/ball definition (continued) LQFP144 UFBGA176+25 LQFP176 LQFP208 TFBGA240+25 Pin name (function after reset) Pin type I/O structure Notes Pin/ball name Alternate functions - - 104 124 K14 PJ11 I/O FT - TIM1_CH2, TIM8_CH2N, SPI5_MISO, LCD_G4, EVENTOUT - - - 105 125 N8 VDD S - - - - - - - - P17 VDD S - - - - - R15 106 126 U1 VSS S - - - - - - - - N17 NC - - - - - - - - - M16 NC - - - - - - - - - M17 NC - - - - - - - - - K15 VSS S - - - - - - - - L16 NC - - - - - - - - - L17 NC - - - - - - - - - K16 NC - - - - - - - - - K17 NC - - - - - - - - - L15 VSS S - - - - - - 107 127 J14 PK0 I/O FT - TIM1_CH1N, TIM8_CH3, SPI5_SCK, LCD_G5, EVENTOUT - - - 108 128 J15 PK1 I/O FT - TIM1_CH1, TIM8_CH3N, SPI5_NSS, LCD_G6, EVENTOUT - - Additional functions - - 109 129 H17 PK2 I/O FT - TIM1_BKIN, TIM8_BKIN, TIM8_BKIN_COMP12, TIM1_BKIN_COMP12, LCD_G7, EVENTOUT - G15 110 130 H16 PG2 I/O FT_ h - TIM8_BKIN, TIM8_BKIN_COMP12, FMC_A12, EVENTOUT - - H13 111 131 H15 PG3 I/O FT_ h - TIM8_BKIN2, TIM8_BKIN2_COMP12, FMC_A13, EVENTOUT - - H10 112 132 - VSS S - - - - - - 113 133 N7 VDD S - - - - DS12923 Rev 1 75/252 104 Pin descriptions STM32H745xI/G Table 8. STM32H745xI/G pin/ball definition (continued) PG4 I/O - F15 115 135 G14 PG5 I/O FT_ h 86 87 F14 G13 116 117 136 137 G15 F16 Pin name (function after reset) PG6 PG7 I/O I/O Notes I/O structure H14 TFBGA240+25 134 LQFP208 114 LQFP176 G14 UFBGA176+25 - FT_ h LQFP144 Pin type Pin/ball name Alternate functions - TIM1_BKIN2, TIM1_BKIN2_COMP12, FMC_A14/FMC_BA0, EVENTOUT - TIM1_ETR, FMC_A15/FMC_BA1, EVENTOUT - - TIM17_BKIN, HRTIM_CHE1, QUADSPI_BK1_NCS, FMC_NE3, DCMI_D12, LCD_R7, EVENTOUT - - HRTIM_CHE2, SAI1_MCLK_A, USART6_CK, FMC_INT, DCMI_D13, LCD_CLK, EVENTOUT - - FT_ h FT_ h Additional functions - 88 G12 118 138 F15 PG8 I/O FT_ h - TIM8_ETR, SPI6_NSS, USART6_RTS/USART6_ DE, SPDIFRX1_IN3, ETH_PPS_OUT, FMC_SDCLK, LCD_G7, EVENTOUT 89 J6 119 139 G16 VSS S - - - - 90 E15 120 140 G17 VDD50USB S - - - - 91 F13 121 141 F17 VDD33USB S - - - - 92 - - - M5 VDD S - - - - - HRTIM_CHA1, TIM3_CH1, TIM8_CH1, DFSDM1_CKIN3, I2S2_MCK, USART6_TX, SDMMC1_D0DIR, FMC_NWAIT, SDMMC2_D6, SDMMC1_D6, DCMI_D0, LCD_HSYNC, EVENTOUT SWPMI_IO 93 76/252 E14 122 142 F14 PC6 I/O FT_ h DS12923 Rev 1 STM32H745xI/G Pin descriptions Table 8. STM32H745xI/G pin/ball definition (continued) 95 D15 D14 124 143 144 F13 E13 PC7 PC8 I/O I/O I/O structure Pin type TFBGA240+25 LQFP208 LQFP176 123 Pin name (function after reset) Notes 94 UFBGA176+25 LQFP144 Pin/ball name Alternate functions Additional functions - TRGIO, HRTIM_CHA2, TIM3_CH2, TIM8_CH2, DFSDM1_DATIN3, I2S3_MCK, USART6_RX, SDMMC1_D123DIR, FMC_NE1, SDMMC2_D7, SWPMI_TX, SDMMC1_D7, DCMI_D1, LCD_G6, EVENTOUT - - TRACED1, HRTIM_CHB1, TIM3_CH3, TIM8_CH3, USART6_CK, UART5_RTS/UART5_DE , FMC_NE2/FMC_NCE, SWPMI_RX, SDMMC1_D0, DCMI_D2, EVENTOUT - - FT_ h FT_ h 96 E13 125 145 E14 PC9 I/O FT_f h - MCO2, TIM3_CH4, TIM8_CH4, I2C3_SDA, I2S_CKIN, UART5_CTS, QUADSPI_BK1_IO0, LCD_G3, SWPMI_SUSPEND, SDMMC1_D1, DCMI_D3, LCD_B2, EVENTOUT - J7 - - - VSS S - - - - - - 126 - L5 VDD S - - - - - MCO1, TIM1_CH1, HRTIM_CHB2, TIM8_BKIN2, I2C3_SCL, USART1_CK, OTG_FS_SOF, UART7_RX, TIM8_BKIN2_COMP12, LCD_B3, LCD_R6, EVENTOUT - 97 B14 127 146 E15 PA8 I/O FT_f ha DS12923 Rev 1 77/252 104 Pin descriptions STM32H745xI/G Table 8. STM32H745xI/G pin/ball definition (continued) 99 100 D13 C14 C15 129 130 147 148 149 D15 D14 E17 PA9 PA10 PA11 I/O I/O I/O I/O structure Pin type TFBGA240+25 LQFP208 LQFP176 128 Pin name (function after reset) Notes 98 UFBGA176+25 LQFP144 Pin/ball name Alternate functions Additional functions - TIM1_CH2, HRTIM_CHC1, LPUART1_TX, I2C3_SMBA, SPI2_SCK/I2S2_CK, USART1_TX, FDCAN1_RXFD_MODE, DCMI_D0, LCD_R5, EVENTOUT OTG_FS_VBUS - TIM1_CH3, HRTIM_CHC2, LPUART1_RX, USART1_RX, FDCAN1_TXFD_MODE, OTG_FS_ID, MDIOS_MDIO, LCD_B4, DCMI_D1, LCD_B1, EVENTOUT - - TIM1_CH4, HRTIM_CHD1, LPUART1_CTS, SPI2_NSS/I2S2_WS, UART4_RX, USART1_CTS/USART1_ NSS, FDCAN1_RX, OTG_FS_DM, LCD_R4, EVENTOUT - - FT_ u FT_ u FT_ u 101 B15 131 150 E16 PA12 I/O FT_ u - TIM1_ETR, HRTIM_CHD2, LPUART1_RTS/LPUART 1_DE, SPI2_SCK/I2S2_CK, UART4_TX, USART1_RTS/USART1_ DE, SAI2_FS_B, FDCAN1_TX, OTG_FS_DP, LCD_R5, EVENTOUT 102 B13 132 151 C15 PA13(JTMS/ SWDIO) I/O FT - JTMS-SWDIO, EVENTOUT - 103 A14 133 152 D17 VCAP S - - - - 104 M6 134 153 - VSS S - - - - 78/252 DS12923 Rev 1 STM32H745xI/G Pin descriptions Table 8. STM32H745xI/G pin/ball definition (continued) LQFP144 UFBGA176+25 LQFP176 LQFP208 TFBGA240+25 Pin name (function after reset) Pin type I/O structure Notes Pin/ball name Alternate functions 105 A13 135 154 C17 VDDLDO - - - - - 106 - 136 155 K5 VDD S - - - - I/O FT_ h - TIM8_CH1N, UART4_TX, FDCAN1_TX, FMC_D21, LCD_G2, EVENTOUT - - TIM8_CH2N, UART4_RX, FDCAN1_RX, FMC_D22, DCMI_D4, LCD_G3, EVENTOUT - - TIM8_CH3N, FDCAN1_TXFD_MODE, FMC_D23, DCMI_D11, LCD_G4, EVENTOUT - - - - - C13 B12 D12 - - - 156 157 158 D16 B17 B16 PH13 PH14 PH15 I/O FT_ h I/O FT_ h Additional functions - - - 159 A16 PI0 I/O FT_ h - TIM5_CH4, SPI2_NSS/I2S2_WS, FDCAN1_RXFD_MODE, FMC_D24, DCMI_D13, LCD_G5, EVENTOUT - J9 - 160 - VSS S - - - - - - - 161 VDD VDD S - - - - - TIM8_BKIN2, SPI2_SCK/I2S2_CK, TIM8_BKIN2_COMP12, FMC_D25, DCMI_D8, LCD_G6, EVENTOUT - - TIM8_CH4, SPI2_MISO/I2S2_SDI, FMC_D26, DCMI_D9, LCD_G7, EVENTOUT - - - - - - - - 162 163 A15 B15 PI1 PI2 I/O FT_ h I/O FT_ h - TIM8_ETR, SPI2_MOSI/I2S2_SDO, FMC_D27, DCMI_D10, EVENTOUT - - - 164 C14 PI3 I/O FT_ h - J10 137 - - VSS S - - - - - - - - VDD VDD S - - - - 107 A12 138 165 B14 PA14(JTCK/ SWCLK) I/O FT - JTCK-SWCLK, EVENTOUT - DS12923 Rev 1 79/252 104 Pin descriptions STM32H745xI/G Table 8. STM32H745xI/G pin/ball definition (continued) 109 110 A11 C12 C11 140 141 166 167 168 A14 A13 B13 PA15(JTDI) PC10 PC11 I/O I/O I/O I/O structure Pin type TFBGA240+25 LQFP208 LQFP176 139 Pin name (function after reset) Notes 108 UFBGA176+25 LQFP144 Pin/ball name Alternate functions Additional functions - JTDI, TIM2_CH1/TIM2_ETR, HRTIM_FLT1, CEC, SPI1_NSS/I2S1_WS, SPI3_NSS/I2S3_WS, SPI6_NSS, UART4_RTS/UART4_DE , UART7_TX, EVENTOUT - - HRTIM_EEV1, DFSDM1_CKIN5, SPI3_SCK/I2S3_CK, USART3_TX, UART4_TX, QUADSPI_BK1_IO1, SDMMC1_D2, DCMI_D8, LCD_R2, EVENTOUT - - HRTIM_FLT2, DFSDM1_DATIN5, SPI3_MISO/I2S3_SDI, USART3_RX, UART4_RX, QUADSPI_BK2_NCS, SDMMC1_D3, DCMI_D4, EVENTOUT - - FT FT_ ha FT_ h 111 B11 142 169 C12 PC12 I/O FT_ h - TRACED3, HRTIM_EEV2, SPI3_MOSI/I2S3_SDO, USART3_CK, UART5_TX, SDMMC1_CK, DCMI_D9, EVENTOUT - J14 - - - VSS S - - - - - - - - VDD VDD S - - - - - DFSDM1_CKIN6, SAI3_SCK_A, UART4_RX, FDCAN1_RX, FMC_D2/FMC_DA2, EVENTOUT - 112 80/252 C10 143 170 D13 PD0 I/O FT_ h DS12923 Rev 1 STM32H745xI/G Pin descriptions Table 8. STM32H745xI/G pin/ball definition (continued) 114 115 116 A10 B10 A9 C9 145 146 147 171 172 173 174 E12 D12 B12 A12 PD1 PD2 PD3 PD4 I/O structure Pin type TFBGA240+25 LQFP208 LQFP176 144 Pin name (function after reset) I/O FT_ h I/O FT_ h I/O Notes 113 UFBGA176+25 LQFP144 Pin/ball name Alternate functions Additional functions - DFSDM1_DATIN6, SAI3_SD_A, UART4_TX, FDCAN1_TX, FMC_D3/FMC_DA3, EVENTOUT - - TRACED2, TIM3_ETR, UART5_RX, SDMMC1_CMD, DCMI_D11, EVENTOUT - - DFSDM1_CKOUT, SPI2_SCK/I2S2_CK, USART2_CTS/USART2_ NSS, FMC_CLK, DCMI_D5, LCD_G7, EVENTOUT - - HRTIM_FLT3, SAI3_FS_A, USART2_RTS/USART2_ DE, FDCAN1_RXFD_MODE, FMC_NOE, EVENTOUT - - FT_ h I/O FT_ h - HRTIM_EEV3, USART2_TX, FDCAN1_TXFD_MODE, FMC_NWE, EVENTOUT 117 B9 148 175 A11 PD5 I/O FT_ h 118 K2 - - - VSS S - - - - 119 - - - VDD VDD S - - - - - SAI1_D1, DFSDM1_CKIN4, DFSDM1_DATIN1, SPI3_MOSI/I2S3_SDO, SAI1_SD_A, USART2_RX, SAI4_SD_A, FDCAN2_RXFD_MODE, SAI4_D1, SDMMC2_CK, FMC_NWAIT, DCMI_D10, LCD_B2, EVENTOUT - 120 D9 149 176 B11 PD6 I/O FT_ h DS12923 Rev 1 81/252 104 Pin descriptions STM32H745xI/G Table 8. STM32H745xI/G pin/ball definition (continued) B8 150 177 C11 PD7 I/O FT_ h - - - - - D11 PJ12 I/O FT - TRGOUT, LCD_G3, LCD_B0, EVENTOUT - - - - - E10 PJ13 I/O FT - LCD_B4, LCD_B1, EVENTOUT - - - - - D10 PJ14 I/O FT - LCD_B2, EVENTOUT - - - - - B10 PJ15 I/O FT - LCD_B3, EVENTOUT - - K6 151 178 - VSS S - - - - - - 152 179 VDD VDD S - - - - - SPI1_MISO/I2S1_SDI, USART6_RX, SPDIFRX1_IN4, QUADSPI_BK2_IO2, SAI2_FS_B, FMC_NE2/FMC_NCE, DCMI_VSYNC, EVENTOUT - - HRTIM_FLT5, SPI1_NSS/I2S1_WS, LCD_G3, SAI2_SD_B, FMC_NE3, DCMI_D2, LCD_B2, EVENTOUT - - LPTIM1_IN2, HRTIM_EEV4, SPI1_SCK/I2S1_CK, SPDIFRX1_IN1, SDMMC2_D2, ETH_MII_TX_EN/ETH_R MII_TX_EN, DCMI_D3, LCD_B3, EVENTOUT - 122 123 124 82/252 A8 C8 A7 153 154 155 LQFP208 121 DFSDM1_DATIN4, SPI1_MOSI/I2S1_SDO, DFSDM1_CKIN1, USART2_CK, SPDIFRX1_IN1, SDMMC2_CMD, FMC_NE1, EVENTOUT LQFP176 Alternate functions LQFP144 Notes I/O structure Pin name (function after reset) Pin type TFBGA240+25 UFBGA176+25 Pin/ball name 180 181 182 A10 A9 B9 PG9 PG10 PG11 I/O I/O I/O FT_ h FT_ h FT_ h DS12923 Rev 1 Additional functions - STM32H745xI/G Pin descriptions Table 8. STM32H745xI/G pin/ball definition (continued) 126 D8 B7 157 183 184 C9 D9 PG12 PG13 I/O I/O I/O structure Pin type TFBGA240+25 LQFP208 LQFP176 156 Pin name (function after reset) Notes 125 UFBGA176+25 LQFP144 Pin/ball name Alternate functions Additional functions - LPTIM1_IN1, HRTIM_EEV5, SPI6_MISO, USART6_RTS/USART6_ DE, SPDIFRX1_IN2, LCD_B4, ETH_MII_TXD1/ETH_R MII_TXD1, FMC_NE4, LCD_B1, EVENTOUT - - TRACED0, LPTIM1_OUT, HRTIM_EEV10, SPI6_SCK, USART6_CTS/USART6_ NSS, ETH_MII_TXD0/ETH_R MII_TXD0, FMC_A24, LCD_R0, EVENTOUT - - FT_ h FT_ h 127 C7 158 185 D8 PG14 I/O FT_ h - TRACED1, LPTIM1_ETR, SPI6_MOSI, USART6_TX, QUADSPI_BK2_IO3, ETH_MII_TXD1/ETH_R MII_TXD1, FMC_A25, LCD_B0, EVENTOUT - K7 159 186 - VSS S - - - - - - 160 187 VDD VDD S - - - - - - - - C8 PK3 I/O FT - LCD_B4, EVENTOUT - - - - - B8 PK4 I/O FT - LCD_B5, EVENTOUT - - - - - A8 PK5 I/O FT - LCD_B6, EVENTOUT - - - - - C7 PK6 I/O FT - LCD_B7, EVENTOUT - - - - - D7 PK7 I/O FT - LCD_DE, EVENTOUT - 128 K8 - - - VSS S - - - - 129 - - - VDD VDD S - - - - - D7 161 188 D6 PG15 I/O FT_ h - USART6_CTS/USART6_ NSS, FMC_SDNCAS, DCMI_D13, EVENTOUT - DS12923 Rev 1 83/252 104 Pin descriptions STM32H745xI/G Table 8. STM32H745xI/G pin/ball definition (continued) 131 A6 B6 163 189 190 C6 B7 PB3(JTDO/T RACESWO) PB4(NJTRS T) I/O I/O I/O structure Pin type TFBGA240+25 LQFP208 LQFP176 162 Pin name (function after reset) Notes 130 UFBGA176+25 LQFP144 Pin/ball name Alternate functions Additional functions - JTDO/TRACESWO, TIM2_CH2, HRTIM_FLT4, SPI1_SCK/I2S1_CK, SPI3_SCK/I2S3_CK, SPI6_SCK, SDMMC2_D2, CRS_SYNC, UART7_RX, EVENTOUT - - NJTRST, TIM16_BKIN, TIM3_CH1, HRTIM_EEV6, SPI1_MISO/I2S1_SDI, SPI3_MISO/I2S3_SDI, SPI2_NSS/I2S2_WS, SPI6_MISO, SDMMC2_D3, UART7_TX, EVENTOUT - - FT FT 132 C6 164 191 A5 PB5 I/O FT - TIM17_BKIN, TIM3_CH2, HRTIM_EEV7, I2C1_SMBA, SPI1_MOSI/I2S1_SDO, I2C4_SMBA, SPI3_MOSI/I2S3_SDO, SPI6_MOSI, FDCAN2_RX, OTG_HS_ULPI_D7, ETH_PPS_OUT, FMC_SDCKE1, DCMI_D10, UART5_RX, EVENTOUT - K9 - - - VSS S - - - - - - - - VDD VDD S - - - - 84/252 DS12923 Rev 1 STM32H745xI/G Pin descriptions Table 8. STM32H745xI/G pin/ball definition (continued) A5 192 B5 PB6 I/O I/O structure Pin type TFBGA240+25 LQFP208 LQFP176 165 Pin name (function after reset) Notes 133 UFBGA176+25 LQFP144 Pin/ball name Alternate functions Additional functions - TIM16_CH1N, TIM4_CH1, HRTIM_EEV8, I2C1_SCL, CEC, I2C4_SCL, USART1_TX, LPUART1_TX, FDCAN2_TX, QUADSPI_BK1_NCS, DFSDM1_DATIN5, FMC_SDNE1, DCMI_D5, UART5_TX, EVENTOUT - PVD_IN FT_f 134 B5 166 193 C5 PB7 I/O FT_f a - TIM17_CH1N, TIM4_CH2, HRTIM_EEV9, I2C1_SDA, I2C4_SDA, USART1_RX, LPUART1_RX, FDCAN2_TXFD_MODE, DFSDM1_CKIN5, FMC_NL, DCMI_VSYNC, EVENTOUT 135 C5 167 194 E8 BOOT0 I B - - VPP - TIM16_CH1, TIM4_CH3, DFSDM1_CKIN7, I2C1_SCL, I2C4_SCL, SDMMC1_CKIN, UART4_RX, FDCAN1_RX, SDMMC2_D4, ETH_MII_TXD3, SDMMC1_D4, DCMI_D6, LCD_B6, EVENTOUT - 136 A2 168 195 D5 PB8 I/O FT_f h DS12923 Rev 1 85/252 104 Pin descriptions STM32H745xI/G Table 8. STM32H745xI/G pin/ball definition (continued) 138 B3 B4 170 196 197 D4 C4 PB9 PE0 I/O I/O I/O structure Pin type TFBGA240+25 LQFP208 LQFP176 169 Pin name (function after reset) Notes 137 UFBGA176+25 LQFP144 Pin/ball name Alternate functions Additional functions - TIM17_CH1, TIM4_CH4, DFSDM1_DATIN7, I2C1_SDA, SPI2_NSS/I2S2_WS, I2C4_SDA, SDMMC1_CDIR, UART4_TX, FDCAN1_TX, SDMMC2_D5, I2C4_SMBA, SDMMC1_D5, DCMI_D7, LCD_B7, EVENTOUT - - LPTIM1_ETR, TIM4_ETR, HRTIM_SCIN, LPTIM2_ETR, UART8_RX, FDCAN1_RXFD_MODE, SAI2_MCLK_A, FMC_NBL0, DCMI_D2, EVENTOUT - - FT_f h FT_ h 139 C4 171 198 B4 PE1 I/O FT_ h - LPTIM1_IN2, HRTIM_SCOUT, UART8_TX, FDCAN1_TXFD_MODE, FMC_NBL1, DCMI_D3, EVENTOUT 140 A4 172 199 A7 VCAP S - - - - 141 K10 173 200 B6 VSS S - - - - 142 D4 174 201 E7 PDR_ON I FT - - - 143 A3 175 202 A6 VDDLDO S - - - - - - - - VDD VDD S - - - - - TIM8_BKIN, SAI2_MCLK_A, TIM8_BKIN_COMP12, FMC_NBL2, DCMI_D5, LCD_B4, EVENTOUT - - 86/252 - - 203 A4 PI4 I/O FT_ h DS12923 Rev 1 STM32H745xI/G Pin descriptions Table 8. STM32H745xI/G pin/ball definition (continued) - - 204 A3 PI5 I/O FT_ h - - - - 205 A2 PI6 I/O FT_ h - TIM8_CH2, SAI2_SD_A, FMC_D28, DCMI_D6, LCD_B6, EVENTOUT - - - - 206 B3 PI7 I/O FT_ h - TIM8_CH3, SAI2_FS_A, FMC_D29, DCMI_D7, LCD_B7, EVENTOUT - - K12 - 207 - VSS S - - - - 144 - 176 208 VDD VDD S - - - - - - - - M15 VSS S - - - - LQFP208 - TIM8_CH1, SAI2_SCK_A, FMC_NBL3, DCMI_VSYNC, LCD_B5, EVENTOUT LQFP176 Alternate functions LQFP144 Notes I/O structure Pin name (function after reset) Pin type TFBGA240+25 UFBGA176+25 Pin/ball name Additional functions - 1. When this pin/ball was previously configured as an oscillator, the oscillator function is kept during and after a reset. This is valid for all resets except for power-on reset. 2. Pxy_C and Pxy pins/balls are two separate pads (analog switch open). The analog switch is configured through a SYSCFG register. Refer to the product reference manual for a detailed description of the switch configuration bits. 3. There is a direct path between Pxy_C and Pxy pins/balls, through an analog switch. Pxy alternate functions are available on Pxy_C when the analog switch is closed. The analog switch is configured through a SYSCFG register. Refer to the product reference manual for a detailed description of the switch configuration bits. DS12923 Rev 1 87/252 104 AF0 AF2 AF3 AF4 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SYS TIM1/2/16/1 7/LPTIM1/ HRTIM1 SAI1/TIM3/ 4/5/12/ HRTIM1 LPUART/ TIM8/ LPTIM2/3/4 /5/HRTIM1/ DFSDM I2C1/2/3/4/ USART1/ TIM15/ LPTIM2/ DFSDM/CEC SPI1/2/3/4/ 5/6/CEC SPI2/3/SAI1 /3/I2C4/ UART4/ DFSDM SPI2/3/6/ USART1/2/ 3/6/UART7 /SDMMC1 SPI6/SAI2/ 4/UART4/5 /8/LPUART /SDMMC1/ SPDIFRX1 SAI4/ FDCAN1/2/ TIM13/14/ QUADSPI/ FMC/ SDMMC2/ LCD/ SPDIFRX1 SAI2/4/ TIM8/ QUADSPI/ SDMMC2/ OTG1_HS/ OTG2_FS/ LCD/CRS I2C4/ UART7/ SWPMI1/ TIM1/8/ DFSDM/ SDMMC2/ MDIOS/ETH TIM1/8/FM C/SDMMC1 /MDIOS/ OTG1_FS/ LCD TIM1/ DCMI/LCD/ COMP UART5/ LCD SYS PA0 - TIM2_CH1/ TIM2_ETR TIM5_CH1 TIM8_ETR TIM15_BKIN - - USART2_ CTS/ USART2_ NSS UART4_TX SDMMC2_ CMD SAI2_SD_B ETH_MII_ CRS - - - EVENT OUT PA1 - TIM2_CH2 TIM5_CH2 LPTIM3_ OUT TIM15_ CH1N - - USART2_ RTS/ USART2_ DE UART4_RX QUADSPI_ BK1_IO3 SAI2_ MCLK_B ETH_MII_RX _CLK/ETH_ RMII_REF_ CLK - - LCD_R2 EVENT OUT PA2 - TIM2_CH3 TIM5_CH3 LPTIM4_ OUT TIM15_CH1 - - USART2_ TX SAI2_SCK _B - - ETH_MDIO MDIOS_ MDIO - LCD_R1 EVENT OUT PA3 - TIM2_CH4 TIM5_CH4 LPTIM5_ OUT TIM15_CH2 - - USART2_ RX - LCD_B2 OTG_HS_ ULPI_D0 ETH_MII_ COL - - LCD_B5 EVENT OUT PA4 D1PWR EN - TIM5_ETR - - SPI1_NSS/ I2S1_WS SPI3_NSS/ I2S3_WS USART2_ CK SPI6_NSS - - - OTG_HS_ SOF DCMI_ HSYNC LCD_ VSYNC EVENT OUT PA5 D2PWR EN TIM2_CH1/ TIM2_ETR - TIM8_ CH1N - SPI1_SCK/ I2S1_CK - - SPI6_SCK - OTG_HS_ ULPI_CK - - - LCD_R4 EVENT OUT PA6 - TIM1_BKIN TIM3_CH1 TIM8_BKIN - SPI1_ MISO/I2S1 _SDI - - SPI6_ MISO TIM13_CH1 TIM8_BKIN _COMP12 MDIOS_ MDC TIM1_BKIN _COMP12 DCMI_PIX CLK LCD_G2 EVENT OUT PA7 - TIM1_CH1N TIM3_CH2 TIM8_ CH1N - SPI1_ MOSI/I2S1 _SDO - - SPI6_ MOSI TIM14_CH1 - ETH_MII_RX _DV/ETH_ RMII_CRS_ DV FMC_SDN WE - - EVENT OUT PA8 MCO1 TIM1_CH1 HRTIM_ CHB2 TIM8_BKIN 2 I2C3_SCL - - USART1_ CK - - OTG_FS_ SOF UART7_RX TIM8_BKIN 2_COMP12 LCD_B3 LCD_R6 EVENT OUT PA9 - TIM1_CH2 HRTIM_ CHC1 LPUART1_ TX I2C3_SMBA SPI2_SCK/ I2S2_CK - USART1_ TX - FDCAN1_ RXFD_ MODE - - - DCMI_D0 LCD_R5 EVENT OUT PA10 - TIM1_CH3 HRTIM_ CHC2 LPUART1_ RX - - - USART1_ RX - FDCAN1_ TXFD_MOD E OTG_FS_ ID MDIOS_ MDIO LCD_B4 DCMI_D1 LCD_B1 EVENT OUT PA11 - TIM1_CH4 HRTIM_ CHD1 LPUART1_ CTS - SPI2_NSS/ I2S2_WS UART4_RX USART1_ CTS/ USART1_ NSS - FDCAN1_ RX OTG_FS_ DM - - - LCD_R4 EVENT OUT Port A DS12923 Rev 1 STM32H745xI/G AF5 Port AF1 Pin descriptions 88/252 Table 9. Port A alternate functions AF0 AF2 AF3 AF4 I2C1/2/3/4/ USART1/ TIM15/ LPTIM2/ DFSDM/CEC AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SPI1/2/3/4/ 5/6/CEC SPI2/3/SAI1 /3/I2C4/ UART4/ DFSDM SPI2/3/6/ USART1/2/ 3/6/UART7 /SDMMC1 SPI6/SAI2/ 4/UART4/5 /8/LPUART /SDMMC1/ SPDIFRX1 SAI4/ FDCAN1/2/ TIM13/14/ QUADSPI/ FMC/ SDMMC2/ LCD/ SPDIFRX1 SAI2/4/ TIM8/ QUADSPI/ SDMMC2/ OTG1_HS/ OTG2_FS/ LCD/CRS I2C4/ UART7/ SWPMI1/ TIM1/8/ DFSDM/ SDMMC2/ MDIOS/ETH TIM1/8/FM C/SDMMC1 /MDIOS/ OTG1_FS/ LCD TIM1/ DCMI/LCD/ COMP UART5/ LCD SYS SYS TIM1/2/16/1 7/LPTIM1/ HRTIM1 SAI1/TIM3/ 4/5/12/ HRTIM1 LPUART/ TIM8/ LPTIM2/3/4 /5/HRTIM1/ DFSDM PA12 - TIM1_ETR HRTIM_ CHD2 LPUART1_ RTS/ LPUART1_ DE - SPI2_SCK/ I2S2_CK UART4_TX USART1_ RTS/ USART1_D E SAI2_FS_B FDCAN1_ TX OTG_FS_ DP - - - LCD_R5 EVENT OUT PA13 JTMSSWDIO - - - - - - - - - - - - - - EVENT OUT PA14 JTCKSWCLK - - - - - - - - - - - - - - EVENT OUT PA15 JTDI TIM2_CH1/ TIM2_ETR HRTIM_ FLT1 - CEC SPI1_NSS/ I2S1_WS SPI3_NSS/ I2S3_WS SPI6_NSS UART4_ RTS/UART 4_DE - - UART7_TX - - - EVENT OUT Port Port A AF1 STM32H745xI/G Table 9. Port A alternate functions (continued) DS12923 Rev 1 Pin descriptions 89/252 AF0 AF2 AF3 AF4 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SYS TIM1/2/16/1 7/LPTIM1/ HRTIM1 SAI1/TIM3/ 4/5/12/ HRTIM1 LPUART/ TIM8/ LPTIM2/3/4 /5/HRTIM1/ DFSDM I2C1/2/3/4/ USART1/ TIM15/ LPTIM2/ DFSDM/CEC SPI1/2/3/4/ 5/6/CEC SPI2/3/SAI1 /3/I2C4/ UART4/ DFSDM SPI2/3/6/ USART1/2/ 3/6/UART7 /SDMMC1 SPI6/SAI2/ 4/UART4/5 /8/LPUART /SDMMC1/ SPDIFRX1 SAI4/ FDCAN1/2/ TIM13/14/ QUADSPI/ FMC/ SDMMC2/ LCD/ SPDIFRX1 SAI2/4/ TIM8/ QUADSPI/ SDMMC2/ OTG1_HS/ OTG2_FS/ LCD/CRS I2C4/ UART7/ SWPMI1/ TIM1/8/ DFSDM/ SDMMC2/ MDIOS/ETH TIM1/8/FM C/SDMMC1 /MDIOS/ OTG1_FS/ LCD TIM1/ DCMI/LCD/ COMP UART5/ LCD SYS PB0 - TIM1_CH2N TIM3_CH3 TIM8_CH2 N - - DFSDM1_ CKOUT - UART4_ CTS LCD_R3 OTG_HS_ ULPI_D1 ETH_MII_RX D2 - - LCD_G1 EVENT OUT PB1 - TIM1_CH3N TIM3_CH4 TIM8_CH3 N - - DFSDM1_ DATIN1 - - LCD_R6 OTG_HS_ ULPI_D2 ETH_MII_RX D3 - - LCD_G0 EVENT OUT PB2 RTC_ OUT - SAI1_D1 - DFSDM1_ CKIN1 - SAI1_SD_A SPI3_ MOSI/I2S3 _SDO SAI4_SD_ A QUADSPI_ CLK SAI4_D1 - - - - EVENT OUT PB3 JTDO/ TRACE SWO TIM2_CH2 HRTIM_ FLT4 - - SPI1_SCK/ I2S1_CK SPI3_SCK/ I2S3_CK - SPI6_SCK SDMMC2_D 2 CRS_SYNC UART7_RX - - - EVENT OUT PB4 NJTRST TIM16_ BKIN TIM3_CH1 HRTIM_ EEV6 - SPI1_ MISO/I2S1 _SDI SPI3_MISO/ I2S3_SDI SPI2_NSS/ I2S2_WS SPI6_ MISO SDMMC2_D 3 - UART7_TX - - - EVENT OUT PB5 - TIM17_ BKIN TIM3_CH2 HRTIM_ EEV7 I2C1_SMBA SPI1_ MOSI/I2S1 _SDO I2C4_SMBA SPI3_ MOSI/I2S3 _SDO SPI6_ MOSI FDCAN2_ RX OTG_HS_ ULPI_D7 ETH_PPS_ OUT FMC_SDCK E1 DCMI_D10 UART5_ RX EVENT OUT PB6 - TIM16_CH1 N TIM4_CH1 HRTIM_ EEV8 I2C1_SCL CEC I2C4_SCL USART1_ TX LPUART1_ TX FDCAN2_ TX QUADSPI_ BK1_NCS DFSDM1_ DATIN5 FMC_SDNE 1 DCMI_D5 UART5_ TX EVENT OUT PB7 - TIM17_CH1 N TIM4_CH2 HRTIM_ EEV9 I2C1_SDA - I2C4_SDA USART1_ RX LPUART1_ RX FDCAN2_ TXFD_ MODE - DFSDM1_ CKIN5 FMC_NL DCMI_ VSYNC - EVENT OUT PB8 - TIM16_CH1 TIM4_CH3 DFSDM1_ CKIN7 I2C1_SCL - I2C4_SCL SDMMC1_ CKIN UART4_RX FDCAN1_ RX SDMMC2_ D4 ETH_MII_TX D3 SDMMC1_ D4 DCMI_D6 LCD_B6 EVENT OUT PB9 - TIM17_CH1 TIM4_CH4 DFSDM1_ DATIN7 I2C1_SDA SPI2_NSS/ I2S2_WS I2C4_SDA SDMMC1_ CDIR UART4_TX FDCAN1_ TX SDMMC2_ D5 I2C4_SMBA SDMMC1_ D5 DCMI_D7 LCD_B7 EVENT OUT PB10 - TIM2_CH3 HRTIM_SC OUT LPTIM2_IN 1 I2C2_SCL SPI2_SCK/ I2S2_CK DFSDM1_ DATIN7 USART3_ TX - QUADSPI_ BK1_NCS OTG_HS_ ULPI_D3 ETH_MII_RX _ER - - LCD_G4 EVENT OUT PB11 - TIM2_CH4 HRTIM_ SCIN LPTIM2_ ETR I2C2_SDA - DFSDM1_ CKIN7 USART3_ RX - - OTG_HS_ ULPI_D4 ETH_MII_TX _EN/ETH_ RMII_TX_EN - - LCD_G5 EVENT OUT PB12 - TIM1_BKIN - - I2C2_SMBA SPI2_NSS/ I2S2_WS DFSDM1_ DATIN1 USART3_ CK - FDCAN2_ RX OTG_HS_ ULPI_D5 ETH_MII_TX D0/ETH_ RMII_TXD0 OTG_HS_ ID TIM1_BKIN _COMP12 UART5_ RX EVENT OUT PB13 - TIM1_CH1N - LPTIM2_ OUT - SPI2_SCK/ I2S2_CK DFSDM1_ CKIN1 USART3_ CTS/ USART3_ NSS - FDCAN2_ TX OTG_HS_ ULPI_D6 ETH_MII_ TXD1/ETH_ RMII_TXD1 - - UART5_ TX EVENT OUT Port B DS12923 Rev 1 STM32H745xI/G AF5 Port AF1 Pin descriptions 90/252 Table 10. Port B alternate functions AF0 AF1 AF2 AF3 AF4 I2C1/2/3/4/ USART1/ TIM15/ LPTIM2/ DFSDM/CEC AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SPI1/2/3/4/ 5/6/CEC SPI2/3/SAI1 /3/I2C4/ UART4/ DFSDM SPI2/3/6/ USART1/2/ 3/6/UART7 /SDMMC1 SPI6/SAI2/ 4/UART4/5 /8/LPUART /SDMMC1/ SPDIFRX1 SAI4/ FDCAN1/2/ TIM13/14/ QUADSPI/ FMC/ SDMMC2/ LCD/ SPDIFRX1 SAI2/4/ TIM8/ QUADSPI/ SDMMC2/ OTG1_HS/ OTG2_FS/ LCD/CRS I2C4/ UART7/ SWPMI1/ TIM1/8/ DFSDM/ SDMMC2/ MDIOS/ETH TIM1/8/FM C/SDMMC1 /MDIOS/ OTG1_FS/ LCD TIM1/ DCMI/LCD/ COMP UART5/ LCD SYS SYS TIM1/2/16/1 7/LPTIM1/ HRTIM1 SAI1/TIM3/ 4/5/12/ HRTIM1 LPUART/ TIM8/ LPTIM2/3/4 /5/HRTIM1/ DFSDM PB14 - TIM1_CH2N TIM12_CH 1 TIM8_CH2 N USART1_TX SPI2_ MISO/I2S2 _SDI DFSDM1_ DATIN2 USART3_ RTS/USAR T3_DE UART4_ RTS/UART 4_DE SDMMC2_ D0 - - OTG_HS_ DM - - EVENT OUT PB15 RTC_ REFIN TIM1_CH3N TIM12_CH 2 TIM8_CH3 N USART1_RX SPI2_ MOSI/I2S2 _SDO DFSDM1_ CKIN2 - UART4_ CTS SDMMC2_D 1 - - OTG_HS_ DP - - EVENT OUT Port B Port STM32H745xI/G Table 10. Port B alternate functions (continued) DS12923 Rev 1 Pin descriptions 91/252 AF0 AF2 AF3 AF4 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SYS TIM1/2/16/1 7/LPTIM1/ HRTIM1 SAI1/TIM3/ 4/5/12/ HRTIM1 LPUART/ TIM8/ LPTIM2/3/4 /5/HRTIM1/ DFSDM I2C1/2/3/4/ USART1/ TIM15/ LPTIM2/ DFSDM/CEC SPI1/2/3/4/ 5/6/CEC SPI2/3/SAI1 /3/I2C4/ UART4/ DFSDM SPI2/3/6/ USART1/2/ 3/6/UART7 /SDMMC1 SPI6/SAI2/ 4/UART4/5 /8/LPUART /SDMMC1/ SPDIFRX1 SAI4/ FDCAN1/2/ TIM13/14/ QUADSPI/ FMC/ SDMMC2/ LCD/ SPDIFRX1 SAI2/4/ TIM8/ QUADSPI/ SDMMC2/ OTG1_HS/ OTG2_FS/ LCD/CRS I2C4/ UART7/ SWPMI1/ TIM1/8/ DFSDM/ SDMMC2/ MDIOS/ETH TIM1/8/FM C/SDMMC1 /MDIOS/ OTG1_FS/ LCD TIM1/ DCMI/LCD/ COMP UART5/ LCD SYS PC0 - - - DFSDM1_ CKIN0 - - DFSDM1_ DATIN4 - SAI2_FS_B - OTG_HS_ ULPI_STP - FMC_SDN WE - LCD_R5 EVENT OUT PC1 TRACE D0 - SAI1_D1 DFSDM1_ DATIN0 DFSDM1_ CKIN4 SPI2_ MOSI/I2S2 _SDO SAI1_SD_A - SAI4_SD_ A SDMMC2_ CK SAI4_D1 ETH_MDC MDIOS_ MDC - - EVENT OUT PC2 C1DSLE EP - - DFSDM1_ CKIN1 - SPI2_ MISO/I2S2 _SDI DFSDM1_ CKOUT - - - OTG_HS_ ULPI_DIR ETH_MII_TX D2 FMC_SDNE 0 - - EVENT OUT PC3 C1 SLEEP - - DFSDM1_ DATIN1 - SPI2_ MOSI/I2S2 _SDO - - - - OTG_HS_ ULPI_NXT ETH_MII_TX _CLK FMC_SDCK E0 - - EVENT OUT PC4 C2 DSLEE P - - DFSDM1_ CKIN2 - I2S1_MCK - - - SPDIFRX1_ IN3 - ETH_MII_RX D0/ETH_ RMII_RXD0 FMC_SDNE 0 - - EVENT OUT PC5 C2 SLEEP - SAI1_D3 DFSDM1_ DATIN2 - - - - - SPDIFRX1_ IN4 SAI4_D3 ETH_MII_RX D1/ETH_ RMII_RXD1 FMC_SDCK E0 COMP1_ OUT - EVENT OUT PC6 - HRTIM_CH A1 TIM3_CH1 TIM8_CH1 DFSDM1_ CKIN3 I2S2_MCK - USART6_ TX SDMMC1_ D0DIR FMC_ NWAIT SDMMC2_ D6 - SDMMC1_ D6 DCMI_D0 LCD_ HSYNC EVENT OUT PC7 TRGIO HRTIM_CH A2 TIM3_CH2 TIM8_CH2 DFSDM1_ DATIN3 - I2S3_MCK USART6_ RX SDMMC1_ D123DIR FMC_NE1 SDMMC2_ D7 SWPMI_TX SDMMC1_ D7 DCMI_D1 LCD_G6 EVENT OUT PC8 TRACE D1 HRTIM_CH B1 TIM3_CH3 TIM8_CH3 - - - USART6_ CK UART5_ RTS/UART 5_DE FMC_NE2/ FMC_NCE - SWPMI_RX SDMMC1_ D0 DCMI_D2 - EVENT OUT PC9 MCO2 - TIM3_CH4 TIM8_CH4 I2C3_SDA I2S_CKIN - - UART5_ CTS QUADSPI_ BK1_IO0 LCD_G3 SWPMI_ SUSPEND SDMMC1_ D1 DCMI_D3 LCD_B2 EVENT OUT PC10 - - HRTIM_EE V1 DFSDM1_ CKIN5 - - SPI3_SCK/I 2S3_CK USART3_ TX UART4_TX QUADSPI_ BK1_IO1 - - SDMMC1_ D2 DCMI_D8 LCD_R2 EVENT OUT PC11 - - HRTIM_ FLT2 DFSDM1_ DATIN5 - - SPI3_MISO/ I2S3_SDI USART3_ RX UART4_RX QUADSPI_ BK2_NCS - - SDMMC1_ D3 DCMI_D4 - EVENT OUT PC12 TRACE D3 - HRTIM_EE V2 - - - SPI3_MOSI/ I2S3_SDO USART3_ CK UART5_TX - - - SDMMC1_ CK DCMI_D9 - EVENT OUT PC13 - - - - - - - - - - - - - - - EVENT OUT Port C DS12923 Rev 1 STM32H745xI/G AF5 Port AF1 Pin descriptions 92/252 Table 11. Port C alternate functions AF0 AF2 AF3 AF4 I2C1/2/3/4/ USART1/ TIM15/ LPTIM2/ DFSDM/CEC AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SPI1/2/3/4/ 5/6/CEC SPI2/3/SAI1 /3/I2C4/ UART4/ DFSDM SPI2/3/6/ USART1/2/ 3/6/UART7 /SDMMC1 SPI6/SAI2/ 4/UART4/5 /8/LPUART /SDMMC1/ SPDIFRX1 SAI4/ FDCAN1/2/ TIM13/14/ QUADSPI/ FMC/ SDMMC2/ LCD/ SPDIFRX1 SAI2/4/ TIM8/ QUADSPI/ SDMMC2/ OTG1_HS/ OTG2_FS/ LCD/CRS I2C4/ UART7/ SWPMI1/ TIM1/8/ DFSDM/ SDMMC2/ MDIOS/ETH TIM1/8/FM C/SDMMC1 /MDIOS/ OTG1_FS/ LCD TIM1/ DCMI/LCD/ COMP UART5/ LCD SYS SYS TIM1/2/16/1 7/LPTIM1/ HRTIM1 SAI1/TIM3/ 4/5/12/ HRTIM1 LPUART/ TIM8/ LPTIM2/3/4 /5/HRTIM1/ DFSDM PC14 - - - - - - - - - - - - - - - EVENT OUT PC15 - - - - - - - - - - - - - - - EVENT OUT Port Port C AF1 STM32H745xI/G Table 11. Port C alternate functions (continued) DS12923 Rev 1 Pin descriptions 93/252 AF0 AF2 AF3 AF4 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SYS TIM1/2/16/1 7/LPTIM1/ HRTIM1 SAI1/TIM3/ 4/5/12/ HRTIM1 LPUART/ TIM8/ LPTIM2/3/4 /5/HRTIM1/ DFSDM I2C1/2/3/4/ USART1/ TIM15/ LPTIM2/ DFSDM/CEC SPI1/2/3/4/ 5/6/CEC SPI2/3/SAI1 /3/I2C4/ UART4/ DFSDM SPI2/3/6/ USART1/2/3/ 6/UART7/SD MMC1 SPI6/SAI2/ 4/UART4/5 /8/LPUART /SDMMC1/ SPDIFRX1 SAI4/ FDCAN1/2/ TIM13/14/ QUADSPI/ FMC/ SDMMC2/ LCD/ SPDIFRX1 SAI2/4/ TIM8/ QUADSPI/ SDMMC2/ OTG1_HS/ OTG2_FS/ LCD/CRS I2C4/ UART7/ SWPMI1/ TIM1/8/ DFSDM/ SDMMC2/ MDIOS/ETH TIM1/8/FM C/SDMMC1 /MDIOS/ OTG1_FS/ LCD TIM1/ DCMI/LCD/ COMP UART5/ LCD SYS PD0 - - - DFSDM1_ CKIN6 - - SAI3_SCK_ A - UART4_RX FDCAN1_ RX - - FMC_D2/ FMC_DA2 - - EVENT OUT PD1 - - - DFSDM1_ DATIN6 - - SAI3_SD_A - UART4_TX FDCAN1_ TX - - FMC_D3/ FMC_DA3 - - EVENT OUT PD2 TRACE D2 - TIM3_ETR - - - - - UART5_RX - - - SDMMC1_ CMD DCMI_D11 - EVENT OUT PD3 - - - DFSDM1_ CKOUT - SPI2_SCK/ I2S2_CK - USART2_ CTS/ USART2_ NSS - - - - FMC_CLK DCMI_D5 LCD_G7 EVENT OUT PD4 - - HRTIM_ FLT3 - - - SAI3_FS_A USART2_ RTS/USART2 _DE - FDCAN1_ RXFD_ MODE - - FMC_NOE - - EVENT OUT PD5 - - HRTIM_EE V3 - - - - USART2_ TX - FDCAN1_ TXFD_ MODE - - FMC_NWE - - EVENT OUT PD6 - - SAI1_D1 DFSDM1_ CKIN4 DFSDM1_ DATIN1 SPI3_ MOSI/I2S3 _SDO SAI1_SD_A USART2_ RX SAI4_SD_ A FDCAN2_ RXFD_ MODE SAI4_D1 SDMMC2_ CK FMC_ NWAIT DCMI_D10 LCD_B2 EVENT OUT PD7 - - - DFSDM1_ DATIN4 - SPI1_ MOSI/I2S1 _SDO DFSDM1_ CKIN1 USART2_ CK - SPDIFRX1_ IN1 - SDMMC2_ CMD FMC_NE1 - - EVENT OUT PD8 - - - DFSDM1_ CKIN3 - - SAI3_SCK_ B USART3_ TX - SPDIFRX1_ IN2 - - FMC_D13/ FMC_DA13 - - EVENT OUT PD9 - - - DFSDM1_ DATIN3 - - SAI3_SD_B USART3_ RX - FDCAN2_ RXFD_ MODE - - FMC_D14/ FMC_DA14 - - EVENT OUT PD10 - - - DFSDM1_ CKOUT - - SAI3_FS_B USART3_ CK - FDCAN2_ TXFD_ MODE - - FMC_D15/ FMC_DA15 - LCD_B3 EVENT OUT PD11 - - - LPTIM2_ IN2 I2C4_SMBA - - USART3_ CTS/ USART3_ NSS - QUADSPI_ BK1_IO0 SAI2_SD_A - FMC_A16 - - EVENT OUT PD12 - LPTIM1_IN1 TIM4_CH1 LPTIM2_IN 1 I2C4_SCL - - USART3_ RTS/ USART3_ DE - QUADSPI_ BK1_IO1 SAI2_FS_A - FMC_A17 - - EVENT OUT Port D DS12923 Rev 1 STM32H745xI/G AF5 Port AF1 Pin descriptions 94/252 Table 12. Port D alternate functions AF0 AF2 AF3 AF4 I2C1/2/3/4/ USART1/ TIM15/ LPTIM2/ DFSDM/CEC AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SPI1/2/3/4/ 5/6/CEC SPI2/3/SAI1 /3/I2C4/ UART4/ DFSDM SPI2/3/6/ USART1/2/3/ 6/UART7/SD MMC1 SPI6/SAI2/ 4/UART4/5 /8/LPUART /SDMMC1/ SPDIFRX1 SAI4/ FDCAN1/2/ TIM13/14/ QUADSPI/ FMC/ SDMMC2/ LCD/ SPDIFRX1 SAI2/4/ TIM8/ QUADSPI/ SDMMC2/ OTG1_HS/ OTG2_FS/ LCD/CRS I2C4/ UART7/ SWPMI1/ TIM1/8/ DFSDM/ SDMMC2/ MDIOS/ETH TIM1/8/FM C/SDMMC1 /MDIOS/ OTG1_FS/ LCD TIM1/ DCMI/LCD/ COMP UART5/ LCD SYS SYS TIM1/2/16/1 7/LPTIM1/ HRTIM1 SAI1/TIM3/ 4/5/12/ HRTIM1 LPUART/ TIM8/ LPTIM2/3/4 /5/HRTIM1/ DFSDM PD13 - LPTIM1_ OUT TIM4_CH2 - I2C4_SDA - - - - QUADSPI_ BK1_IO3 SAI2_SCK_ A - FMC_A18 - - EVENT OUT PD14 - - TIM4_CH3 - - - SAI3_MCLK _B - UART8_ CTS - - - FMC_D0/ FMC_DA0 - - EVENT OUT PD15 - - TIM4_CH4 - - - SAI3_MCLK _A - UART8_ RTS/ UART8_DE - - - FMC_D1/ FMC_DA1 - - EVENT OUT Port Prot D AF1 STM32H745xI/G Table 12. Port D alternate functions (continued) DS12923 Rev 1 Pin descriptions 95/252 AF0 AF2 AF3 AF4 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SYS TIM1/2/16/1 7/LPTIM1/ HRTIM1 SAI1/TIM3/ 4/5/12/ HRTIM1 LPUART/ TIM8/ LPTIM2/3/4 /5/HRTIM1/ DFSDM I2C1/2/3/4/ USART1/ TIM15/ LPTIM2/ DFSDM/CEC SPI1/2/3/4/ 5/6/CEC SPI2/3/SAI1 /3/I2C4/ UART4/ DFSDM SPI2/3/6/ USART1/2/ 3/6/UART7 /SDMMC1 SPI6/SAI2/ 4/UART4/5 /8/LPUART /SDMMC1/ SPDIFRX1 SAI4/ FDCAN1/2/ TIM13/14/ QUADSPI/ FMC/ SDMMC2/ LCD/ SPDIFRX1 SAI2/4/ TIM8/ QUADSPI/ SDMMC2/ OTG1_HS/ OTG2_FS/ LCD/CRS I2C4/ UART7/ SWPMI1/ TIM1/8/ DFSDM/ SDMMC2/ MDIOS/ETH TIM1/8/FM C/SDMMC1 /MDIOS/ OTG1_FS/ LCD TIM1/ DCMI/LCD/ COMP UART5/ LCD SYS PE0 - LPTIM1_ ETR TIM4_ETR HRTIM_ SCIN LPTIM2_ ETR - - - UART8_RX FDCAN1_ RXFD_ MODE SAI2_ MCLK_A - FMC_NBL0 DCMI_D2 - EVENT OUT PE1 - LPTIM1_IN2 - HRTIM_ SCOUT - - - - UART8_TX FDCAN1_ TXFD_ MODE - - FMC_NBL1 DCMI_D3 - EVENT OUT PE2 TRACE CLK - SAI1_CK1 - - SPI4_SCK SAI1_MCLK _A - SAI4_ MCLK_A QUADSPI_ BK1_IO2 SAI4_CK1 ETH_MII_TX D3 FMC_A23 - - EVENT OUT PE3 TRACE D0 - - - TIM15_BKIN - SAI1_SD_B - SAI4_SD_ B - - - FMC_A19 - - EVENT OUT PE4 TRACE D1 - SAI1_D2 DFSDM1_ DATIN3 TIM15_CH1 N SPI4_NSS SAI1_FS_A - SAI4_FS_A - SAI4_D2 - FMC_A20 DCMI_D4 LCD_B0 EVENT OUT PE5 TRACE D2 - SAI1_CK2 DFSDM1_ CKIN3 TIM15_CH1 SPI4_ MISO SAI1_SCK_ A - SAI4_SCK _A - SAI4_CK2 - FMC_A21 DCMI_D6 LCD_G0 EVENT OUT PE6 TRACE D3 TIM1_BKIN 2 SAI1_D1 - TIM15_CH2 SPI4_ MOSI SAI1_SD_A - SAI4_SD_ A SAI4_D1 SAI2_ MCLK_B TIM1_BKIN2 _COMP12 FMC_A22 DCMI_D7 LCD_G1 EVENT OUT PE7 - TIM1_ETR - DFSDM1_ DATIN2 - - - UART7_RX - - QUADSPI_ BK2_IO0 - FMC_D4/ FMC_DA4 - - EVENT OUT PE8 - TIM1_CH1N - DFSDM1_ CKIN2 - - - UART7_TX - - QUADSPI_ BK2_IO1 - FMC_D5/ FMC_DA5 COMP2_ OUT - EVENT OUT PE9 - TIM1_CH1 - DFSDM1_ CKOUT - - - UART7_ RTS/ UART7_DE - - QUADSPI_ BK2_IO2 - FMC_D6/ FMC_DA6 - - EVENT OUT PE10 - TIM1_CH2N - DFSDM1_ DATIN4 - - - UART7_ CTS - - QUADSPI_ BK2_IO3 - FMC_D7/ FMC_DA7 - - EVENT OUT PE11 - TIM1_CH2 - DFSDM1_ CKIN4 - SPI4_NSS - - - - SAI2_SD_B - FMC_D8/ FMC_DA8 - LCD_G3 EVENT OUT PE12 - TIM1_CH3N - DFSDM1_ DATIN5 - SPI4_SCK - - - - SAI2_SCK_ B - FMC_D9/ FMC_DA9 COMP1_ OUT LCD_B4 EVENT OUT PE13 - TIM1_CH3 - DFSDM1_ CKIN5 - SPI4_ MISO - - - - SAI2_FS_B - FMC_D10/ FMC_DA10 COMP2_ OUT LCD_DE EVENT OUT Port E DS12923 Rev 1 STM32H745xI/G AF5 Port AF1 Pin descriptions 96/252 Table 13. Port E alternate functions AF0 AF2 AF3 AF4 I2C1/2/3/4/ USART1/ TIM15/ LPTIM2/ DFSDM/CEC AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SPI1/2/3/4/ 5/6/CEC SPI2/3/SAI1 /3/I2C4/ UART4/ DFSDM SPI2/3/6/ USART1/2/ 3/6/UART7 /SDMMC1 SPI6/SAI2/ 4/UART4/5 /8/LPUART /SDMMC1/ SPDIFRX1 SAI4/ FDCAN1/2/ TIM13/14/ QUADSPI/ FMC/ SDMMC2/ LCD/ SPDIFRX1 SAI2/4/ TIM8/ QUADSPI/ SDMMC2/ OTG1_HS/ OTG2_FS/ LCD/CRS I2C4/ UART7/ SWPMI1/ TIM1/8/ DFSDM/ SDMMC2/ MDIOS/ETH TIM1/8/FM C/SDMMC1 /MDIOS/ OTG1_FS/ LCD TIM1/ DCMI/LCD/ COMP UART5/ LCD SYS SYS TIM1/2/16/1 7/LPTIM1/ HRTIM1 SAI1/TIM3/ 4/5/12/ HRTIM1 LPUART/ TIM8/ LPTIM2/3/4 /5/HRTIM1/ DFSDM PE14 - TIM1_CH4 - - - SPI4_ MOSI - - - - SAI2_MCL K_B - FMC_D11/ FMC_DA11 - LCD_CL K EVENT OUT PE15 - TIM1_BKIN - - - - - - - - - - FMC_D12/ FMC_DA12 TIM1_BKIN _COMP12/ COMP_ TIM1_BKIN LCD_R7 EVENT OUT Port Prot E AF1 STM32H745xI/G Table 13. Port E alternate functions (continued) DS12923 Rev 1 Pin descriptions 97/252 AF0 AF2 AF3 AF4 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SYS TIM1/2/16/1 7/LPTIM1/ HRTIM1 SAI1/TIM3/ 4/5/12/ HRTIM1 LPUART/ TIM8/ LPTIM2/3/4 /5/HRTIM1/ DFSDM I2C1/2/3/4/ USART1/ TIM15/ LPTIM2/ DFSDM/CEC SPI1/2/3/4/ 5/6/CEC SPI2/3/SAI1 /3/I2C4/ UART4/ DFSDM SPI2/3/6/ USART1/2/ 3/6/UART7 /SDMMC1 SPI6/SAI2/ 4/UART4/5 /8/LPUART /SDMMC1/ SPDIFRX1 SAI4/ FDCAN1/2/ TIM13/14/ QUADSPI/ FMC/ SDMMC2/ LCD/ SPDIFRX1 SAI2/4/ TIM8/ QUADSPI/ SDMMC2/ OTG1_HS/ OTG2_FS/ LCD/CRS I2C4/ UART7/ SWPMI1/ TIM1/8/ DFSDM/ SDMMC2/ MDIOS/ETH TIM1/8/FM C/SDMMC1 /MDIOS/ OTG1_FS/ LCD TIM1/ DCMI/LCD/ COMP UART5/ LCD SYS PF0 - - - - I2C2_SDA - - - - - - - FMC_A0 - - EVENT OUT PF1 - - - - I2C2_SCL - - - - - - - FMC_A1 - - EVENT OUT PF2 - - - - I2C2_SMBA - - - - - - - FMC_A2 - - EVENT OUT PF3 - - - - - - - - - - - - FMC_A3 - - EVENT OUT PF4 - - - - - - - - - - - - FMC_A4 - - EVENT OUT PF5 - - - - - - - - - - - - FMC_A5 - - EVENT OUT PF6 - TIM16_CH1 - - - SPI5_NSS SAI1_SD_B UART7_RX SAI4_SD_ B QUADSPI_ BK1_IO3 - - - - - EVENT OUT PF7 - TIM17_CH1 - - - SPI5_SCK SAI1_MCLK _B UART7_TX SAI4_ MCLK_B QUADSPI_ BK1_IO2 - - - - - EVENT OUT PF8 - TIM16_CH1 N - - - SPI5_ MISO SAI1_SCK_ B UART7_ RTS/ UART7_DE SAI4_SCK _B TIM13_CH1 QUADSPI_ BK1_IO0 - - - - EVENT OUT PF9 - TIM17_CH1 N - - - SPI5_ MOSI SAI1_FS_B UART7_ CTS SAI4_FS_B TIM14_CH1 QUADSPI_ BK1_IO1 - - - - EVENT OUT PF10 - TIM16_BKI N SAI1_D3 - - - - - - QUADSPI_ CLK SAI4_D3 - - DCMI_D11 LCD_DE EVENT OUT PF11 - - - - - SPI5_ MOSI - - - - SAI2_SD_B - FMC_ SDNRAS DCMI_D12 - EVENT OUT PF12 - - - - - - - - - - - - FMC_A6 - - EVENT OUT PF13 - - - DFSDM1_ DATIN6 I2C4_SMBA - - - - - - - FMC_A7 - - EVENT OUT PF14 - - - DFSDM1_ CKIN6 I2C4_SCL - - - - - - - FMC_A8 - - EVENT OUT PF15 - - - - I2C4_SDA - - - - - - - FMC_A9 - - EVENT OUT Port F DS12923 Rev 1 STM32H745xI/G AF5 Port AF1 Pin descriptions 98/252 Table 14. Port F alternate functions AF0 AF2 AF3 AF4 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SYS TIM1/2/16/1 7/LPTIM1/ HRTIM1 SAI1/TIM3/ 4/5/12/ HRTIM1 LPUART/ TIM8/ LPTIM2/3/4 /5/HRTIM1/ DFSDM I2C1/2/3/4/ USART1/ TIM15/ LPTIM2/ DFSDM/CEC SPI1/2/3/4/ 5/6/CEC SPI2/3/SAI1 /3/I2C4/ UART4/ DFSDM SPI2/3/6/ USART1/2/ 3/6/UART7 /SDMMC1 SPI6/SAI2/ 4/UART4/5 /8/LPUART /SDMMC1/ SPDIFRX1 SAI4/ FDCAN1/2/ TIM13/14/ QUADSPI/ FMC/ SDMMC2/ LCD/ SPDIFRX1 SAI2/4/ TIM8/ QUADSPI/ SDMMC2/ OTG1_HS/ OTG2_FS/ LCD/CRS I2C4/ UART7/ SWPMI1/ TIM1/8/ DFSDM/ SDMMC2/ MDIOS/ETH TIM1/8/FM C/SDMMC1 /MDIOS/ OTG1_FS/ LCD TIM1/ DCMI/LCD/ COMP UART5/ LCD SYS PG0 - - - - - - - - - - - - FMC_A10 - - EVENT OUT PG1 - - - - - - - - - - - - FMC_A11 - - EVENT OUT PG2 - - - TIM8_BKIN - - - - - - - TIM8_BKIN_ COMP12 FMC_A12 - - EVENT OUT PG3 - - - TIM8_BKIN 2 - - - - - - - TIM8_BKIN2 _COMP12 FMC_A13 - - EVENT OUT PG4 - TIM1_BKIN 2 - - - - - - - - - TIM1_BKIN2 _COMP12 FMC_A14/ FMC_BA0 - - EVENT OUT PG5 - TIM1_ETR - - - - - - - - - - FMC_A15/ FMC_BA1 - - EVENT OUT PG6 - TIM17_ BKIN HRTIM_ CHE1 - - - - - - - QUADSPI_ BK1_NCS - FMC_NE3 DCMI_D12 LCD_R7 EVENT OUT PG7 - - HRTIM_ CHE2 - - - SAI1_MCLK _A USART6_ CK - - - - FMC_INT DCMI_D13 LCD_CL K EVENT OUT PG8 - - - TIM8_ETR - SPI6_NSS - USART6_ RTS/ USART6_ DE - - ETH_PPS_ OUT FMC_ SDCLK - LCD_G7 EVENT OUT PG9 - - - - - SPI1_ MISO/I2S1 _SDI - USART6_ RX SPDIFRX1 _ IN4 QUADSPI_ BK2_IO2 SAI2_FS_B - FMC_NE2/ FMC_NCE DCMI_ VSYNC - EVENT OUT PG10 - - HRTIM_ FLT5 - - SPI1_NSS/ I2S1_WS - - - LCD_G3 SAI2_SD_B - FMC_NE3 DCMI_D2 LCD_B2 EVENT OUT PG11 - LPTIM1_IN2 HRTIM_ EEV4 - - SPI1_SCK/ I2S1_CK - - - SDMMC2_ D2 ETH_MII_ TX_EN/ETH _RMII_TX_ EN - DCMI_D3 LCD_B3 EVENT OUT PG12 - LPTIM1_IN1 HRTIM_ EEV5 - - SPI6_ MISO - USART6_ RTS/ USART6_ DE LCD_B4 - ETH_MII_TX D1/ETH_ RMII_TXD1 FMC_NE4 - LCD_B1 EVENT OUT Port G DS12923 Rev 1 SPDIFRX1 _ IN3 SPDIFRX1 _ IN1 SPDIFRX1 _IN2 99/252 Pin descriptions AF5 Port AF1 STM32H745xI/G Table 15. Port G alternate functions AF0 AF2 AF3 AF4 I2C1/2/3/4/ USART1/ TIM15/ LPTIM2/ DFSDM/CEC AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SPI1/2/3/4/ 5/6/CEC SPI2/3/SAI1 /3/I2C4/ UART4/ DFSDM SPI2/3/6/ USART1/2/ 3/6/UART7 /SDMMC1 SPI6/SAI2/ 4/UART4/5 /8/LPUART /SDMMC1/ SPDIFRX1 SAI4/ FDCAN1/2/ TIM13/14/ QUADSPI/ FMC/ SDMMC2/ LCD/ SPDIFRX1 SAI2/4/ TIM8/ QUADSPI/ SDMMC2/ OTG1_HS/ OTG2_FS/ LCD/CRS I2C4/ UART7/ SWPMI1/ TIM1/8/ DFSDM/ SDMMC2/ MDIOS/ETH TIM1/8/FM C/SDMMC1 /MDIOS/ OTG1_FS/ LCD TIM1/ DCMI/LCD/ COMP UART5/ LCD SYS SYS TIM1/2/16/1 7/LPTIM1/ HRTIM1 SAI1/TIM3/ 4/5/12/ HRTIM1 LPUART/ TIM8/ LPTIM2/3/4 /5/HRTIM1/ DFSDM PG13 TRACE D0 LPTIM1_ OUT HRTIM_ EEV10 - - SPI6_SCK - USART6_ CTS/ USART6_ NSS - - - ETH_MII_TX D0/ETH_ RMII_TXD0 FMC_A24 - LCD_R0 EVENT OUT PG14 TRACE D1 LPTIM1_ ETR - - - SPI6_ MOSI - USART6_ TX - QUADSPI_ BK2_IO3 - ETH_MII_TX D1/ETH_ RMII_TXD1 FMC_A25 - LCD_B0 EVENT OUT PG15 - - - - - - - USART6_ CTS/ USART6_ NSS - - - - FMC_ SDNCAS DCMI_D13 - EVENT OUT Port Prot G AF1 Pin descriptions 100/252 Table 15. Port G alternate functions (continued) DS12923 Rev 1 STM32H745xI/G AF0 AF2 AF3 AF4 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SYS TIM1/2/16/1 7/LPTIM1/ HRTIM1 SAI1/TIM3/ 4/5/12/ HRTIM1 LPUART/ TIM8/ LPTIM2/3/4 /5/HRTIM1/ DFSDM I2C1/2/3/4/ USART1/ TIM15/ LPTIM2/ DFSDM/CEC SPI1/2/3/4/ 5/6/CEC SPI2/3/SAI1 /3/I2C4/ UART4/ DFSDM SPI2/3/6/ USART1/2/ 3/6/UART7 /SDMMC1 SPI6/SAI2/ 4/UART4/5 /8/LPUART /SDMMC1/ SPDIFRX1 SAI4/ FDCAN1/2/ TIM13/14/ QUADSPI/ FMC/ SDMMC2/ LCD/ SPDIFRX1 SAI2/4/ TIM8/ QUADSPI/ SDMMC2/ OTG1_HS/ OTG2_FS/ LCD/CRS I2C4/ UART7/ SWPMI1/ TIM1/8/ DFSDM/ SDMMC2/ MDIOS/ETH TIM1/8/FM C/SDMMC1 /MDIOS/ OTG1_FS/ LCD TIM1/ DCMI/LCD/ COMP UART5/ LCD SYS PH0 - - - - - - - - - - - - - - - EVENT OUT PH1 - - - - - - - - - - - - - - - EVENT OUT PH2 - LPTIM1_IN2 - - - - - - - QUADSPI_ BK2_IO0 SAI2_SCK_ B ETH_MII_ CRS FMC_ SDCKE0 - LCD_R0 EVENT OUT PH3 - - - - - - - - - QUADSPI_ BK2_IO1 SAI2_ MCLK_B ETH_MII_ COL FMC_SDNE 0 - LCD_R1 EVENT OUT PH4 - - - - I2C2_SCL - - - - LCD_G5 OTG_HS_U LPI_NXT - - - LCD_G4 EVENT OUT PH5 - - - - I2C2_SDA SPI5_NSS - - - - - - FMC_SDN WE - - EVENT OUT PH6 - - TIM12_CH 1 - I2C2_SMBA SPI5_SCK - - - - - ETH_MII_RX D2 FMC_SDNE 1 DCMI_D8 - EVENT OUT PH7 - - - - I2C3_SCL SPI5_ MISO - - - - - ETH_MII_RX D3 FMC_ SDCKE1 DCMI_D9 - EVENT OUT PH8 - - TIM5_ETR - I2C3_SDA - - - - - - - FMC_D16 DCMI_HSY NC LCD_R2 EVENT OUT PH9 - - TIM12_CH 2 - I2C3_SMBA - - - - - - - FMC_D17 DCMI_D0 LCD_R3 EVENT OUT PH10 - - TIM5_CH1 - I2C4_SMBA - - - - - - - FMC_D18 DCMI_D1 LCD_R4 EVENT OUT PH11 - - TIM5_CH2 - I2C4_SCL - - - - - - - FMC_D19 DCMI_D2 LCD_R5 EVENT OUT PH12 - - TIM5_CH3 - I2C4_SDA - - - - - - - FMC_D20 DCMI_D3 LCD_R6 EVENT OUT PH13 - - - TIM8_CH1 N - - - - UART4_TX FDCAN1_ TX - - FMC_D21 - LCD_G2 EVENT OUT PH14 - - - TIM8_CH2 N - - - - UART4_RX FDCAN1_ RX - - FMC_D22 DCMI_D4 LCD_G3 EVENT OUT PH15 - - - TIM8_CH3 N - - - - - FDCAN1_ TXFD_ MODE - - FMC_D23 DCMI_D11 LCD_G4 EVENT OUT Port H DS12923 Rev 1 101/252 Pin descriptions AF5 Port AF1 STM32H745xI/G Table 16. Port H alternate functions AF0 AF2 AF3 AF4 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SYS TIM1/2/16/1 7/LPTIM1/ HRTIM1 SAI1/TIM3/ 4/5/12/ HRTIM1 LPUART/ TIM8/ LPTIM2/3/4 /5/HRTIM1/ DFSDM I2C1/2/3/4/ USART1/ TIM15/ LPTIM2/ DFSDM/CEC SPI1/2/3/4/ 5/6/CEC SPI2/3/SAI1 /3/I2C4/ UART4/ DFSDM SPI2/3/6/ USART1/2/ 3/6/UART7 /SDMMC1 SPI6/SAI2/ 4/UART4/5 /8/LPUART /SDMMC1/ SPDIFRX1 SAI4/ FDCAN1/2/ TIM13/14/ QUADSPI/ FMC/ SDMMC2/ LCD/ SPDIFRX1 SAI2/4/ TIM8/ QUADSPI/ SDMMC2/ OTG1_HS/ OTG2_FS/ LCD/CRS I2C4/ UART7/ SWPMI1/ TIM1/8/ DFSDM/ SDMMC2/ MDIOS/ETH TIM1/8/FM C/SDMMC1 /MDIOS/ OTG1_FS/ LCD TIM1/ DCMI/LCD/ COMP UART5/ LCD SYS PI0 - - TIM5_CH4 - - SPI2_NSS/ I2S2_WS - - - FDCAN1_ RXFD_MODE - - FMC_D24 DCMI_D13 LCD_G5 EVENT OUT PI1 - - - TIM8_BKIN 2 - SPI2_SCK/ I2S2_CK - - - - - TIM8_BKIN2 _COMP12 FMC_D25 DCMI_D8 LCD_G6 EVENT OUT PI2 - - - TIM8_CH4 - SPI2_MIS O/I2S2_SD I - - - - - - FMC_D26 DCMI_D9 LCD_G7 EVENT OUT PI3 - - - TIM8_ETR - SPI2_ MOSI/I2S2 _SDO - - - - - - FMC_D27 DCMI_D10 - EVENT OUT PI4 - - - TIM8_BKIN - - - - - - SAI2_ MCLK_A TIM8_BKIN_ COMP12 FMC_NBL2 DCMI_D5 LCD_B4 EVENT OUT PI5 - - - TIM8_CH1 - - - - - - SAI2_SCK_ A - FMC_NBL3 DCMI_ VSYNC LCD_B5 EVENT OUT PI6 - - - TIM8_CH2 - - - - - - SAI2_SD_A - FMC_D28 DCMI_D6 LCD_B6 EVENT OUT PI7 - - - TIM8_CH3 - - - - - - SAI2_FS_A - FMC_D29 DCMI_D7 LCD_B7 EVENT OUT PI8 - - - - - - - - - - - - - - - EVENT OUT PI9 - - - - - - - - UART4_RX FDCAN1_ RX - - FMC_D30 - LCD_VS YNC EVENT OUT PI10 - - - - - - - - - FDCAN1_ RXFD_MODE - ETH_MII_RX _ER FMC_D31 - LCD_HS YNC EVENT OUT PI11 - - - - - - - - - LCD_G6 OTG_HS_ ULPI_DIR - - - - EVENT OUT PI12 - - - - - - - - - - - - - - LCD_HS YNC EVENT OUT PI13 - - - - - - - - - - - - - - LCD_VS YNC EVENT OUT PI14 - - - - - - - - - - - - - - LCD_CL K EVENT OUT PI15 - - - - - - - - - LCD_G2 - - - - LCD_R0 EVENT OUT Port I DS12923 Rev 1 STM32H745xI/G AF5 Port AF1 Pin descriptions 102/252 Table 17. Port I alternate functions AF0 AF2 AF3 AF4 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SYS TIM1/2/16/1 7/LPTIM1/ HRTIM1 SAI1/TIM3/ 4/5/12/ HRTIM1 LPUART/ TIM8/ LPTIM2/3/4 /5/HRTIM1/ DFSDM I2C1/2/3/4/ USART1/ TIM15/ LPTIM2/ DFSDM/CEC SPI1/2/3/4/ 5/6/CEC SPI2/3/SAI1 /3/I2C4/ UART4/ DFSDM SPI2/3/6/ USART1/2/ 3/6/UART7 /SDMMC1 SPI6/SAI2/ 4/UART4/5 /8/LPUART /SDMMC1/ SPDIFRX1 SAI4/ FDCAN1/2/ TIM13/14/ QUADSPI/ FMC/ SDMMC2/ LCD/ SPDIFRX1 SAI2/4/ TIM8/ QUADSPI/ SDMMC2/ OTG1_HS/ OTG2_FS/ LCD/CRS I2C4/ UART7/ SWPMI1/ TIM1/8/ DFSDM/ SDMMC2/ MDIOS/ETH TIM1/8/FM C/SDMMC1 /MDIOS/ OTG1_FS/ LCD TIM1/ DCMI/LCD/ COMP UART5/ LCD SYS PJ0 - - - - - - - - - LCD_R7 - - - - LCD_R1 EVENT OUT PJ1 - - - - - - - - - - - - - - LCD_R2 EVENT OUT PJ2 - - - - - - - - - - - - - - LCD_R3 EVENT OUT PJ3 - - - - - - - - - - - - - - LCD_R4 EVENT OUT PJ4 - - - - - - - - - - - - - - LCD_R5 EVENT OUT PJ5 - - - - - - - - - - - - - - LCD_R6 EVENT OUT PJ6 - - - TIM8_CH2 - - - - - - - - - - LCD_R7 EVENT OUT PJ7 TRGIN - - TIM8_CH2 N - - - - - - - - - - LCD_G0 EVENT OUT PJ8 - TIM1_CH3N - TIM8_CH1 - - - - UART8_TX - - - - - LCD_G1 EVENT OUT PJ9 - TIM1_CH3 - TIM8_CH1 N - - - - UART8_RX - - - - - LCD_G2 EVENT OUT PJ10 - TIM1_CH2N - TIM8_CH2 - SPI5_ MOSI - - - - - - - - LCD_G3 EVENT OUT PJ11 - TIM1_CH2 - TIM8_CH2 N - SPI5_ MISO - - - - - - - - LCD_G4 EVENT OUT PJ12 TRGOU T - - - - - - - - LCD_G3 - - - - LCD_B0 EVENT OUT PJ13 - - - - - - - - - LCD_B4 - - - - LCD_B1 EVENT OUT PJ14 - - - - - - - - - - - - - - LCD_B2 EVENT OUT PJ15 - - - - - - - - - - - - - - LCD_B3 EVENT OUT Port J DS12923 Rev 1 103/252 Pin descriptions AF5 Port AF1 STM32H745xI/G Table 18. Port J alternate functions AF0 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SYS TIM1/2/16/1 7/LPTIM1/ HRTIM1 SAI1/TIM3/ 4/5/12/ HRTIM1 LPUART/ TIM8/ LPTIM2/3/4 /5/HRTIM1/ DFSDM I2C1/2/3/4/ USART1/ TIM15/ LPTIM2/ DFSDM/CEC SPI1/2/3/4/ 5/6/CEC SPI2/3/SAI1 /3/I2C4/ UART4/ DFSDM SPI2/3/6/ USART1/2/ 3/6/UART7 /SDMMC1 SPI6/SAI2/ 4/UART4/5 /8/LPUART /SDMMC1/ SPDIFRX1 SAI4/ FDCAN1/2/ TIM13/14/ QUADSPI/ FMC/ SDMMC2/ LCD/ SPDIFRX1 SAI2/4/ TIM8/ QUADSPI/ SDMMC2/ OTG1_HS/ OTG2_FS/ LCD/CRS I2C4/ UART7/ SWPMI1/ TIM1/8/ DFSDM/ SDMMC2/ MDIOS/ETH TIM1/8/FM C/SDMMC1 /MDIOS/ OTG1_FS/ LCD TIM1/ DCMI/LCD/ COMP UART5/ LCD SYS PK0 - TIM1_CH1N - TIM8_CH3 - SPI5_SCK - - - - - - - - LCD_G5 EVENT OUT PK1 - TIM1_CH1 - TIM8_CH3 N - SPI5_NSS - - - - - - - - LCD_G6 EVENT OUT PK2 - TIM1_BKIN - TIM8_BKIN - - - - - - TIM8_BKIN _COMP12 TIM1_BKIN_ COMP12 - - LCD_G7 EVENT OUT PK3 - - - - - - - - - - - - - - LCD_B4 EVENT OUT PK4 - - - - - - - - - - - - - - LCD_B5 EVENT OUT PK5 - - - - - - - - - - - - - - LCD_B6 EVENT OUT PK6 - - - - - - - - - - - - - - LCD_B7 EVENT OUT PK7 - - - - - - - - - - - - - - LCD_DE EVENT OUT Port K Port AF1 Pin descriptions 104/252 Table 19. Port K alternate functions DS12923 Rev 1 STM32H745xI/G STM32H745xI/G 6 6.1 Electrical characteristics Electrical characteristics Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. 6.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of junction temperature, supply voltage and frequencies by tests in production on 100% of the devices with an junction temperature at TJ = 25 C and TJ = TJmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3). 6.1.2 Typical values Unless otherwise specified, typical data are based on TJ = 25 C, VDD = 3.3 V (for the 1.7 V VDD 3.6 V voltage range). They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean2). 6.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 6.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 11. 6.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 12. Figure 11. Pin loading conditions Figure 12. Pin input voltage MCU pin MCU pin C = 50 pF VIN MS19011V2 DS12923 Rev 1 MS19010V2 105/252 228 Electrical characteristics 6.1.6 STM32H745xI/G Power supply scheme VDD33USB Step Down Coverter (SMPS) VLXSMPS VFBSMPS VSSSMPS USB regulator VDDLDO VCAP Core domain (VCORE) Level shifter IOs N(1) x 100 nF + 1 x 4.7 F VDD D3 domain (System logic, EXTI, IO logic Peripherals, RAM) Power switch Power switch VSS D2 domain (peripherals, RAM) D1 domain (CPU, peripherals, RAM) VDD domain VBAT charging HSI, CSI, HSI48, HSE, PLLs Backup domain Backup VBKP regulator VSW VBAT Power switch Power switch LSI, LSE, RTC, Wakeup logic, backup IO registers, logic Reset BKUP IOs VREF 100 nF + 1 x 1 F 100 nF + 1 x 1 F VDDA VDDA Flash VSS VDD VBAT 1.2 to 3.6V VSS Voltage regulator VDDLDO 4..7F 2 x 2.2F VDD50USB USB IOs VSS VDDSMPS VDD50USB 100 nF VDD33USB 100 nF Figure 13. Power supply scheme VSS Analog domain REF_BUF VREF+ ADC, DAC VREF+ VREF- VREF- Backup RAM VSS OPAMP, Comparator VSSA MSv62410V1 1. N corresponds to the number of VDD pins available on the package. 2. A tolerance of +/- 20% is acceptable on decoupling capacitors. Caution: 106/252 Each power supply pair (VDD/VSS, VDDA/VSSA ...) must be decoupled with filtering ceramic capacitors as shown above. These capacitors must be placed as close as possible to, or below, the appropriate pins on the underside of the PCB to ensure good operation of the DS12923 Rev 1 STM32H745xI/G Electrical characteristics device. It is not recommended to remove filtering capacitors to reduce PCB size or cost. This might cause incorrect operation of the device. 6.1.7 Current consumption measurement Figure 14. Current consumption measurement scheme IDD_VBAT VBAT IDD VDD VDDA ai14126 6.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 20: Voltage characteristics, Table 21: Current characteristics, and Table 22: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and the functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 20. Voltage characteristics (1) Symbols VDDX - VSS VIN(2) Ratings Min Max Unit -0.3 4.0 V Input voltage on FT_xxx pins VSS-0.3 Min(VDD, VDDA, VDD33USB, VBAT) +4.0(3)(4) V Input voltage on TT_xx pins VSS-0.3 4.0 V Input voltage on BOOT0 pin VSS 9.0 V VSS-0.3 4.0 V - 50 mV - 50 mV External main supply voltage (including VDD, VDDLDO, VDDSMPS, VDDA, VDD33USB, VBAT) Input voltage on any other pins |VDDX| Variations between different VDDX power pins of the same domain |VSSx-VSS| Variations between all the different ground pins 1. All main power (VDD, VDDA, VDD33USB, VDDSMPS, VBAT) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. VIN maximum must always be respected. Refer to Table 68: I/O current injection susceptibility for the maximum allowed injected current values. 3. This formula has to be applied on power supplies related to the IO structure described by the pin definition table. 4. To sustain a voltage higher than 4V the internal pull-up/pull-down resistors must be disabled. DS12923 Rev 1 107/252 228 Electrical characteristics STM32H745xI/G Table 21. Current characteristics Symbols Ratings Max IVDD Total current into sum of all VDD power lines (source)(1) 620 IVSS (1) 620 Total current out of sum of all VSS ground lines (sink) IVDD (1) Maximum current into each VDD power pin (source) 100 IVSS Maximum current out of each VSS ground pin (sink)(1) 100 Output current sunk by any I/O and control pin IIO 20 (2) I(PIN) Total output current sunk by sum of all I/Os and control pins 140 Total output current sourced by sum of all I/Os and control pins(2) 140 Injected current on FT_xxx, TT_xx, RST and B pins except PA4, IINJ(PIN)(3)(4) PA5 Injected current on PA4, PA5 IINJ(PIN) Total injected current (sum of all I/Os and control Unit mA -5/+0 -0/0 pins)(5) 25 1. All main power (VDD, VDDA, VDD33USB) and ground (VSS, VSSA) pins must always be connected to the external power supplies, in the permitted range. 2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins referring to high pin count QFP packages. 3. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value. 4. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. IINJ(PIN) must never be exceeded. Refer also to Table 20: Voltage characteristics for the maximum allowed input voltage values. 5. When several inputs are submitted to a current injection, the maximum IINJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values). Table 22. Thermal characteristics Symbol TSTG TJ Ratings Storage temperature range Maximum junction temperature 1. For industrial temperature range 6. 2. For extended industrial temperature range 3. 108/252 DS12923 Rev 1 Value Unit - 65 to +150 125(1) 140(2) C STM32H745xI/G Electrical characteristics 6.3 Operating conditions 6.3.1 General operating conditions Table 23. General operating conditions Symbol Parameter VDD Standard operating voltage Operating conditions Supply voltage for the internal regulator VDDSMPS Supply voltage for the internal SMPS Step-down converter VDD33USB Standard operating voltage, USB domain Analog operating voltage Typ Max Unit 1.62(1) - 3.6 V (1) - 3.6 1.2(2) - 3.6 1.62(1) - 3.6 3.0 - 3.6 0 - 3.6 ADC or COMP used 1.62 - DAC used 1.8 - OPAMP used 2.0 - VREFBUF used 1.8 - 0 - -0.3 - VDD+0.3 0 - 9 - Min(VDD, VDDA, VDD33USB) +3.6V < 5.5V(3)(4) - VDDLDO VDDA Min VDDLDO VDD VDDSMPS = VDD USB used USB not used ADC, DAC, OPAMP, COMP, VREFBUF not used TT_xx I/O BOOT0 VIN 1.62 I/O Input voltage All I/O except BOOT0 and TT_xx DS12923 Rev 1 -0.3 V V 3.6 V 109/252 228 Electrical characteristics STM32H745xI/G Table 23. General operating conditions (continued) Symbol Parameter Internal regulator ON (LDO) VCORE Internal regulator ON (SMPS stepdown converter)(7) Operating conditions Min Typ Max VOS3 (max frequency 200 MHz) 0.95 1.0 1.26 VOS2 (max frequency 300 MHz) 1.05 1.10 1.26 VOS1 (max frequency 400 MHz) 1.15 1.20 1.26 VOS0(5) (max frequency 480 MHz(6)) 1.26 1.35 1.40 VOS3 (max frequency 200 MHz) 0.95 1.0 1.26 VOS2 (max frequency 300 MHz) 1.05 1.10 1.26 VOS1 (max frequency 400 MHz) 1.15 1.20 1.26 VOS3 (max frequency 200 MHz) 0.98 1.03 1.26 1.08 1.13 1.26 1.17 1.23 1.26 1.37 1.38 1.40 VOS2 (max frequency Regulator OFF: external VCORE 300 MHz) voltage must be supplied from external VOS1 (max frequency regulator on two VCAP pins 400 MHz) VOS0 (max frequency 480 MHz(6)) 110/252 DS12923 Rev 1 Unit V STM32H745xI/G Electrical characteristics Table 23. General operating conditions (continued) Symbol fCPU1 Operating conditions Parameter Arm(R) Cortex(R)-M7 clock frequency Arm(R) Cortex(R)-M4 clock frequency fCPU2 fACLK AXI clock frequency fHCLK AHB clock frequency fPCLK APB clock frequency Min Typ Max VOS3 - - 200 VOS2 - - 300 VOS1 - - 400 VOS0 - - 480(6) VOS3 - - 200 VOS2 - - 150 VOS1 - - 200 VOS0 - - 240(6) VOS3 - - 100 VOS2 - - 150 VOS1 - - 200 VOS0 - - 240(6) VOS3 - - 100 VOS2 - - 150 VOS1 - - 200 VOS0 - - 240(6) VOS3 - - 50(8) VOS2 - - 75 VOS1 - - 100 VOS0 - - 120(6) Unit MHz 1. When RESET is released functionality is guaranteed down to VBOR0 min 2. Only for power-up sequence when the SMPS step-down converter is configured to supply the LDO and TJMax = 105 C. 3. This formula has to be applied on power supplies related to the IO structure described by the pin definition table. 4. For operation with voltage higher than Min (VDD, VDDA, VDD33USB) +0.3V, the internal Pull-up and Pull-Down resistors must be disabled. 5. VOS0 is available only when the LDO regulator is ON. 6. TJmax = 105 C. 7. At startup, the external VCORE voltage must remain higher or equal to 1.10 V before disabling the internal regulator (LDO). 8. Maximum APB clock frequency when at least one peripheral is enabled. Table 24. Supply voltage and maximum frequency configuration Power scale VOS0 VCORE source Max TJ (C) Max frequency (MHz) Min VDD (V) LDO 105 480 1.7 SMPS step-down converter(1) - - - DS12923 Rev 1 111/252 228 Electrical characteristics STM32H745xI/G Table 24. Supply voltage and maximum frequency configuration (continued) Power scale VCORE source Max TJ (C) Max frequency (MHz) Min VDD (V) SMPS step-down converter 125 400 1.62 LDO 125 SMPS step-down converter 125 300 1.62 64 1.2(2) 200 1.62 N/A 1.62 N/A 1.62 LDO VOS1 VOS2 LDO SVOS5 105 LDO 125 SMPS step-down converter 125 VOS3 SVOS4 140 (2) 140 (3) LDO 105 SMPS step-down converter 125 140(3) LDO 105 SMPS step-down converter 125 140(3) 1. VOS0 (power scale 0) is not available when the SMPS step-down converter directly supplies VCORE. 2. Only for power-up sequence when the SMPS step-down converter supplies the LDO. 3. Extended Industrial temperature range sales types (range 3). 6.3.2 VCAP external capacitor Stabilization for the main regulator is achieved by connecting an external capacitor CEXT to the VCAP pin. CEXT is specified in Table 25. Two external capacitors can be connected to VCAP pins. Figure 15. External capacitor CEXT C ESR R Leak MS19044V2 1. Legend: ESR is the equivalent series resistance. Table 25. VCAP operating conditions(1) 112/252 Symbol Parameter Conditions CEXT Capacitance of external capacitor 2.2 F(2) ESR ESR of external capacitor < 100 m DS12923 Rev 1 STM32H745xI/G Electrical characteristics 1. When bypassing the voltage regulator, the two 2.2 F VCAP capacitors are not required and should be replaced by two 100 nF decoupling capacitors. 2. This value corresponds to CEXT typical value. A variation of +/-20% is tolerated. 6.3.3 SMPS step-down converter The devices embed a high power efficiency SMPS step-down converter. SMPS characteristics for external usage are given in Table 27. The SMPS step-down converter requires external components that are specified in Figure 16 and Table 26. Figure 16. External components for SMPS step-down converter VDDSMPS VDDSMPS VVDD DD VLXSMPS VLXSMPS L Cin VSSSMPS VSSSMPS 2xCout VSSSMPS VSSSMPS VCAP VCAP VCAP VCAP VDDLDO VDDLDO Cout2 VSS VSS SMPS SMPS P (ON) (ON N) Cfilt VFBSMPS VFBSMPS VVDD_ DD_ External External Cout1 VLXSMPS VLXSMPS L Cin SMPS SMPS (ON) (ON) Cfilt VFBSMPS VFBSMPS VDDSMPS VDDSMPS VVDD DD VDDLDO VDDLDO VVCORE CORE VV reg reg (OFF) (OFF) CEXT VSS VSS VVCORE CORE VV reg reg (ON) (ON) External SMPS supply, LDO supplied by SMPS Direct SMPS supply MSv61398V2 Table 26. Characteristics of SMPS step-down converter external components Symbol Cin Parameter Capacitance of external capacitor on VDDSMPS Conditions 4.7 F ESR of external capacitor 100 m Capacitance of external capacitor on VLXSMPS pin 220 pF Capacitance of external capacitor on VFBSMPS pin 10 F ESR of external capacitor 20 m L Inductance of external Inductor on VLXSMPS pin 2.2 H - Serial DC resistor 150 m Cfilt COUT ISAT DC current at which the inductance drops 30% from its value without current. 1.7 A IRMS Average current for a 40 C rise: rated current for which the temperature of the inductor is raised 40C by DC current 1.4 A DS12923 Rev 1 113/252 228 Electrical characteristics STM32H745xI/G Table 27. SMPS step-down converter characteristics for external usage Parameters VDDSMPS(1) VOUT(2) IOUT Conditions Min Typ Max VOUT = 1.8 V 2.3 - 3.6 VOUT = 2.5 V 3 - 3.6 2.25 2.5 2.75 1.62 1.8 1.98 - - 600 - - 600 Iout=600 mA internal and external usage (3) External usage only Unit V V mA RDSON - - 100 120 m IDDSMPS_Q Quiescent current - 220 - A VOUT = 1.8 V - - 225 VOUT = 2.5 V - - 300 TSMPS_START s 1. The switching frequency is 2.4 MHz10% 2. Including line transient and load transient. 3. These characteristics are given for SDEXTHP bit is set in the PWR_CR3 register. 6.3.4 Operating conditions at power-up / power-down Subject to general operating conditions for TA. Table 28. Operating conditions at power-up / power-down (regulator ON) Symbol tVDD tVDDA tVDDUSB 114/252 Parameter Min Max VDD rise time rate 0 VDD fall time rate 10 VDDA rise time rate 0 VDDA fall time rate 10 VDDUSB rise time rate 0 VDDUSB fall time rate 10 DS12923 Rev 1 Unit s/V STM32H745xI/G 6.3.5 Electrical characteristics Embedded reset and power control block characteristics The parameters given in Table 29 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 23: General operating conditions. Table 29. Reset and power control block characteristics Symbol Parameter Conditions Min Typ Max Unit tRSTTEMPO(1) Reset temporization after BOR0 released - - 377 - s VBOR0 Brown-out reset threshold 0 Rising edge(1) 1.62 1.67 1.71 Falling edge 1.58 1.62 1.68 VBOR1 Brown-out reset threshold 1 2.04 2.10 2.15 1.95 2.00 2.06 VBOR2 Brown-out reset threshold 2 2.34 2.41 2.47 2.25 2.31 2.37 VBOR3 Brown-out reset threshold 3 2.63 2.70 2.78 2.54 2.61 2.68 VPVD0 Programmable Voltage Detector threshold 0 Rising edge 1.90 1.96 2.01 1.81 1.86 1.91 VPVD1 Programmable Voltage Detector threshold 1 Rising edge 2.05 2.10 2.16 1.96 2.01 2.06 VPVD2 Programmable Voltage Detector threshold 2 Rising edge 2.19 2.26 2.32 2.10 2.15 2.21 VPVD3 Programmable Voltage Detector threshold 3 Rising edge 2.35 2.41 2.47 2.25 2.31 2.37 VPVD4 Programmable Voltage Detector threshold 4 Rising edge 2.49 2.56 2.62 2.39 2.45 2.51 VPVD5 Programmable Voltage Detector threshold 5 Rising edge 2.64 2.71 2.78 2.55 2.61 2.68 VPVD6 Programmable Voltage Detector threshold 6 Rising edge 2.78 2.86 2.94 2.69 2.76 2.83 Vhyst_BOR_PVD Hysteresis voltage of BOR (unless BOR0) and PVD Hysteresis in Run mode - 100 - mV IDD_BOR_PVD(1) BOR(2) (unless BOR0) and PVD consumption from VDD - - 0.630 A Rising edge Falling edge Rising edge Falling edge Rising edge Falling edge Falling edge Falling edge Falling edge Falling edge Falling edge Falling edge Falling edge in Run mode DS12923 Rev 1 V 115/252 228 Electrical characteristics STM32H745xI/G Table 29. Reset and power control block characteristics (continued) Symbol Parameter Conditions Min Typ Max VAVM_0 Analog voltage detector for VDDA threshold 0 Rising edge 1.66 1.71 1.76 1.56 1.61 1.66 VAVM_1 Analog voltage detector for VDDA threshold 1 Rising edge 2.06 2.12 2.19 1.96 2.02 2.08 VAVM_2 Analog voltage detector for VDDA threshold 2 Rising edge 2.42 2.50 2.58 2.35 2.42 2.49 VAVM_3 Analog voltage detector for VDDA threshold 3 Rising edge 2.74 2.83 2.91 2.64 2.72 2.80 Vhyst_VDDA Hysteresis of VDDA voltage detector - - 100 - mV IDD_PVM PVM consumption from VDD(1) - - - 0.25 A IDD_VDDA Voltage detector consumption on VDDA(1) - - 2.5 A Falling edge Falling edge Falling edge Falling edge Resistor bridge Unit V 1. Guaranteed by design. 2. BOR0 is enabled in all modes and its consumption is therefore included in the supply current characteristics tables (refer to Section 6.3.7: Supply current characteristics). 6.3.6 Embedded reference voltage The parameters given in Table 30 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 23: General operating conditions. Table 30. Embedded reference voltage Symbol VREFINT tS_vrefint(1)(2) tS_vbat(1)(2) Irefbuf(2) VREFINT(2) Tcoeff(2) VDDcoeff(2) 116/252 Parameter Conditions Min Typ Max Unit -40C < TJ < 140 C, VDD = 3.3 V 1.180 1.216 1.255 V ADC sampling time when reading the internal reference voltage - 4.3 - - VBAT sampling time when reading the internal VBAT reference voltage - 9 - - VDDA=3.3 V 9 13.5 23 A Internal reference voltage spread over the temperature range -40C < TJ < 140 C - 5 15 mV Average temperature coefficient Average temperature coefficient - 20 70 ppm/C 3.0V < VDD < 3.6V - 10 1370 ppm/V Internal reference voltages Reference Buffer consumption for ADC Average Voltage coefficient s DS12923 Rev 1 STM32H745xI/G Electrical characteristics Table 30. Embedded reference voltage (continued) Symbol Parameter Conditions Min Typ Max VREFINT_DIV1 1/4 reference voltage - - 25 - VREFINT_DIV2 1/2 reference voltage - - 50 - VREFINT_DIV3 3/4 reference voltage - - 75 - 1. The shortest sampling time for the application can be determined by multiple iterations. 2. Guaranteed by design. Unit % VREFINT Table 31. Internal reference voltage calibration values Symbol Parameter Raw data acquired at temperature of 30 C, VDDA = 3.3 V VREFIN_CAL 6.3.7 Memory address 1FF1E860 - 1FF1E861 Supply current characteristics The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code. The current consumption is measured as described in Figure 14: Current consumption measurement scheme. All the run-mode current consumption measurements given in this section are performed with a CoreMark code. Typical and maximum current consumption The MCU is placed under the following conditions: * All I/O pins are in analog input mode. * All peripherals are disabled except when explicitly mentioned. * The Flash memory access time is adjusted with the minimum wait states number, depending on the fACLK frequency (refer to the table "Number of wait states according to CPU clock (frcc_c_ck) frequency and VCORE range" available in the reference manual). * When the peripherals are enabled, the AHB clock frequency is the CPU1 frequency divided by 2 and the APB clock frequency is AHB clock frequency divided by 2. The parameters given in the below tables are derived from tests performed under ambient temperature and supply voltage conditions summarized in Table 23: General operating conditions. DS12923 Rev 1 117/252 228 Electrical characteristics STM32H745xI/G Table 32. Typical and maximum current consumption in Run mode, code with data processing running from ITCM for Cortex-M7 core, and Flash memory for Cortex-M4 (ART accelerator ON), LDO regulator ON(1)(2) Symbol Parameter Conditions VOS0 IDD Arm Arm Cortex- CortexM4 M7 fCPU2 fCPU1 (MHz) (MHz) Max(3) Typ Tj= Tj= Tj= Tj= Tj= 25 C 85 C 105C 125C 140C 480 240 179 272 387 498 All peripherals VOS1 disabled VOS2 400 200 151 - - - 400 200 132 181 292 382 502 300 150 91 122 211 281 377 VOS3 200 100 56 79 150 206 284 480 240 247 374 462 571 Supply current in Run mode VOS0 All peripherals VOS1 enabled VOS2 400 200 208 - - - 400 200 181 232 337 422 541 300 150 126 163 248 318 414 VOS3 200 100 78 104 173 229 307 382 Unit mA 406 1. Data are in DTCM for best computation performance, the cache has no influence on consumption in this case. 2. The grayed cells correspond to the forbidden configurations. 3. Guaranteed by characterization results, unless otherwise specified. Table 33. Typical and maximum current consumption in Run mode, code with data processing running from ITCM for Arm Cortex-M7 and Flash memory for Arm Cortex-M4, ART accelerator ON, SMPS regulator(1) Symbol Parameter IDD Supply current in Run mode Conditions All peripherals disabled All peripherals enabled Arm Max Arm Cortex- CortexM4 Typ Unit M7 Tj= Tj= Tj= Tj= Tj= fCPU2 fCPU1 25 C 85 C 105C 125C 140C (MHz) (MHz) VOS1 400 200 58.3 79.0 129.0 175.1 236.0 - VOS2 300 150 37.0 50.2 84.7 115.6 161.1 218.4 VOS3 200 100 21.5 29.9 56.1 77.1 107.6 152.3 VOS1 400 200 78.1 100.1 148.9 193.4 254.3 - VOS2 300 150 51.2 65.5 100.8 130.9 176.9 235.5 VOS3 200 100 29.5 39.4 63.9 86.7 116.3 161.9 mA 1. The parameters given in the above table for the SMPS regulator are derived by extrapolation from the LDO consumption and typical SMPS efficiency factors . 118/252 DS12923 Rev 1 STM32H745xI/G Electrical characteristics Table 34. Typical and maximum current consumption in Run mode, code with data processing running from Flash memory, both cores running, cache ON, ART accelerator ON, LDO regulator ON(1) Symbol Parameter Conditions VOS0 IDD Arm Arm Cortex CortexM4 -M7 fCPU2 fCPU1 (MHz) (MHz) Max(2) Typ Tj= Tj= Tj= Tj= Tj= 25 C 85 C 105C 125C 140C 480 240 173 268 385 496 All peripherals VOS1 disabled VOS2 400 200 147 - - - 400 200 128 175 288 379 499 300 150 88 120 209 279 374 VOS3 200 100 55 77 149 205 283 VOS0 480 240 242 368 459 569 All VOS1 peripherals enabled VOS2 400 200 178 (3) 334 419(3) 537 300 150 123 161 246 316 412 VOS3 200 100 77 102 172 228 306 Supply current in Run mode 229 381 Unit mA 405 1. The grayed cells correspond to the forbidden configurations. 2. Guaranteed by characterization results, unless otherwise specified. 3. Guaranteed by tests in production. Table 35. Typical and maximum current consumption in Run mode, code with data processing running from Flash memory, both cores running, cache OFF, ART accelerator OFF, LDO regulator ON(1) Symbol Parameter IDD Supply current in Run mode Conditions Arm Arm Cortex Cortex -M4 -M7 fCPU1 fCPU2 (MHz) (MHz) Max(2) Typ Tj= Tj= Tj= Tj= Tj= 25 C 85 C 105C 125C 140C VOS0 480 240 109 191 330 444 All VOS1 peripherals VOS2 disabled 400 200 96 149 256 347 468 300 150 67 95 187 257 354 VOS3 200 100 43 62 136 192 270 VOS0 480 240 178 291 403 517 All VOS1 peripherals VOS2 enabled 400 200 147 224 310 401 523 300 150 103 136 224 295 392 VOS3 200 100 64 87 159 215 293 368 Unit mA 392 1. The grayed cells correspond to the forbidden configurations. 2. Guaranteed by characterization results, unless otherwise specified. DS12923 Rev 1 119/252 228 Electrical characteristics STM32H745xI/G Table 36. Typical and maximum current consumption in Run mode, code with data processing running from ITCM, only Arm Cortex-M7 running, LDO regulator ON(1)(2) Max(3) Symbol Parameter Conditions VOS0 VOS1 All peripherals disabled IDD Supply current in Run mode VOS2 VOS3 VOS0 All VOS1 peripherals enabled VOS2 VOS3 fCPU1 (MHz) Typ 480 Tj=25 C Tj=85 C Tj=105 Tj=125 Tj=140 C C C 148 226 307 390 400 125 - - - 400 110 168 230 296 384 300 84 - - - - 300 76 114 170 224 297 216 56 88 152 205 278 200 53 - - - - 200 47 71 121 164 223 295 180 43 64 116 159 218 291 168 40 63 115 158 217 290 144 35 55 109 153 212 284 60 16 36 92 135 194 267 25 12 24 83 126 185 257 480 226 222 439 550 400 190 - - - 400 167 222 327 416 536 300 135 - - - - 300 122 160 248 320 419 200 85 - - - - 200 76 103 174 233 313 413 1. Data are in DTCM for best computation performance, the cache has no influence on consumption in this case. 2. The grayed cells correspond to the forbidden configurations. 3. Guaranteed by characterization results, unless otherwise specified. 120/252 DS12923 Rev 1 Unit mA STM32H745xI/G Electrical characteristics Table 37. Typical and maximum current consumption in Run mode, code with data processing running from ITCM, only Arm Cortex-M7 running, SMPS regulator(1)(2) Max Symbol IDD Parameter Supply current in Run mode fCPU1 (MHz) Typ VOS1 All peripherals VOS2 disabled VOS3 400 VOS1 Conditions All peripherals VOS2 enabled VOS3 Tj=25 C Tj=85 C Tj=105 C Tj=125 C 48.6 73.3 100.4 132.4 176.0 300 31.3 46.3 68.3 90.0 122.2 164.5 200 18.0 26.9 45.3 60.6 82.4 111.7 400 72.9 95.8 144.5 190.7 252.0 300 49.6 64.3 99.6 131.7 179.1 238.2 200 28.8 38.5 64.3 88.3 118.6 164.7 Unit Tj=140 C mA 1. The parameters given in the above table for the SMPS regulator are derived by extrapolation from the LDO consumption and typical SMPS efficiency factors . 2. The grayed cells correspond to the forbidden configurations. Table 38. Typical and maximum current consumption in Run mode, code with data processing running from Flash memory, only Arm Cortex-M7 running, cache ON, LDO regulator ON(1) Max(2) Symbol Parameter Conditions VOS0 All peripherals disabled VOS1 VOS2 IDD Supply current in Run mode VOS3 VOS0 All peripherals enabled VOS1 VOS2 VOS3 fCPU1 (MHz) Typ 480 110 222 304 388 400 91 - - - 400 80 162 228 294 381 300 61.5 - - - - 300 55 111 168 222 294 200 38.5 - - - - 200 34.5 69 120 163 222 480 220 342 436 546 400 195 - - - 400 175 264 336 424 544 300 135 - - - - 300 120 180 246 318 418 200 83 - - - - 200 75 114 173 232 312 Tj=25 Tj=85 Tj=105 Tj=125 Tj=140 C C C C C 294 Unit mA 412 1. The grayed cells correspond to the forbidden configurations. 2. Guaranteed by characterization results, unless otherwise specified. DS12923 Rev 1 121/252 228 Electrical characteristics STM32H745xI/G Table 39. Typical and maximum current consumption in Run mode, code with data processing running from Flash memory, only Arm Cortex-M7 running, cache OFF, LDO regulator ON(1) Max(2) Symbol Parameter Typ VOS0 480 VOS1 Conditions All peripherals disabled IDD fCPU1 (MHz) Supply current in Run mode All peripherals enabled Tj=25 C Tj=85 C Tj=105 Tj=125 Tj=140 C C C 87 157 259 342 400 73 123 201 267 355 VOS2 300 52 85 150 204 277 VOS3 200 34 54 109 152 212 VOS0 480 168 276 390 504 VOS1 400 135 224 308 397 519 VOS2 300 100 154 228 301 401 VOS3 200 70 103 167 226 307 284 Unit mA 407 1. The grayed cells correspond to the forbidden configurations. 2. Guaranteed by characterization results, unless otherwise specified. Table 40. Typical and maximum current consumption batch acquisition mode, LDO regulator ON Max(1) Symbol Parameter IDD Supply current in batch acquisition mode Conditions D1 Standby, D2 Standby, D3 Run VOS3 D1 Stop, D2 Stop, D3 Run VOS3 fHCLK (MHz) Typ 64 8 Tj=25 C Tj=85 C 2.7 4.7 12.9 19.0 27.5 37.8 1.1 - - - - - Unit mA 64 5.4 18.4 83.7 132.6 202.4 289.3 8 3.8 - - - - - 1. Guaranteed by characterization results, unless otherwise specified. 122/252 Tj=105 Tj=125 Tj=140 C C C DS12923 Rev 1 STM32H745xI/G Electrical characteristics Table 41. Typical and maximum current consumption in Run mode, code with data processing running from Flash memory, only Arm Cortex-M4 running, ART accelerator ON, LDO regulator ON(1) Max(2) Symbol Parameter Conditions IDD Supply current in Run mode 240 Tj=85 C Tj=105 C 121 203 339 453 200 90 - - - 200 79 123 234 323 444 150 61 - - - - VOS2 150 56 85 178 250 350 VOS3 100 35 59 131 189 269 240 190 303 412 525 200 146 - - - VOS1 200 129 195 287 376 499 VOS2 150 90 134 214 287 386 VOS3 100 61 100 158 216 297 VOS1 VOS0 All peripherals enabled Typ Tj=25 C VOS0 All peripherals disabled fCPU2 (MHz) Tj=125 Tj=140 C C Unit 369 mA 398 1. The grayed cells correspond to the forbidden configurations. 2. Guaranteed by characterization results, unless otherwise specified. Table 42. Typical and maximum current consumption in Run mode, code with data processing running from Flash bank 2, only Arm Cortex-M4 running, ART accelerator ON, SMPS regulator(1)(2) Max Symbol IDD Parameter Supply current in Run mode Conditions All peripherals disabled All peripherals enabled Typ Tj=25 C Tj=85 C Tj=105 C Tj=125 C Tj=140 C VOS1 35.3 54.3 102.1 144.4 203.5 VOS2 23.3 35.0 70.6 99.2 145.8 207.0 VOS3 13.6 22.3 49.0 69.8 101.9 147.1 VOS1 57.0 84.1 126.8 172.3 234.6 VOS2 36.6 54.5 84.9 118.1 165.0 223.7 VOS3 23.1 37.4 58.4 79.8 112.5 158.7 Unit mA 1. The parameters given in the above table for the SMPS regulator are derived by extrapolation from the LDO consumption and typical SMPS efficiency factors . 2. The grayed cells correspond to the forbidden configurations. DS12923 Rev 1 123/252 228 Electrical characteristics STM32H745xI/G Table 43. Typical and maximum current consumption in Stop, LDO regulator ON(1)(2) Max(3) Symbol Parameter Conditions Typ Tj=25C Tj=85C D1 Stop, D2 Stop, D3 Stop D1 Stop, IDD (Stop) D2 Standby, D3 Stop SVOS5 Flash memory SVOS4 OFF, no IWDG SVOS3 SVOS5 Flash memory SVOS4 ON, no IWDG SVOS3 SVOS5 Flash memory SVOS4 OFF, no IWDG SVOS3 SVOS5 Flash memory SVOS4 ON, no IWDG SVOS3 SVOS5 Flash D1 Standby, memory D2 Stop, SVOS4 OFF, no D3 Stop IWDG SVOS3 SVOS5 Flash D1 Standby, memory D2 Standby, SVOS4 OFF, no D3 Stop IWDG SVOS3 Tj=105 C 1.27 6.3 42.5 72.0 1.96 9.4 57.4 94.6 2.78 13.8 75.9 121.3(4) 1.27 6.3 42.5 72.0 2.25 9.8 57.9 95.2 3.07 14.1 76.4 122.0 0.91 4.6 30.4 51.2 1.42 6.8 41.1 67.3 2.02 10.0 54.4 86.6 0.91 4.6 30.4 51.2 1.70 7.2 41.5 67.9 2.31 10.3 54.9 87.1 0.49 2.4 16.5 28.0 0.76 3.6 22.2 36.6 1.10 5.3 29.3 46.9 4.3 7.3(4) 0.15 (4) 0.7 (4) 0.22 1.0 5.8 9.6 0.35 1.5(4) 7.8 12.3(4) Tj=125 C Tj=140 C 183.8 264.9 184.8 266.5 130.0 186.1 130.8 187.2 71.2 102.2 18.6 26.6 Unit mA 1. The parameters given in the above table for the SMPS regulator are derived by extrapolation from the LDO consumption and typical SMPS efficiency factors . 2. The grayed cells correspond to the forbidden configurations. 3. Guaranteed by characterization results, unless otherwise specified. 4. Guaranteed by tests in production. 124/252 DS12923 Rev 1 STM32H745xI/G Electrical characteristics Table 44. Typical and maximum current consumption in Stop, SMPS regulator(1) Max Symbol Parameter Conditions Typ Tj=25C Tj=85C D1 Stop, D2 Stop, D3 Stop IDD (Stop) D1 Stop, D2 Standby, D3 Stop Flash OFF, no IWDG Flash ON, no IWDG Flash OFF, no IWDG Flash ON, no IWDG D1 Standby, D2 Stop, D3 Stop Flash OFF, no IWDG D1 Standby, D2 Standby, D3 Stop Flash ON, no IWDG Tj=105 C Tj=125 C Tj=140 C SVOS5 0.36 1.73 11.91 21.53 - - SVOS4 0.63 3.05 19.57 33.51 - - SVOS3 1.00 4.98 29.11 47.13 68.76 100.34 SVOS5 0.36 1.73 11.91 21.53 - - SVOS4 0.73 3.18 19.74 33.72 - - SVOS3 1.11 5.09 29.31 47.40 69.14 100.95 SVOS5 0.25 1.24 8.21 14.00 - - SVOS4 0.46 2.21 14.01 22.94 - - SVOS3 0.73 3.57 19.62 32.80 49.24 68.77 SVOS5 0.25 1.24 8.21 14.00 - - SVOS4 0.55 2.34 14.15 23.15 - - SVOS3 0.83 3.67 19.81 32.99 49.55 69.18 SVOS5 0.15 0.67 4.51 7.85 - - SVOS4 0.26 1.17 7.21 12.32 - - SVOS3 0.40 1.90 10.57 17.12 26.97 39.20 SVOS5 0.06 0.20 1.18 2.05 - - SVOS4 0.08 0.33 1.90 3.11 - - SVOS3 0.13 0.54 2.80 4.47 6.77 9.58 Unit mA 1. The parameters given in the above table for the SMPS regulator are derived by extrapolation from the LDO consumption and typical SMPS efficiency factors . DS12923 Rev 1 125/252 228 Electrical characteristics STM32H745xI/G Table 45. Typical and maximum current consumption in Sleep mode, LDO regulator ON(1)(2) Max(3) Symbol Parameter Conditions VOS0 All peripherals disabled VOS1 VOS2 IDD (Sleep) Supply current in Sleep mode VOS3 VOS0 All peripherals enabled VOS1 VOS2 VOS3 fHCLK (MHz) Typ 480 50.7 96.3 253.4 366.1 400 43.4 87.8 245.5 357.9 400 35.3 66.5 181.3 265.8 379.6 300 27.9 - - - - 300 24.6 47.3 139.1 207.3 300.4 200 18.8 - - - - 200 16.5 33.6 106.4 160.9 236.1 480 136.0 194.7 348.5 464.4 400 115.0 169.0 325.9 441.7 400 97.7 138.2 251.3 338.4 456.4 300 74.9 - - - - 300 67.3 95.8 187.6 257.9 354.1 200 52.8 - - - - 200 47.1 69.3 141.4 197.7 275.1 Tj=25 Tj=85 Tj=105 Tj=125 Tj=140 C C C C C 330.3 Unit mA 372.8 1. The parameters given in the above table for the SMPS regulator are derived by extrapolation from the LDO consumption and typical SMPS efficiency factors . 2. The grayed cells correspond to the forbidden configurations. 3. Guaranteed by characterization results, unless otherwise specified. Table 46. Typical and maximum current consumption in Sleep mode, SMPS regulator(1)(2)(3) Max Symbol Parameter Conditions IDD (Sleep) Supply current in Sleep mode All peripherals Enabled Typ 400 Tj=25 C Tj=85 C Tj=105 C Tj=125 C 15.93 29.69 79.01 118.72 173.80 300 12.58 - - - - 300 10.21 19.63 56.46 82.14 123.46 177.95 200 7.89 - - - - - VOS3 200 6.50 12.98 39.73 59.35 87.10 125.00 VOS1 400 42.65 59.62 110.88 153.00 211.65 - VOS2 300 27.70 38.94 75.26 102.22 147.38 208.16 VOS3 200 17.95 26.14 52.75 72.95 104.09 148.48 VOS1 All peripherals disabled fHCLK (MHz) VOS2 Tj=140 C 1. The parameters given in the above table for the SMPS regulator are derived by extrapolation from the LDO consumption and typical SMPS efficiency factors . 126/252 DS12923 Rev 1 Unit mA STM32H745xI/G Electrical characteristics 2. The parameters given in the above table for the SMPS regulator are derived by extrapolation from the LDO consumption and typical SMPS efficiency factors . 3. The grayed cells correspond to the forbidden configurations. Table 47. Typical and maximum current consumption in Standby Max(1) Typ Conditions 3V Symbol Parameter 3V 3.3 V OFF OFF 1,92 1,95 2,06 2,16 4 18 40 90 140 ON OFF 3,33 3,44 3,6 3,79 8.2 47 83 141 230 OFF ON 2,43 2,57 2,77 2,95 - - - - - ON ON 3,82 4,05 4,31 4,55 - - - - - Backup SRAM IDD (Standby) Supply current in Standby mode Unit RTC 1.62 V 2.4 V and LSE Tj=25 Tj=85 Tj=105 Tj=125 Tj=140 C C C C C A 1. Guaranteed by characterization results, unless otherwise specified. Table 48. Typical and maximum current consumption in VBAT mode Conditions Symbol IDD (VBAT) Parameter Supply current in VBAT mode Max(1) Typ 3V Backup SRAM RTC and LSE 1.2 V 2V 3V 3.4 V OFF OFF 0,02 0,02 0,03 0,05 0,5 4,1 10 24 47 ON OFF 1,33 1,45 1,58 1,7 4,4 22 48 87 132 OFF ON 0,46 0,57 0,75 0,87 - - - - - ON ON 1,77 2 2,3 2,5 - - - - - Unit Tj=25 Tj=85 Tj=105 Tj=125 Tj=140 C C C C C A 1. Guaranteed by characterization results, unless otherwise specified. DS12923 Rev 1 127/252 228 Electrical characteristics STM32H745xI/G Typical SMPS efficiency versus load current and temperature Figure 17. Typical SMPS efficiency (%) vs load current (A) in Run mode at TJ = 30 C 100 90 80 70 VDDSMPS = 1.8V, VOS1 VDDSMPS = 3.3V, VOS1 VDDSMPS = 1.8V, VOS2 VDDSMPS = 3.3V, VOS2 VDDSMPS = 1.8V, VOS3 VDDSMPS = 3.3V, VOS3 60 50 40 30 20 10 0 0.001 0.01 0.1 1 MSv62424V1 Figure 18. Typical SMPS efficiency (%) vs load current (A) in Run mode at TJ = TJmax 100 90 80 70 VDDSMPS = 1.8V, VOS1 VDDSMPS = 3.3V, VOS1 VDDSMPS = 1.8V, VOS2 VDDSMPS = 3.3V, VOS2 VDDSMPS = 1.8V, VOS3 VDDSMPS = 3.3V, VOS3 60 50 40 30 20 10 0 0.001 0.01 0.1 1 MSv62425V1 128/252 DS12923 Rev 1 STM32H745xI/G Electrical characteristics Figure 19. Typical SMPS efficiency (%) vs load current (A) in low-power mode at TJ = 30 C 100 90 80 70 VDDSMPS = 1.8V, SVOS5 VDDSMPS = 3.3V, SVOS5 VDDSMPS = 1.8V, SVOS4 VDDSMPS = 3.3V, SVOS4 VDDSMPS = 1.8V, SVOS3 VDDSMPS = 3.3V, SVOS3 60 50 40 30 20 10 0 0.00001 0.0001 0.001 0.01 0.1 MSv62426V1 DS12923 Rev 1 129/252 228 Electrical characteristics STM32H745xI/G Figure 20. Typical SMPS efficiency (%) vs load current (A) in low-power mode at TJ = TJmax 100 90 80 70 VDDSMPS = 1.8V, SVOS5 VDDSMPS = 3.3V, SVOS5 VDDSMPS = 1.8V, SVOS4 VDDSMPS = 3.3V, SVOS4 VDDSMPS = 1.8V, SVOS3 VDDSMPS = 3.3V, SVOS3 60 50 40 30 20 10 0 0.00001 0.0001 0.001 0.01 0.1 MSv62427V1 I/O system current consumption The current consumption of the I/O system has two components: static and dynamic. I/O static current consumption All the I/Os used as inputs with pull-up generate a current consumption when the pin is externally held low. The value of this current consumption can be simply computed by using the pull-up/pull-down resistors values given in Table 69: I/O static characteristics. For the output pins, any external pull-down or external load must also be considered to estimate the current consumption. An additional I/O current consumption is due to I/Os configured as inputs if an intermediate voltage level is externally applied. This current consumption is caused by the input Schmitt trigger circuits used to discriminate the input value. Unless this specific configuration is required by the application, this supply current consumption can be avoided by configuring these I/Os in analog mode. This is notably the case of ADC input pins which should be configured as analog inputs. Caution: 130/252 Any floating input pin can also settle to an intermediate voltage level or switch inadvertently, as a result of external electromagnetic noise. To avoid a current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. This can be done either by using pull-up/down resistors or by configuring the pins in output mode. DS12923 Rev 1 STM32H745xI/G Electrical characteristics I/O dynamic current consumption In addition to the internal peripheral current consumption (see Table 49: Peripheral current consumption in Run mode), the I/Os used by an application also contribute to the current consumption. When an I/O pin switches, it uses the current from the MCU supply voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load (internal or external) connected to the pin: I SW = V DDx x f SW x C L where ISW is the current sunk by a switching I/O to charge/discharge the capacitive load VDDx is the MCU supply voltage fSW is the I/O switching frequency CL is the total capacitance seen by the I/O pin: C = CINT+ CEXT The test pin is configured in push-pull output mode and is toggled by software at a fixed frequency. On-chip peripheral current consumption The MCU is placed under the following conditions: * At startup, all I/O pins are in analog input configuration. * All peripherals are disabled unless otherwise mentioned. * The I/O compensation cell is enabled. * frcc_c_ck is the CPU clock. fPCLK = frcc_c_ck/4, and fHCLK = frcc_c_ck/2. The given value is calculated by measuring the difference of current consumption * - with all peripherals clocked off - with only one peripheral clocked on - frcc_c_ck = 480 MHz (Scale 0), frcc_c_ck = 400 MHz (Scale 1), frcc_c_ck = 300 MHz (Scale 2), frcc_c_ck = 200 MHz (Scale 3) The ambient operating temperature is 25 C and VDD=3.3 V. DS12923 Rev 1 131/252 228 Electrical characteristics STM32H745xI/G Table 49. Peripheral current consumption in Run mode Bus AHB3 AHB1 132/252 Peripheral VOS0 VOS1 VOS2 VOS3 MDMA 4.6 3.8 3.4 3.2 DMA2D 2.9 2.4 2.1 1.9 JPGDEC 4.1 3.7 3.4 3.1 FLASH 17.0 15.0 14.0 12.0 FMC registers 0.9 1.1 0.9 0.8 FMC kernel 7.0 6.1 5.6 5.0 QUADSPI registers 1.5 1.5 1.4 1.3 QSPI kernel 1.0 0.9 0.8 0.7 SDMMC1 registers 8.2 7.2 6.7 6.0 SDMMC1 kernel 1.3 1.2 0.9 0.9 DTCM1 7.9 6.8 6.0 5.3 DTCM2 8.3 7.2 6.4 5.7 ITCM 7.0 6.3 5.6 5.1 D1SRAM1 13.0 11.0 9.9 8.7 AHB3 bridge 35.0 32.0 29.0 26.0 Total AHB3 120 106 96 86 DMA1 54.0 48.0 41.0 37.0 DMA2 55.0 49.0 42.0 37.0 ADC12 registers 4.5 4.1 3.7 3.3 ADC12 kernel 1.0 0.7 0.4 0.6 ART accelerator 4.1 3.7 3.2 2.9 ETH1MAC 17.0 15.0 14.0 12.0 ETH1TX 0.1 0.1 0.1 0.1 ETH1RX 0.1 0.1 0.1 0.1 USB1 OTG registers 23.0 21.0 19.0 17.0 USB1 OTG kernel 8.2 0.5 8.3 8.2 USB1 ULPI 0.1 0.1 0.1 0.1 USB2 OTG registers 21.0 19.0 17.0 15.0 USB2 OTG kernel 8.5 0.4 8.6 8.3 USB2 ULPI 23.0 19.0 20.0 19.0 AHB1 bridge 0.1 0.1 0.1 0.1 Total AHB1 220 181 178 161 DS12923 Rev 1 Unit A/MHz STM32H745xI/G Electrical characteristics Table 49. Peripheral current consumption in Run mode (continued) Bus AHB2 AHB4 APB3 Peripheral VOS0 VOS1 VOS2 VOS3 DCMI 2.1 1.9 1.8 1.6 RNG registers 1.7 2.0 1.3 1.2 RNG kernel 11.0 0.1 9.7 9.4 SDMMC2 registers 47.0 41.0 37.0 34.0 SDMMC2 kernel 1.7 1.2 1.1 1.0 D2SRAM1 5.7 4.9 4.4 3.9 D2SRAM2 5.2 4.5 4.0 3.5 D2SRAM3 4.1 3.6 3.2 2.8 AHB2 bridge 0.1 0.1 0.1 0.1 Total AHB2 79 60 63 58 GPIOA 1.5 1.3 1.3 1.1 GPIOB 1.2 1.0 1.0 0.9 GPIOC 0.8 0.7 0.7 0.6 GPIOD 1.1 1.0 1.0 0.9 GPIOE 0.7 0.7 0.7 0.6 GPIOF 0.8 0.8 0.7 0.6 GPIOG 0.9 0.8 0.8 0.7 GPIOH 1.1 1.0 1.0 0.9 GPIOI 0.9 0.9 0.8 0.7 GPIOJ 0.8 0.8 0.7 0.7 GPIOK 0.7 0.8 0.7 0.6 CRC 0.4 0.5 0.4 0.3 BDMA 6.6 5.9 5.3 4.8 ADC3 registers 1.7 1.5 1.2 1.2 ADC3 kernel 0.4 0.3 0.5 0.2 BKPRAM 2.3 1.9 1.7 1.5 AHB4 bridge 0.1 0.1 0.1 0.1 Total AHB4 22 20 19 16 WWDG1 0.7 0.5 0.5 0.2 LCD-TFT 81.0 36.0 33.0 30.0 APB3 bridge 0.3 0.2 0.1 0.1 Total APB3 87 41 38 34 DS12923 Rev 1 Unit A/MHz A/MHz 133/252 228 Electrical characteristics STM32H745xI/G Table 49. Peripheral current consumption in Run mode (continued) Bus APB1 134/252 Peripheral VOS0 VOS1 VOS2 VOS3 TIM2 7.7 3.6 3.3 3.0 TIM3 6.7 3.2 3.0 2.7 TIM4 6.3 3.1 2.8 2.5 TIM5 7.4 3.5 3.2 2.8 TIM6 1.4 0.7 0.8 0.6 TIM7 1.4 0.7 0.7 0.6 TIM12 3.2 1.5 1.5 1.3 TIM13 2.3 1.1 1.1 0.9 TIM14 2.1 1.1 1.1 0.9 LPTIM1 registers 0.7 0.5 0.8 0.7 LPTIM1 kernel 2.4 2.3 1.9 1.7 WWDG2 0.6 0.5 0.5 0.4 SPI2 registers 2.0 1.8 1.7 1.4 SPI2 kernel 0.8 0.6 0.5 0.6 SPI3 registers 1.8 1.6 1.6 1.3 SPI3 kernel 0.7 0.9 0.7 0.7 SPDIFRX1 registers 0.5 0.7 0.7 0.6 SPDIFRX1 kernel 3.5 2.8 2.4 2.2 USART2 registers 1.9 1.7 1.4 1.3 USART2 kernel 4.3 3.9 3.6 3.2 USART3 registers 1.9 1.7 1.4 1.3 USART3 kernel 4.4 3.9 3.5 3.2 UART4 registers 1.7 1.5 1.4 1.4 UART4 kernel 3.9 3.4 3.1 2.8 UART5 registers 1.6 1.4 1.4 1.3 UART5 kernel 3.8 3.4 3.0 2.7 I2C1 registers 1.1 0.8 0.9 0.8 I2C1 kernel 2.5 2.3 2.0 1.9 I2C2 registers 1.0 0.8 0.9 0.8 DS12923 Rev 1 Unit A/MHz STM32H745xI/G Electrical characteristics Table 49. Peripheral current consumption in Run mode (continued) Bus APB1 (continued) APB2 Peripheral VOS0 VOS1 VOS2 VOS3 I2C2 kernel 2.3 2.2 1.9 1.7 I2C3 registers 0.8 1.0 0.8 0.8 I2C3 kernel 2.4 1.9 1.8 1.6 HDMI-CEC registers 0.7 0.5 0.6 0.5 HDMI-CEC kernel 0.1 0.1 3.2 0.1 DAC12 3.6 1.3 1.2 1.0 USART7 registers 1.8 1.8 1.6 1.4 USART7 kernel 4.0 3.3 3.0 2.8 USART8 registers 2.0 1.6 1.6 1.4 USART8 kernel 3.9 3.4 3.1 2.8 CRS 6.4 5.5 5.0 4.5 SWPMI registers 2.7 2.4 2.3 1.9 SWPMI kernel 0.1 0.1 0.1 0.1 OPAMP 0.2 0.3 0.3 0.2 MDIO 3.3 2.9 2.6 2.3 FDCAN registers 19.0 17.0 15.0 13.0 FDCAN kernel 9.1 7.9 6.9 6.4 APB1 bridge 0.1 0.1 0.1 0.1 Total APB1 142 108 102 88 TIM1 11.0 5.0 4.5 4.0 TIM8 10.0 4.7 4.3 3.8 USART1 registers 3.6 2.5 2.7 2.9 USART1 kernel 0.1 0.1 0.1 0.1 USART6 registers 4.5 3.0 3.1 3.4 USART6 kernel 0.1 0.1 0.1 0.1 SPI1 registers 2.0 1.7 1.6 1.4 SPI1 kernel 0.9 0.8 0.7 0.6 SPI4 registers 2.1 1.7 1.6 1.5 SPI4 kernel 0.6 0.5 0.5 0.3 TIM15 5.5 2.5 2.3 2.1 TIM16 4.1 2.0 1.8 1.7 TIM17 4.1 1.9 1.8 1.6 SPI5 registers 2.0 1.8 1.6 1.3 SPI5 kernel 0.5 0.4 0.4 0.5 SAI1 registers 1.3 1.1 1.1 1.0 DS12923 Rev 1 Unit A/MHz 135/252 228 Electrical characteristics STM32H745xI/G Table 49. Peripheral current consumption in Run mode (continued) Bus APB2 (continued) APB4 136/252 Peripheral VOS0 VOS1 VOS2 VOS3 SAI1 kernel 1.4 1.1 1.0 0.8 SAI2 registers 1.5 1.3 1.2 1.0 SAI2 kernel 1.1 1.0 0.9 0.9 SAI3 registers 1.6 1.3 1.1 1.0 SAI3 kernel 1.1 1.2 1.1 0.9 DFSDM1 registers 6.5 5.8 5.2 4.7 DFSDM1 kernel 0.3 0.2 0.2 0.4 HRTIM 84.0 39.0 35.0 32.0 APB2 bridge 0.2 0.1 0.1 0.2 Total APB2 150 81 74 68 SYSCFG 0.9 1.0 0.7 0.8 LPUART1 registers 1.1 1.3 1.0 0.8 LPUART1 kernel 2.9 2.2 2.2 2.1 SPI6 registers 1.8 1.6 1.4 1.3 SPI6 kernel 0.4 0.4 0.5 0.3 I2C4 registers 0.9 0.7 0.7 0.4 I2C4 kernel 2.2 2.1 1.9 1.8 LPTIM2 registers 0.8 0.6 0.7 0.5 LPTIM2 kernel 2.3 2.1 1.8 1.4 LPTIM3 registers 0.7 0.7 0.7 0.4 LPTIM3 kernel 2.1 1.7 1.6 1.5 LPTIM4 registers 0.8 0.4 0.6 0.4 LPTIM4 kernel 2.2 2.0 1.7 1.5 LPTIM5 registers 0.5 0.4 0.6 0.4 LPTIM5 kernel 2.0 1.8 1.5 1.2 COMP12 0.6 0.4 0.5 0.2 VREF 0.4 0.2 0.2 0.1 RTC 1.1 0.9 1.0 0.6 SAI4 registers 1.7 1.4 1.3 1.0 SAI4 kernel 2.0 2.0 1.8 1.6 APB4 bridge 0.1 0.1 0.1 0.1 Total APB4 28 24.4 22.4 18.9 DS12923 Rev 1 Unit A/MHz STM32H745xI/G 6.3.8 Electrical characteristics Wakeup time from low-power modes The wakeup times given in Table 50 are measured starting from the wakeup event trigger up to the first instruction executed by the CPU: * For Stop or Sleep modes: the wakeup event is WFE. * WKUP (PC1) pin is used to wakeup from Standby, Stop and Sleep modes. All timings are derived from tests performed under ambient temperature and VDD=3.3 V. Table 50. Low-power mode wakeup timings(1) Symbol Parameter Conditions Typ(2) Max(2) Unit tWUSLEEP(3) Wakeup from Sleep - 9 10 CPU clock cycles VOS3, HSI, Flash memory in normal mode 4.4 5.6 VOS3, HSI, Flash memory in low-power mode 12 15 VOS4, HSI, Flash memory in normal mode 15 20 VOS4, HSI, Flash memory in low-power mode 23 28 VOS5, HSI, Flash memory in normal mode 39 71 VOS5, HSI, Flash memory in low-power mode 39 47 VOS3, CSI, Flash memory in normal mode 30 37 VOS3, CSI, Flash memory in low power mode 36 50 VOS4, CSI, Flash memory in normal mode 38 48 VOS4, CSI, Flash memory in low-power mode 47 61 VOS5, CSI, Flash memory in normal mode 68 75 VOS5, CSI, Flash memory in low-power mode 68 77 VOS3, HSI, Flash memory in normal mode 2.6 3.4 VOS3, CSI, Flash memory in normal mode 26 36 - 390 500 tWUSTOP (3) tWUSTOP_ KERON (3) tWUSTDBY(3) Wakeup from Stop Wakeup from Stop, clock kept running Wakeup from Standby mode s 1. The wakeup timings is valid for both CPUs. 2. Guaranteed by characterization results. 3. The wakeup times are measured from the wakeup event to the point in which the application code reads the first instruction. DS12923 Rev 1 137/252 228 Electrical characteristics 6.3.9 STM32H745xI/G External clock source characteristics High-speed external user clock generated from an external source In bypass mode the HSE oscillator is switched off and the input pin is a standard I/O. The external clock signal has to respect the Table 69: I/O static characteristics. However, the recommended clock input waveform is shown in Figure 21. Table 51. High-speed external user clock characteristics(1) Symbol Parameter Min Typ Max Unit fHSE_ext User external clock source frequency 4 25 50 MHz 0.7VDD - VDD VSS - 0.3VSS 7 - - VSW OSC_IN amplitude (VHSEH - VHSEL) VDC OSC_IN input voltage tW(HSE) OSC_IN high or low time V ns 1. Guaranteed by design. Figure 21. High-speed external clock source AC timing diagram VHSEH 90 % 10 % VHSEL tr(HSE) tf(HSE) tW(HSE) t tW(HSE) THSE External clock source fHSE_ext OSC_IN IL STM32 ai17528b 138/252 DS12923 Rev 1 STM32H745xI/G Electrical characteristics Low-speed external user clock generated from an external source In bypass mode the LSE oscillator is switched off and the input pin is a standard I/O. The external clock signal has to respect the Table 69: I/O static characteristics. However, the recommended clock input waveform is shown in Figure 22. Table 52. Low-speed external user clock characteristics(1) Symbol Parameter Conditions Min Typ Max Unit kHz fLSE_ext User external clock source frequency - - 32.768 1000 VLSEH OSC32_IN input pin high level voltage - 0.7 VDDIOx - VDDIOx VLSEL OSC32_IN input pin low level voltage - VSS - 0.3 VDDIOx - 250 - - tw(LSEH) OSC32_IN high or low time tw(LSEL) V ns 1. Guaranteed by design. Note: For information on selecting the crystal, refer to the application note AN2867 "Oscillator design guide for ST microcontrollers" available from the ST website www.st.com. Figure 22. Low-speed external clock source AC timing diagram VLSEH 90% VLSEL 10% tr(LSE) tf(LSE) tW(LSE) OSC32_IN IL tW(LSE) t TLSE External clock source fLSE_ext STM32 ai17529b DS12923 Rev 1 139/252 228 Electrical characteristics STM32H745xI/G High-speed external clock generated from a crystal/ceramic resonator The high-speed external (HSE) clock can be supplied with a 4 to 48 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 53. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Table 53. 4-48 MHz HSE oscillator characteristics(1) Symbol Parameter Operating conditions(2) Min Typ Max Unit F Oscillator frequency - 4 - 48 MHz RF Feedback resistor - - 200 - k During startup(3) - - 4 VDD=3 V, Rm=30 CL=10pF@4MHz - 0.35 - VDD=3 V, Rm=30 CL=10 pF at 8 MHz - 0.40 - VDD=3 V, Rm=30 CL=10 pF at 16 MHz - 0.45 - VDD=3 V, Rm=30 CL=10 pF at 32 MHz - 0.65 - VDD=3 V, Rm=30 CL=10 pF at 48 MHz - 0.95 - IDD(HSE) HSE current consumption mA Gmcritmax Maximum critical crystal gm Startup - - 1.5 mA/V tSU(4) Start-up time VDD is stabilized - 2 - ms 1. Guaranteed by design. 2. Resonator characteristics given by the crystal/ceramic resonator manufacturer. 3. This consumption level occurs during the first 2/3 of the tSU(HSE) startup time. 4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer. For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the 5 pF to 25 pF range (typical), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see Figure 23). CL1 and CL2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. The PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing CL1 and CL2. Note: 140/252 For information on selecting the crystal, refer to the application note AN2867 "Oscillator design guide for ST microcontrollers" available from the ST website www.st.com. DS12923 Rev 1 STM32H745xI/G Electrical characteristics Figure 23. Typical application with an 8 MHz crystal Resonator with integrated capacitors CL1 8 MHz resonator CL2 fHSE OSC_IN REXT(1) RF Bias controlled gain OSC_OU T STM32 ai17530b 1. REXT value depends on the crystal characteristics. Low-speed external clock generated from a crystal/ceramic resonator The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 54. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Table 54. Low-speed external user clock characteristics(1) Symbol Parameter Operating conditions(2) Min Typ Max Unit F Oscillator frequency - - 32.768 - kHz LSEDRV[1:0] = 00, Low drive capability - 290 - LSEDRV[1:0] = 01, Medium Low drive capability - 390 - LSEDRV[1:0] = 10, Medium high drive capability - 550 - LSEDRV[1:0] = 11, High drive capability - 900 - LSEDRV[1:0] = 00, Low drive capability - - 0.5 LSEDRV[1:0] = 01, Medium Low drive capability - - 0.75 LSEDRV[1:0] = 10, Medium high drive capability - - 1.7 LSEDRV[1:0] = 11, High drive capability - - 2.7 VDD is stabilized - 2 - IDD Gmcritmax tSU(3) LSE current consumption Maximum critical crystal gm Startup time nA A/V s 1. Guaranteed by design. 2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 "Oscillator design guide for ST microcontrollers. 3. tSU is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768k Hz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer. DS12923 Rev 1 141/252 228 Electrical characteristics Note: STM32H745xI/G For information on selecting the crystal, refer to the application note AN2867 "Oscillator design guide for ST microcontrollers" available from the ST website www.st.com. Figure 24. Typical application with a 32.768 kHz crystal Resonator with integrated capacitors CL1 fLSE OSC32_IN Bias RF controlled gain 32.768 kH z resonator OSC32_OU T CL2 STM32 ai17531b 1. An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden to add one. 6.3.10 Internal clock source characteristics The parameters given in Table 55 to Table 58 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 23: General operating conditions. 48 MHz high-speed internal RC oscillator (HSI48) Table 55. HSI48 oscillator characteristics Symbol fHSI48 TRIM(2) Parameter HSI48 frequency USER trimming step USER TRIM COVERAGE(3) USER TRIMMING Coverage DuCy(HSI48)(2) Duty Cycle Conditions Min Typ Max Unit VDD=3.3 V, TJ=30 C 47.5(1) 48 48.5(1) MHz - - 0.175 - % 32 steps 4.79 5.60 - % - 45 - 55 % ACCHSI48_REL(3)(4) Accuracy of the HSI48 oscillator over temperature (factory calibrated) TJ=-40 to 125 C -4.5 - 3.5 TJ=-40 to 140 C -4.5 - 4 VDD(HSI48)(3) HSI48 oscillator frequency drift with VDD(5) VDD=3 to 3.6 V - 0.025 0.05 VDD=1.62 V to 3.6 V - 0.05 0.1 % tsu(HSI48)(2) HSI48 oscillator start-up time - - 2.1 4.0 s IDD(HSI48)(2) HSI48 oscillator power consumption - - 350 400 A NT jitter Next transition jitter Accumulated jitter on 28 cycles(6) - - 0.15 - ns PT jitter Paired transition jitter Accumulated jitter on 56 cycles(6) - - 0.25 - ns 1. Guaranteed by test in production. 2. Guaranteed by design. 3. Guaranteed by characterization. 4. % fHSI = ACCHSI48_REL + VDD. 142/252 DS12923 Rev 1 STM32H745xI/G Electrical characteristics 5. These values are obtained by using the formula: (Freq(3.6V) - Freq(3.0V)) / Freq(3.0V) or (Freq(3.6V) - Freq(1.62V)) / Freq(1.62V). 6. Jitter measurements are performed without clock source activated in parallel. 64 MHz high-speed internal RC oscillator (HSI) Table 56. HSI oscillator characteristics(1) Symbol Parameter HSI frequency fHSI TRIM HSI user trimming step DuCy(HSI) Duty Cycle VDD (HSI) HSI oscillator frequency drift over VDD (reference is 3.3 V) TEMP (HSI) HSI oscillator frequency drift over temperature (reference is 64 MHz) tsu(HSI) HSI oscillator start-up time tstab(HSI) HSI oscillator stabilization time IDD(HSI) HSI oscillator power consumption Conditions Min Typ Max Unit VDD=3.3 V, TJ=30 C 63.7(2) 64 64.3(2) MHz Trimming is not a multiple of 32 - 0.24 0.32 Trimming is 128, 256 and 384 -5.2 -1.8 - Trimming is 64, 192, 320 and 448 -1.4 -0.8 - Other trimming are a multiple of 32 (not including multiple of 64 and 128) -0.6 -0.25 - - 45 - 55 % VDD=1.62 to 3.6 V -0.12 - 0.03 % TJ=-20 to 105 C -1(3) - 1(3) TJ=-40 to TJmax C -2(3) - 1(3) - - 1.4 2 s at 1% of target frequency - 4 8 s - - 300 400 A % % 1. Guaranteed by design unless otherwise specified. 2. Guaranteed by test in production. 3. Guaranteed by characterization. 4 MHz low-power internal RC oscillator (CSI) Table 57. CSI oscillator characteristics(1) Symbol Parameter Conditions Min Typ Max Unit fCSI CSI frequency VDD=3.3 V, TJ=30 C 3.96(2) 4 4.04(2) MHz TRIM Trimming step - - 0.35 - % Duty Cycle - 45 - 55 % TJ = 0 to 85 C - -3.7(3) 4.5(3) TJ = -40 to 140 C - -11(3) 7.5(3) VDD = 1.62 to 3.6 V - -0.06 0.06 DuCy(CSI) TEMP (CSI) CSI oscillator frequency drift over temperature DVDD (CSI) CSI oscillator frequency drift over VDD DS12923 Rev 1 % % 143/252 228 Electrical characteristics STM32H745xI/G Table 57. CSI oscillator characteristics(1) (continued) Symbol Conditions Min Typ Max Unit CSI oscillator startup time - - 1 2 s tstab(CSI) CSI oscillator stabilization time (to reach 3% of fCSI) - - - 4 cycle IDD(CSI) CSI oscillator power consumption - - 23 30 A Typ Max Unit 32 32.6(1) TJ = -40 to 110 C, VDD = 1.62 to 29.76(2) 3.6 V - 33.6(2) TJ = -40 to 125 C, VDD = 1.62 to 3.6 V 29.4 - 33.6 TJ = -40 to 140 C, VDD = 1.62 to 3.6 V 29.4 - 33.6 - - 80 130 tsu(CSI) Parameter 1. Guaranteed by design. 2. Guaranteed by test in production. 3. Guaranteed by characterization. Low-speed internal (LSI) RC oscillator Table 58. LSI oscillator characteristics Symbol Parameter Conditions VDD = 3.3 V, TJ = 25 C fLSI LSI frequency 31.4(1) tsu(LSI)(3) LSI oscillator startup time tstab(LSI)(3) LSI oscillator stabilization time (5% of final value) - - 120 170 IDD(LSI)(3) LSI oscillator power consumption - - 130 280 kHz s 1. Guaranteed by test in production. 2. Guaranteed by characterization results. 3. Guaranteed by design. 144/252 Min DS12923 Rev 1 nA STM32H745xI/G 6.3.11 Electrical characteristics PLL characteristics The parameters given in Table 59 are derived from tests performed under temperature and VDD supply voltage conditions summarized in Table 23: General operating conditions. Table 59. PLL characteristics (wide VCO frequency range)(1) Symbol fPLL_IN fPLL_P_OUT fVCO_OUT tLOCK Parameter Conditions Min Typ Max Unit PLL input clock - 2 - 16 MHz PLL input clock duty cycle - 10 - 90 % PLL multiplier output clock P Cycle-to-cycle jitter(4) 1.5 - 480 VOS1 1.5 - 400(2) VOS2 1.5 - 300(2) VOS3 1.5 - 200(2) - 192 - 960 Long term jitter 150(3) - 50 Sigma-delta mode (CKIN 8 MHz) - 58(3) 166(3) VCO = 192 MHz - 134 - VCO = 200 MHz - 134 - VCO = 400 MHz - 76 - VCO = 800 MHz - 39 - VCO = 800 MHz - 0.7 - Sigma-delta VCO = mode (CKIN = 800 MHz 16 MHz) - 0.8 - VDDA - 590 1500 VCORE - 720 - VDDA - 180 600 VCORE - 280 - - VCO freq = 836 MHz PLL power consumption on VDD (3) Normal mode Normal mode Jitter IDD(PLL)(3) VOS0 PLL VCO output PLL lock time (2) VCO freq = 192 MHz MHz s ps % A 1. Guaranteed by design unless otherwise specified. 2. This value must be limited to the maximum frequency due to the product limitation (480 MHz for VOS0, 400 MHz for VOS1, 300 MHz for VOS2, 200 MHz for VOS3). 3. Guaranteed by characterization results. 4. Integer mode only. DS12923 Rev 1 145/252 228 Electrical characteristics STM32H745xI/G Table 60. PLL characteristics (medium VCO frequency range)(1) Symbol fPLL_IN fPLL_OUT fVCO_OUT tLOCK Parameter Conditions Min Typ Max Unit PLL input clock - 1 - 2 MHz PLL input clock duty cycle - 10 - 90 % VOS1 1.17 - 210 VOS2 1.17 - 210 VOS3 1.17 - 200 - 150 - 420 - 60(2) 100(2) PLL multiplier output clock P, Q, R PLL VCO output Normal mode PLL lock time Cycle-to-cycle Sigma-delta mode jitter(3) - Jitter Period jitter Long term jitter I(PLL)(2) fPLL_OUT = 50 MHz Normal mode VCO freq = 420MHz PLL power consumption on VDD VCO freq = 150MHz 1. Guaranteed by design unless otherwise specified. 2. Guaranteed by characterization results. 3. Integer mode only. 146/252 DS12923 Rev 1 forbidden VCO = 150 MHz - 145 - VCO = 300 MHz - 91 - VCO = 400 MHz - 64 - VCO = 420 MHz - 63 - VCO = 150 MHz - 55 - VCO = 400 MHz - 30 - VCO = 400 MHz - 0.3 - VDD - 440 1150 VCORE - 530 - VDD - 180 500 VCORE - 200 - MHz s ps -ps % A STM32H745xI/G 6.3.12 Electrical characteristics Memory characteristics Flash memory The characteristics are given at TJ = -40 to 125 C unless otherwise specified. The devices are shipped to customers with the Flash memory erased. Table 61. Flash memory characteristics Symbol Parameter Supply current IDD Conditions Min Typ Max Write / Erase 8-bit mode - 6.5 - Write / Erase 16-bit mode - 11.5 - Write / Erase 32-bit mode - 20 - Write / Erase 64-bit mode - 35 - Unit mA Table 62. Flash memory programming (single bank configuration nDBANK=1) Symbol tprog tERASE128KB tME Parameter Word (266 bits) programming time Sector (128 KB) erase time Mass erase time Conditions Min(1) Typ Max(1) Program/erase parallelism x 8 - 290 580(2) Program/erase parallelism x 16 - 180 360 Program/erase parallelism x 32 - 130 260 Program/erase parallelism x 64 - 100 200 Program/erase parallelism x 8 - 2 4 Program/erase parallelism x 16 - 1.8 3.6 Program/erase parallelism x 32 - Program/erase parallelism x 8 - 13 26 Program/erase parallelism x 16 - 8 16 Program/erase parallelism x 32 - 6 12 Program/erase parallelism x 64 - 5 10 1.62 - 3.6 1.8 - 3.6 Unit s s Program parallelism x 8 Vprog Programming voltage Program parallelism x 16 Program parallelism x 32 Program parallelism x 64 V 1. Guaranteed by characterization results. 2. The maximum programming time is measured after 10K erase operations. DS12923 Rev 1 147/252 228 Electrical characteristics STM32H745xI/G Table 63. Flash memory endurance and data retention Value Symbol NEND tRET Parameter Conditions Unit Min(1) Endurance TJ = -40 to +125 C (6 suffix versions) 10 Data retention 1 kcycle at TA = 85 C 30 10 kcycles at TA = 55 C 20 kcycles Years 1. Guaranteed by characterization results. 6.3.13 EMC characteristics Susceptibility tests are performed on a sample basis during device characterization. Functional EMS (electromagnetic susceptibility) While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs: * Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard. * FTB: A burst of fast transient voltage (positive and negative) is applied to VDD and VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard. A device reset allows normal operations to be resumed. The test results are given in Table 64. They are based on the EMS levels and classes defined in application note AN1709. Table 64. EMS characteristics Symbol VFESD VFTB Parameter Conditions Voltage limits to be applied on any I/O pin to induce VDD = 3.3 V, TA = +25 C, a functional disturbance UFBGA240, frcc_c_ck = Fast transient voltage burst limits to be applied 400 MHz, conforms to through 100 pF on VDD and VSS pins to induce a IEC 61000-4-2 functional disturbance Level/ Class 3B 5A As a consequence, it is recommended to add a serial resistor (1 k) located as close as possible to the MCU to the pins exposed to noise (connected to tracks longer than 50 mm on PCB). 148/252 DS12923 Rev 1 STM32H745xI/G Electrical characteristics Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application. Software recommendations The software flowchart must include the management of runaway conditions such as: * Corrupted program counter * Unexpected reset * Critical Data corruption (control registers...) Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015). Electromagnetic Interference (EMI) The electromagnetic field emitted by the device are monitored while a simple application, executing EEMBC code, is running. This emission test is compliant with SAE IEC61967-2 standard which specifies the test board and the pin loading. Table 65. EMI characteristics Symbol Parameter Conditions Monitored frequency band Max vs. [fHSE/fCPU] Unit 8/400 MHz SEMI VDD = 3.6 V, TA = 25 C, UFBGA240 package, Peak level conforming to IEC61967-2 DS12923 Rev 1 0.1 to 30 MHz 11 30 to 130 MHz 6 130 MHz to 1 GHz 12 1 GHz to 2 GHz 7 EMI Level 2.5 dBV - 149/252 228 Electrical characteristics 6.3.14 STM32H745xI/G Absolute maximum ratings (electrical sensitivity) Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity. Electrostatic discharge (ESD) Electrostatic discharges (a positive then a negative pulse) are applied to the pins of each sample according to each pin combination. This test conforms to the ANSI/ESDA/JEDEC JS-001 and ANSI/ESDA/JEDEC JS-002 standards. Table 66. ESD absolute maximum ratings Conditions Packages Class Maximum value(1) Electrostatic discharge VESD(HBM) voltage (human body model) TA = +25 C conforming to ANSI/ESDA/JEDEC JS001 All 1C 1000 Electrostatic discharge VESD(CDM) voltage (charge device model) TA = +25 C conforming to ANSI/ESDA/JEDEC JS002 All Symbol Ratings V C1 250 1. Guaranteed by characterization results. Static latchup Two complementary static tests are required on six parts to assess the latchup performance: * A supply overvoltage is applied to each power supply pin * A current injection is applied to each input, output and configurable I/O pin These tests are compliant with JESD78 IC latchup standard. Table 67. Electrical sensitivities Symbol LU 150/252 Parameter Static latchup class Conditions TA = +25 C conforming to JESD78 DS12923 Rev 1 Unit Class II level A STM32H745xI/G 6.3.15 Electrical characteristics I/O current injection characteristics As a general rule, a current injection to the I/O pins, due to external voltage below VSS or above VDD (for standard, 3.3 V-capable I/O pins) should be avoided during the normal product operation. However, in order to give an indication of the robustness of the microcontroller in cases when an abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during the device characterization. Functional susceptibility to I/O current injection While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures. The failure is indicated by an out of range parameter: ADC error above a certain limit (higher than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out of -5 A/+0 A range), or other functional failure (for example reset, oscillator frequency deviation). The following tables are the compilation of the SIC1/SIC2 and functional ESD results. Negative induced A negative induced leakage current is caused by negative injection and positive induced leakage current by positive injection. Table 68. I/O current injection susceptibility(1) Functional susceptibility Symbol IINJ Description Negative injection Positive injection PA7, PC5, PG1, PB14, PJ7, PA11, PA12, PA13, PA14, PA15, PJ12, PB4 5 0 PA2, PH2, PH3, PE8, PA6, PA7, PC4, PE7, PE10, PE11 0 NA PA0, PA_C, PA1, PA1_C, PC2, PC2_C, PC3, PC3_C, PA4, PA5, PH4, PH5, BOOT0 0 0 All other I/Os 5 NA Unit mA 1. Guaranteed by characterization. DS12923 Rev 1 151/252 228 Electrical characteristics 6.3.16 STM32H745xI/G I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table 69: I/O static characteristics are derived from tests performed under the conditions summarized in Table 23: General operating conditions. All I/Os are CMOS and TTL compliant (except for BOOT0). Table 69. I/O static characteristics Symbol Parameter Condition Min Typ Max - - 0.3VDD(1) - - 0.4VDD-0. 1(2) BOOT0 I/O input low level voltage - - 0.19VDD+ 0.1(2) I/O input high level voltage except BOOT0 0.7VDD(1) - - 0.47VDD+0. 25(2) - - 0.17VDD+0. 6(2) - - - 250 - - 200 - 0< VIN Max(VDDXXX)(9) - - +/-250 Max(VDDXXX) < VIN 5.5 V (5)(6)(9) - - 1500 0< VIN Max(VDDXXX)(9) - - +/- 350 Max(VDDXXX) < VIN 5.5 V (5)(6)(9) - - 5000(7) 0< VIN Max(VDDXXX) (9) - - +/-250 0< VIN VDDIOX - - 15 I/O input low level voltage except BOOT0 VIL VIH I/O input low level voltage except BOOT0 I/O input high level voltage except BOOT0(3) 1.62 V<VDDIOx<3.6 V 1.62 V<VDDIOx<3.6 V BOOT0 I/O input high level voltage(3) VHYS(2) TT_xx, FT_xxx and NRST I/O input hysteresis 1.62 V< VDDIOx <3.6 V BOOT0 I/O input hysteresis FT_xx Input leakage Ileak (4) current(2) FT_u IO TT_xx Input leakage current VPP (BOOT0 alternate function) RPU Weak pull-up equivalent resistor(8) RPD Weak pull-down equivalent resistor(8) CIO I/O pin capacitance VDDIOX < VIN 9 V V V mV nA 35 VIN=VSS 30 40 50 VIN=VDD(9) 30 40 50 - - 5 - k 1. Compliant with CMOS requirements. 2. Guaranteed by design. 3. VDDIOx represents VDDIO1, VDDIO2 or VDDIO3. VDDIOx= VDD. 4. This parameter represents the pad leakage of the I/O itself. The total product pad leakage is provided by the following formula: ITotal_Ileak_max = 10 A + [number of I/Os where VIN is applied on the pad] Ilkg(Max). 5. All FT_xx IO except FT_lu, FT_u and PC3. 152/252 Unit DS12923 Rev 1 pF STM32H745xI/G Electrical characteristics 6. VIN must be less than Max(VDDXXX) + 3.6 V. 7. To sustain a voltage higher than MIN(VDD, VDDA, VDD33USB) +0.3 V, the internal pull-up and pull-down resistors must be disabled. 8. The pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This PMOS/NMOS contribution to the series resistance is minimal (~10% order). 9. Max(VDDXXX) is the maximum value of all the I/O supplies. All I/Os are CMOS and TTL compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters. The coverage of these requirements for FT I/Os is shown in Figure 25. Figure 25. VIL/VIH for all I/Os except BOOT0 3 2.5 2 Voltage D uirem S req CMO 1.5 +0.25 0.47VDD in= tion VIHm imula ed on s TLL requirement: VIHmin = 2 V 0.7V D in= V IHm ent: Bas -0.1 0.4VDD VILmax= ulation im s n o =0.3VDD Based max ment: VIL require CMOS TLL requirement: VILmin = 0.8 V 1 0.5 0 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 MSv46121V3 Output driving current The GPIOs (general purpose input/outputs) can sink or source up to 8 mA, and sink or source up to 20 mA (with a relaxed VOL/VOH). In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in Section 6.2. In particular: * The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating IVDD (see Table 21). * The sum of the currents sunk by all the I/Os on VSS plus the maximum Run consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating IVSS (see Table 21). DS12923 Rev 1 153/252 228 Electrical characteristics STM32H745xI/G Output voltage levels Unless otherwise specified, the parameters given in Table 70: Output voltage characteristics for all I/Os except PC13, PC14, PC15 and PI8 and Table 71: Output voltage characteristics for PC13, PC14, PC15 and PI8 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 23: General operating conditions. All I/Os are CMOS and TTL compliant. Table 70. Output voltage characteristics for all I/Os except PC13, PC14, PC15 and PI8(1) Symbol Parameter Conditions(3) Min Max Output low level voltage CMOS IIO=8 mA 2.7 V VDD 3.6 V - 0.4 Output high level voltage CMOS port(2) IIO=-8 mA 2.7 V VDD 3.6 V VDD-0.4 - Output low level voltage TTL port(2) IIO=8 mA 2.7 V VDD 3.6 V - 0.4 Output high level voltage TTL port(2) IIO=-8 mA 2.7 V VDD 3.6 V 2.4 - VOL(3) Output low level voltage IIO=20 mA 2.7 V VDD 3.6 V - 1.3 VOH(3) Output high level voltage IIO=-20 mA 2.7 V VDD 3.6 V VDD-1.3 - VOL(3) Output low level voltage IIO=4 mA 1.62 V VDD 3.6 V - 0.4 VOH (3) Output high level voltage IIO=-4 mA 1.62 VVDD<3.6 V VDD--0.4 - IIO= 20 mA 2.3 V VDD3.6 V - 0.4 IIO= 10 mA 1.62 V VDD 3.6 V - 0.4 Unit port(2) VOL VOH VOL(3) VOH (3) VOLFM+(3) Output low level voltage for an FTf I/O pin in FM+ mode V 1. The IIO current sourced or sunk by the device must always respect the absolute maximum rating specified in Table 20: Voltage characteristics, and the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always respect the absolute maximum ratings IIO. 2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52. 3. Guaranteed by design. 154/252 DS12923 Rev 1 STM32H745xI/G Electrical characteristics Table 71. Output voltage characteristics for PC13, PC14, PC15 and PI8(1) Conditions(3) Min Max Output low level voltage CMOS port(2) IIO=3 mA 2.7 V VDD 3.6 V - 0.4 Output high level voltage CMOS port(2) IIO=-3 mA 2.7 V VDD 3.6 V VDD-0.4 - Output low level voltage TTL port(2) IIO=3 mA 2.7 V VDD 3.6 V - 0.4 Output high level voltage TTL port(2) IIO=-3 mA 2.7 V VDD 3.6 V 2.4 - VOL(2) Output low level voltage IIO=1.5 mA 1.62 V VDD 3.6 V - 0.4 VOH(2) Output high level voltage IIO=-1.5 mA 1.62 V VDD 3.6 V VDD-0.4 - Symbol VOL VOH VOL(3) VOH (2) Parameter Unit V 1. The IIO current sourced or sunk by the device must always respect the absolute maximum rating specified in Table 20: Voltage characteristics, and the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always respect the absolute maximum ratings IIO. 2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52. 3. Guaranteed by design. DS12923 Rev 1 155/252 228 Electrical characteristics STM32H745xI/G Output buffer timing characteristics (HSLV option disabled) The HSLV bit of SYSCFG_CCCSR register can be used to optimize the I/O speed when the product voltage is below 2.7 V. Table 72. Output timing characteristics (HSLV OFF)(1)(2) Speed Symbol Fmax(3) Parameter Maximum frequency 00 tr/tf(4) Fmax(3) Output high to low level fall time and output low to high level rise time Maximum frequency 01 tr/tf(4) 156/252 Output high to low level fall time and output low to high level rise time conditions Min Max C=50 pF, 2.7 V VDD3.6 V - 12 C=50 pF, 1.62 VVDD2.7 V - 3 C=30 pF, 2.7 VVDD3.6 V - 12 C=30 pF, 1.62 VVDD2.7 V - 3 C=10 pF, 2.7 VVDD3.6 V - 16 C=10 pF, 1.62 VVDD2.7 V - 4 C=50 pF, 2.7 V VDD3.6 V - 16.6 C=50 pF, 1.62 VVDD2.7 V - 33.3 C=30 pF, 2.7 VVDD3.6 V - 13.3 C=30 pF, 1.62 VVDD2.7 V - 25 C=10 pF, 2.7 VVDD3.6 V - 10 C=10 pF, 1.62 VVDD2.7 V - 20 C=50 pF, 2.7 V VDD3.6 V - 60 C=50 pF, 1.62 VVDD2.7 V - 15 C=30 pF, 2.7 VVDD3.6 V - 80 C=30 pF, 1.62 VVDD2.7 V - 15 C=10 pF, 2.7 VVDD3.6 V - 110 C=10 pF, 1.62 VVDD2.7 V - 20 C=50 pF, 2.7 V VDD3.6 V - 5.2 C=50 pF, 1.62 VVDD2.7 V - 10 C=30 pF, 2.7 VVDD3.6 V - 4.2 C=30 pF, 1.62 VVDD2.7 V - 7.5 C=10 pF, 2.7 VVDD3.6 V - 2.8 C=10 pF, 1.62 VVDD2.7 V - 5.2 DS12923 Rev 1 Unit MHz ns MHz ns STM32H745xI/G Electrical characteristics Table 72. Output timing characteristics (HSLV OFF)(1)(2) (continued) Speed Symbol Parameter conditions Min Max C=50 pF, 2.7 VVDD3.6 V - 85 C=50 pF, 1.62 VVDD2.7 V(5) - 35 - 110 C=30 pF, 1.62 VVDD2.7 V - 40 C=10 pF, 2.7 VVDD3.6 V(5) - 166 C=10 pF, 1.62 VVDD2.7 V(5) - 100 - 3.8 (5) (5) Fmax(3) Maximum frequency 10 C=30 pF, 2.7 VVDD3.6 V (5) (5) C=50 pF, 2.7 VVDD3.6 V (5) C=50 pF, 1.62 VVDD2.7 V tr/tf(4) Output high to low level fall time and output low to high level rise time - 6.9 V(5) - 2.8 C=30 pF, 1.62 VVDD2.7 V(5) - 5.2 C=10 pF, 2.7 VVDD3.6 V(5) - 1.8 Vv - 3.3 Vv - 100 C=30 pF, 2.7 VVDD3.6 C=10 pF, 1.62 VVDD2.7 C=50 pF, 2.7 VVDD3.6 C=50 pF, 1.62 VVDD2.7 V(5) Fmax(3) Maximum frequency 11 - 50 C=30 pF, 2.7 VVDD3.6 Vv - 133 C=30 pF, 1.62 VVDD2.7 V(5) - 66 C=10 pF, 2.7 VVDD3.6 V(5) - 220 C=10 pF, 1.62 VVDD2.7 V(5) - 85 V(5) - 3.3 V(5) - 6.6 V(5) - 2.4 C=30 pF, 1.62 VVDD2.7 V(5) - 4.5 C=10 pF, 2.7 VVDD3.6 V(5) - 1.5 V(5) - 2.7 C=50 pF, 2.7 VVDD3.6 C=50 pF, 1.62 VVDD2.7 tr/tf(4) Output high to low level fall time and output low to high level rise time C=30 pF, 2.7 VVDD3.6 C=10 pF, 1.62 VVDD2.7 Unit MHz ns MHz ns 1. Guaranteed by design. 2. The frequency of the GPIOs that can be supplied in VBAT mode (PC13, PC14, PC15 and PI8) is limited to 2 MHz 3. The maximum frequency is defined with the following conditions: (tr+tf) 2/3 T Skew 1/20 T 45%<Duty cycle<55% 4. The fall and rise times are defined between 90% and 10% and between 10% and 90% of the output waveform, respectively. 5. Compensation system enabled. DS12923 Rev 1 157/252 228 Electrical characteristics STM32H745xI/G Output buffer timing characteristics (HSLV option enabled) Table 73. Output timing characteristics (HSLV ON)(1) Speed Symbol Fmax (2) Parameter Maximum frequency 00 tr/tf(3) Fmax (2) Output high to low level fall time and output low to high level rise time Maximum frequency 01 tr/tf(3) Fmax (2) Output high to low level fall time and output low to high level rise time Maximum frequency 10 tr/tf(3) Fmax (2) Output high to low level fall time and output low to high level rise time Maximum frequency 11 tr/tf(3) Output high to low level fall time and output low to high level rise time conditions Min Max C=50 pF, 1.62 VVDD2.7 V - 10 C=30 pF, 1.62 VVDD2.7 V - 10 C=10 pF, 1.62 VVDD2.7 V - 10 C=50 pF, 1.62 VVDD2.7 V - 11 C=30 pF, 1.62 VVDD2.7 V - 9 C=10 pF, 1.62 VVDD2.7 V - 6.6 C=50 pF, 1.62 VVDD2.7 V - 50 C=30 pF, 1.62 VVDD2.7 V - 58 C=10 pF, 1.62 VVDD2.7 V - 66 C=50 pF, 1.62 VVDD2.7 V - 6.6 C=30 pF, 1.62 VVDD2.7 V - 4.8 C=10 pF, 1.62 VVDD2.7 V - 3 C=50 pF, 1.62 VVDD2.7 V(4) - 55 C=30 pF, 1.62 VVDD2.7 V(4) - 80 C=10 pF, 1.62 VVDD2.7 V(4) - 133 C=30 pF, 1.62 VVDD2.7 V(4) - 5.8 C=30 pF, 1.62 VVDD2.7 V(4) - 4 C=30 pF, 1.62 VVDD2.7 V(4) - 2.4 C=30 pF, 1.62 VVDD2.7 V(4) - 60 C=30 pF, 1.62 VVDD2.7 V(4) - 90 C=30 pF, 1.62 VVDD2.7 V(4) - 175 C=30 pF, 1.62 VVDD2.7 V(4) - 5.3 C=30 pF, 1.62 VVDD2.7 V(4) - 3.6 (4) - 1.9 C=30 pF, 1.62 VVDD2.7 V Unit MHz ns MHz ns MHz ns MHz ns 1. Guaranteed by design. 2. The maximum frequency is defined with the following conditions: (tr+tf) 2/3 T Skew 1/20 T 45%<Duty cycle<55% 3. The fall and rise times are defined between 90% and 10% and between 10% and 90% of the output waveform, respectively. 4. Compensation system enabled. 158/252 DS12923 Rev 1 STM32H745xI/G 6.3.17 Electrical characteristics NRST pin characteristics The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, RPU (see Table 69: I/O static characteristics). Unless otherwise specified, the parameters given in Table 74 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 23: General operating conditions. Table 74. NRST pin characteristics Symbol RPU(2) Parameter Conditions Min Typ Max Unit VIN = VSS 30 40 50 1.71 V < VDD < 3.6 V - - 50 1.71 V < VDD < 3.6 V 300 - - 1.62 V < VDD < 3.6 V 1000 - - Weak pull-up equivalent resistor(1) VF(NRST)(2) NRST Input filtered pulse VNF(NRST)(2) NRST Input not filtered pulse ns 1. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance must be minimum (~10% order). 2. Guaranteed by design. Figure 26. Recommended NRST pin protection VDD External reset circuit (1) RPU NRST (2) Internal Reset Filter 0.1 F STM32 ai14132d 1. The reset network protects the device against parasitic resets. 2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in Table 69. Otherwise the reset is not taken into account by the device. 6.3.18 FMC characteristics Unless otherwise specified, the parameters given in Table 75 to Table 88 for the FMC interface are derived from tests performed under the ambient temperature, fHCLK frequency and VDD supply voltage conditions summarized in Table 23: General operating conditions, with the following configuration: * Output speed is set to OSPEEDRy[1:0] = 11 * Measurement points are done at CMOS levels: 0.5VDD * IO Compensation cell activated. * HSLV activated when VDD 2.7 V * VOS level set to VOS1. DS12923 Rev 1 159/252 228 Electrical characteristics STM32H745xI/G Refer to Section 6.3.16: I/O port characteristics for more details on the input/output alternate function characteristics. Asynchronous waveforms and timings Figure 27 through Figure 29 represent asynchronous waveforms and Table 75 through Table 82 provide the corresponding timings. The results shown in these tables are obtained with the following FMC configuration: * AddressSetupTime = 0x1 * AddressHoldTime = 0x1 * DataSetupTime = 0x1 (except for asynchronous NWAIT mode , DataSetupTime = 0x5) * BusTurnAroundDuration = 0x0 * Capacitive load CL = 30 pF In all timing tables, the TKERCK is the fmc_ker_ck clock period. Figure 27. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms tw(NE) FMC_NE tv(NOE_NE) t w(NOE) t h(NE_NOE) FMC_NOE FMC_NWE tv(A_NE) FMC_A[25:0] t h(A_NOE) Address tv(BL_NE) t h(BL_NOE) FMC_NBL[1:0] t h(Data_NE) t su(Data_NOE) th(Data_NOE) t su(Data_NE) Data FMC_D[15:0] t v(NADV_NE) tw(NADV) FMC_NADV (1) FMC_NWAIT th(NE_NWAIT) tsu(NWAIT_NE) MS32753V1 1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used. 160/252 DS12923 Rev 1 STM32H745xI/G Electrical characteristics Table 75. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings(1) Symbol Parameter Min tw(NE) FMC_NE low time 3Tfmc_ker_ck-1 tv(NOE_NE) FMC_NEx low to FMC_NOE low 0 0.5 tw(NOE) FMC_NOE low time 2Tfmc_ker_ck -1 2Tfmc_ker_ck+1 th(NE_NOE) FMC_NOE high to FMC_NE high hold time 0 - tv(A_NE) FMC_NEx low to FMC_A valid - 0.5 th(A_NOE) Address hold time after FMC_NOE high 0 - tsu(Data_NE) Data to FMC_NEx high setup time 11 - tsu(Data_NOE) Data to FMC_NOEx high setup time 11 - th(Data_NOE) Data hold time after FMC_NOE high 0 - th(Data_NE) Data hold time after FMC_NEx high 0 - - 0 - Tfmc_ker_ck+1 tv(NADV_NE) FMC_NEx low to FMC_NADV low tw(NADV) FMC_NADV low time Max Unit 3Tfmc_ker_ck+1 ns 1. Guaranteed by characterization results. Table 76. Asynchronous non-multiplexed SRAM/PSRAM/NOR read-NWAIT timings(1)(2) Symbol Parameter Min Max Unit tw(NE) FMC_NE low time 7Tfmc_ker_ck+1 7Tfmc_ker_ck+1 tw(NOE) FMC_NOE low time 5Tfmc_ker_ck-1 5Tfmc_ker_ck +1 tw(NWAIT) FMC_NWAIT low time Tfmc_ker_ck- 0.5 tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 4Tfmc_ker_ck +11 - th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid 3Tfmc_ker_ck+11.5 - ns 1. Guaranteed by characterization results. 2. NWAIT pulse width is equal to 1 AHB cycle. DS12923 Rev 1 161/252 228 Electrical characteristics STM32H745xI/G Figure 28. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms tw(NE) FMC_NEx FMC_NOE tv(NWE_NE) tw(NWE) t h(NE_NWE) FMC_NWE tv(A_NE) FMC_A[25:0] th(A_NWE) Address tv(BL_NE) FMC_NBL[1:0] th(BL_NWE) NBL tv(Data_NE) th(Data_NWE) Data FMC_D[15:0] t v(NADV_NE) FMC_NADV (1) tw(NADV) FMC_NWAIT th(NE_NWAIT) tsu(NWAIT_NE) MS32754V1 1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used. 162/252 DS12923 Rev 1 STM32H745xI/G Electrical characteristics Table 77. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings(1) Symbol Parameter Min Max tw(NE) FMC_NE low time 3Tfmc_ker_ck -1 3Tfmc_ker_ck tv(NWE_NE) FMC_NEx low to FMC_NWE low Tfmc_ker_ck Tfmc_ker_ck+1 tw(NWE) FMC_NWE low time Tfmc_ker_ck -0.5 Tfmc_ker_ck+0.5 th(NE_NWE) FMC_NWE high to FMC_NE high hold time Tfmc_ker_ck - tv(A_NE) FMC_NEx low to FMC_A valid - 2 th(A_NWE) Address hold time after FMC_NWE high Tfmc_ker_ck -0.5 - tv(BL_NE) FMC_NEx low to FMC_BL valid - 0.5 th(BL_NWE) FMC_BL hold time after FMC_NWE high Tfmc_ker_ck -0.5 - tv(Data_NE) Data to FMC_NEx low to Data valid - Tfmc_ker_ck+ 2.5 th(Data_NWE) Data hold time after FMC_NWE high Tfmc_ker_ck+0.5 - tv(NADV_NE) FMC_NEx low to FMC_NADV low - 0 tw(NADV) FMC_NADV low time - Tfmc_ker_ck+ 1 Unit ns 1. Guaranteed by characterization results. Table 78. Asynchronous non-multiplexed SRAM/PSRAM/NOR write-NWAIT timings(1)(2) Symbol Parameter Min Max tw(NE) FMC_NE low time 8Tfmc_ker_ck -1 8Tfmc_ker_ck+1 tw(NWE) FMC_NWE low time 6Tfmc_ker_ck -1.5 6Tfmc_ker_ck+0.5 tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 5Tfmc_ker_ck+13 - th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid 4Tfmc_ker_ck+13 - Unit ns 1. Guaranteed by characterization results. 2. NWAIT pulse width is equal to 1 AHB cycle. DS12923 Rev 1 163/252 228 Electrical characteristics STM32H745xI/G Figure 29. Asynchronous multiplexed PSRAM/NOR read waveforms tw(NE) FMC_ NE tv(NOE_NE) t h(NE_NOE) FMC_NOE t w(NOE) FMC_NWE th(A_NOE) tv(A_NE) FMC_ A[25:16] Address tv(BL_NE) th(BL_NOE) FMC_ NBL[1:0] NBL th(Data_NE) tsu(Data_NE) t v(A_NE) FMC_ AD[15:0] tsu(Data_NOE) th(Data_NOE) Data Address th(AD_NADV) t v(NADV_NE) tw(NADV) FMC_NADV FMC_NWAIT th(NE_NWAIT) tsu(NWAIT_NE) MS32755V1 164/252 DS12923 Rev 1 STM32H745xI/G Electrical characteristics Table 79. Asynchronous multiplexed PSRAM/NOR read timings(1) Symbol Parameter Min Max tw(NE) FMC_NE low time 4Tfmc_ker_ck -1 4Tfmc_ker_ck +1 tv(NOE_NE) FMC_NEx low to FMC_NOE low 2Tfmc_ker_ck 2Tfmc_ker_ck +0.5 ttw(NOE) FMC_NOE low time Tfmc_ker_ck -1 th(NE_NOE) FMC_NOE high to FMC_NE high hold time 0 - tv(A_NE) FMC_NEx low to FMC_A valid - 0.5 tv(NADV_NE) FMC_NEx low to FMC_NADV low 0 0.5 tw(NADV) FMC_NADV low time Tfmc_ker_ck -0.5 Tfmc_ker_ck +1 th(AD_NADV) FMC_AD(address) valid hold time after FMC_NADV high) Tfmc_ker_ck +0.5 - th(A_NOE) Address hold time after FMC_NOE high Tfmc_ker_ck -0.5 - tsu(Data_NE) Data to FMC_NEx high setup time 11 - tsu(Data_NOE) Data to FMC_NOE high setup time 11 - th(Data_NE) Data hold time after FMC_NEx high 0 - th(Data_NOE) Data hold time after FMC_NOE high 0 - Unit Tfmc_ker_ck +1 ns 1. Guaranteed by characterization results. Table 80. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings(1)(2) Symbol Parameter Min Max Unit tw(NE) FMC_NE low time 8Tfmc_ker_ck -1 8Tfmc_ker_ck tw(NOE) FMC_NWE low time 5Tfmc_ker_ck -1.5 5Tfmc_ker_ck +0.5 tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 4Tfmc_ker_ck +11 - th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid 3Tfmc_ker_ck +11.5 - ns 1. Guaranteed by characterization results. 2. NWAIT pulse width is equal to 1 AHB cycle. DS12923 Rev 1 165/252 228 Electrical characteristics STM32H745xI/G Table 81. Asynchronous multiplexed PSRAM/NOR write timings(1) Symbol Parameter Min Max tw(NE) FMC_NE low time 4Tfmc_ker_ck -1 4Tfmc_ker_ck tv(NWE_NE) FMC_NEx low to FMC_NWE low Tfmc_ker_ck -1 Tfmc_ker_ck +0.5 tw(NWE) FMC_NWE low time 2Tfmc_ker_ck -0.5 2Tfmc_ker_ck +0.5 th(NE_NWE) FMC_NWE high to FMC_NE high hold time Tfmc_ker_ck -0.5 - tv(A_NE) FMC_NEx low to FMC_A valid - 0 tv(NADV_NE) FMC_NEx low to FMC_NADV low 0 0.5 tw(NADV) FMC_NADV low time Tfmc_ker_ck Tfmc_ker_ck + 1 th(AD_NADV) FMC_AD(adress) valid hold time after FMC_NADV high) Tfmc_ker_ck +0.5 - th(A_NWE) Address hold time after FMC_NWE high Tfmc_ker_ck +0.5 - th(BL_NWE) FMC_BL hold time after FMC_NWE high Tfmc_ker_ck - 0.5 - tv(BL_NE) FMC_NEx low to FMC_BL valid - 0.5 tv(Data_NADV) FMC_NADV high to Data valid - Tfmc_ker_ck +2 th(Data_NWE) Data hold time after FMC_NWE high Tfmc_ker_ck +0.5 - Unit ns 1. Guaranteed by characterization results. Table 82. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings(1)(2) Symbol Parameter Min Max tw(NE) FMC_NE low time 9Tfmc_ker_ck -1 9Tfmc_ker_ck tw(NWE) FMC_NWE low time 7Tfmc_ker_ck -0.5 7Tfmc_ker_ck +0.5 tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 5Tfmc_ker_ck +11 - th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid 4Tfmc_ker_ck +11.5 - Unit ns 1. Guaranteed by characterization results. 2. NWAIT pulse width is equal to 1 AHB cycle. Synchronous waveforms and timings Figure 30 through Figure 33 represent synchronous waveforms and Table 83 through Table 86 provide the corresponding timings. The results shown in these tables are obtained with the following FMC configuration: 166/252 * BurstAccessMode = FMC_BurstAccessMode_Enable * MemoryType = FMC_MemoryType_CRAM * WriteBurst = FMC_WriteBurst_Enable * CLKDivision = 1 * DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM DS12923 Rev 1 STM32H745xI/G Electrical characteristics In all the timing tables, the Tfmc_ker_ck is the fmc_ker_ck clock period, with the following FMC_CLK maximum values: * For 2.7 V<VDD<3.6 V, FMC_CLK = 125 MHz at 20 pF * For 1.8 V<VDD<1.9 V, FMC_CLK = 100 MHz at 20 pF * For 1.62 V<VDD<1.8 V, FMC_CLK = 100 MHz at 15 pF Figure 30. Synchronous multiplexed NOR/PSRAM read timings BUSTURN = 0 tw(CLK) tw(CLK) FMC_CLK Data latency = 0 td(CLKL-NExL) FMC_NEx t d(CLKL-NADVL) td(CLKH-NExH) td(CLKL-NADVH) FMC_NADV td(CLKL-AV) td(CLKH-AIV) FMC_A[25:16] td(CLKL-NOEL) td(CLKH-NOEH) FMC_NOE t d(CLKL-ADV) FMC_AD[15:0] td(CLKL-ADIV) tsu(ADV-CLKH) AD[15:0] th(CLKH-ADV) tsu(ADV-CLKH) D1 tsu(NWAITV-CLKH) FMC_NWAIT (WAITCFG = 1b, WAITPOL + 0b) FMC_NWAIT (WAITCFG = 0b, WAITPOL + 0b) tsu(NWAITV-CLKH) tsu(NWAITV-CLKH) th(CLKH-ADV) D2 th(CLKH-NWAITV) th(CLKH-NWAITV) th(CLKH-NWAITV) MS32757V1 DS12923 Rev 1 167/252 228 Electrical characteristics STM32H745xI/G Table 83. Synchronous multiplexed NOR/PSRAM read timings(1) Symbol Parameter Min Max tw(CLK) FMC_CLK period 2Tfmc_ker_ck -1 - td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) - 1 td(CLKH_NExH) FMC_CLK high to FMC_NEx high (x= 0...2) Tfmc_ker_ck+0.5 - td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 1 td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 0 - td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16...25) - 2.5 td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x=16...25) Tfmc_ker_ck - td(CLKL-NOEL) FMC_CLK low to FMC_NOE low - 1.5 td(CLKH-NOEH) FMC_CLK high to FMC_NOE high Tfmc_ker_ck -0.5 - td(CLKL-ADV) FMC_CLK low to FMC_AD[15:0] valid - 3 td(CLKL-ADIV) FMC_CLK low to FMC_AD[15:0] invalid 0 - tsu(ADV-CLKH) FMC_A/D[15:0] valid data before FMC_CLK high 2 - th(CLKH-ADV) FMC_A/D[15:0] valid data after FMC_CLK high 1 - tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 2 - th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 2 - 1. Guaranteed by characterization results. 168/252 DS12923 Rev 1 Unit ns STM32H745xI/G Electrical characteristics Figure 31. Synchronous multiplexed PSRAM write timings BUSTURN = 0 tw(CLK) tw(CLK) FMC_CLK Data latency = 0 td(CLKL-NExL) td(CLKH-NExH) FMC_NEx td(CLKL-NADVL) td(CLKL-NADVH) FMC_NADV td(CLKH-AIV) td(CLKL-AV) FMC_A[25:16] td(CLKH-NWEH) td(CLKL-NWEL) FMC_NWE td(CLKL-ADIV) td(CLKL-ADV) FMC_AD[15:0] td(CLKL-Data) td(CLKL-Data) AD[15:0] D1 D2 FMC_NWAIT (WAITCFG = 0b, WAITPOL + 0b) tsu(NWAITV-CLKH) th(CLKH-NWAITV) td(CLKH-NBLH) FMC_NBL MS32758V1 DS12923 Rev 1 169/252 228 Electrical characteristics STM32H745xI/G Table 84. Synchronous multiplexed PSRAM write timings(1) Symbol Parameter Min Max tw(CLK) FMC_CLK period, VDD = 2.7 to 3.6 V 2Tfmc_ker_ck -1 1 - td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x =0..2) - 1 td(CLKH-NExH) FMC_CLK high to FMC_NEx high (x = 0...2) Tfmc_ker_ck +0.5 - td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 1.5 td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 0 - td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x =16...25) - 2 td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x =16...25) Tfmc_ker_ck - td(CLKL-NWEL) FMC_CLK low to FMC_NWE low - 1.5 t(CLKH-NWEH) FMC_CLK high to FMC_NWE high Tfmc_ker_ck +0.5 - td(CLKL-ADV) FMC_CLK low to to FMC_AD[15:0] valid - 2.5 td(CLKL-ADIV) FMC_CLK low to FMC_AD[15:0] invalid 0 - td(CLKL-DATA) FMC_A/D[15:0] valid data after FMC_CLK low - 2.5 td(CLKL-NBLL) FMC_CLK low to FMC_NBL low - 2 td(CLKH-NBLH) FMC_CLK high to FMC_NBL high Tfmc_ker_ck +0.5 - tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 2 - th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 2 - 1. Guaranteed by characterization results. 170/252 DS12923 Rev 1 Unit Ns STM32H745xI/G Electrical characteristics Figure 32. Synchronous non-multiplexed NOR/PSRAM read timings tw(CLK) tw(CLK) FMC_CLK td(CLKL-NExL) td(CLKH-NExH) Data latency = 0 FMC_NEx td(CLKL-NADVL) td(CLKL-NADVH) FMC_NADV td(CLKH-AIV) td(CLKL-AV) FMC_A[25:0] td(CLKL-NOEL) td(CLKH-NOEH) FMC_NOE tsu(DV-CLKH) th(CLKH-DV) tsu(DV-CLKH) FMC_D[15:0] FMC_NWAIT (WAITCFG = 1b, WAITPOL + 0b) FMC_NWAIT (WAITCFG = 0b, WAITPOL + 0b) D1 tsu(NWAITV-CLKH) tsu(NWAITV-CLKH) tsu(NWAITV-CLKH) th(CLKH-DV) D2 th(CLKH-NWAITV) t h(CLKH-NWAITV) th(CLKH-NWAITV) MS32759V1 DS12923 Rev 1 171/252 228 Electrical characteristics STM32H745xI/G Table 85. Synchronous non-multiplexed NOR/PSRAM read timings(1) Symbol Parameter Min Max tw(CLK) FMC_CLK period 2Tfmc_ker_ck -1 - t(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) - 1 td(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0...2) 2Tfmc_ker_ck+0.5 - td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 0.5 td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 0 - td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16...25) - 2 td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x=16...25) 2Tfmc_ker_ck - td(CLKL-NOEL) FMC_CLK low to FMC_NOE low - 1.5 td(CLKH-NOEH) FMC_CLK high to FMC_NOE high 2Tfmc_ker_ck-0.5 - tsu(DV-CLKH) FMC_D[15:0] valid data before FMC_CLK high 2 - th(CLKH-DV) FMC_D[15:0] valid data after FMC_CLK high 1 - t(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 2 - th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 2 - 1. Guaranteed by characterization results. 172/252 DS12923 Rev 1 Unit ns STM32H745xI/G Electrical characteristics Figure 33. Synchronous non-multiplexed PSRAM write timings tw(CLK) tw(CLK) FMC_CLK td(CLKL-NExL) td(CLKH-NExH) Data latency = 0 FMC_NEx td(CLKL-NADVL) td(CLKL-NADVH) FMC_NADV td(CLKH-AIV) td(CLKL-AV) FMC_A[25:0] td(CLKL-NWEL) td(CLKH-NWEH) FMC_NWE td(CLKL-Data) td(CLKL-Data) D1 FMC_D[15:0] D2 FMC_NWAIT (WAITCFG = 0b, WAITPOL + 0b) tsu(NWAITV-CLKH) td(CLKH-NBLH) th(CLKH-NWAITV) FMC_NBL MS32760V1 DS12923 Rev 1 173/252 228 Electrical characteristics STM32H745xI/G Table 86. Synchronous non-multiplexed PSRAM write timings(1) Symbol Parameter Min Max t(CLK) FMC_CLK period 2Tfmc_ker_ck -1 - td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) - 2 t(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0...2) Tfmc_ker_ck+0.5 - td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 0.5 td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 0 - td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16...25) - 2. td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x=16...25) Tfmc_ker_ck - td(CLKL-NWEL) FMC_CLK low to FMC_NWE low - 1.5 td(CLKH-NWEH) FMC_CLK high to FMC_NWE high Tfmc_ker_ck+1 - td(CLKL-Data) FMC_D[15:0] valid data after FMC_CLK low - 3.5 td(CLKL-NBLL) FMC_CLK low to FMC_NBL low - 2 td(CLKH-NBLH) FMC_CLK high to FMC_NBL high Tfmc_ker_ck+1 - tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 2 - th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 2 - 1. Guaranteed by characterization results. 174/252 DS12923 Rev 1 Unit ns STM32H745xI/G Electrical characteristics NAND controller waveforms and timings Figure 34 through Figure 37 represent synchronous waveforms, and Table 87 and Table 88 provide the corresponding timings. The results shown in this table are obtained with the following FMC configuration: * COM.FMC_SetupTime = 0x01 * COM.FMC_WaitSetupTime = 0x03 * COM.FMC_HoldSetupTime = 0x02 * COM.FMC_HiZSetupTime = 0x01 * ATT.FMC_SetupTime = 0x01 * ATT.FMC_WaitSetupTime = 0x03 * ATT.FMC_HoldSetupTime = 0x02 * ATT.FMC_HiZSetupTime = 0x01 * Bank = FMC_Bank_NAND * MemoryDataWidth = FMC_MemoryDataWidth_16b * ECC = FMC_ECC_Enable * ECCPageSize = FMC_ECCPageSize_512Bytes * TCLRSetupTime = 0 * TARSetupTime = 0 * Capacitive load CL = 30 pF In all timing tables, the Tfmc_ker_ck is the fmc_ker_ck clock period. Figure 34. NAND controller waveforms for read access FMC_NCEx ALE (FMC_A17) CLE (FMC_A16) FMC_NWE td(ALE-NOE) th(NOE-ALE) FMC_NOE (NRE) tsu(D-NOE) th(NOE-D) FMC_D[15:0] MS32767V1 DS12923 Rev 1 175/252 228 Electrical characteristics STM32H745xI/G Figure 35. NAND controller waveforms for write access FMC_NCEx ALE (FMC_A17) CLE (FMC_A16) th(NWE-ALE) td(ALE-NWE) FMC_NWE FMC_NOE (NRE) th(NWE-D) tv(NWE-D) FMC_D[15:0] MS32768V1 Figure 36. NAND controller waveforms for common memory read access FMC_NCEx ALE (FMC_A17) CLE (FMC_A16) th(NOE-ALE) td(ALE-NOE) FMC_NWE tw(NOE) FMC_NOE tsu(D-NOE) th(NOE-D) FMC_D[15:0] MS32769V1 176/252 DS12923 Rev 1 STM32H745xI/G Electrical characteristics Figure 37. NAND controller waveforms for common memory write access FMC_NCEx ALE (FMC_A17) CLE (FMC_A16) td(ALE-NOE) tw(NWE) th(NOE-ALE) FMC_NWE FMC_N OE td(D-NWE) tv(NWE-D) th(NWE-D) FMC_D[15:0] MS32770V1 Table 87. Switching characteristics for NAND Flash read cycles(1) Symbol Parameter Min Max tw(N0E) FMC_NOE low width 4Tfmc_ker_ck - 0.5 4Tfmc_ker_ck+0.5 tsu(D-NOE) FMC_D[15-0] valid data before FMC_NOE high 8 - th(NOE-D) FMC_D[15-0] valid data after FMC_NOE high 0 - - 3Tfmc_ker_ck +1 4Tfmc_ker_ck -2 - td(ALE-NOE) FMC_ALE valid before FMC_NOE low th(NOE-ALE) FMC_NWE high to FMC_ALE invalid Unit ns 1. Guaranteed by characterization results. Table 88. Switching characteristics for NAND Flash write cycles(1) Symbol Parameter Min Max tw(NWE) FMC_NWE low width 4Tfmc_ker_ck - 0.5 4Tfmc_ker_ck +0.5 tv(NWE-D) FMC_NWE low to FMC_D[15-0] valid 0 - th(NWE-D) FMC_NWE high to FMC_D[15-0] invalid 2Tfmc_ker_ck - 0.5 - td(D-NWE) FMC_D[15-0] valid before FMC_NWE high 5Tfmc_ker_ck - 1 - td(ALE-NWE) FMC_ALE valid before FMC_NWE low - 3Tfmc_ker_ck +0.5 th(NWE-ALE) FMC_NWE high to FMC_ALE invalid 2Tfmc_ker_ck - 1 - Unit ns 1. Guaranteed by characterization results. DS12923 Rev 1 177/252 228 Electrical characteristics STM32H745xI/G SDRAM waveforms and timings In all timing tables, the TKERCK is the fmc_ker_ck clock period, with the following FMC_SDCLK maximum values: * For 2.7 V<VDD<3.6 V: FMC_CLK =110 MHz at 20 pF * For 1.8 V<VDD<1.9 V: FMC_CLK =100 MHz at 20 pF * For 1.62 V<DD<1.8 V, FMC_CLK =100 MHz at 15 pF Figure 38. SDRAM read access waveforms (CL = 1) FMC_SDCLK td(SDCLKL_AddC) th(SDCLKL_AddR) td(SDCLKL_AddR) FMC_A[12:0] Row n Col1 Col2 Coli Coln th(SDCLKL_AddC) th(SDCLKL_SNDE) td(SDCLKL_SNDE) FMC_SDNE[1:0] td(SDCLKL_NRAS) th(SDCLKL_NRAS) FMC_SDNRAS th(SDCLKL_NCAS) td(SDCLKL_NCAS) FMC_SDNCAS FMC_SDNWE tsu(SDCLKH_Data) FMC_D[31:0] th(SDCLKH_Data) Data1 Data2 Datai Datan MS32751V2 178/252 DS12923 Rev 1 STM32H745xI/G Electrical characteristics Table 89. SDRAM read timings(1) Symbol Parameter Min Max tw(SDCLK) FMC_SDCLK period 2Tfmc_ker_ck - 1 2Tfmc_ker_ck +0.5 tsu(SDCLKH _Data) Data input setup time 2 - th(SDCLKH_Data) Data input hold time 1 - td(SDCLKL_Add) Address valid time - 1.5 td(SDCLKL- SDNE) Chip select valid time - 1.5 th(SDCLKL_SDNE) Chip select hold time 0.5 - td(SDCLKL_SDNRAS) SDNRAS valid time - 1 th(SDCLKL_SDNRAS) SDNRAS hold time 0.5 - td(SDCLKL_SDNCAS) SDNCAS valid time - 0.5 th(SDCLKL_SDNCAS) SDNCAS hold time 0 - Unit ns 1. Guaranteed by characterization results. Table 90. LPSDR SDRAM read timings(1) Symbol Parameter Min Max Unit tW(SDCLK) FMC_SDCLK period 2Tfmc_ker_ck - 1 2Tfmc_ker_ck+0.5 tsu(SDCLKH_Data) Data input setup time 2 - th(SDCLKH_Data) Data input hold time 1.5 - td(SDCLKL_Add) Address valid time - 2.5 td(SDCLKL_SDNE) Chip select valid time - 2.5 th(SDCLKL_SDNE) Chip select hold time 0 - td(SDCLKL_SDNRAS SDNRAS valid time - 0.5 th(SDCLKL_SDNRAS) SDNRAS hold time 0 - td(SDCLKL_SDNCAS) SDNCAS valid time - 1.5 th(SDCLKL_SDNCAS) SDNCAS hold time 0 - ns 1. Guaranteed by characterization results. DS12923 Rev 1 179/252 228 Electrical characteristics STM32H745xI/G Figure 39. SDRAM write access waveforms FMC_SDCLK td(SDCLKL_AddC) th(SDCLKL_AddR) td(SDCLKL_AddR) FMC_A[12:0] Row n Col1 Col2 Coli Coln th(SDCLKL_AddC) th(SDCLKL_SNDE) td(SDCLKL_SNDE) FMC_SDNE[1:0] th(SDCLKL_NRAS) td(SDCLKL_NRAS) FMC_SDNRAS td(SDCLKL_NCAS) th(SDCLKL_NCAS) td(SDCLKL_NWE) th(SDCLKL_NWE) FMC_SDNCAS FMC_SDNWE td(SDCLKL_Data) Data1 FMC_D[31:0] Data2 Datai Datan th(SDCLKL_Data) td(SDCLKL_NBL) FMC_NBL[3:0] MS32752V2 Table 91. SDRAM Write timings(1) Symbol Parameter tw(SDCLK) FMC_SDCLK period td(SDCLKL _Data) Data output valid time - 1 th(SDCLKL _Data) Data output hold time 0 - td(SDCLKL_Add) Address valid time - 1.5 td(SDCLKL_SDNWE) SDNWE valid time - 1.5 th(SDCLKL_SDNWE) SDNWE hold time 0.5 - td(SDCLKL_ SDNE) Chip select valid time - 1.5 th(SDCLKL-_SDNE) Chip select hold time 0.5 - td(SDCLKL_SDNRAS) SDNRAS valid time - 1 th(SDCLKL_SDNRAS) SDNRAS hold time 0.5 - td(SDCLKL_SDNCAS) SDNCAS valid time - 1 td(SDCLKL_SDNCAS) SDNCAS hold time 0.5 - 1. Guaranteed by characterization results. 180/252 DS12923 Rev 1 Min Max Unit 2Tfmc_ker_ck - 1 2Tfmc_ker_ck+0.5 ns STM32H745xI/G Electrical characteristics Table 92. LPSDR SDRAM Write timings(1) Symbol Parameter Min Max tw(SDCLK) FMC_SDCLK period td(SDCLKL _Data) Data output valid time - 2.5 th(SDCLKL _Data) Data output hold time 0 - td(SDCLKL_Add) Address valid time - 2.5 td(SDCLKL-SDNWE) SDNWE valid time - 2.5 th(SDCLKL-SDNWE) SDNWE hold time 0 - td(SDCLKL- SDNE) Chip select valid time - 3 th(SDCLKL- SDNE) Chip select hold time 0 - td(SDCLKL-SDNRAS) SDNRAS valid time - 1.5 th(SDCLKL-SDNRAS) SDNRAS hold time 0 - td(SDCLKL-SDNCAS) SDNCAS valid time - 1.5 td(SDCLKL-SDNCAS) SDNCAS hold time 0 - Unit 2Tfmc_ker_ck - 1 2Tfmc_ker_ck+0.5 ns 1. Guaranteed by characterization results. 6.3.19 Quad-SPI interface characteristics Unless otherwise specified, the parameters given in Table 93 and Table 94 for QUADSPI are derived from tests performed under the ambient temperature, fAHB frequency and VDD supply voltage conditions summarized in Table 23: General operating conditions, with the following configuration: * Output speed is set to OSPEEDRy[1:0] = 11 * Measurement points are done at CMOS levels: 0.5VDD * IO Compensation cell activated. * HSLV activated when VDD 2.7 V * VOS level set to VOS1 Refer to Section 6.3.16: I/O port characteristics for more details on the input/output alternate function characteristics. The following table summarizes the parameters measured in SDR mode. Table 93. QUADSPI characteristics in SDR mode(1) Symbol Fck11/TCK Parameter QUADSPI clock frequency Conditions Min Typ Max 2.7<VDD<3.6 V CL = 20 pF - - 133 1.62<VDD<3.6 V CL = 15 pF - - 100 DS12923 Rev 1 Unit MHz 181/252 228 Electrical characteristics STM32H745xI/G Table 93. QUADSPI characteristics in SDR mode(1) (continued) Symbol Parameter tw(CKH) QUADSPI clock high and low time Even division PRESCALER[7:0] = n = 0,1,3,5... tw(CKL) QUADSPI clock high and low time Odd division PRESCALER[7:0] = n = 2,4,6,8... ts(IN) Data input setup time th(IN) Data input hold time tv(OUT) Data output valid time th(OUT) Data output hold time tw(CKL) tw(CKH) Conditions Min Typ Max TCK/2-0.5 - TCK/2 TCK/2 - TCK/2+0.5 (n/2)*TCK/(n+1)-0.5 - (n/2)*TCK/ (n+1) (n/2+1)*TCK/(n+1) - (n/2+1)*TCK/ (n+1)+0.5 1 - - 3.5 - - - - 1 2 - 0 - - - Unit ns 1. Guaranteed by characterization results. The following table summarizes the parameters measured in DDR mode. Table 94. QUADSPI characteristics in DDR mode(1) Symbol Fck11/TCK tw(CKH) tw(CKL) tw(CKH) tw(CKL) Parameter QUADSPI clock frequency Conditions Min Typ Max 2.7<VDD<3.6 V CL = 20 pF - - 100 1.62<VDD<3.6 V CL = 15 pF - - 100 TCK/2-0.5 - TCK/2 TCK/2 - TCK/2+0.5 (n/2)*TCK/ (n+1)-0.5 - (n/2)*TCK/ (n+1) (n/2+1)*TCK/ (n+1) - (n/2+1)*TCK / (n+1)+0.5 QUADSPI clock high and PRESCALER[7:0] = low time Even division n = 0,1,3,5... QUADSPI clock high and PRESCALER[7:0] = low time Odd division n = 2,4,6,8... MHz tsr(IN), tsf(IN) Data input setup time - 1.5 - - thr(IN),thf(IN) Data input hold time - 3.5 - - DHHC=0 - 5 6 DHHC=1 PRESCALER[7:0] = 1,2... - TCK/4+1 TCK/4+2 DHHC=0 3 - - TCK/4 - - tvr(OUT), tvf(OUT) thr(OUT), thf(OUT) Data output valid time Data output hold time DHHC=1 PRESCALER[7:0]=1 ,2... 1. Guaranteed by characterization results. 182/252 DS12923 Rev 1 Unit ns STM32H745xI/G Electrical characteristics Figure 40. Quad-SPI timing diagram - SDR mode tr(CK) t(CK) tw(CKH) tw(CKL) tf(CK) Clock tv(OUT) th(OUT) Data output D1 D0 D2 ts(IN) Data input D0 th(IN) D1 D2 MSv36878V1 Figure 41. Quad-SPI timing diagram - DDR mode tr(CK) t(CK) tw(CKH) tw(CKL) tf(CK) Clock tvf(OUT) Data output thr(OUT) D0 tvr(OUT) D1 D2 thf(OUT) D3 D4 tsf(IN) thf(IN) Data input D0 D1 D5 tsr(IN) thr(IN) D3 D2 D4 D5 MSv36879V1 6.3.20 Delay block (DLYB) characteristics Unless otherwise specified, the parameters given in Table 95 for Delay Block are derived from tests performed under the ambient temperature, frcc_c_ck frequency and VDD supply voltage summarized in Table 23: General operating conditions, with the following configuration: Table 95. Delay Block characteristics Symbol Parameter Conditions Min Typ Max Unit tinit Initial delay - 1400 2200 2400 ps t Unit Delay - 35 40 45 - DS12923 Rev 1 183/252 228 Electrical characteristics 6.3.21 STM32H745xI/G 16-bit ADC characteristics Unless otherwise specified, the parameters given in Table 96 are derived from tests performed under the ambient temperature, fPCLK2 frequency and VDDA supply voltage conditions summarized in Table 23: General operating conditions. Table 96. ADC characteristics(1)(2) Symbol Parameter Conditions Min Typ Max Unit VDDA Analog supply voltage for ADC ON - 1.62 - 3.6 V VREF+ Positive reference voltage - 1.62 - VDDA V VREF- Negative reference voltage - fADC 184/252 ADC clock frequency 1.62 V VDDA 3.6 V DS12923 Rev 1 V VSSA BOOST = 11 0.12 - 50 BOOST = 10 0.12 - 25 BOOST = 01 0.12 - 12.5 BOOST = 00 - - 6.25 MHz STM32H745xI/G Electrical characteristics Table 96. ADC characteristics(1)(2) (continued) Symbol Parameter Conditions Resolution = 16 bits, VDDA >2.5 V - - 3.60 Resolution = 16 bits fADC=37 MHz SMP = 2.5 - - 3.35 Resolution = 14 bits fADC = 50 MHz SMP = 2.5 - - 5.00 fADC = 50 MHz SMP = 2.5 - - 5.50 TJ = 90 C TJ = 125 C fADC = 50 MHz SMP = 1.5 - - 7.10 Resolution = 8 bits fADC = 50 MHz SMP = 1.5 - - 8.30 Resolution = 14 bits fADC = 49 MHz SMP = 2.5 - - 4.90 fADC = 50 MHz SMP = 2.5 - - 5.50 Resolution = 10 bits TJ = 140 C fADC = 50 MHz SMP = 1.5 - - 6.70 fADC = 50 MHz SMP = 1.5 - - 8.30 fADC=32 MHz SMP = 2.5 - - 2.90 Resolution = 16 bits fADC=31 MHz SMP = 2.5 - - 2.80 Resolution = 14 bits fADC = 33 MHz SMP = 2.5 - - 3.30 Resolution = 12 bits fADC = 39 MHz SMP = 2.5 - - 4.30 fADC = 48 MHz SMP = 2.5 - - 6.00 fADC = 50 MHz SMP = 2.5 - - 7.10 fADC = 37 MHz SMP = 2.5 - - 4.10 fADC = 46 MHz SMP = 2.5 - - 5.70 fADC = 50 MHz SMP = 2.5 - - 7.10 - - resolution = 14 bits - - resolution = 12 bits - - - - - - - - - - - - Resolution = 10 bits Resolution = 8 bits Resolution = 16 bits, VDDA >2.5 V Sampling rate for Fast channels Resolution = 10 bits TJ = 90 C TJ = 125 C Resolution = 8 bits Resolution = 12 bits Resolution = 10 bits TJ = 140 C Resolution = 8 bits Resolution = 16 bits Sampling rate for Slow channels Max SMP = 1.5 Resolution = 12 bits fs(3) Typ fADC=36 MHz Resolution = 12 bits Sampling rate for Direct channels Min resolution = 10 bits TJ = 90 C TJ = 125 C fADC = 10 MHz resolution = 8 bits resolution = 12 bits resolution = 10 bits TJ = 140 C resolution = 8 bits SMP = 1.5 Unit MSps 1.00 tTRIG External trigger period Resolution = 16 bits - - 10 1/ fADC VAIN(4) Conversion voltage range - 0 - VREF+ V VCMIV Common mode input voltage - VREF/2 - 10% VREF/ 2 VREF/2 + 10% V DS12923 Rev 1 185/252 228 Electrical characteristics STM32H745xI/G Table 96. ADC characteristics(1)(2) (continued) Symbol RAIN(5) Parameter External input impedance Conditions Min Typ Max Resolution = 16 bits, TJ = 140 C - - - - 50 Resolution = 16 bits, TJ = 125 C - - - - 170 Resolution = 14 bits, TJ = 140 C - - - - 200 Resolution = 14 bits, TJ = 125 C - - - - 435 Resolution = 12 bits, TJ = 140 C - - - - 700 Resolution = 12 bits, TJ =125 C - - - - 1150 Resolution = 10 bits, TJ = 140 C - - - - 3700 Resolution = 10 bits, TJ = 125 C - - - - 5650 Resolution = 8 bits, TJ = 140 C - - - - 18000 Resolution = 8 bits, TJ = 125 C - - - - 26500 Unit CADC Internal sample and hold capacitor - - 4 - pF tADCVREG _STUP ADC LDO startup time - - 5 10 us tSTAB ADC Power-up time LDO already started 1 - - conver sion cycle tCAL Offset and linearity calibration time - 165010 - - 1/fADC tOFF_ Offset calibration time - 1280 - - 1/fADC Trigger conversion latency regular and injected channels without conversion abort CKMODE = 00 1.5 2 2.5 CKMODE = 01 - - 2.5 CKMODE = 10 - - 2.5 CKMODE = 11 - - 2.25 Trigger conversion latency regular injected channels aborting a regular conversion CKMODE = 00 2.5 3 3.5 CKMODE = 01 - - 3.5 CKMODE = 10 - - 3.5 CKMODE = 11 - - 3.25 CAL tLATR tLATRINJ 1/fADC 1/fADC tS Sampling time - 1.5 - 810.5 1/fADC tCONV Total conversion time (including sampling time) Resolution = N bits ts + 0.5 + N/2 - - 1/fADC 186/252 DS12923 Rev 1 STM32H745xI/G Electrical characteristics Table 96. ADC characteristics(1)(2) (continued) Symbol IDDA_D (ADC) IDDA_SE( ADC) IDD (ADC) Parameter Conditions Min Typ Max ADC consumption on VDDA, BOOST=11, Differential mode Resolution = 16 bits, fADC=25 MHz - - - 1440 - Resolution = 14 bits, fADC=30 MHz - - - 1350 - Resolution = 12 bits, fADC=40 MHz - - - 990 - ADC consumption on VDDA BOOST=10, Differential mode fADC=25 MHz Resolution = 16 bits - - - 1080 - Resolution = 14 bits - - - 810 - Resolution = 12 bits - - - 585 - ADC consumption on VDDA BOOST=01, Differential mode fADC=12.5 MHz Resolution = 16 bits - - - 630 - Resolution = 14 bits - - - 432 - Resolution = 12 bits - - - 315 - ADC consumption on VDDA BOOST=00, Differential mode fADC=6.25 MHz Resolution = 16 bits - - - 360 - Resolution = 14 bits - - - 270 - Resolution = 12 bits - - - 225 - ADC consumption on VDDA BOOST=11, Single-ended mode Resolution = 16 bits, fADC=25 MHz - - - 720 - Resolution = 14 bits, fADC=30 MHz - - - 675 - Resolution = 12 bits, fADC=40 MHz - - - 495 - ADC consumption on VDDA BOOST=10, Singl-ended mode fADC=25 MHz Resolution = 16 bits - - - 540 - Resolution = 14 bits - - - 405 - Resolution = 12 bits - - - 292.5 - ADC consumption on VDDA BOOST=01, Single-ended mode fADC=12.5 MHz Resolution = 16 bits - - - 315 - Resolution = 14 bits - - - 216 - Resolution = 12 bits - - - 157.5 - ADC consumption on VDDA BOOST=00, Single-ended mode fADC=6.25 MHz Resolution = 16 bits - - - 180 - Resolution = 14 bits - - - 135 - Resolution = 12 bits - - - 112.5 - fADC=50 MHz - - - 400 - fADC=25 MHz - - - 220 - ADC consumption on VDD Unit A fADC=12.5 MHz - - - 180 - fADC=6.25 MHz - - - 120 - fADC=3.125 MHz - - - 80 - 1. Guaranteed by design. 2. The voltage booster on ADC switches must be used for VDDA < 2.4 V (embedded I/O switches). 3. These values are valid for UFBGA176+25 and one ADC. The values for other packages and multiple ADCs may be different. 4. Depending on the package, VREF+ can be internally connected to VDDA and VREF- to VSSA. 5. The tolerance is 10 LSBs for 16-bit resolution, 4 LSBs for 14-bit resolution, and 2 LSBs for 12-bit, 10-bit and 8-bit resolutions. DS12923 Rev 1 187/252 228 Electrical characteristics STM32H745xI/G Table 97. Minimum sampling time vs RAIN(1)(2) Minimum sampling time (s) Resolution RAIN () Direct channels(3) 16 bits 47 7.37E-08 1.14E-07 1.72E-07 47 6.29E-08 9.74E-08 1.55E-07 68 6.84E-08 1.02E-07 1.58E-07 100 7.80E-08 1.12E-07 1.62E-07 150 9.86E-08 1.32E-07 1.80E-07 220 1.32E-07 1.61E-07 2.01E-07 47 5.32E-08 8.00E-08 1.29E-07 68 5.74E-08 8.50E-08 1.32E-07 100 6.58E-08 9.31E-08 1.40E-07 150 8.37E-08 1.10E-07 1.51E-07 220 1.11E-07 1.34E-07 1.73E-07 330 1.56E-07 1.78E-07 2.14E-07 470 2.16E-07 2.39E-07 2.68E-07 680 3.01E-07 3.29E-07 3.54E-07 47 4.34E-08 6.51E-08 1.08E-07 68 4.68E-08 6.89E-08 1.11E-07 100 5.35E-08 7.55E-08 1.16E-07 150 6.68E-08 8.77E-08 1.26E-07 220 8.80E-08 1.08E-07 1.40E-07 330 1.24E-07 1.43E-07 1.71E-07 470 1.69E-07 1.89E-07 2.13E-07 680 2.38E-07 2.60E-07 2.80E-07 1000 3.45E-07 3.66E-07 3.84E-07 1500 5.15E-07 5.35E-07 5.48E-07 2200 7.42E-07 7.75E-07 7.78E-07 3300 1.10E-06 1.14E-06 1.14E-06 14 bits 12 bits 10 bits 188/252 DS12923 Rev 1 Fast channels(4) Slow channels(5) STM32H745xI/G Electrical characteristics Table 97. Minimum sampling time vs RAIN(1)(2) (continued) Minimum sampling time (s) Resolution 8 bits RAIN () Direct channels(3) 47 3.32E-08 5.10E-08 8.61E-08 68 3.59E-08 5.35E-08 8.83E-08 100 4.10E-08 5.83E-08 9.22E-08 150 5.06E-08 6.76E-08 9.95E-08 220 6.61E-08 8.22E-08 1.11E-07 330 9.17E-08 1.08E-07 1.32E-07 470 1.24E-07 1.40E-07 1.63E-07 680 1.74E-07 1.91E-07 2.12E-07 1000 2.53E-07 2.70E-07 2.85E-07 1500 3.73E-07 3.93E-07 4.05E-07 2200 5.39E-07 5.67E-07 5.75E-07 3300 8.02E-07 8.36E-07 8.38E-07 4700 1.13E-06 1.18E-06 1.18E-06 6800 1.62E-06 1.69E-06 1.68E-06 10000 2.36E-06 2.47E-06 2.45E-06 15000 3.50E-06 3.69E-06 3.65E-06 Fast channels(4) Slow channels(5) 1. Guaranteed by design. 2. Data valid at up to 140 C, with a 47 pF PCB capacitor, and VDDA=1.6 V. 3. Direct channels are connected to analog I/Os (PA0_C, PA1_C, PC2_C and PC3_C) to optimize ADC performance. 4. Fast channels correspond to PF3, PF5, PF7, PF9, PA6, PC4, PB1, PF11 and PF13. 5. Slow channels correspond to all ADC inputs except for the Direct and Fast channels. DS12923 Rev 1 189/252 228 Electrical characteristics STM32H745xI/G Table 98. ADC accuracy(1)(2) Symbol Parameter Conditions(3) Direct channel ET Total undadjusted error Fast channel Slow channel Min Typ Max Single ended - +10/-20 - Differential - 15 - Single ended - +10/-20 - Differential - 15 - Single ended - 10 - 10 - Differential EO Offset error - - 10 - EG Gain error - - 15 - Single ended - +3/-1 - Differential - +4.5/-1 - Single ended - 11 - Differential - 7 - Single ended - 13 - Differential - 7 - Single ended - 10 - Differential - 6 - Single ended - 12.2 - Differential - 13.2 - Single ended - 75.2 - Differential - 81.2 - Single ended - 77.0 - Differential - 81.0 - Single ended - 87 - Differential - 90 - ED Differential linearity error Direct channel EL Integral linearity error Fast channel Slow channel ENOB Effective number of bits SINAD Signal-to-noise and distortion ratio SNR Signal-to-noise ratio THD Total harmonic distortion Unit LSB Bits dB 1. Data guaranteed by characterization for BGA packages. The values for LQFP packages might differ. 2. ADC DC accuracy values are measured after internal calibration. 3. ADC clock frequency = 25 MHz, ADC resolution = 16 bits, VDDA=VREF+=3.3 V and BOOST=11. Note: ADC accuracy vs. negative injection current: injecting a negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents. Any positive injection current within the limits specified for IINJ(PIN) and IINJ(PIN) in Section 6.3.15 does not affect the ADC accuracy. 190/252 DS12923 Rev 1 STM32H745xI/G Electrical characteristics Figure 42. ADC accuracy characteristics (12-bit resolution) [1LSB IDEAL = V REF+ 4096 (or V DDA 4096 depending on package)] EG 4095 4094 4093 (2) ET (3) 7 (1) 6 5 EO 4 EL 3 ED 2 1L SBIDEAL 1 0 1 2 3 456 7 V SSA 4093 4094 4095 4096 VDDA ai14395c 1. Example of an actual transfer curve. 2. Ideal transfer curve. 3. End point correlation line. 4. ET = Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves. EO = Offset Error: deviation between the first actual transition and the first ideal one. EG = Gain Error: deviation between the last ideal transition and the last actual one. ED = Differential Linearity Error: maximum deviation between actual steps and the ideal one. EL = Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line. Figure 43. Typical connection diagram using the ADC STM32 VDD RAIN(1) AINx VAIN Cparasitic Sample and hold ADC converter VT 0.6 V RADC(1) VT 0.6 V IL1 A 12-bit converter C ADC(1) ai17534b 1. Refer to Table 96 for the values of RAIN, RADC and CADC. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 5 pF). A high Cparasitic value downgrades conversion accuracy. To remedy this, fADC should be reduced. DS12923 Rev 1 191/252 228 Electrical characteristics STM32H745xI/G General PCB design guidelines Power supply decoupling should be performed as shown in Figure 44 or Figure 45, depending on whether VREF+ is connected to VDDA or not. The 100 nF capacitors should be ceramic (good quality). They should be placed them as close as possible to the chip. Figure 44. Power supply and reference decoupling (VREF+ not connected to VDDA) STM32 VREF+(1) 1 F // 100 nF VDDA 1 F // 100 nF VSSA/VREF+(1) MSv50648V1 1. VREF+ input is available on all package whereas the VREF- s available only on UFBGA176+25 and TFBGA240+25. When VREF- is not available, it is internally connected to VDDA and VSSA. Figure 45. Power supply and reference decoupling (VREF+ connected to VDDA) STM32 VREF+/VDDA(1) 1 F // 100 nF VREF-/VSSA(1) MSv50649V1 1. VREF+ input is available on all package whereas the VREF- s available only on UFBGA176+25 and TFBGA240+25. When VREF- is not available, it is internally connected to VDDA and VSSA. 192/252 DS12923 Rev 1 STM32H745xI/G 6.3.22 Electrical characteristics DAC characteristics Table 99. DAC characteristics(1)(2) Symbol Parameter Conditions Min Typ Max VDDA Analog supply voltage - 1.8 3.3 3.6 VREF+ Positive reference voltage - 1.80 - VDDA VREF- Negative reference voltage - - VSSA - connected to VSSA 5 - - connected to VDDA 25 - - 10.3 13 16 VDD = 2.7 V - - 1.6 VDD = 2.0 V - - 2.6 VDD = 2.7 V - - 17.8 VDD = 2.0 V - - 18.7 DAC output buffer OFF - - 50 pF Sample and Hold mode - 0.1 1 F DAC output buffer ON 0.2 - VDDA -0.2 V DAC output buffer OFF 0 - VREF+ 0.5 LSB - 2.05 - 1 LSB - 1.97 - 2 LSB - 1.67 - 4 LSB - 1.66 - 8 LSB - 1.65 - - 1.7 2 - 5 7.5 RL Resistive Load DAC output buffer ON RO Output Impedance RBON Output impedance sample and hold mode, output buffer ON DAC output buffer ON Output impedance sample and hold mode, output buffer OFF DAC output buffer OFF RBOFF CL CSH VDAC_OUT Capacitive Load Voltage on DAC_OUT output Settling time (full scale: for a 12-bit code transition between the lowest and the highest input codes tSETTLING when DAC_OUT reaches the final value of 0.5LSB, 1LSB, 2LSB, 4LSB, 8LSB) DAC output buffer OFF Normal mode, DAC output buffer ON, CL 50 pF, RL 5 Normal mode, DAC output buffer OFF, 1LSB CL=10 pF Wakeup time from off Normal mode, DAC output buffer state (setting the ENx bit ON, CL 50 pF, RL = 5 tWAKEUP(3) in the DAC Control Normal mode, DAC output buffer register) until the final OFF, CL 10 pF value of 1LSB is reached PSRR DC VDDA supply rejection ratio Normal mode, DAC output buffer ON, CL 50 pF, RL = 5 DS12923 Rev 1 Unit V k k k s s - 2 5 -80 -28 dB 193/252 228 Electrical characteristics STM32H745xI/G Table 99. DAC characteristics(1)(2) (continued) Symbol Parameter Conditions Min Typ Max Unit MODE<2:0>_V12=100/101 (BUFFER ON) - 0.7 2.6 tSAMP Sampling time in Sample and Hold mode CL=100 nF (code transition between the lowest input code and the highest input code when DAC_OUT reaches the 1LSB final value) MODE<2:0>_V12=110 (BUFFER OFF) - 11.5 18.7 MODE<2:0>_V12=111 (INTERNAL BUFFER OFF) - 0.3 0.6 s ms CIint Internal sample and hold capacitor - 1.8 2.2 2.6 pF tTRIM Middle code offset trim time Minimum time to verify the each code 50 - - s Voffset Middle code offset for 1 trim code step VREF+ = 3.6 V - 850 - VREF+ = 1.8 V - 425 - No load, middle code (0x800) - 360 - No load, worst code (0xF1C) - 490 - No load, middle/wor st code (0x800) - 20 - - 360*TON/ (TON+TOFF) - No load, middle code (0x800) - 170 - No load, worst code (0xF1C) - 170 - No load, middle/wor st code (0x800) - 160 - Sample and Hold mode, Buffer ON, CSH=100 nF (worst code) - 170*TON/ (TON+TOFF) - Sample and Hold mode, Buffer OFF, CSH=100 nF (worst code) - 160*TON/ (TON+TOFF) - DAC output buffer ON IDDA(DAC) DAC quiescent consumption from VDDA DAC output buffer OFF Sample and Hold mode, CSH=100 nF DAC output buffer ON IDDV(DAC) DAC consumption from VREF+ DAC output buffer OFF 1. Guaranteed by design unless otherwise specified. 194/252 DS12923 Rev 1 (4) (4) (4) V A STM32H745xI/G Electrical characteristics 2. TBD stands for "to be defined". 3. In buffered mode, the output can overshoot above the final value for low input code (starting from the minimum value). 4. TON is the refresh phase duration, while TOFF is the hold phase duration. Refer to the product reference manual for more details. Table 100. DAC accuracy(1) Symbol Parameter Conditions Min Typ Max DNL Differential non linearity(2) DAC output buffer ON -2 - 2 DAC output buffer OFF -2 - 2 - Monotonicity 10 bits - - - DAC output buffer ON, CL 50 pF, RL 5 -4 - 4 DAC output buffer OFF, CL 50 pF, no RL -4 - 4 VREF+ = 3.6 V - - 15 VREF+ = 1.8 V - - 30 DAC output buffer OFF, CL 50 pF, no RL - - 8 DAC output buffer OFF, CL 50 pF, no RL - - 5 VREF+ = 3.6 V - - 6 VREF+ = 1.8 V - - 7 DAC output buffer ON,CL 50 pF, RL 5 - - 1 DAC output buffer OFF, CL 50 pF, no RL - - 1 DAC output buffer ON,CL 50 pF, RL 5 , 1 kHz, BW = 500 KHz - 67.8 - DAC output buffer OFF, CL 50 pF, no RL,1 kHz, BW = 500 KHz - 67.8 - DAC output buffer ON, CL 50 pF, RL 5 , 1 kHz - -78.6 - DAC output buffer OFF, CL 50 pF, no RL, 1 kHz - -78.6 - DAC output buffer ON, CL 50 pF, RL 5 , 1 kHz - 67.5 - DAC output buffer OFF, CL 50 pF, no RL, 1 kHz - 67.5 - INL Offset Integral non linearity(3) Offset error at code 0x800 (3) Offset1 Offset error at code 0x001(4) OffsetCal Offset error at code 0x800 after factory calibration Gain SNR THD SINAD Gain error(5) Signal-to-noise ratio(6) Total harmonic distortion(6) Signal-to-noise and distortion ratio(6) DAC output buffer ON, CL 50 pF, RL 5 DAC output buffer ON, CL 50 pF, RL 5 DS12923 Rev 1 Unit LSB - LSB LSB LSB LSB % dB dB dB 195/252 228 Electrical characteristics STM32H745xI/G Table 100. DAC accuracy(1) (continued) Symbol ENOB Parameter Effective number of bits Conditions Min Typ Max DAC output buffer ON, CL 50 pF, RL 5 , 1 kHz - 10.9 - DAC output buffer OFF, CL 50 pF, no RL, 1 kHz - Unit bits 10.9 - 1. Guaranteed by characterization. 2. Difference between two consecutive codes minus 1 LSB. 3. Difference between the value measured at Code i and the value measured at Code i on a line drawn between Code 0 and last Code 4095. 4. Difference between the value measured at Code (0x001) and the ideal value. 5. Difference between the ideal slope of the transfer function and the measured slope computed from code 0x000 and 0xFFF when the buffer is OFF, and from code giving 0.2 V and (VREF+ - 0.2 V) when the buffer is ON. 6. Signal is -0.5dBFS with Fsampling=1 MHz. Figure 46. 12-bit buffered /non-buffered DAC Buffered/Non-buffered DAC Buffer(1) RL DAC_OUTx 12-bit digital to analog converter CL ai17157V3 1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the DAC_CR register. 196/252 DS12923 Rev 1 STM32H745xI/G 6.3.23 Electrical characteristics Voltage reference buffer characteristics Table 101. VREFBUF characteristics(1) Symbol Parameter Conditions Normal mode VDDA Analog supply voltage Degraded mode Normal mode VREFBUF _OUT Voltage Reference Buffer Output, at 30 C, Iload= 100 A Degraded Min Typ Max VSCALE = 000 2.8 3.3 3.6 VSCALE = 001 2.4 - 3.6 VSCALE = 010 2.1 - 3.6 VSCALE = 011 1.8 - 3.6 VSCALE = 000 1.62 - 2.80 VSCALE = 001 1.62 - 2.40 VSCALE = 010 1.62 - 2.10 VSCALE = 011 1.62 - 1.80 VSCALE = 000 2.498 2.5 2.5035 VSCALE = 001 2.046 2.049 2.052 VSCALE = 010 1.801 1.804 1.806 VSCALE = 011 1.4995 1.5015 1.504 VSCALE = 000 VDDA- 150 mV - VDDA VSCALE = 001 VDDA- 150 mV - VDDA VSCALE = 010 VDDA- 150 mV - VDDA VSCALE = 011 VDDA- 150 mV - VDDA mode(2) Unit V TRIM Trim step resolution - - - 0.05 0.1 % CL Load capacitor - - 0.5 1 1.50 uF esr Equivalent Serial Resistor of CL - - - - 2 Iload Static load current - - - - 4 mA Iline_reg Line regulation 2.8 V VDDA 3.6 V Iload = 500 A - 200 - Iload = 4 mA - 100 - Iload_reg Load regulation 500 A ILOAD 4 mA Normal Mode - 50 - ppm/ mA Tcoeff Temperature coefficient - - Tcoeff VREFINT + 100 ppm/ C PSRR Power supply rejection -40 C < TJ < +125 C DC - - 60 - 100KHz - - 40 - DS12923 Rev 1 ppm/V dB 197/252 228 Electrical characteristics STM32H745xI/G Table 101. VREFBUF characteristics(1) (continued) Symbol tSTART IINRUSH IDDA(VRE FBUF) Parameter Conditions Start-up time Typ Max CL=0.5 F - - 300 - CL=1 F - - 500 - CL=1.5 F - - 650 - - 8 - Control of maximum DC current drive on VREFBUF_OUT during startup phase(3) - VREFBUF consumption from VDDA Min Unit s mA ILOAD = 0 A - - 15 25 ILOAD = 500 A - - 16 30 ILOAD = 4 mA - - 32 50 A 1. Guaranteed by design. 2. In degraded mode, the voltage reference buffer cannot accurately maintain the output voltage (VDDA-drop voltage). 3. To properly control VREFBUF IINRUSH current during the startup phase and the change of scaling, VDDA voltage should be in the range of 1.8 V-3.6 V, 2.1 V-3.6 V, 2.4 V-3.6 V and 2.8 V-3.6 V for VSCALE = 011, 010, 001 and 000, respectively. 6.3.24 Temperature sensor characteristics Table 102. Temperature sensor characteristics Symbol Parameter TL(1) (2) Avg_Slope V30(3) tstart_run tS_temp (1) Isens(1) Isensbuf(1) Min Typ Max Unit VSENSE linearity with temperature - - 3 C Average slope - 2 - mV/C Voltage at 30C 5 C - 0.62 - V Startup time in Run mode (buffer startup) - - 25.2 ADC sampling time when reading the temperature 9 - - Sensor consumption - 0.18 0.31 Sensor buffer consumption - 3.8 6.5 s A 1. Guaranteed by design. 2. Guaranteed by characterization. 3. Measured at VDDA = 3.3 V 10 mV. The V30 ADC conversion result is stored in the TS_CAL1 byte. Table 103. Temperature sensor calibration values Symbol 198/252 Parameter Memory address TS_CAL1 Temperature sensor raw data acquired value at 30 C, VDDA=3.3 V 0x1FF1 E820 -0x1FF1 E821 TS_CAL2 Temperature sensor raw data acquired value at 110 C, VDDA=3.3 V 0x1FF1 E840 - 0x1FF1 E841 DS12923 Rev 1 STM32H745xI/G 6.3.25 Electrical characteristics Temperature and VBAT monitoring Table 104. VBAT monitoring characteristics Symbol Parameter Min Typ Max Unit R Resistor bridge for VBAT - 26 - K Q Ratio on VBAT measurement - 4 - - -10 - +10 % s (1) Error on Q Er tS_vbat(1) ADC sampling time when reading VBAT input 9 - - VBAThigh High supply monitoring - 3.55 - VBATlow Low supply monitoring - 1.36 - V 1. Guaranteed by design. Table 105. VBAT charging characteristics Symbol RBC Parameter Battery charging resistor Condition Min Typ Max VBRS in PWR_CR3= 0 - 5 - 1.5 - VBRS in PWR_CR3= 1 Unit K Table 106. Temperature monitoring characteristics Symbol 6.3.26 Parameter Min Typ Max TEMPhigh High temperature monitoring - 117 - TEMPlow Low temperature monitoring - -25 - Unit C Voltage booster for analog switch Table 107. Voltage booster for analog switch characteristics(1) Symbol VDD Parameter Condition Min Typ Max Unit - 1.62 2.6 3.6 V - - - 50 s 1.62 V VDD 2.7 V - - 125 2.7 V < VDD < 3.6 V - - 250 Supply voltage tSU(BOOST) Booster startup time IDD(BOOST) Booster consumption A 1. Guaranteed by characterization results. DS12923 Rev 1 199/252 228 Electrical characteristics 6.3.27 STM32H745xI/G Comparator characteristics Table 108. COMP characteristics(1) Symbol Conditions Min Typ Max Analog supply voltage - 1.62 3.3 3.6 VIN Comparator input voltage range - 0 - VDDA V VBG Scaler input voltage - VSC Scaler offset voltage - - 5 10 mV BRG_EN=0 (bridge disable) - 0.2 0.3 BRG_EN=1 (bridge enable) - 0.8 1 - - 140 250 High-speed mode - 2 5 Medium mode - 5 20 Ultra-low-power mode - 15 80 High-speed mode - 50 80 Medium mode - 0.5 1.2 Ultra-low-power mode - 2.5 7 High-speed mode - 50 120 Medium mode - 0.5 1.2 Ultra-low-power mode - 2.5 7 Full common mode range - 5 20 No hysteresis - 0 - Low hysteresis 5 10 22 Medium hysteresis 8 20 37 High hysteresis 16 30 52 Static - 400 600 With 50 kHz 100 mV overdrive square signal - 800 - Static - 5 7 - 6 - Static - 70 100 With 50 kHz 100 mV overdrive square signal - 75 - VDDA IDDA(SCALER) Parameter Scaler static consumption from VDDA tSTART_SCALER Scaler startup time tSTART Comparator startup time to reach propagation delay specification Propagation delay for 200 mV step with 100 mV overdrive tD(3) Voffset Vhys Propagation delay for step > 200 mV with 100 mV overdrive only on positive inputs Comparator offset error Comparator hysteresis Ultra-lowpower mode IDDA(COMP) Comparator consumption from VDDA Medium mode With 50 kHz 100 mV overdrive square signal High-speed mode 1. Guaranteed by design, unless otherwise specified. 2. Refer to Table 30: Embedded reference voltage. 200/252 DS12923 Rev 1 Unit (2) A s s ns s ns s mV mV nA A STM32H745xI/G Electrical characteristics 3. Guaranteed by characterization results. 6.3.28 Operational amplifier characteristics Table 109. Operational amplifier characteristics Symbol Parameter Conditions Min Typ Max VDDA Analog supply voltage Range - 2 3.3 3.6 CMIR Common Mode Input Range - 0 - VDDA 25C, no load on output - - 1.5 Unit V VIOFFSET Input offset voltage All voltages and temperature, no load - - 2.5 VIOFFSET Input offset voltage drift - - 3.0 - TRIMOFFSETP TRIMLPOFFSETP Offset trim step at low common input voltage (0.1*VDDA) - - 1.1 1.5 TRIMOFFSETN TRIMLPOFFSETN Offset trim step at high common input voltage (0.9*VDDA) - - 1.1 1.5 ILOAD Drive current - - - 500 ILOAD_PGA Drive current in PGA mode - - - 270 CLOAD Capacitive load - - - 50 pF CMRR Common mode rejection ratio - - 80 - dB PSRR Power supply rejection ratio CLOAD 50pf / RLOAD 4 k(1) at 1 kHz, Vcom=VDDA/2 50 66 - dB GBW Gain bandwidth for high supply range 200 mV Output dynamic range VDDA - 200 mV 4 7.3 12.3 MHz SR Slew rate (from 10% and 90% of output voltage) Normal mode - 3 - High-speed mode - 30 - AO Open loop gain 200 mV Output dynamic range VDDA - 200 mV 59 90 129 dB m Phase margin - - 55 - GM Gain margin - - 12 - dB VOHSAT High saturation voltage Iload=max or RLOAD=min, Input at VDDA VDDA -100 mV - - Low saturation voltage Iload=max or RLOAD=min, Input at 0 V - - VOLSAT mV V/C mV DS12923 Rev 1 A V/s mV 100 201/252 228 Electrical characteristics STM32H745xI/G Table 109. Operational amplifier characteristics (continued) Symbol tWAKEUP Parameter Wake up time from OFF state Non inverting gain error value PGA gain Inverting gain error value External non-inverting gain error value R2/R1 internal resistance values in non-inverting PGA mode(2) Rnetwork R2/R1 internal resistance values in inverting PGA mode(2) Delta R 202/252 Resistance variation (R1 or R2) Conditions Min Typ Max 0.8 3.2 Normal mode CLOAD 50pf, RLOAD 4 k, follower configuration - High speed mode CLOAD 50pf, RLOAD 4 k, follower configuration - 0.9 2.8 PGA gain = 2 -1 - 1 PGA gain = 4 -2 - 2 PGA gain = 8 -2.5 - 2.5 PGA gain = 16 -3 - 3 PGA gain = 2 -1 - 1 PGA gain = 4 -1 - 1 PGA gain = 8 -2 - 2 PGA gain = 16 -3 - 3 PGA gain = 2 -1 - 1 PGA gain = 4 -3 - 3 PGA gain = 8 -3.5 - 3.5 PGA gain = 16 -4 - 4 PGA Gain=2 - 10/10 - PGA Gain=4 - 30/10 - PGA Gain=8 - 70/10 - PGA Gain=16 - 150/10 - PGA Gain = -1 - 10/10 - PGA Gain = -3 - 30/10 - PGA Gain = -7 - 70/10 - PGA Gain = -15 - 150/10 - - -15 - 15 DS12923 Rev 1 Unit s % k/ k % STM32H745xI/G Electrical characteristics Table 109. Operational amplifier characteristics (continued) Symbol Parameter Conditions Min Typ Max Gain=2 - GBW/2 - Gain=4 - GBW/4 - Gain=8 - GBW/8 - Gain=16 - GBW/16 - Gain = -1 - 5.00 - Gain = -3 - 3.00 - Gain = -7 - 1.50 - Gain = -15 - 0.80 - - 140 - - 55 - - 570 1000 - 610 1200 PGA bandwidth for different non inverting gain PGA BW PGA bandwidth for different inverting gain en Voltage noise density IDDA(OPAMP) OPAMP consumption from VDDA at 1 KHz at 10 KHz Normal mode Highspeed mode output loaded with 4 k no Load, quiescent mode, follower Unit MHz MHz nV/ Hz A 1. RLOAD is the resistive load connected to VSSA or to VDDA. 2. R2 is the internal resistance between the OPAMP output and th OPAMP inverting input. R1 is the internal resistance between the OPAMP inverting input and ground. PGA gain = 1 + R2/R1. 6.3.29 Digital filter for Sigma-Delta Modulators (DFSDM) characteristics Unless otherwise specified, the parameters given in Table 110 for DFSDM are derived from tests performed under the ambient temperature, fPCLKx frequency and supply voltage conditions summarized in Table 23: General operating conditions. * Output speed is set to OSPEEDRy[1:0] = 10 * Capacitive load CL = 30 pF * Measurement points are done at CMOS levels: 0.5VDD * VOS level set to VOS1 Refer to Section 6.3.16: I/O port characteristics for more details on the input/output alternate function characteristics (DiFSDM_CKINx, DFSDM_DATINx, DFSDM_CKOUT for DFSDM). DS12923 Rev 1 203/252 228 Electrical characteristics STM32H745xI/G Table 110. DFSDM measured timing 1.62-3.6 V Symbol Parameter Conditions Min Typ Max fDFSDMCLK DFSDM clock 1.62 < VDD < 3.6 V - - 133 SPI mode (SITP[1:0]=0,1), External clock mode (SPICKSEL[1:0]=0), 1.62 < VDD < 3.6 V - - 20 SPI mode (SITP[1:0]=0,1), External clock mode (SPICKSEL[1:0]=0), 2.7 < VDD < 3.6 V - - 20 SPI mode (SITP[1:0]=0,1), Internal clock mode (SPICKSEL[1:0]0), 1.62 < VDD < 3.6 V - - 20 SPI mode (SITP[1:0]=0,1), Internal clock mode (SPICKSEL[1:0]0), 2.7 < VDD < 3.6 V - - 20 Output clock frequency 1.62 < VDD < 3.6 V - - 20 Output clock frequency duty cycle 1.62 < VDD < 3.6 V 45 50 55 twh(CKIN) twl(CKIN) Input clock high and low time SPI mode (SITP[1:0]=0,1), External clock mode (SPICKSEL[1:0]=0), 1.62 < VDD < 3.6 V TCKIN/2-0.5 TCKIN/2 - tsu Data input setup time SPI mode (SITP[1:0]=0,1), External clock mode (SPICKSEL[1:0]=0), 1.62 < VDD < 3.6 V 1.5 - - Data input hold time SPI mode (SITP[1:0]=0,1), External clock mode (SPICKSEL[1:0]=0), 1.62 < VDD < 3.6 V 0.5 fCKIN (1/TCKIN) fCKOUT DuCyCKOU T th Input clock frequency MH z DS12923 Rev 1 % ns Manchester Manchester mode (SITP[1:0]=2,3), (CKOUTDIV+1) data period Internal clock mode TManchester * TDFSDMCLK (recovered (SPICKSEL[1:0]0), clock period) 1.62 < VDD < 3.6 V 204/252 Unit - - - (2*CKOUTDIV) * TDFSDMCLK STM32H745xI/G Electrical characteristics DFSDM_CKINy DFSDM_DATINy DFSDM_CKOUT (SPICKSEL=0) tsu th twl twh tr tf tr tf SITP = 00 tsu th SITP = 01 SPICKSEL=3 SPICKSEL=2 SPICKSEL=1 tsu DFSDM_DATINy SPI timing : SPICKSEL = 1, 2, 3 SPI timing : SPICKSEL = 0 Figure 47. Channel transceiver timing diagrams th twl twh SITP = 0 tsu th SITP = 1 DFSDM_DATINy Manchester timing SITP = 2 SITP = 3 recovered clock recovered data 0 0 1 1 0 MS30766V2 DS12923 Rev 1 205/252 228 Electrical characteristics 6.3.30 STM32H745xI/G Camera interface (DCMI) timing specifications Unless otherwise specified, the parameters given in Table 111 for DCMI are derived from tests performed under the ambient temperature, fHCLK frequency and VDD supply voltage summarized in Table 23: General operating conditions, with the following configuration: * DCMI_PIXCLK polarity: falling * DCMI_VSYNC and DCMI_HSYNC polarity: high * Data formats: 14 bits * Capacitive load CL=30 pF * Measurement points are done at CMOS levels: 0.5VDD * VOS level set to VOS1 Table 111. DCMI characteristics(1) Symbol Parameter Min Max Unit - Frequency ratio DCMI_PIXCLK/fHCLK - 0.4 - DCMI_PIXCLK Pixel Clock input - 80 MHz Dpixel Pixel Clock input duty cycle 30 70 % tsu(DATA) Data input setup time 3 - th(DATA) Data hold time 1 - tsu(HSYNC), tsu(VSYNC) DCMI_HSYNC/ DCMI_VSYNC input setup time 2 - ns th(HSYNC), th(VSYNC) DCMI_HSYNC/ DCMI_VSYNC input hold time 1 - - - 1. Guaranteed by characterization results. Figure 48. DCMI timing diagram 1/DCMI_PIXCLK DCMI_PIXCLK tsu(HSYNC) th(HSYNC) DCMI_HSYNC tsu(VSYNC) th(HSYNC) DCMI_VSYNC tsu(DATA) th(DATA) DATA[0:13] MS32414V2 206/252 DS12923 Rev 1 STM32H745xI/G 6.3.31 Electrical characteristics LCD-TFT controller (LTDC) characteristics Unless otherwise specified, the parameters given in Table 112 for LCD-TFT are derived from tests performed under the ambient temperature, fHCLK frequency and VDD supply voltage summarized in Table 23: General operating conditions, with the following configuration: * LCD_CLK polarity: high * LCD_DE polarity: low * LCD_VSYNC and LCD_HSYNC polarity: high * Pixel formats: 24 bits * Output speed is set to OSPEEDRy[1:0] = 11 * Capacitive load CL=30 pF * Measurement points are done at CMOS levels: 0.5VDD * IO Compensation cell activated. * HSLV activated when VDD 2.7 V * VOS level set to VOS1 Table 112. LTDC characteristics(1) Symbol fCLK Parameter Min 2.7<VDD<3.6 V 20pF LTDC clock output frequency 2.7<VDD<3.6 V Max 150 - 1.62<VDD<3.6 V 133 LTDC clock output duty cycle 45 55 tw(CLKH), tw(CLKL) Clock High time, low time tw(CLK)//2-0.5 tw(CLK)//2+0.5 th(DATA) tv(DATA) tv(HSYNC), tv(VSYNC), tv(DE) th(HSYNC), th(VSYNC), th(DE) 2.7<VDD<3.6 V Data output valid time 1.62<VDD<3.6 V Data output hold time HSYNC/VSYNC/DE output valid time - 0.5 % - 5 0 - 2.7<VDD<3.6 V - 0.5 1.62<VDD<3.6 V - 5 0 - HSYNC/VSYNC/DE output hold time MHz 90 DCLK tv(DATA) Unit 1. Guaranteed by characterization results. DS12923 Rev 1 207/252 228 Electrical characteristics STM32H745xI/G Figure 49. LCD-TFT horizontal timing diagram tCLK LCD_CLK LCD_VSYNC tv(HSYNC) tv(HSYNC) LCD_HSYNC th(DE) tv(DE) LCD_DE tv(DATA) LCD_R[0:7] LCD_G[0:7] LCD_B[0:7] Pixel Pixel 1 2 Pixel N th(DATA) HSYNC Horizontal width back porch Active width Horizontal back porch One line MS32749V1 Figure 50. LCD-TFT vertical timing diagram tCLK LCD_CLK tv(VSYNC) tv(VSYNC) LCD_VSYNC LCD_R[0:7] LCD_G[0:7] LCD_B[0:7] M lines data VSYNC Vertical width back porch Active width Vertical back porch One frame MS32750V1 208/252 DS12923 Rev 1 STM32H745xI/G 6.3.32 Electrical characteristics Timer characteristics The parameters given in Table 113 are guaranteed by design. Refer to Section 6.3.16: I/O port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output). Table 113. TIMx characteristics(1)(2) Symbol tres(TIM) fEXT ResTIM tMAX_COUNT Conditions(3) Min Max Unit AHB/APBx prescaler=1 or 2 or 4, fTIMxCLK = 240 MHz 1 - tTIMxCLK AHB/APBx prescaler>4, fTIMxCLK = 120 MHz 1 - tTIMxCLK Timer external clock frequency on CH1 to CH4 f TIMxCLK = 240 MHz 0 fTIMxCLK/2 MHz Timer resolution - 16/32 bit - 65536 x 65536 tTIMxCLK Parameter Timer resolution time Maximum possible count with 32-bit counter - 1. TIMx is used as a general term to refer to the TIM1 to TIM17 timers. 2. Guaranteed by design. 3. The maximum timer frequency on APB1 or APB2 is up to 240 MHz, by setting the TIMPRE bit in the RCC_CFGR register, if APBx prescaler is 1 or 2 or 4, then TIMxCLK = rcc_hclk1, otherwise TIMxCLK = 4x Frcc_pclkx_d2. 6.3.33 Communication interfaces I2C interface characteristics The I2C interface meets the timings requirements of the I2C-bus specification and user manual revision 03 for: * Standard-mode (Sm): with a bit rate up to 100 kbit/s * Fast-mode (Fm): with a bit rate up to 400 kbit/s * Fast-mode Plus (Fm+): with a bit rate up to 1 Mbit/s. The I2C timings requirements are guaranteed by design when the I2C peripheral is properly configured (refer to RM0399 reference manual) and when the i2c_ker_ck frequency is greater than the minimum shown in the table below: DS12923 Rev 1 209/252 228 Electrical characteristics STM32H745xI/G Table 114. Minimum i2c_ker_ck frequency in all I2C modes Symbol Parameter Condition Standard-mode Fast-mode f(I2CCLK) I2CCLK frequency Fast-mode Plus Min - 2 Analog Filtre ON DNF=0 8 Analog Filtre OFF DNF=1 9 Analog Filtre ON DNF=0 17 Analog Filtre OFF DNF=1 16 Unit MHz - The SDA and SCL I/O requirements are met with the following restrictions: * The SDA and SCL I/O pins are not "true" open-drain. When configured as open-drain, the PMOS connected between the I/O pin and VDDIOx is disabled, but still present. * The 20 mA output drive requirement in Fast-mode Plus is not supported. This limits the maximum load CLoad supported in Fm+, which is given by these formulas: tr(SDA/SCL)=0.8473xRPxCLoad RP(min)= (VDD-VOL(max))/IOL(max) Where RP is the I2C lines pull-up. Refer to Section 6.3.16: I/O port characteristics for the I2C I/Os characteristics. All I2C SDA and SCL I/Os embed an analog filter. Refer to the table below for the analog filter characteristics: Table 115. I2C analog filter characteristics(1) Symbol Parameter Min Max Unit tAF Maximum pulse width of spikes that are suppressed by analog filter 50(2) 80(3) ns 1. Guaranteed by characterization results. 2. Spikes with widths below tAF(min) are filtered. 3. Spikes with widths above tAF(max) are not filtered. USART interface characteristics Unless otherwise specified, the parameters given in Table 116 for USART are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 23: General operating conditions, with the following configuration: 210/252 * Output speed is set to OSPEEDRy[1:0] = 10 * Capacitive load CL = 30 pF * Measurement points are done at CMOS levels: 0.5VDD * IO Compensation cell activated. * VOS level set to VOS1 DS12923 Rev 1 STM32H745xI/G Electrical characteristics Refer to Section 6.3.16: I/O port characteristics for more details on the input/output alternate function characteristics (NSS, CK, TX, RX for USART). Table 116. USART characteristics(1) Symbol Parameter fCK USART clock frequency tsu(NSS) NSS setup time th(NSS) Min Typ - - Slave mode tker+1 - - NSS hold time Slave mode 2 - - tw(SCKH), tw(SCKL) CK high and low time Master mode 1/fCK/2-2 1/fCK/2 1/fCK/2+2 tsu(RX) Data input setup time Master mode tker+6 - - Slave mode 1.5 - - th(RX) Data input hold time Master mode 0 - - Slave mode 1.5 - - Slave mode - 12 20 Master mode - 0.5 1 Slave mode 9 - - Master mode 0 - - tv(TX) Data output valid time th(TX) Data output hold time Conditions Master mode Slave mode Max 12.5 25 Unit MHz - ns 1. Guaranteed by characterization results. DS12923 Rev 1 211/252 228 Electrical characteristics STM32H745xI/G Figure 51. USART timing diagram in Master mode High NSS input SCK Output CPHA= 0 CPOL=0 SCK Output tc(SCK) CPHA=1 CPOL=0 CPHA= 0 CPOL=1 CPHA=1 CPOL=1 tsu(MI) MISO INP UT tw(SCKH) tw(SCKL) tr(SCK) tf(SCK) BIT6 IN MSB IN LSB IN th(MI) MOSI OUTPUT B I T1 OUT MSB OUT tv(MO) LSB OUT th(MO) ai14136c 1. Measurement points are done at 0.5VDD and with external CL = 30 pF. Figure 52. USART timing diagram in Slave mode NSS input tc(SCK) tsu(NSS) th(NSS) tw(SCKH) tr(SCK) SCK input CPHA=0 CPOL=0 CPHA=0 CPOL=1 ta(SO) tw(SCKL) tv(SO) First bit OUT MISO output th(SO) Next bits OUT tf(SCK) tdis(SO) Last bit OUT th(SI) tsu(SI) MOSI input First bit IN Next bits IN Last bit IN MSv41658V1 212/252 DS12923 Rev 1 STM32H745xI/G Electrical characteristics SPI interface characteristics Unless otherwise specified, the parameters given in Table 117 for SPI are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 23: General operating conditions, with the following configuration: * Output speed is set to OSPEEDRy[1:0] = 11 * Capacitive load CL = 30 pF * Measurement points are done at CMOS levels: 0.5VDD * IO Compensation cell activated. * HSLV activated when VDD 2.7 V * VOS level set to VOS1 Refer to Section 6.3.16: I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO for SPI). Table 117. SPI characteristics(1) Symbol fSCK Parameter SPI clock frequency Conditions Min Typ Max Master mode 1.62<VDD<3.6 V SPI1, 2, 3 80 Master mode 2.7<VDD<3.6 V SPI1, 2, 3 100 Master mode 1.62<VDD<3.6 V SPI4, 5, 6 - - 50 Slave receiver mode 1.62<VDD<3.6 V 100 Slave mode transmitter/full duplex 2.7<VDD<3.6 V 31 Slave mode transmitter/full duplex 1.62 <VDD<3.6 V 29 tsu(NSS) NSS setup time Slave mode 2 - - th(NSS) NSS hold time Slave mode 1 - - tw(SCKH), tw(SCKL) SCK high and low time Master mode TPCLK-2 TPCLK TPCLK+2 DS12923 Rev 1 Unit MHz - 213/252 228 Electrical characteristics STM32H745xI/G Table 117. SPI characteristics(1) (continued) Symbol Parameter tsu(MI) Conditions Data input setup time tsu(SI) th(MI) Data input hold time th(SI) Min Typ Max Master mode 1 - - Slave mode 1 - - Master mode 4 - - Slave mode 2 - - ta(SO) Data output access time Slave mode 9 13 27 tdis(SO) Data output disable time Slave mode 0 1 5 Slave mode 2.7<VDD<3.6 V - 12.5 16 Slave mode 1.62<VDD<3.6 V - 12.5 17 tv(MO) Master mode - 1 3 th(SO) Slave mode 1.62<VDD<3.6 V 10 - - Master mode 0 - - tv(SO) Data output valid time Data output hold time th(MO) Unit ns 1. Guaranteed by characterization results. Figure 53. SPI timing diagram - slave mode and CPHA = 0 NSS input tc(SCK) SCK input tsu(NSS) th(NSS) tw(SCKH) tr(SCK) CPHA=0 CPOL=0 CPHA=0 CPOL=1 ta(SO) tw(SCKL) MISO output tv(SO) First bit OUT th(SO) Next bits OUT tf(SCK) tdis(SO) Last bit OUT th(SI) tsu(SI) MOSI input First bit IN Next bits IN Last bit IN MSv41658V1 214/252 DS12923 Rev 1 STM32H745xI/G Electrical characteristics Figure 54. SPI timing diagram - slave mode and CPHA = 1(1) NSS input tc(SCK) tsu(NSS) tw(SCKH) ta(SO) tw(SCKL) tf(SCK) th(NSS) SCK input CPHA=1 CPOL=0 CPHA=1 CPOL=1 tv(SO) th(SO) First bit OUT MISO output tsu(SI) tr(SCK) Next bits OUT tdis(SO) Last bit OUT th(SI) MOSI input First bit IN Next bits IN Last bit IN MSv41659V1 1. Measurement points are done at 0.5VDD and with external CL = 30 pF. Figure 55. SPI timing diagram - master mode(1) High NSS input SCK Output CPHA= 0 CPOL=0 SCK Output tc(SCK) CPHA=1 CPOL=0 CPHA= 0 CPOL=1 CPHA=1 CPOL=1 tsu(MI) MISO INP UT tw(SCKH) tw(SCKL) MSB IN tr(SCK) tf(SCK) BIT6 IN LSB IN th(MI) MOSI OUTPUT MSB OUT tv(MO) B I T1 OUT LSB OUT th(MO) ai14136c 1. Measurement points are done at 0.5VDD and with external CL = 30 pF. DS12923 Rev 1 215/252 228 Electrical characteristics STM32H745xI/G I2S Interface characteristics Unless otherwise specified, the parameters given in Table 118 for I2S are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 23: General operating conditions, with the following configuration: * Output speed is set to OSPEEDRy[1:0] = 10 * Capacitive load CL = 30 pF * Measurement points are done at CMOS levels: 0.5VDD * IO Compensation cell activated. * HSLV activated when VDD 2.7 V * VOS level set to VOS1 Refer to Section 6.3.16: I/O port characteristics for more details on the input/output alternate function characteristics (CK,SD,WS). Table 118. I2S dynamic characteristics(1) Symbol fMCK Parameter I2S Conditions main clock output Min Max Unit 256x8K 256FS MHz Master data - 64FS Slave data - 64FS - fCK I2S clock frequency tv(WS) WS valid time Master mode - 3 th(WS) WS hold time Master mode 0 - tsu(WS) WS setup time Slave mode 1 - th(WS) WS hold time Slave mode 1 - Master receiver 1 - Slave receiver 1 - Master receiver 4 - Slave receiver 2 - Slave transmitter (after enable edge) - 17 tv(SD_MT) Master transmitter (after enable edge) - 3 th(SD_ST) Slave transmitter (after enable edge) 9 - Master transmitter (after enable edge) 0 - tsu(SD_MR) tsu(SD_SR) th(SD_MR) th(SD_SR) Data input setup time Data input hold time tv(SD_ST) Data output valid time Data output hold time th(SD_MT) 1. Guaranteed by characterization results. 216/252 DS12923 Rev 1 MHz ns STM32H745xI/G Electrical characteristics Figure 56. I2S slave timing diagram (Philips protocol)(1) 1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. Figure 57. I2S master timing diagram (Philips protocol)(1) 1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. DS12923 Rev 1 217/252 228 Electrical characteristics STM32H745xI/G SAI characteristics Unless otherwise specified, the parameters given in Table 119 for SAI are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 23: General operating conditions, with the following configuration: * Output speed is set to OSPEEDRy[1:0] = 10 * Capacitive load CL = 30 pF * IO Compensation cell activated. * Measurement points are done at CMOS levels: 0.5VDD * VOS level set to VOS1. Refer to Section 6.3.16: I/O port characteristics for more details on the input/output alternate function characteristics (SCK,SD,WS). Table 119. SAI characteristics(1) 218/252 Symbol Parameter Conditions Min Max fMCK SAI Main clock output - 256x8K 256xFS fCK SAI clock frequency(2) Master Data: 32 bits - 128xFS(3) MHz Slave Data: 32 bits - 128xFS(3) DS12923 Rev 1 Unit STM32H745xI/G Electrical characteristics Table 119. SAI characteristics(1) (continued) Symbol Parameter Conditions Min Max Master mode 2.7VDD3.6 - 13 Master mode 1.62VDD3.6 - 20 FS hold time Master mode 8 - FS setup time Slave mode 1 - FS hold time Slave mode 1 - Master receiver 0.5 - Slave receiver 1 - Master receiver 3.5 - Slave receiver 2 - Slave transmitter (after enable edge) 2.7VDD3.6 - 14 Slave transmitter (after enable edge) 1.62VDD3.6 - 20 Slave transmitter (after enable edge) 9 - Master transmitter (after enable edge) 2.7VDD3.6 - 12 Master transmitter (after enable edge) 1.62VDD3.6 - 19 Master transmitter (after enable edge) 7.5 - tv(FS) FS valid time tsu(FS) th(FS) tsu(SD_A_MR) tsu(SD_B_SR) th(SD_A_MR) th(SD_B_SR) tv(SD_B_ST) th(SD_B_ST) tv(SD_A_MT) th(SD_A_MT) Data input setup time Data input hold time Data output valid time Data output hold time Data output valid time Data output hold time Unit ns 1. Guaranteed by characterization results. 2. APB clock frequency must be at least twice SAI clock frequency. 3. With FS=192 kHz. DS12923 Rev 1 219/252 228 Electrical characteristics STM32H745xI/G Figure 58. SAI master timing waveforms 1/fSCK SAI_SCK_X th(FS) SAI_FS_X (output) tv(FS) th(SD_MT) tv(SD_MT) SAI_SD_X (transmit) Slot n tsu(SD_MR) Slot n+2 th(SD_MR) SAI_SD_X (receive) Slot n MS32771V1 Figure 59. SAI slave timing waveforms 1/fSCK SAI_SCK_X tw(CKH_X) SAI_FS_X (input) tw(CKL_X) th(FS) tsu(FS) th(SD_ST) tv(SD_ST) SAI_SD_X (transmit) Slot n tsu(SD_SR) SAI_SD_X (receive) Slot n+2 th(SD_SR) Slot n MS32772V1 MDIO characteristics Table 120. MDIO Slave timing parameters 220/252 Symbol Parameter Min Typ Max Unit FMDC Management Data Clock - - 30 MHz td(MDIO) Management Data Iput/output output valid time 8 10 19 tsu(MDIO) Management Data Iput/output setup time 1 - - th(MDIO) Management Data Iput/output hold time 1 - - DS12923 Rev 1 ns STM32H745xI/G Electrical characteristics Figure 60. MDIO Slave timing diagram tMDC) td(MDIO) tsu(MDIO) th(MDIO) MSv40460V1 SD/SDIO MMC card host interface (SDMMC) characteristics Unless otherwise specified, the parameters given in Table 121 and Table 122 for SDIO are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage summarized in Table 23: General operating conditions, with the following configuration: * Output speed is set to OSPEEDRy[1:0] = 0x11 * Capacitive load CL=30 pF * Measurement points are done at CMOS levels: 0.5VDD * IO Compensation cell activated. * HSLV activated when VDD 2.7 V * VOS level set to VOS1 Refer to Section 6.3.16: I/O port characteristics for more details on the input/output characteristics. Table 121. Dynamics characteristics: SD / MMC characteristics, VDD=2.7 to 3.6 V(1)(2) Symbol Parameter Conditions Min Typ Max Unit fPP Clock frequency in data transfer mode - 0 - 133 MHz - SDIO_CK/fPCLK2 frequency ratio - - - 8/3 - tW(CKL) Clock low time fPP =52MHz 8.5 9.5 - tW(CKH) Clock high time fPP =52MHz 8.5 9.5 - ns CMD, D inputs (referenced to CK) in eMMC legacy/SDR/DDR and SD HS/SDR(3)/DDR(3) mode tISU Input setup time HS - 1.5 - - tIH Input hold time HS - 1.5 - - tIDW(4) Input valid window (variable window) - 3 - - ns - CMD, D outputs (referenced to CK) in eMMC legacy/SDR/DDR and SD HS/SDR/DDR(3) mode tOV Output valid time HS - - 3.5 5 tOH Output hold time HS - 2 - - DS12923 Rev 1 ns 221/252 228 Electrical characteristics STM32H745xI/G Table 121. Dynamics characteristics: SD / MMC characteristics, VDD=2.7 to 3.6 V(1)(2) (continued) Symbol Parameter Conditions Min Typ Max Unit CMD, D inputs (referenced to CK) in SD default mode tISUD Input setup time SD - 1.5 - tIHD Input hold time SD - 1.5 - ns CMD, D outputs (referenced to CK) in SD default mode tOVD Output valid default time SD - - 0.5 2 tOHD Output hold default time SD - 0 - - ns 1. Guaranteed by characterization results. 2. Above 100 MHz, CL = 20 pF. 3. An external voltage converter is required to support SD 1.8 V. 4. The minimum window of time where the data needs to be stable for proper sampling in tuning mode. Table 122. Dynamics characteristics: eMMC characteristics VDD=1.71V to 1.9V(1)(2) Symbol Parameter Conditions Min Typ Max Unit fPP Clock frequency in data transfer mode - 0 - 120 MHz - SDIO_CK/fPCLK2 frequency ratio - - - 8/3 - tW(CKL) Clock low time fPP =52 MHz 8.5 9.5 - tW(CKH) Clock high time fPP =52 MHz 8.5 9.5 - ns CMD, D inputs (referenced to CK) in eMMC mode tISU Input setup time HS - 1 - - tIH Input hold time HS - 2.5 - - tIDW(3) Input valid window (variable window) - 3.5 - - ns CMD, D outputs (referenced to CK) in eMMC mode tOVD Output valid time HS - - 5 7 tOHD Output hold time HS - 3 - - 1. Guaranteed by characterization results. 2. CL = 20 pF. 3. The minimum window of time where the data needs to be stable for proper sampling in tuning mode. 222/252 DS12923 Rev 1 ns STM32H745xI/G Electrical characteristics Figure 61. SDIO high-speed mode Figure 62. SD default mode CK tOVD tOHD D, CMD (output) ai14888 Figure 63. DDR mode tr(CK) t(CK) tw(CKH) tw(CKL) tf(CK) Clock tvf(OUT) Data output thr(OUT) D0 tvr(OUT) D1 D2 thf(OUT) D3 tsf(IN) thf(IN) Data input D0 D1 D4 D5 tsr(IN) thr(IN) D2 D3 D4 D5 MSv36879V1 DS12923 Rev 1 223/252 228 Electrical characteristics STM32H745xI/G USB OTG_HS characteristics Unless otherwise specified, the parameters given in Table 123 for ULPI are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage summarized in Table 23: General operating conditions, with the following configuration: * Output speed is set to OSPEEDRy[1:0] = 11 * Capacitive load CL=20 pF * Measurement points are done at CMOS levels: 0.5VDD * IO Compensation cell activated. * VOS level set to VOS1 Refer to Section 6.3.16: I/O port characteristics for more details on the input/output characteristics. Table 123. Dynamics characteristics: USB ULPI(1) Symbol Parameter Condition Min Typ Max tSC Control in (ULPI_DIR , ULPI_NXT) setup time - 2.5 - - tHC Control in (ULPI_DIR, ULPI_NXT) hold time - 2 - - tSD Data in setup time - 2.5 - - tHD Data in hold time - 0 - - 2.7<VDD<3.6 V CL=20 pF - 9 9.5 1.71<VDD<3.6 V CL=15 pF - 9 14 tDC/tDD Control/Datal output delay Unit ns 1. Guaranteed by characterization results. Figure 64. ULPI timing diagram Clock Control In (ULPI_DIR, ULPI_NXT) tSC tHC tSD tHD data In (8-bit) tDC Control out (ULPI_STP) tDC tDD data out (8-bit) ai17361c 224/252 DS12923 Rev 1 STM32H745xI/G Electrical characteristics Ethernet interface characteristics Unless otherwise specified, the parameters given in Table 124, Table 125 and Table 126 for SMI, RMII and MII are derived from tests performed under the ambient temperature, frcc_c_ck frequency and VDD supply voltage conditions summarized in Table 23: General operating conditions, with the following configuration: * Output speed is set to OSPEEDRy[1:0] = 10 * Capacitive load CL=20 pF * Measurement points are done at CMOS levels: 0.5VDD * IO Compensation cell activated. * HSLV activated when VDD 2.7 V * VOS level set to VOS1 Refer to Section 6.3.16: I/O port characteristics for more details on the input/output characteristics: Table 124. Dynamics characteristics: Ethernet MAC signals for SMI (1) Symbol Parameter Min Typ Max tMDC MDC cycle time( 2.5 MHz) 400 400 403 Td(MDIO) Write data valid time 0.5 1.5 4 tsu(MDIO) Read data setup time 12.5 - - th(MDIO) Read data hold time 0 - - Unit ns 1. Guaranteed by characterization results. Figure 65. Ethernet SMI timing diagram tMDC ETH_MDC td(MDIO) ETH_MDIO(O) tsu(MDIO) th(MDIO) ETH_MDIO(I) MS31384V1 DS12923 Rev 1 225/252 228 Electrical characteristics STM32H745xI/G Table 125. Dynamics characteristics: Ethernet MAC signals for RMII (1) Symbol Parameter Min Typ Max tsu(RXD) Receive data setup time 2 - - tih(RXD) Receive data hold time 2 - - tsu(CRS) Carrier sense setup time 1.5 - - tih(CRS) Carrier sense hold time 1.5 - - td(TXEN) Transmit enable valid delay time 7 8 9.5 td(TXD) Transmit data valid delay time 8 9 11 Unit ns 1. Guaranteed by characterization results. Figure 66. Ethernet RMII timing diagram RMII_REF_CLK td(TXEN) td(TXD) RMII_TX_EN RMII_TXD[1:0] tsu(RXD) tsu(CRS) tih(RXD) tih(CRS) RMII_RXD[1:0] RMII_CRS_DV ai15667b Table 126. Dynamics characteristics: Ethernet MAC signals for MII (1) Symbol Parameter Min Typ Max tsu(RXD) Receive data setup time 2 - - tih(RXD) Receive data hold time 2 - - tsu(DV) Data valid setup time 1.5 - - tih(DV) Data valid hold time 1.5 - - tsu(ER) Error setup time 1.5 - - tih(ER) Error hold time 0.5 - - td(TXEN) Transmit enable valid delay time 9 10 11 td(TXD) Transmit data valid delay time 8.5 9.5 12.5 1. Guaranteed by characterization results. 226/252 DS12923 Rev 1 Unit ns STM32H745xI/G Electrical characteristics Figure 67. Ethernet MII timing diagram MII_RX_CLK tsu(RXD) tsu(ER) tsu(DV) tih(RXD) tih(ER) tih(DV) MII_RXD[3:0] MII_RX_DV MII_RX_ER MII_TX_CLK td(TXEN) td(TXD) MII_TX_EN MII_TXD[3:0] ai15668b JTAG/SWD interface characteristics Unless otherwise specified, the parameters given in Table 127 and Table 128 for JTAG/SWD are derived from tests performed under the ambient temperature, frcc_c_ck frequency and VDD supply voltage summarized in Table 23: General operating conditions, with the following configuration: * Output speed is set to OSPEEDRy[1:0] = 0x10 * Capacitive load CL=30 pF * Measurement points are done at CMOS levels: 0.5VDD * VOS level set to VOS1 Refer to Section 6.3.16: I/O port characteristics for more details on the input/output characteristics: Table 127. Dynamics JTAG characteristics Symbol Fpp 1/tc(TCK) Parameter TCK clock frequency Conditions Min Typ Max 2.7V <VDD< 3.6 V - - 37 1.62 <VDD< 3.6 V - - 27.5 Unit MHz tisu(TMS) TMS input setup time - 2.5 - - tih(TMS) TMS input hold time - 1 - - tisu(TDI) TDI input setup time - 1.5 - - - tih(TDI) TDI input hold time - 1 - - - tov(TDO) TDO output valid time 2.7V <VDD< 3.6 V - 8 13.5 - 1.62 <VDD< 3.6 V - 8 18 - toh(TDO) TDO output hold time - 7 - - - DS12923 Rev 1 227/252 228 Electrical characteristics STM32H745xI/G Table 128. Dynamics SWD characteristics: Symbol Fpp 1/tc(SWCLK) Parameter SWCLK clock frequency Conditions Min Typ Max 2.7V <VDD< 3.6 V - - 71 1.62 <VDD< 3.6 V - - 52.5 Unit MHz tisu(SWDIO) SWDIO input setup time - 2.5 - - - tih(SWDIO) SWDIO input hold time - 1 - - - 2.7V <VDD< 3.6 V - 8.5 14 - - 8.5 19 - 8 - - - tov(SWDIO) SWDIO output valid time 1.62 <VDD< 3.6 V toh(SWDIO) SWDIO output hold time - Figure 68. JTAG timing diagram tc(TCK) TCK tsu(TMS/TDI) th(TMS/TDI) tw(TCKL) tw(TCKH) TDI/TMS tov(TDO) toh(TDO) TDO MSv40458V1 Figure 69. SWD timing diagram tc(SWCLK) SWCLK tsu(SWDIO) th(SWDIO) twSWCLKL) tw(SWCLKH) SWDIO (receive) tov(SWDIO) toh(SWDIO) SWDIO (transmit) MSv40459V1 228/252 DS12923 Rev 1 STM32H745xI/G 7 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at www.st.com. ECOPACK(R) is an ST trademark. DS12923 Rev 1 229/252 250 Package information 7.1 STM32H745xI/G LQFP144 package information LQFP144 is a 144-pin, 20 x 20 mm low-profile quad flat package. Figure 70. LQFP144 package outline SEATING PLANE c A1 A2 A C 0.25 mm GAUGE PLANE D L D1 K A1 ccc C L1 D3 108 73 109 E 37 144 PIN 1 E1 E3 b 72 1 36 IDENTIFICATION e 1A_ME_V4 1. Drawing is not to scale. 230/252 DS12923 Rev 1 STM32H745xI/G Package information Table 129. LQFP144 package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 21.800 22.000 22.200 0.8583 0.8661 0.8740 D1 19.800 20.000 20.200 0.7795 0.7874 0.7953 D3 - 17.500 - - 0.6890 - E 21.800 22.000 22.200 0.8583 0.8661 0.8740 E1 19.800 20.000 20.200 0.7795 0.7874 0.7953 E3 - 17.500 - - 0.6890 - e - 0.500 - - 0.0197 - L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - k 0 3.5 7 0 3.5 7 ccc - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. DS12923 Rev 1 231/252 250 Package information STM32H745xI/G Figure 71. LQFP144 package recommended footprint 108 109 73 1.35 72 0.35 0.5 19.9 17.85 22.6 144 37 1 36 19.9 22.6 ai14905e 1. Dimensions are expressed in millimeters. 232/252 DS12923 Rev 1 STM32H745xI/G Package information Device marking for LQFP144 The following figure gives an example of topside marking versus pin 1 position identifier location. The printed markings may differ depending on the supply chain. Other optional marking or inset/upset marks, which depend on supply chain operations, are not indicated below. Figure 72. LQFP144 marking example (package top view) Revision code R Product identification(1) ES32H745ZIT6 Date code Y WW Pin 1 identifier MSv50637V1 1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. DS12923 Rev 1 233/252 250 Package information 7.2 STM32H745xI/G LQFP176 package information LQFP176 is a 176-pin, 24 x 24 mm low profile quad flat package. Figure 73. LQFP176 package outline c A1 A2 A C Seating plane 0.25 mm gauge plane k A1 L HD PIN 1 IDENTIFICATION L1 D ZE E HE e ZD b 1T_ME_V2 1. Drawing is not to scale. Table 130. LQFP176 package mechanical data Dimensions Ref. Inches(1) Millimeters Min. Typ. Max. Min. Typ. Max. A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 - 1.450 0.0531 - 0.0571 b 0.170 - 0.270 0.0067 - 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 234/252 DS12923 Rev 1 STM32H745xI/G Package information Table 130. LQFP176 package mechanical data (continued) Dimensions Ref. Inches(1) Millimeters Min. Typ. Max. Min. Typ. Max. D 23.900 - 24.100 0.9409 - 0.9488 HD 25.900 - 26.100 1.0197 - 1.0276 ZD - 1.250 - - 0.0492 - E 23.900 - 24.100 0.9409 - 0.9488 HE 25.900 - 26.100 1.0197 - 1.0276 ZE - 1.250 - - 0.0492 - e - 0.500 - - 0.0197 - L(2) 0.450 - 0.750 0.0177 - 0.0295 L1 - 1.000 - - 0.0394 - k 0 - 7 0 - 7 ccc - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. 2. L dimension is measured at gauge plane at 0.25 mm above the seating plane. DS12923 Rev 1 235/252 250 Package information STM32H745xI/G Figure 74. LQFP176 package recommended footprint 1.2 1 176 133 132 0.5 21.8 26.7 0.3 44 45 89 88 1.2 21.8 26.7 1T_FP_V1 1. Dimensions are expressed in millimeters. 236/252 DS12923 Rev 1 STM32H745xI/G Package information Device marking for LQFP176 The following figure gives an example of topside marking versus pin 1 position identifier location. The printed markings may differ depending on the supply chain. Other optional marking or inset/upset marks, which depend on supply chain operations, are not indicated below. Figure 75. LQFP176 marking example (package top view) Product identification(1) ES32H745IIT6 Y WW Revision code Date code R Pin 1identifier MSv50641V1 1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. DS12923 Rev 1 237/252 250 Package information 7.3 STM32H745xI/G LQFP208 package information LQFP208 is a 208-pin, 28 x 28 mm low-profile quad flat package. Figure 76. LQFP208 package outline SEATING PLANE c A1 A A2 C ccc C 0.25 mm A1 GAUGE PLANE K L D L1 D1 D3 105 156 104 208 PIN 1 IDENTIFICATION E E3 E1 b 157 53 1 52 e UH_ME_V2 1. Drawing is not to scale. 238/252 DS12923 Rev 1 STM32H745xI/G Package information Table 131. LQFP208 package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 29.800 30.000 30.200 1.1811 1.1732 1.1890 D1 27.800 28.000 28.200 1.1024 1.0945 1.1102 D3 - 25.500 - - 1.0039 - E 29.800 30.000 30.200 1.1811 1.1732 1.1890 E1 27.800 28.000 28.200 1.1024 1.0945 1.1102 E3 - 25.500 - - 1.0039 - e - 0.500 - - 0.0197 - L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - k 0 3.5 7 0 3.5 7 ccc - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. DS12923 Rev 1 239/252 250 Package information STM32H745xI/G Figure 77. LQFP208 package recommended footprint 208 157 0.5 30.7 28.3 1.25 156 0.3 1 52 105 53 104 1.2 25.8 30.7 UH_FP_V2 1. Dimensions are expressed in millimeters. 240/252 DS12923 Rev 1 STM32H745xI/G Package information Device marking for LQFP208 The following figure gives an example of topside marking versus pin 1 position identifier location. The printed markings may differ depending on the supply chain. Other optional marking or inset/upset marks, which depend on supply chain operations, are not indicated below. Figure 78. LQFP208 marking example (package top view) Revision code R Product identification(1) ES32H745BIT6 Y WW Date code Pin 1 identifier MSv50643V1 1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. DS12923 Rev 1 241/252 250 Package information 7.4 STM32H745xI/G UFBGA176+25 package information UFBGA176+25 is a 201-ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch ball grid array package. Figure 79. UFBGA176+25 package outline C Seating plane A4 ddd C A3 A2 A1 b e A A1 ball identifier E1 A1 ball index area A E Z A Z D1 D e B R 15 1 BOTTOM VIEW Ob (176 + 25 balls) TOP VIEW O eee M C A B O fff M C A0E7_ME_V8 1. Drawing is not to scale. Table 132. UFBGA176+25 package mechanical data inches(1) millimeters Symbol 242/252 Min. Typ. Max. Min. Typ. Max. A - - 0.600 - - 0.0236 A1 - - 0.110 - - 0.0043 A2 - 0.130 - - 0.0051 - A3 - 0.450 - - 0.0177 - A4 - 0.320 - - 0.0126 - b 0.240 0.290 0.340 0.0094 0.0114 0.0134 D 9.850 10.000 10.150 0.3878 0.3937 0.3996 D1 - 9.100 - - 0.3583 - E 9.850 10.000 10.150 0.3878 0.3937 0.3996 E1 - 9.100 - - 0.3583 - e - 0.650 - - 0.0256 - Z - 0.450 - - 0.0177 - ddd - - 0.080 - - 0.0031 DS12923 Rev 1 STM32H745xI/G Package information Table 132. UFBGA176+25 package mechanical data (continued) inches(1) millimeters Symbol Min. Typ. Max. Min. Typ. Max. eee - - 0.150 - - 0.0059 fff - - 0.050 - - 0.0020 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 80. UFBGA176+25 package recommended footprint Dpad Dsm A0E7_FP_V1 Table 133. UFBGA176+25 recommended PCB design rules (0.65 mm pitch BGA) Dimension Recommended values Pitch 0.65 mm Dpad 0.300 mm Dsm 0.400 mm typ. (depends on the soldermask registration tolerance) Stencil opening 0.300 mm Stencil thickness Between 0.100 mm and 0.125 mm Pad trace width 0.100 mm DS12923 Rev 1 243/252 250 Package information STM32H745xI/G Device marking for UFBGA176+25 The following figure gives an example of topside marking versus pin 1 position identifier location. The printed markings may differ depending on the supply chain. Other optional marking or inset/upset marks, which depend on supply chain operations, are not indicated below. Figure 81. UFBGA176+25 marking example (package top view) Revision code R Product identification(1) ES32H745 IIK6 Date code Y WW Ball A1identifier MSv46113V1 1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. 244/252 DS12923 Rev 1 STM32H745xI/G TFBGA240+25 package information TFBGA240+25 is a 265 ball, 14x14 mm, 0.8 mm pitch, fine pitch ball grid array package. ddd C Figure 82. TFBGA240+25 package outline SEATING PLANE A1 A C A2 A1 ball identifier D1 D e E G A E1 7.5 Package information e S 1 17 F BOTTOM VIEW b (240 + 25 balls) TOP VIEW A07U_ME_V1 1. Dimensions are expressed in millimeters. DS12923 Rev 1 245/252 250 Package information STM32H745xI/G Table 134. TFBG240+25 ball package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.100 - - 0.0433 A1 0.150 - - 0.0059 - - A2 - 0.760 - - 0.0299 - b 0.350 0.400 0.450 0.0138 0.0157 0.0177 D 13.850 14.000 14.150 0.5453 0.5512 0.5571 D1 - 12.800 - - 0.5039 - E 13.850 14.000 14.150 0.5453 0.5512 0.5571 E1 - 12.800 - - 0.5039 - e - 0.800 - - 0.0315 - F - 0.600 - - 0.0236 - G - 0.600 - - 0.0236 - ddd - - 0.100 - - 0.0039 eee - - 0.150 - - 0.0059 fff - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 83. TFBGA240+25 package recommended footprint Dpad Dsm A07U_FP_V2 1. Dimensions are expressed in millimeters. 246/252 DS12923 Rev 1 STM32H745xI/G Package information Table 135. TFBGA240+25 recommended PCB design rules (0.8 mm pitch) Dimension Recommended values Pitch 0.8 mm Dpad 0.225 mm Dsm 0.290 mm typ. (depends on the soldermask registration tolerance) Stencil opening 0.250 mm Stencil thickness 0.100 mm Device marking for TFBGA240+25 The following figure gives an example of topside marking versus pin 1 position identifier location. The printed markings may differ depending on the supply chain. Other optional marking or inset/upset marks, which depend on supply chain operations, are not indicated below. Figure 84. TFBGA240+25 marking example (package top view) Product identification(1) ES32H745XIH6 Revision code R Date code Ball A1identifier Y WW MSv61381V1 1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. DS12923 Rev 1 247/252 250 Package information 7.6 STM32H745xI/G Thermal characteristics The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated using the following equation: TJ max = TA max + (PD max x JA) Where: * TA max is the maximum ambient temperature in C, * JA is the package junction-to-ambient thermal resistance, in C/W, * PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax), * PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip internal power. PI/O max represents the maximum power dissipation on output pins where: PI/O max = (VOL x IOL) + ((VDD - VOH) x IOH), taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the application. Table 136. Thermal characteristics Symbol JA JC 248/252 Definition Thermal resistance junction-ambient Thermal resistance junction-case Parameter Value Thermal resistance junction-ambient LQFP144 - 20 x 20 mm /0.5 mm pitch 43.7 Thermal resistance junction-ambient LQFP176 - 24 x 24 mm /0.5 mm pitch 43.0 Thermal resistance junction-ambient LQFP208 - 28 x 28 mm /0.5 mm pitch 42.4 Thermal resistance junction-ambient UFBGA176+25 - 10 x 10 mm /0.65 mm pitch 37.4 Thermal resistance junction-ambient TFBGA240+25 - 14 x 14 mm / 0.8 mm pitch 36.6 Thermal resistance junction-ambient LQFP144 - 20 x 20 mm /0.5 mm pitch 11.3 Thermal resistance junction-ambient LQFP176 - 24 x 24 mm /0.5 mm pitch 11.2 Thermal resistance junction-ambient LQFP208 - 28 x 28 mm /0.5 mm pitch 11.1 Thermal resistance junction-ambient UFBGA176+25 - 10 x 10 mm /0.65 mm pitch 23.9 Thermal resistance junction-ambient TFBGA240+25 - 14 x 14 mm / 0.8 mm pitch 7.4 DS12923 Rev 1 Unit C/W C/W STM32H745xI/G Package information Table 136. Thermal characteristics Symbol JB 7.6.1 Definition Thermal resistance junction-board Parameter Value Thermal resistance junction-ambient LQFP144 - 20 x 20 mm /0.5 mm pitch 38.3 Thermal resistance junction-ambient LQFP176 - 24 x 24 mm /0.5 mm pitch 39.4 Thermal resistance junction-ambient LQFP208 - 28 x 28 mm /0.5 mm pitch 40.3 Thermal resistance junction-ambient UFBGA176+25 - 10 x 10 mm /0.65 mm pitch 19.3 Thermal resistance junction-ambient TFBGA240+25 - 14 x 14 mm / 0.8 mm pitch 24.3 Unit C/W Reference document * JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air). Available from www.jedec.org. * For information on thermal management, refer to application note "Thermal management guidelines for STM32 32-bit Arm Cortex MCUs applications" (AN5036) available from www.st.com. DS12923 Rev 1 249/252 250 Ordering information 8 STM32H745xI/G Ordering information Example: STM32 H 745 X I T 6 TR Device family STM32 = Arm-based 32-bit microcontroller Product type H = High performance Device subfamily 745 = STM32H7x5 High performance and industrial line Pin count Z = 144 pins I = 176 pins/balls B = 208 pins X = 240 balls Flash memory size G = 1 Mbytes I = 2 Mbytes Package T = LQFP ECOPACK(R)2 K = UFBGA pitch 0.65 mm ECOPACK(R)2 H = TFBGA ECOPACK(R)2 Temperature range 3 = Extended temperature range: -40 to 125 C 6 = -40 to 85 C Packing TR = tape and reel No character = tray or tube For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST sales office. 250/252 DS12923 Rev 1 STM32H745xI/G 9 Revision history Revision history Table 137. Document revision history Date Revision 16-May-2019 1 Changes Initial release. DS12923 Rev 1 251/252 251 STM32H745xI/G IMPORTANT NOTICE - PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST's terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers' products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. (c) 2019 STMicroelectronics - All rights reserved 252/252 DS12923 Rev 1