This is information on a product in full production.
May 2019 DS12923 Rev 1 1/252
STM32H745xI/G
Dual 32-bit Arm
®
Cortex
®
-M7 up to 480MHz and -M4 MCUs,
up to 2MB Flash, 1MB RAM, 46 com. and analog interfaces, SMPS
Datasheet - production data
Features
Dual core
•32-bit Arm® Cortex®-M7 core with double-
precision FPU and L1 cache: 16 Kbytes of data
and 16 Kbytes of instruction cache; frequency
up to 480 MHz, MPU, 1027 DMIPS/
2.14 DMIPS/MHz (Dhrystone 2.1), and DSP
instructions
•32-bit Arm® 32-bit Cortex®-M4 core with FPU,
Adaptive real-time accelerator (ART
Accelerator™) for internal Flash memory and
external memories, frequency up to 240 MHz,
MPU, 300 DMIPS/1.25 DMIPS /MHz
(Dhrystone 2.1), and DSP instructions
Memories
•Up to 2 Mbytes of Flash memory with read-
while-write support
•1 Mbyte of RAM: 192 Kbytes of TCM RAM (inc.
64 Kbytes of ITCM RAM + 128 Kbytes of
DTCM RAM for time critical routines),
864 Kbytes of user SRAM, and 4 Kbytes of
SRAM in Backup domain
•Dual mode Quad-SPI memory interface
running up to 133 MHz
•Flexible external memory controller with up to
32-bit data bus: SRAM, PSRAM,
SDRAM/LPSDR SDRAM, NOR/NAND Flash
memory clocked up to 125 MHz in
Synchronous mode
•CRC calculation unit
Security
•ROP, PC-ROP, active tamper
General-purpose input/outputs
•Up to 168 I/O ports with interrupt capability
Reset and power management
•3 separate power domains which can be
independently clock-gated or switched off:
– D1: high-performance capabilities
– D2: communication peripherals and timers
– D3: reset/clock control/power management
•1.62 to 3.6 V application supply and I/Os
•POR, PDR, PVD and BOR
•Dedicated USB power embedding a 3.3 V
internal regulator to supply the internal PHYs
•Embedded regulator (LDO) to supply the digital
circuitry
•High power-efficiency SMPS step-down
converter regulator to directly supply VCORE
and/or external circuitry
•Voltage scaling in Run and Stop mode (6
configurable ranges)
•Backup regulator (~0.9 V)
•Voltage reference for analog peripheral/VREF+
•1.2 to 3.6 V VBAT supply
•Low-power modes: Sleep, Stop, Standby and
VBAT supporting battery charging
Low-power consumption
•VBAT battery operating mode with charging
capability
•CPU and domain power state monitoring pins
•2.95 µA in Standby mode (Backup SRAM OFF,
RTC/LSE ON)
FBGA
TFBGA240+25
(14x14 mm)
UFBGA176+25
(10x10 mm)
FBGA
LQFP144
(20x20 mm)
LQFP176
(24x24 mm)
LQFP208
(28x28 mm)
www.st.com
STM32H745xI/G
2/252 DS12923 Rev 1
Clock management
•Internal oscillators: 64 MHz HSI, 48 MHz
HSI48, 4 MHz CSI, 32 kHz LSI
•External oscillators: 4-48 MHz HSE,
32.768 kHz LSE
•3× PLLs (1 for the system clock, 2 for kernel
clocks) with Fractional mode
Interconnect matrix
•3 bus matrices (1 AXI and 2 AHB)
•Bridges (5× AHB2-APB, 2× AXI2-AHB)
4 DMA controllers to unload the CPU
•1× high-speed master direct memory access
controller (MDMA) with linked list support
•2× dual-port DMAs with FIFO
•1× basic DMA with request router capabilities
Up to 35 communication peripherals
•4× I2Cs FM+ interfaces (SMBus/PMBus)
•4× USARTs/4x UARTs (ISO7816 interface,
LIN, IrDA, up to 12.5 Mbit/s) and 1x LPUART
•6× SPIs, 3 with muxed duplex I2S audio class
accuracy via internal audio PLL or external
clock, 1x I2S in LP domain (up to 150 MHz)
•4x SAIs (serial audio interface)
•SPDIFRX interface
•SWPMI single-wire protocol master I/F
•MDIO Slave interface
•2× SD/SDIO/MMC interfaces (up to 125 MHz)
•2× CAN controllers: 2 with CAN FD, 1 with
time-triggered CAN (TT-CAN)
•2× USB OTG interfaces (1FS, 1HS/FS) crystal-
less solution with LPM and BCD
•Ethernet MAC interface with DMA controller
•HDMI-CEC
•8- to 14-bit camera interface (up to 80 MHz)
11 analog peripherals
•3× ADCs with 16-bit max. resolution (up to 36
channels, up to 3.6 MSPS)
•1× temperature sensor
•2× 12-bit D/A converters (1 MHz)
•2× ultra-low-power comparators
•2× operational amplifiers (7.3 MHz bandwidth)
•1× digital filters for sigma delta modulator
(DFSDM) with 8 channels/4 filters
Graphics
•LCD-TFT controller up to XGA resolution
•Chrom-ART graphical hardware Accelerator™
(DMA2D) to reduce CPU load
•Hardware JPEG Codec
Up to 22 timers and watchdogs
•1× high-resolution timer (2.1 ns max
resolution)
•2× 32-bit timers with up to 4 IC/OC/PWM or
pulse counter and quadrature (incremental)
encoder input (up to 240 MHz)
•2× 16-bit advanced motor control timers (up to
240 MHz)
•10× 16-bit general-purpose timers (up to
240 MHz)
•5× 16-bit low-power timers (up to 240 MHz)
•4× watchdogs (independent and window)
•2× SysTick timers
•RTC with sub-second accuracy and hardware
calendar
Debug mode
•SWD & JTAG interfaces
•4-Kbyte Embedded Trace Buffer
True random number generators (3
oscillators each)
96-bit unique ID
Optional support of extended temperature
range up to 125 °C (specific part numbers)
All packages are ECOPACK®2 compliant
Table 1. Device summary
Reference Part number
STM32H745xI STM32H745ZI, STM32H745II,
STM32H745BI, STM32H745XI
STM32H745xG STM32H745ZG, STM32H745IG,
STM32H745BG, STM32H745XG
DS12923 Rev 1 3/252
STM32H745xI/G Contents
6
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.1 Dual Arm® Cortex® cores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.1.1 Arm® Cortex®-M7 with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.1.2 Arm® Cortex®-M4 with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.2 Memory protection unit (MPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.3 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.3.1 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.3.2 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.3.3 ART™ accelerator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.4 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.5 Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.5.1 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.5.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.5.3 Voltage regulator (SMPS step-down converter and LDO) . . . . . . . . . . . 28
3.5.4 SMPS step-down converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.6 Low-power strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.7 Reset and clock controller (RCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.7.1 Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.7.2 System reset sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.8 General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.9 Bus-interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.10 DMA controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.11 Chrom-ART Accelerator™ (DMA2D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.12 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . 34
3.13 Extended interrupt and event controller (EXTI) . . . . . . . . . . . . . . . . . . . . 34
3.14 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 34
3.15 Flexible memory controller (FMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.16 Quad-SPI memory interface (QUADSPI) . . . . . . . . . . . . . . . . . . . . . . . . . 35
Contents STM32H745xI/G
4/252 DS12923 Rev 1
3.17 Analog-to-digital converters (ADCs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.18 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.19 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.20 Digital-to-analog converters (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.21 Ultra-low-power comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.22 Operational amplifiers (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.23 Digital filter for sigma-delta modulators (DFSDM) . . . . . . . . . . . . . . . . . . 38
3.24 Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.25 LCD-TFT controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.26 JPEG Codec (JPEG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.27 Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.28 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.28.1 High-resolution timer (HRTIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.28.2 Advanced-control timers (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.28.3 General-purpose timers (TIMx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.28.4 Basic timers TIM6 and TIM7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.28.5 Low-power timers (LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5) . . . . 44
3.28.6 Independent watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.28.7 Window watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.28.8 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.29 Real-time clock (RTC), backup SRAM and backup registers . . . . . . . . . . 45
3.30 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.31 Universal synchronous/asynchronous receiver transmitter (USART) . . . 46
3.32 Low-power universal asynchronous receiver transmitter (LPUART) . . . . 47
3.33 Serial peripheral interface (SPI)/inter- integrated sound interfaces (I2S) . 48
3.34 Serial audio interfaces (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.35 SPDIFRX Receiver Interface (SPDIFRX) . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.36 Single wire protocol master interface (SWPMI) . . . . . . . . . . . . . . . . . . . . 49
3.37 Management Data Input/Output (MDIO) slaves . . . . . . . . . . . . . . . . . . . . 50
3.38 SD/SDIO/MMC card host interfaces (SDMMC) . . . . . . . . . . . . . . . . . . . . 50
3.39 Controller area network (FDCAN1, FDCAN2) . . . . . . . . . . . . . . . . . . . . . 50
3.40 Universal serial bus on-the-go high-speed (OTG_HS) . . . . . . . . . . . . . . . 51
3.41 Ethernet MAC interface with dedicated DMA controller (ETH) . . . . . . . . . 51
DS12923 Rev 1 5/252
STM32H745xI/G Contents
6
3.42 High-definition multimedia interface (HDMI)
- consumer electronics control (CEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.43 Debug infrastructure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
4 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
5 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . 107
6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
6.3.2 VCAP external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
6.3.3 SMPS step-down converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
6.3.4 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . 114
6.3.5 Embedded reset and power control block characteristics . . . . . . . . . . 115
6.3.6 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
6.3.7 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
6.3.8 Wakeup time from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . 137
6.3.9 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 138
6.3.10 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 142
6.3.11 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
6.3.12 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
6.3.13 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
6.3.14 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 150
6.3.15 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
6.3.16 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
6.3.17 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
6.3.18 FMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Contents STM32H745xI/G
6/252 DS12923 Rev 1
6.3.19 Quad-SPI interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
6.3.20 Delay block (DLYB) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
6.3.21 16-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
6.3.22 DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
6.3.23 Voltage reference buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . 197
6.3.24 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
6.3.25 Temperature and VBAT monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
6.3.26 Voltage booster for analog switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
6.3.27 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
6.3.28 Operational amplifier characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 201
6.3.29 Digital filter for Sigma-Delta Modulators (DFSDM) characteristics . . . 203
6.3.30 Camera interface (DCMI) timing specifications . . . . . . . . . . . . . . . . . . 206
6.3.31 LCD-TFT controller (LTDC) characteristics . . . . . . . . . . . . . . . . . . . . . 207
6.3.32 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
6.3.33 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
7.1 LQFP144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
7.2 LQFP176 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
7.3 LQFP208 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
7.4 UFBGA176+25 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
7.5 TFBGA240+25 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
7.6 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
7.6.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
8 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
DS12923 Rev 1 7/252
STM32H745xI/G List of tables
10
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Table 2. STM32H745xI/G features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 3. System vs domain low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 4. DFSDM implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 5. Timer feature comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 6. USART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 7. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 8. STM32H745xI/G pin/ball definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 9. Port A alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 10. Port B alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 11. Port C alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table 12. Port D alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Table 13. Port E alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Table 14. Port F alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Table 15. Port G alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 16. Port H alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Table 17. Port I alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Table 18. Port J alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Table 19. Port K alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Table 20. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Table 21. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Table 22. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Table 23. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Table 24. Supply voltage and maximum frequency configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Table 25. VCAP operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Table 26. Characteristics of SMPS step-down converter external components . . . . . . . . . . . . . . . . 113
Table 27. SMPS step-down converter characteristics for external usage . . . . . . . . . . . . . . . . . . . . 114
Table 28. Operating conditions at power-up / power-down (regulator ON) . . . . . . . . . . . . . . . . . . . 114
Table 29. Reset and power control block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Table 30. Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Table 31. Internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Table 32. Typical and maximum current consumption in Run mode, code with data processing
running from ITCM for Cortex-M7 core, and Flash memory for Cortex-M4
(ART accelerator ON), LDO regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Table 33. Typical and maximum current consumption in Run mode, code with data processing
running from ITCM for Arm Cortex-M7 and Flash memory for Arm Cortex-M4,
ART accelerator ON, SMPS regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Table 34. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory, both cores running, cache ON,
ART accelerator ON, LDO regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Table 35. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory, both cores running, cache OFF,
ART accelerator OFF, LDO regulator ON. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Table 36. Typical and maximum current consumption in Run mode, code with data processing
running from ITCM, only Arm Cortex-M7 running, LDO regulator ON . . . . . . . . . . . . . . . 120
Table 37. Typical and maximum current consumption in Run mode, code with data processing
running from ITCM, only Arm Cortex-M7 running, SMPS regulator. . . . . . . . . . . . . . . . . 121
Table 38. Typical and maximum current consumption in Run mode, code with data processing
List of tables STM32H745xI/G
8/252 DS12923 Rev 1
running from Flash memory, only Arm Cortex-M7 running, cache ON,
LDO regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Table 39. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory, only Arm Cortex-M7 running, cache OFF,
LDO regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Table 40. Typical and maximum current consumption batch acquisition mode,
LDO regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Table 41. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory, only Arm Cortex-M4 running, ART accelerator ON,
LDO regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Table 42. Typical and maximum current consumption in Run mode, code with data processing
running from Flash bank 2, only Arm Cortex-M4 running, ART accelerator ON,
SMPS regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Table 43. Typical and maximum current consumption in Stop, LDO regulator ON . . . . . . . . . . . . . 124
Table 44. Typical and maximum current consumption in Stop, SMPS regulator . . . . . . . . . . . . . . . 125
Table 45. Typical and maximum current consumption in Sleep mode, LDO regulator ON . . . . . . . 126
Table 46. Typical and maximum current consumption in Sleep mode, SMPS regulator . . . . . . . . . 126
Table 47. Typical and maximum current consumption in Standby . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Table 48. Typical and maximum current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . 127
Table 49. Peripheral current consumption in Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Table 50. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Table 51. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Table 52. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Table 53. 4-48 MHz HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Table 54. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Table 55. HSI48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Table 56. HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Table 57. CSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Table 58. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Table 59. PLL characteristics (wide VCO frequency range) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Table 60. PLL characteristics (medium VCO frequency range) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Table 61. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Table 62. Flash memory programming (single bank configuration nDBANK=1) . . . . . . . . . . . . . . . 147
Table 63. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Table 64. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Table 65. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Table 66. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Table 67. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Table 68. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Table 69. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Table 70. Output voltage characteristics for all I/Os except PC13, PC14, PC15 and PI8 . . . . . . . . 154
Table 71. Output voltage characteristics for PC13, PC14, PC15 and PI8 . . . . . . . . . . . . . . . . . . . . 155
Table 72. Output timing characteristics (HSLV OFF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Table 73. Output timing characteristics (HSLV ON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Table 74. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Table 75. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . 161
Table 76. Asynchronous non-multiplexed SRAM/PSRAM/NOR read-NWAIT timings . . . . . . . . . . . 161
Table 77. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 163
Table 78. Asynchronous non-multiplexed SRAM/PSRAM/NOR write-NWAIT timings. . . . . . . . . . . 163
Table 79. Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Table 80. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 165
Table 81. Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 166
DS12923 Rev 1 9/252
STM32H745xI/G List of tables
10
Table 82. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 166
Table 83. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Table 84. Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Table 85. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 172
Table 86. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Table 87. Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Table 88. Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Table 89. SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Table 90. LPSDR SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Table 91. SDRAM Write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Table 92. LPSDR SDRAM Write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Table 93. QUADSPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Table 94. QUADSPI characteristics in DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Table 95. Delay Block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Table 96. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Table 97. Minimum sampling time vs RAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Table 98. ADC accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Table 99. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Table 100. DAC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Table 101. VREFBUF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Table 102. Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Table 103. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Table 104. VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Table 105. VBAT charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Table 106. Temperature monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Table 107. Voltage booster for analog switch characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Table 108. COMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Table 109. Operational amplifier characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Table 110. DFSDM measured timing 1.62-3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Table 111. DCMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Table 112. LTDC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Table 113. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Table 114. Minimum i2c_ker_ck frequency in all I2C modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Table 115. I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Table 116. USART characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Table 117. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Table 118. I2S dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Table 119. SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Table 120. MDIO Slave timing parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Table 121. Dynamics characteristics: SD / MMC characteristics, VDD=2.7 to 3.6 V . . . . . . . . . . . . . 221
Table 122. Dynamics characteristics: eMMC characteristics VDD=1.71V to 1.9V . . . . . . . . . . . . . . . 222
Table 123. Dynamics characteristics: USB ULPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Table 124. Dynamics characteristics: Ethernet MAC signals for SMI . . . . . . . . . . . . . . . . . . . . . . . . 225
Table 125. Dynamics characteristics: Ethernet MAC signals for RMII . . . . . . . . . . . . . . . . . . . . . . . . 226
Table 126. Dynamics characteristics: Ethernet MAC signals for MII . . . . . . . . . . . . . . . . . . . . . . . . . 226
Table 127. Dynamics JTAG characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Table 128. Dynamics SWD characteristics: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Table 129. LQFP144 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Table 130. LQFP176 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
Table 131. LQFP208 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
Table 132. UFBGA176+25 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
Table 133. UFBGA176+25 recommended PCB design rules (0.65 mm pitch BGA) . . . . . . . . . . . . . 243
List of tables STM32H745xI/G
10/252 DS12923 Rev 1
Table 134. TFBG240+25 ball package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
Table 135. TFBGA240+25 recommended PCB design rules (0.8 mm pitch) . . . . . . . . . . . . . . . . . . . 247
Table 136. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
Table 137. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
DS12923 Rev 1 11/252
STM32H745xI/G List of figures
12
List of figures
Figure 1. STM32H745xI/G block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 2. TFBGA240+25 ball assignment differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 3. ART™ accelerator schematic and environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 4. Power-up/power-down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 5. STM32H745xI/G bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 6. LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 7. LQFP176 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 8. UFBGA176+25 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 9. LQFP208 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 10. TFBGA240+25 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 11. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Figure 12. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Figure 13. Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Figure 14. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Figure 15. External capacitor CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Figure 16. External components for SMPS step-down converter . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Figure 17. Typical SMPS efficiency (%) vs load current (A) in Run mode at TJ = 30 °C. . . . . . . . . . 128
Figure 18. Typical SMPS efficiency (%) vs load current (A) in Run mode at TJ = TJmax . . . . . . . . 128
Figure 19. Typical SMPS efficiency (%) vs load current (A) in low-power mode at TJ = 30 °C . . . . . 129
Figure 20. Typical SMPS efficiency (%) vs load current (A) in low-power mode at TJ = TJmax . . . 130
Figure 21. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Figure 22. Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Figure 23. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Figure 24. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Figure 25. VIL/VIH for all I/Os except BOOT0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Figure 26. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Figure 27. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 160
Figure 28. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 162
Figure 29. Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 164
Figure 30. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Figure 31. Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Figure 32. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 171
Figure 33. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Figure 34. NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Figure 35. NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Figure 36. NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 176
Figure 37. NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 177
Figure 38. SDRAM read access waveforms (CL = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Figure 39. SDRAM write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Figure 40. Quad-SPI timing diagram - SDR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Figure 41. Quad-SPI timing diagram - DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Figure 42. ADC accuracy characteristics (12-bit resolution) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Figure 43. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Figure 44. Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . 192
Figure 45. Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . 192
Figure 46. 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Figure 47. Channel transceiver timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Figure 48. DCMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
List of figures STM32H745xI/G
12/252 DS12923 Rev 1
Figure 49. LCD-TFT horizontal timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Figure 50. LCD-TFT vertical timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Figure 51. USART timing diagram in Master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Figure 52. USART timing diagram in Slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Figure 53. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Figure 54. SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Figure 55. SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Figure 56. I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Figure 57. I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Figure 58. SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Figure 59. SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Figure 60. MDIO Slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Figure 61. SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Figure 62. SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Figure 63. DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Figure 64. ULPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Figure 65. Ethernet SMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Figure 66. Ethernet RMII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
Figure 67. Ethernet MII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Figure 68. JTAG timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Figure 69. SWD timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Figure 70. LQFP144 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
Figure 71. LQFP144 package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
Figure 72. LQFP144 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
Figure 73. LQFP176 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
Figure 74. LQFP176 package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
Figure 75. LQFP176 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
Figure 76. LQFP208 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
Figure 77. LQFP208 package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
Figure 78. LQFP208 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
Figure 79. UFBGA176+25 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
Figure 80. UFBGA176+25 package recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
Figure 81. UFBGA176+25 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
Figure 82. TFBGA240+25 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
Figure 83. TFBGA240+25 package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
Figure 84. TFBGA240+25 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . 247
DS12923 Rev 1 13/252
STM32H745xI/G Introduction
54
1 Introduction
This document provides information on STM32H745xI/G microcontrollers, such as
description, functional overview, pin assignment and definition, electrical characteristics,
packaging, and ordering information.
This document should be read in conjunction with the STM32H745xI/G reference manual
(RM0399), available from the STMicroelectronics website www.st.com.
For information on the Arm®(a) Cortex®-M7 core and Arm® Cortex®-M4 core, please refer to
the Cortex®-M7 Technical Reference Manual, available from the http://www.arm.com
website.
a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
Description STM32H745xI/G
14/252 DS12923 Rev 1
2 Description
STM32H745xI/G devices are based on the high-performance Arm® Cortex®-M7 and
Cortex®-M4 32-bit RISC cores. The Cortex®-M7 core operates at up to 480 MHz and the
Cortex®-M4 core at up to 240 MHz. Both cores feature a floating point unit (FPU) which
supports Arm® single- and double-precision (Cortex®-M7 core) operations and conversions
(IEEE 754 compliant), including a full set of DSP instructions and a memory protection unit
(MPU) to enhance application security.
STM32H745xI/G devices incorporate high-speed embedded memories with a dual-bank
Flash memory of up to 2 Mbytes, up to 1 Mbyte of RAM (including 192 Kbytes of TCM RAM,
up to 864 Kbytes of user SRAM and 4 Kbytes of backup SRAM), as well as an extensive
range of enhanced I/Os and peripherals connected to APB buses, AHB buses, 2x32-bit
multi-AHB bus matrix and a multi layer AXI interconnect supporting internal and external
memory access.
All the devices offer three ADCs, two DACs, two ultra-low power comparators, a low-power
RTC, a high-resolution timer, 12 general-purpose 16-bit timers, two PWM timers for motor
control, five low-power timers, a true random number generator (RNG). The devices support
four digital filters for external sigma-delta modulators (DFSDM). They also feature standard
and advanced communication interfaces.
•Standard peripherals
–Four I
2Cs
– Four USARTs, four UARTs and one LPUART
– Six SPIs, three I2Ss in Half-duplex mode. To achieve audio class accuracy, the I2S
peripherals can be clocked by a dedicated internal audio PLL or by an external
clock to allow synchronization.
– Four SAI serial audio interfaces
– One SPDIFRX interface
– One SWPMI (Single Wire Protocol Master Interface)
– Management Data Input/Output (MDIO) slaves
– Two SDMMC interfaces
– A USB OTG full-speed and a USB OTG high-speed interface with full-speed
capability (with the ULPI)
– One FDCAN plus one TT-FDCAN interface
– An Ethernet interface
– Chrom-ART Accelerator™
– HDMI-CEC
•Advanced peripherals including
– A flexible memory control (FMC) interface
– A Quad-SPI Flash memory interface
– A camera interface for CMOS sensors
– An LCD-TFT display controller
– A JPEG hardware compressor/decompressor
Refer to Table 2: STM32H745xI/G features and peripheral counts for the list of peripherals
available on each part number.
DS12923 Rev 1 15/252
STM32H745xI/G Description
54
STM32H745xI/G devices operate in the –40 to +85 °C temperature range from a 1.62 to
3.6 V power supply. The supply voltage can drop down to 1.62 V by using an external power
supervisor (see Section 3.5.2: Power supply supervisor) and connecting the PDR_ON pin to
VSS. Otherwise the supply voltage must stay above 1.71 V with the embedded power
voltage detector enabled.
Dedicated supply inputs for USB (OTG_FS and OTG_HS) are available on all packages to
allow a greater power supply choice.
A comprehensive set of power-saving modes allows the design of low-power applications.
STM32H745xI/G devices are offered in 5 packages ranging from 144 pins to 240 pins/balls.
The set of included peripherals changes with the device chosen.
These features make STM32H745xI/G microcontrollers suitable for a wide range of
applications:
•Motor drive and application control
•Medical equipment
•Industrial applications: PLC, inverters, circuit breakers
•Printers, and scanners
•Alarm systems, video intercom, and HVAC
•Home audio appliances
•Mobile applications, Internet of Things
•Wearable devices: smart watches.
Figure 1 shows the device block diagram.
Description STM32H745xI/G
16/252 DS12923 Rev 1
Table 2. STM32H745xI/G features and peripheral counts
Peripherals
STM32H745ZG
STM32H745IG
STM32H745BG
STM32H745XG
STM32H745ZI
STM32H745II
STM32H745BI
STM32H745XI
Flash memory in Kbytes 2 x 512 Kbytes 2 x 1 Mbyte
SRAM in
Kbytes
SRAM
mapped
onto AXI bus
512
SRAM1
(D2 domain) 128
SRAM2
(D2 domain) 128
SRAM3
(D2 domain) 32
SRAM4
(D3 domain) 64
TCM RAM in
Kbytes
ITCM RAM
(instruction) 64
DTCM RAM
(data) 128
Backup SRAM (Kbytes) 4
FMC Yes
General-purpose
input/outputs 97 119/128 148 168 97 119/128 148 168
Quad-SPI Yes
Ethernet Yes
Timers
High-
resolution 1
General-
purpose 10
Advanced-
control
(PWM)
2
Basic 2
Low-power 5
Wakeup pins
Tamper pins
4
2
6
3
4
2
6
3
DS12923 Rev 1 17/252
STM32H745xI/G Description
54
Random number generator Yes
Communicati
on interfaces
SPI / I2S6/3
(1)
I2C4
USART/
UART/
LPUART
4/4
/1
SAI 4
SPDIFRX 4 inputs
SWPMI Yes
MDIO Yes
SDMMC 2
FDCAN/TT-
FDCAN 1/1
USB
OTG_FS Yes
USB
OTG_HS Yes
Ethernet and camera
interface Yes
LCD-TFT Yes
JPEG Codec Yes
Chrom-ART Accelerator™
(DMA2D) Yes
16-bit ADCs
Number of Direct channels
Number of Fast channels
Number of Slow channels
3
2
6
15
2
9
17
4
9
23
2
9
21
4
9
23
2
6
15
2
9
17
4
9
23
2
9
21
4
9
23
12-bit DAC
Number of channels
Yes
2
Comparators 2
Operational amplifiers 2
DFSDM Yes
Table 2. STM32H745xI/G features and peripheral counts (continued)
Peripherals
STM32H745ZG
STM32H745IG
STM32H745BG
STM32H745XG
STM32H745ZI
STM32H745II
STM32H745BI
STM32H745XI
Description STM32H745xI/G
18/252 DS12923 Rev 1
Maximum CPU frequency
480 MHz(2)
400 MHz(3)
300 MHz(4)
Operating voltage 1.62 to 3.6 V(5)
Operating
temperatures
Ambient
temperature –40 up to +85 °C(6)
Junction
temperature –40 to + 125 °C
Extended
operating
temperatures
Ambient
temperature –40 to + 125 °C(4)(7)
Junction
temperature –40 to + 140 °C(8)
Package LQFP
144
LQFP
176
UFBGA
176+25
LQFP
208
TFBGA
240+25
LQFP
144
LQFP
176
UFBGA
176+25
LQFP
208
TFBGA
240+25
1. The SPI1, SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either the SPI mode or the I2S audio
mode.
2. The product junction temperature must be kept within the –40 to +105 °C range.
3. The product junction temperature must be kept within the –40 to +125 °C range.
4. Up to 300 MHz for STM32H745xxx3 sales types (extended industrial temperature range).
5. VDD/VDDA can drop down to 1.62 V by using an external power supervisor (see Section 3.5.2: Power supply supervisor) and
connecting PDR_ON pin to VSS. Otherwise the supply voltage must stay above 1.71 V with the embedded power voltage
detector enabled.
6. Using appropriate cooling methods to guarantee that the maximum junction temperature (125 °C) is not exceeded, the
maximum ambient temperature (85°C) can be exceeded.
7. The product junction temperature must be kept within the –40 to +140 °C range.
8. It is mandatory to use the SMPS step-down converter when the maximum junction temperature is higher than 125 °C.
Table 2. STM32H745xI/G features and peripheral counts (continued)
Peripherals
STM32H745ZG
STM32H745IG
STM32H745BG
STM32H745XG
STM32H745ZI
STM32H745II
STM32H745BI
STM32H745XI
DS12923 Rev 1 19/252
STM32H745xI/G Description
54
Figure 1. STM32H745xI/G block diagram
MSv43754V13
FDCAN1
FDCAN2
I2C1/SMBUS
I2C2/SMBUS
I2C3/SMBUS
AXI/AHB12 (200MHz)
4 compl. chan. (TIM1_CH1[1:4]N),
4 chan. (TIM1_CH1[1:4]ETR, BKIN as AF
APB1 30MHz
TX, RX
SCL, SDA, SMBAL as AF
APB1 100 MHz (max)
MDMA
PK[7:0]
4 compl. chan.(TIM8_CH1[1:4]N),
4 chan. (TIM8_CH1[1:4], ETR, BKIN as
AF
RX, TX, SCK, CTS, RTS as AF
SCL, SDA, SMBAL as AF
SCL, SDA, SMBAL as AF
MOSI, MISO, SCK, NSS/SDO,
SDI, CK, WS, MCK, as AF
TX, RX
RX, TX as AF
RX, TX as AF
RX, TX, SCK
CTS, RTS as AF
RX, TX, SCK, CTS,
RTS as AF
1 channel as AF
smcard
irDA
1 channel as AF
2 channels as AF
4 channels
4 channels, ETR as AF
4 channels, ETR as AF
4 channels, ETR as AF
RX, TX as AF
FIFO
LCD-TFT
FIFO
CHROM-ART
(DMA2D)
SD, SCK, FS, MCLK as AF
FIFO
LCD_R[7:0], LCD_G[7:0],
LCD_B[7:0], LCD_HSYNC,
LCD_VSYNC, LCD_DE,
LCD_CLK
CLK, CS,D[7:0]
64-bit AXI BUS-MATRIX
CEC as AF
IN[1:4] as AF
MDC, MDIO
AXIM
A
XI
M
AHBP
AHBS
TRACECK
TRACED[3:0]
JTRST, JTDI,
JTCK/SWCLK
JTDO/SWD, JTDO
JTAG/SW
ETM
I-Cache
16KB
D-Cache
16KB
I-
TCM
64KB
D-
TCM
64KB
16 Streams
FIFO
SDMMC1
SDMMC_D[7:0],SDMMC_D[7:3,1]Dir
SDMMC_D0dir, SDMMC_D2dir
CMD, CMDdir, CK, Ckin,
CKio as AF
FIFO
DMA1
FIFOs
8 Stream
DMA2
FIFOs
ETHER
MAC SDMMC2
FIFO
OTG_HS
FIFO
OTG_FS
FIFO
SRAM1
128 KB
8 Stream
FMC_signals
DMA DMA/ DMA/
PHY PHY
MII / RMII
MDIO
as AF
DP, DM, STP,
NXT,ULPI:CK
, D[7:0], DIR,
ID, VBUS
AHB1 (200MHz)
ADC1
DAC1_OUT, DAC2_OUT as AF
16b
AXI/AHB34 (200MHz)
JPEGWWDG1
AHB2 (200MHz)
AHB2 (200MHz)
PA..J[15:0]
HSYNC, VSYNC, PUIXCLK, D[13:0]
SAI3
MOSI, MISO, SCK, NSS as AF
MOSI, MISO, SCK, NSS as AF
smcard
irDA
32-bit AHB BUS-MATRIX
32-bit AHB BUS-MATRIX
AHB4 (200MHz)
BDMA
DMA
Mux2
Up to 20 analog inputs
common to ADC1 & 2
HSEM
AHB4 (200MHz)
AHB3
AHB4
AHB4
AHB4
AHB4
AHB4
APB4 100 MHz (max)
VDDA, VSSA
NRESET
WKUP[5:0]
@VDD
RCC
Reset &
control
OSC32_IN
OSC32_OUT
VBAT = 1.2 to 3.6 V
AWU
VDD12 POWER MANAGEMENT
LS LS
OSC_IN
OSC_OUT
RTC_TS
RTC_TAMP[1:3]
RTC_OUT
RTC_REFIN
VDD = 1.62 to 3.6V
VDD33USB = 3.0 to 3.6V
VSS
VCAP
VDDMMC33 = 1.8 to 3.6V
VDDSMPS, VSSSMPS
VLXSMP, VFBSMPS,
@VDD
@VDD33
@VSW
IWDG1
PWRCTRL
AHB4 (200MHz)
SUPPLY SUPERVISION
Int
POR
reset
@VDD
LPTIM1_IN1, LPTIM1_IN2,
LPTIM1_OUT as AF
OPAMPx_VINM
OPAMPx_VINP
OPAMPx_VOUT as AF
HRTIM1_CH[A..E]x
HRTIM1_FLT[5:1],
HRTIM1_FLT[5:1]_in, SYSFLT
DFSDM1_CKOUT,
DFSDM1_DATAIN[0:7],
DFSDM1_CKIN[0:7]
2 compl. chan.(TIM15_CH1[1:2]N),
2 chan. (TIM_CH15[1:2], BKIN as AF
1 compl. chan.(TIM16_CH1N),
1 chan. (TIM16_CH1, BKIN as AF
1 compl. chan.(TIM17_CH1N),
1 chan. (TIM17_CH1, BKIN as AF
SDMMC_
D[7:0],
CMD, CK as AF
Up to 17 analog inputs
common to ADC1 and 2
SD, SCK, FS, MCLK,
PDM_DI/CK[4:1] as AF
SCL, SDA, SMBAL as AF
COMPx_INP, COMPx_INM,
COMPx_OUT as AF
LPTIM5_OUT as AF
D-
TCM
64KB
AHB/APB
Quad-SPI
Up to 1 MB
FLASH
Up to 1 MB
FLASH
512 KB AXI
SRAM
FMC
Delay block
DCMI AHB/APB
HRTIM1
DFSDM1
FIFO
SAI2
SD, SCK, FS, MCLK, D[3:1],
CK[2:1] as AF
FIFO
SAI1
SPI5
TIM17
TIM16
TIM15
SPI4
MOSI, MISO, SCK, NSS /
SDO, SDI, CK, WS, MCK, as AF SPI/I2S1
USART6
RX, TX, SCK, CTS, RTS as AF irDA USART1
TIM1/PWM 16b
TIM8/PWM 16b
APB2 100 MHz (max)
ADC3
GPIO PORTA.. J
GPIO PORTK
SAI4
COMP1&2
LPTIM5
LPTIM4_OUT as AF LPTIM4
LPTIM3_OUT as AF LPTIM3
I2C4
MISO, MOSI, SCK, NSS as AF SPI6
RX, TX, CK, CTS, RTS as AF LPUART1
LPTIM2
VREF
SYSCFG
EXTI WKUP
CRC
DAP
RNG
DMA
Mux1
To APB1-2
peripherals
SRAM2
128 KB
SRAM3
32 KB
ADC2
AHB/APB
TIM6 16b
TIM7 16b
SWPMI
TIM2
32b
TIM3
16b
TIM4
16b
TIM5
32b
TIM12
16b
TIM13
16b
TIM14
16b
USART2
smcard
irDA
USART3
UART4
UART5
UART7
RX, TX as AF
UART8
SPI2/I2S2
MOSI, MISO, SCK, NSS/SDO,
SDI, CK, WS, MCK, as AF
SPI3/I2S3
Digital filter
MDIOS
FIFO
10 KB SRAM
RAM
I/F
CRS
SPDIFRX1
HDMI-CEC
DAC1&2
LPTIM1
WWDG2
AHB/APB
XTAL 32 kHz
RTC
Backup registers
XTAL OSC
4- 48 MHz
64 MHz HSI RC
32 KHz LSI RC
PLL1+PLL2+PLL3
POR/PDR/BOR
PVD
smcard
Voltage regulator
3.3 to 1.2V
LSI
HSI
CSI
RC48
LPTIM2_OUT as AF
AHB1 (200MHz)
DP, DM, ID,
VBUS
64 KB SRAM 4 KB BKP
RAM
AHB4
Arm
Cortex
M4
Arm
Cortex
M7
I-
Bus
D-
Bus
S-
Bus
ART
(instruction cache)
AHB ART (200MHz)
AHB ART(200MHz)
SD, SCK, FS, MCLK as AF
OPAMP1&2
IWDG1
IWDG2
SMPS step-down
converter
4 MHz CSI
48 MHz HSI48 RC
APB4 100 MHz (max)
APB4 100 MHz (max)
IWDG2
VDDREF_ADC Tem. sensor
Description STM32H745xI/G
20/252 DS12923 Rev 1
Compatibility throughout the family
STM32H745xI/G devices are not pin-to-pin compatible with STM32H7x3 devices (single
core line):
•The TFBGA240+25 ballout is compatible with STM32H7x3 devices, except for a few
I/O balls as shown in Figure 2.
•LQFP208 and LQFP176 pinouts, as well as UFBGA176+25 ballout are not compatible
with STM32H7x3 devices.
Figure 2. TFBGA240+25 ball assignment differences
1. The balls highlighted in gray correspond to different signals on STM32H745xI/G and STM32H7x3 devices.
MSv48801V2
VDD
SMPS
STM32H7x5
12345678910 11121314151617
AVSS PI6 PI5 PI4 PB5 VDDLDO VCAP PK5 PG10 PG9 PD5 PD4 PC10 PA15 PI1 PI0 VSS
BVBAT VSS PI7 PE1 PB6 VSS PB4 PK4 PG11 PJ15 PD6 PD3 PC11 PA14 PI2 PH15 PH14
C
PC15-
OSC32_
OUT
PC14-
OSC32_
IN
PE2 PE0 PB7 PB3 PK6 PK3 PG12 VSS PD7 PC12 VSS PI3 PA13 VSS VDDLDO
DPE5 PE4 PE3 PB9 PB8 PG15 PK7 PG14 PG13 PJ14 PJ12 PD2 PD0 PA10 PA9 PH13 VCAP
EPI9 PC13 PI8 PE6 VDD PDR
_ON BOOT0 VDD PJ13 VDD PD1 PC8 PC9 PA8 PA12 PA11
FPI10 PI11 VDD PC7 PC6 PG8 PG7 VDD33
USB
GPF2 PF1 PF0 VDD VSS VSS VSS VSS VSS VDD PG5 PG6 VSS VDD50
USB
HPI12 PI13 PI14 PF3 VDD VSS VSS VSS VSS VSS VDD PG4 PG3 PG2 PK2
J
PH1-
OSC_
OUT
PH0-
OSC_IN VSS PF5 PF4 VSS VSS VSS VSS VSS VDD PK0 PK1 VSS VSS
KNRST PF6 PF7 PF8 VDD VSS VSS VSS VSS VSS VDD PJ11 VSS NC NC
LVDDA PC0 PF10 PF9 VDD VSS VSS VSS VSS VSS VDD PJ10 VSS NC NC
MVREF+ PC1 PC2 PC3 VDD VDD PJ9 VSS NC NC
NVREF- PH2 PA2 PA1 PA0 PJ0 VDD VDD PE10 VDD VDD VDD PJ8 PJ7 PJ6 VSS NC
PVSSA PH3 PH4 PH5 PI15 PJ1 PF13 PF14 PE9 PE11 PB10 PB11 PH10 PH11 PD15 PD14 VDD
RPC2_C PC3_C PA6 VSS PA7 PB2 PF12 VSS PF15 PE12 PE15 PJ5 PH9 PH12 PD11 PD12 PD13
TPA0_C PA1_C PA5 PC4 PB1 PJ2 PF11 PG0 PE8 PE13 PH6 VSS PH8 PB12 PB15 PD10 PD9
UVSS PA3 PA4 PC5 PB0 PJ3 PJ4 PG1 PE7 PE14 VCAP VDDLDO PH7 PB13 PB14 PD8 VSS
PI9
PF2
STM32H7x3
VLX
SMPS
VSS
SMPS
VFB
SMPS
NC
PI9
PF2
NC
NC
NC
DS12923 Rev 1 21/252
STM32H745xI/G Functional overview
54
3 Functional overview
3.1 Dual Arm® Cortex® cores
The industrial STM32H745xI/G devices embed two Arm® cores, a Cortex®-M7 and a
Cortex®-M4. The Cortex®-M4 offers optimal performance for real-time applications while the
Cortex®-M7 core can execute high-performance tasks in parallel.
The two cores belong to separate power domains. This allows designing gradual high-
power efficiency solutions in combination with the low-power modes already available on all
STM32 microcontrollers.
3.1.1 Arm® Cortex®-M7 with FPU
The Arm® Cortex®-M7 with double-precision FPU processor is the latest generation of Arm
processors for embedded systems. It was developed to provide a low-cost platform that
meets the needs of MCU implementation, with a reduced pin count and optimized power
consumption, while delivering outstanding computational performance and low interrupt
latency.
The Cortex®-M7 processor is a highly efficient high-performance featuring:
•Six-stage dual-issue pipeline
•Dynamic branch prediction
•Harvard architecture with L1 caches (16 Kbytes of I-cache and 16 Kbytes of D-cache)
•64-bit AXI interface
•64-bit ITCM interface
•2x32-bit DTCM interfaces
The following memory interfaces are supported:
•Separate Instruction and Data buses (Harvard Architecture) to optimize CPU latency
•Tightly Coupled Memory (TCM) interface designed for fast and deterministic SRAM
accesses
•AXI Bus interface to optimize Burst transfers
•Dedicated low-latency AHB-Lite peripheral bus (AHBP) to connect to peripherals.
The processor supports a set of DSP instructions which allow efficient signal processing and
complex algorithm execution.
It also supports single and double precision FPU (floating point unit) speeds up software
development by using metalanguage development tools, while avoiding saturation.
Figure 1 shows the general block diagram of the STM32H745xI/G family.
Note: Cortex®-M7 with FPU core is binary compatible with the Cortex®-M4 core.
Functional overview STM32H745xI/G
22/252 DS12923 Rev 1
3.1.2 Arm® Cortex®-M4 with FPU
The Arm® Cortex®-M4 processor is a high-performance embedded processor which
supports DSP instructions. It was developed to provide an optimized power consumption
MCU, while delivering outstanding computational performance and low interrupt latency.
The Arm® Cortex®-M4 processor is a highly efficient MCU featuring:
•3-stage pipeline with branch prediction
•Harvard architecture
•32-bit System (S-BUS) interface
•32-bit I-BUS interface
•32-bit D-BUS interface
The Arm® Cortex®-M4 processor also features a dedicated hardware adaptive real-time
accelerator (ART Accelerator™). This is an instruction cache memory composed of sixty-
four 256-bit lines, a 256-bit cache buffer connected to the 64-bit AXI interface and a 32-bit
interface for non-cacheable accesses.
3.2 Memory protection unit (MPU)
The devices feature two memory protection units. Each MPU manages the CPU access
rights and the attributes of the system resources. It has to be programmed and enabled
before use. Its main purposes are to prevent an untrusted user program to accidentally
corrupt data used by the OS and/or by a privileged task, but also to protect data processes
or read-protect memory regions.
The MPU defines access rules for privileged accesses and user program accesses. It
allows defining up to 16 protected regions that can in turn be divided into up to 8
independent subregions, where region address, size, and attributes can be configured. The
protection area ranges from 32 bytes to 4 Gbytes of addressable memory.
When an unauthorized access is performed, a memory management exception is
generated.
DS12923 Rev 1 23/252
STM32H745xI/G Functional overview
54
3.3 Memories
3.3.1 Embedded Flash memory
The STM32H745xI/G devices embed up to 2 Mbytes of Flash memory that can be used for
storing programs and data.
The Flash memory is organized as 266-bit Flash words memory that can be used for storing
both code and data constants. Each word consists of:
•One Flash word (8 words, 32 bytes or 256 bits)
•10 ECC bits.
The Flash memory is divided into two independent banks. Each bank is organized as
follows:
•A user Flash memory block of 512 Kbytes (STM32H7xxxG) or 1-Mbyte (STM32H7xxxI)
containing eight user sectors of 128 Kbytes (4 K Flash memory words)
•128 Kbytes of System Flash memory from which the device can boot
•2 Kbytes (64 Flash words) of user option bytes for user configuration
3.3.2 Embedded SRAM
All devices feature around 1 Mbyte of RAM with hardware ECC. The RAM is divided as
follows:
•512 Kbytes of AXI-SRAM mapped onto AXI bus on D1 domain.
•SRAM1 mapped on D2 domain: 128 Kbytes
•SRAM2 mapped on D2 domain: 128 Kbytes
•SRAM3 mapped on D2 domain: 32 Kbytes
•SRAM4 mapped on D3 domain: 64 Kbytes
•4 Kbytes of backup SRAM
The content of this area is protected against possible unwanted write accesses,
and is retained in Standby or VBAT mode.
•RAM mapped to TCM interface (ITCM and DTCM):
Both ITCM and DTCM RAMs are 0 wait state memories. They can be accessed either
from the Arm® Cortex®-M7 CPU or the MDMA (even in Sleep mode) through a specific
AHB slave of the Cortex®-M7(AHBS):
– 64 Kbytes of ITCM-RAM (instruction RAM)
This RAM is connected to ITCM 64-bit interface designed for execution of critical
real-times routines by the Cortex®-M7.
– 128 Kbytes of DTCM-RAM (2x 64-Kbyte DTCM-RAMs on 2x32-bit DTCM ports)
The DTCM-RAM could be used for critical real-time data, such as interrupt service
routines or stack/heap memory. Both DTCM-RAMs can be used in parallel (for
load/store operations) thanks to the Cortex®-M7 dual issue capability.
The MDMA can be used to load code or data in ITCM or DTCM RAMs.
Functional overview STM32H745xI/G
24/252 DS12923 Rev 1
Error code correction (ECC)
Over the product lifetime, and/or due to external events such as radiations, invalid bits in
memories may occur. They can be detected and corrected by ECC. This is an expected
behavior that has to be managed at final-application software level in order to ensure data
integrity through ECC algorithms implementation.
SRAM data are protected by ECC:
•7 ECC bits are added per 32-bit word.
•8 ECC bits are added per 64-bit word for AXI-SRAM and ITCM-RAM.
The ECC mechanism is based on the SECDED algorithm. It supports single-error correction
and double-error detection.
3.3.3 ART™ accelerator
The ART™ (adaptive real-time) accelerator block speeds up instruction fetch accesses of
the Cortex®-M4 core from D1-domain internal memories (Flash memory bank 1, Flash
memory bank 2, AXI SRAM) and from D1-domain external memories attached via Quad-
SPI controller and Flexible memory controller (FMC).
The ART™ accelerator is a 256-bit cache line using 64-bit WRAP4 accesses from the 64-bit
AXI D1 domain. The acceleration is achieved by loading selected code into an embedded
cache and making it instantly available to Cortex®-M4 core, thus avoiding latency due to
memory wait states.
Figure 3. shows the block schematic and the environment of the ART accelerator.
DS12923 Rev 1 25/252
STM32H745xI/G Functional overview
54
Figure 3. ART™ accelerator schematic and environment
3.4 Boot modes
By default, the boot codes are executed simultaneously by both cores. However, by
programming the appropriate Flash user option byte, it is possible to boot from one core
while clock-gating the other core.
At startup, the boot memory space is selected by the BOOT pin and BOOT_ADDx option
bytes, allowing to program any boot memory address from 0x0000 0000 to 0x3FFF FFFF
which includes:
•All Flash address space
•Flash memory and SRAMs (except for ITCM /DTCM RAMs which cannot be accessed
by the Cortex®-M4 core)
MSv39757V2
64-bit AXI bus matrix
Flash bank 1
Flash bank 2
AXI SRAM
QSPI
FMC
AHB from D2 domain
32-bit bus
64-bit bus
Bus multiplexer
Legend
Master interface
Slave interface
AXI AHB
ART accelerator
AHB switch
Non-cacheable
access path
Cacheable
access path
AXI access
AHB access
D1 domain
Control
control
Cache memory
64 x 256-bit
Cache memory
64 x 256-bit
Cache buffer
1 x 256-bit
Cache
non-
cacheable
access
Detect of
write to cacheable page instruction
fetch
cache
hit
cache
miss
cache
refill
Cache
manager
Functional overview STM32H745xI/G
26/252 DS12923 Rev 1
The bootloader is located in non-user System memory. It is used to reprogram the Flash
memory through a serial interface (USART, I2C, SPI, USB-DFU). Refer to STM32
microcontroller System memory Boot mode application note (AN2606) for details.
3.5 Power supply management
3.5.1 Power supply scheme
STM32H745xI/G power supply voltages are the following:
•VDD = 1.62 to 3.6 V: external power supply for I/Os, provided externally through VDD
pins.
•VDDLDO = 1.62 to 3.6 V: supply voltage for the internal regulator supplying VCORE
•VDDA = 1.62 to 3.6 V: external analog power supplies for ADC, DAC, COMP and
OPAMP.
•VDD33USB and VDD50USB:
VDD50USB can be supplied through the USB cable to generate the VDD33USB via the
USB internal regulator. This allows supporting a VDD supply different from 3.3 V.
The USB regulator can be bypassed to supply directly VDD33USB if VDD = 3.3 V.
•VBAT = 1.2 to 3.6 V: power supply for the VSW domain when VDD is not present.
•VCAP: VCORE supply voltage, which values depend on voltage scaling (1.0 V, 1.1 V,
1.2 V or 1.35 V). They are configured through VOS bits in PWR_D3CR register and
ODEN bit in the SYSCFG_PWRCR register. The VCORE domain is split into the
following power domains that can be independently switch off.
– D1 domain containing some peripherals and the Cortex®-M7 core.
– D2 domain containing a large part of the peripherals and the Cortex®-M4 core.
– D3 domain containing some peripherals and the system control.
•VDDSMPS= 1.62 V to 3.6 V: SMPS step-down converter power supply
VDDSMPS must be kept at the same voltage level as VDD.
•VLXSMPS = SMPS step-down converter output coupled to an inductor.
•VFBSMPS = VCORE, 1.8 V or 2.5 V external SMPS step-down converter feedback
voltage sense input.
During power-up and power-down phases, the following power sequence requirements
must be respected (see Figure 4):
•When VDD is below 1 V, other power supplies (VDDA, VDD33USB, VDD50USB) must
remain below VDD + 300 mV.
•When VDD is above 1 V, all power supplies are independent (except for VDDSMPS,
which must remain at the same level as VDD).
During the power-down phase, VDD can temporarily become lower than other supplies only
if the energy provided to the microcontroller remains below 1 mJ. This allows external
decoupling capacitors to be discharged with different time constants during the power-down
transient phase.