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©2003-2008 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0108-06 www.psemi.com
VDD = 3.0 V, -40° C TA 85° C, unless otherwise specified
The PE3513 is a high-performance static UltraCMOS™
prescaler with a fixed divide ratio of 8. Its operating frequency
range is DC to 1500 MHz. The PE3513 operates on a nominal
3 V supply and draws only 8 mA. The input and output
interfaces support both AC-coupled, low-Z RF as well as direct
connection to low voltage positive logic devices. It is packaged
in a small 6-lead SC-70 and is ideal for frequency scaling
solutions
The PE3513 is manufactured on Peregrine’s UltraCMOS™
process, a patented variation of silicon-on-insulator (SOI)
technology on a sapphire substrate, offering the performance
of GaAs with the economy and integration of conventional
CMOS.
Product Specification
1500 MHz Low Power UltraCMOS™
Divide-by-8 Prescaler
Product Description
Figure 1. Functional Schematic Diagram
PE3513
Features
• DC to 1500 MHz operation
• Fixed divide ratio of 8
• Low-power consumption: 8 mA typical
@ 3V
• RF or LV Digital Interface
• Ultra-small package: 6-lead SC-70
Table 1. Electrical Specifications (ZS = ZL = 50 )
Figure 2. Package Type
6-lead SC70
Parameter Conditions Minimum Typical Maximum Units
Supply Voltage 2.85 3.0 3.15 V
Supply Current 8 12 mA
Input Frequency (Fin) DC 1500 MHz
Input Power (Pin) DC < Fin 1000 MHz (Note 1) -10 +10 dBm
1000 MHz < Fin 1500 -3 dBm
Output Power (Pout) DC < Fin 1500 MHz 2 dBm
Note 1: CMOS logic levels can be used to drive the reference input if DC coupled. Voltage input needs to be a minimum of 0.5 Vp-p. The
input edge rate should be faster than 80mV/ns from DC - 10 MHz.
D
QB
Q
CLK
D
QB
Q
CLK
Pre-Amp Output
Buffer
IN OUT
D
QB
Q
CLK
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Product Specification
PE3513
Page 2 of 9
©2003-2008 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0108-06 UltraCMOS™ RFIC Solutions
Table 2. DC Electrical Characteristics (-40° C ≤ TA ≤ 85° C)
Table 3. AC Characteristics (-40° C ≤ TA ≤ 85° C)
Table 4. Typical Output Swing (VDD = 2.7 V)
* See figure 5 for AC test circuit
Symbol Parameter Condition Typical Unit
VIH High Level Input Voltage 2.7 V VDD 3.3 V 2.0 V
VIL Low Level Input Voltage 2.7 V VDD 3.3 V 0.8 V
VOH High Level Output Voltage VDD = 2.7 V; IOH = 2.9 mA 2.2 V
VOL Low Level Output Voltage VDD = 2.7 V; IOL = 2.6 mA 0.4 V
Symbol Parameter Condition* Typical Unit
tPHL Propagation Delay
(High to Low) 50 MHz Pulse Train Input;
CL = 10 pF, RL = 500
4.1
ns
tPLH Propagation Delay
(Low to High) 50 MHz Pulse Train Input;
CL = 10 pF, RL = 500
3.9
ns
tr Output Rise Time
(10% to 90%) 50 MHz Pulse Train Input;
CL = 10 pF, RL = 500
2.0
ns
tf Output Fall Time
(90% to 10%) 50 MHz Pulse Train Input;
CL = 10 pF, RL = 500
2.0
ns
Frequency Condition Typical Unit
50 MHz 200 mVp-p Sinusoidal Input;
CL = 10 pF, RL = 500 2.3 Vp-p
500 MHz 200 mVp-p Sinusoidal Input;
CL = 10 pF, RL = 500 2.3 Vp-p
1500 MHz 200 mVp-p Sinusoidal Input;
CL = 10 pF, RL = 500 2.2 Vp-p
OBSOLETE
Product Specification
PE3513
Page 3 of 9
©2003-2008 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0108-06 www.psemi.com
Table 5. Pin Descriptions
Table 6. Absolute Maximum Ratings
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS™ device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the rating specified in Table 6.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS™
devices are immune to latch-up.
Figure 3. Pin Configuration (Top View)
Device Functional Considerations
The PE3513 divides an input signal, up to a
frequency of 1500 MHz, by a factor of eight
thereby producing an output frequency at one-
eighth the input frequency. To work properly with
low impedance, ground referenced interfaces, the
input and output signals (pins 3 & 6) must be AC
coupled via an external capacitor, as shown in the
test circuit in Figure 4.
The ground pattern on the board should be made
as wide as possible to minimize ground
impedance. See Figure 9 for a layout example.
Exceeding absolute maximum ratings may cause
permanent damage. Operation should be
restricted to the limits in the Operating Ranges
table. Operation between operating range
maximum and absolute maximum for extended
periods may reduce reliability.
Pin
No. Pin
Name Description
1 N/C No Connect. This pin should be left open.
2 GND
Ground pin. Ground pattern on the board
should be as wide as possible to reduce
ground impedance.
3 IN
Input signal pin. DC blocking capacitor
required (100 pF typical).
4 VDD Power supply pin. Bypassing is required.
5 GND Ground pin.
6 OUT
Divided frequency output pin. DC blocking
capacitor required (100 pF typical).
Symbol Parameter/Conditions Min Max Units
VDD Supply voltage 4.0 V
Pin Input Power 13 dBm
TST Storage temperature
range -65 150 °C
TOP Operating temperature
range -40 85 °C
VESD ESD voltage (Human
Body Model) 2000 V
.
513
1
2
3 4
5
6
OUT
GND
V
DD
NC
GND
IN
pin 1
SC-70
OBSOLETE
Product Specification
PE3513
Page 4 of 9
©2003-2008 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0108-06 UltraCMOS™ RFIC Solutions
Figure 4. Test Circuit Block Diagram
Figure 5. AC Test Circuit
GND
IN VDD
GND
OUTN/C1
2
34
5
6
PE3513
50 Ohm
100 pF
100 pF 1000 pF
VDD
3V +/- 0.15 V
100 pF
50 Ohm
Spectrum
Analyzer
Signal
Generator
PE3513
Pulse
Generator
R
L
C
L
R
T
V
DD
R
T =
Zout of pulse generator
(usually 50 ohm)
OBSOLETE
Product Specification
PE3513
Page 5 of 9
©2003-2008 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0108-06 www.psemi.com
Figure 6. Input Sensitivity Figure 7. Device Current
Typical Performance Data: VDD = 3.0 V
Figure 8. Output Power
OBSOLETE
Product Specification
PE3513
Page 6 of 9
©2003-2008 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0108-06 UltraCMOS™ RFIC Solutions
Evaluation Kit
Figure 9. Evaluation Board Layouts
Figure 10. Evaluation Board Schematic
Peregrine Specification 102/0191
Peregrine Specification 101/0110
Applications Support
If you have a problem with your evaluation kit or if
you have applications questions call (858) 731-9400
and ask for applications support. You may also con-
tact us by fax or e-mail:
Fax: (858) 731-9499
E-Mail: help@psemi.com
Evaluation Kit Operation
The SC-70 Prescaler Evaluation Board was
designed to help customers evaluate the PE3513
divide-by-8 prescaler. On this board, the device
input (pin 3) is connected to connector J1 through a
50 transmission line. A series capacitor (C1)
provides the necessary DC block for the device
input. A value of 100 pF was used for this board
layout; other applications may require a different
value.
The device output (pin 6) is connected to J3 through
a 50 transmission line. A series capacitor (C5)
provides the necessary DC block for the device
output. This capacitor value must be chosen to have
a low impedance at the desired output frequency of
the device. A value of 100 pF was chosen for the
evaluation board. At both input and output, select a
capacitor value that offers low series reactance while
ensuring that any parasitic resonances are well
above the operating bandwidth.
The board is constructed of a two-layer FR4 material
with a total thickness of 0.031”. The bottom layer
provides ground for the RF transmission lines. The
transmission lines were designed using a coplanar
waveguide above ground plane mod el with trace
width of 0.030”, trace gaps of 0.007”, dielectric
thickness of 0.028”, metal thickness of 0.0014”, and
r of 4.4. Note that the predominate mode of these
transmission lines is coplanar waveguide. Liberal
numbers of plated through holes unite the top and
bottom ground areas for best performance.
J6 provides DC power to the device via pin 4. Two
decoupling capacitors (100 pF, 1000 pF) are
included on this trace. It is the customer’s
responsibility to determine proper supply decoupling
for their design application.
OBSOLETE
Product Specification
PE3513
Page 7 of 9
©2003-2008 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0108-06 www.psemi.com
Figure 11. Package Drawing
6-lead SC-70
1.80
2.20
0.65
BSC
1.80
2.40
1.15
1.35
0.15
0.30
0.80
1.10
0.80
1.00
0.10
0.30
0.10
0.40 0.10
0.18
0.00
0.10
OBSOLETE
Product Specification
PE3513
Page 8 of 9
©2003-2008 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0108-06 UltraCMOS™ RFIC Solutions
Table 7. Ordering Information
Order Code Part Marking Description Package Shipping Method
3513-51 513 PE3513G-06SC70-7680A Green 6-lead SC-70 Tape or loose
3513-52 513 PE3513G-06SC70-3000C Green 6-lead SC-70 3000 units / T&R
3513-00 PE3513-EK PE3513-06SC70-EK Evaluation Kit 1 / Box
Figure 12. Tape and Reel Specifications
Pin 1
Tape Feed Direction
OBSOLETE
Product Specification
PE3513
Page 9 of 9
©2003-2008 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0108-06 www.psemi.com
Sales Offices
The Americas
Peregrine Semiconductor Corporation
9380 Carroll Park Drive
San Diego, CA 92121
Tel: 858-731-9400
Fax: 858-731-9499
Europe
Peregrine Semiconductor Europe
Bâtiment Maine
13-15 rue des Quatre Vents
F-92380 Garches, France
Tel: +33-1-4741-9173
Fax : +33-1-4741-9173
For a list of representatives in your area, pleas e refer to our W eb site at: www.psemi.com
Data Sheet Identification
Advance Information
The product is in a formative or design stage. The data
sheet contains design targ et specifications for product
development. Specifications and features may change in
any manner without notice.
Preliminary Specification
The data sheet contains preli m inary data. Additional data
may be added at a later date. Peregrine reserves the right
to change specifications at any time without notice in order
to supply the best possible product.
Product Specification
The data sheet contains final data. In the event Peregrine
decides to change the specifications, Peregrine will notify
customers of the intended changes by issuing a DCN
(Document Change Notice).
The information in this data sheet is believed to be reliable.
However, Peregrine assumes no li ability for the use of this
information. Use shall be entirely at the user ’s own risk.
No patent rights or licenses to any circuits describe d in this
data sheet are implied or gran ted to any third party.
Peregrine’s products are not designed or intended for use in
devices or systems intended for surgical implant, or in other
applications intended to support or sustain life, or in any
application in which the failur e of the Peregrine product could
create a situation in which personal injury or death might occur.
Peregrine assumes no liability for damages, including
consequential or incidental da mages, arising out of the use of
its products in such applications.
The Peregrine name, logo, an d UTSi are registered trademarks
and UltraCMOS and HaRP ar e trademarks of Peregrine
Semiconductor Corp.
Space and Defense Products
Americas:
Tel: 858-731-9453
Europe, Asia Pacific:
180 Rue Jean de Guiram and
13852 Aix-En-Provence Cedex 3, France
Tel: +33-4-4239-3361
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Shanghai, 200040, P.R. China
Tel: +86-21-5836-8276
Fax: +86-21-5836-7652
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#B-2607, Kolon Tripolis, #210
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Tel: +82-31-728-4300
Fax: +82-31-728-4305
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Teikoku Hotel Tower 10B-6
1-1-1 Uchisaiwai-cho, Chiyoda-ku
Tokyo 100-0011 Japan
Tel: +81-3-3502-5211
Fax: +81-3-3502-5213
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