TC74HC161,163AP/AF
2012-02-29
1
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC74HC161AP,TC74HC161AF
TC74HC163AP,TC74HC163AF
Synchronous Presettable 4-Bit Counter
TC74HC161AP/AF Binary, Asynchronous
Clear
TC74HC163AP/AF Binary, Synchronous
Clear
The TC74HC161A and 163A are high speed CMOS BINARY
PRESETTABLE COUNTERs fabricated with silicon gate C2MOS
technology.
They achieve the high speed operation similar to equivalent
LSTTL while maintaining the CMOS low power dissipation.
The CK input is active on the rising edge. Both LOAD and
CLR inputs are active on low logic level.
Presetting of their IC’s is synchronous to the rising edge of CK.
The clear function of the TC74HC163A is synchronous to CK,
while the TC74HC161A is cleared asynchronously.
Two enable inputs (ENP and ENT) and CO are provided to
enable easy cascading of counters, which facilitates easy
implementation of n-bit counters without using external gates.
All inputs are equipped with protection circuits against static
discharge or transient excess voltage.
Features
• High speed: fmax = 63 MHz (typ.) at VCC = 5 V
• Low power dissipation: ICC = 4 μA (max) at Ta = 25°C
• High noise immunity: VNIH = VNIL = 28% VCC (min)
• Output drive capability: 10 LSTTL loads
• Symmetrical output impedance: |IOH| = IOL = 4 mA (min)
• Balanced propagation delays: tpLH ∼
−
tpHL
• Wide operating voltage range: VCC (opr) = 2 to 6 V
• Pin and function compatible with 74LS161, 163
Pin Assignment
TC74HC161AP, TC74HC163AP
TC74HC161AF, TC74HC163AF
Weight
DIP16-P-300-2.54A : 1.00 g (typ.)
SOP16-P-300-1.27A : 0.18 g (typ.)
TC74HC161,163AP/AF
2012-02-29
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IEC Logic Symbol
TC74HC161A TC74HC163A
Truth Table
TC74HC161A TC74HC163A
Inputs Inputs
Outputs
CLR LD ENP ENT CK CLR LD ENP ENT CK QA QB QC QD
Function
L X X X X L X X X L L L L Reset to “0”
H L X X H L X X A B C D Preset Data
H H X L H H X L No Change No Count
H H L X H H L X No Change No Count
H H H H H H H H Count Up Count
H X X X X X X X No Change No Count
X: Don’t care
A, B, C, D: Logic level of data inputs
Carry: Carry = ENT･QA･QB･QC･QD
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2012-02-29
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Timing Chart
TC74HC161,163AP/AF
2012-02-29
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System Diagram
Note: Truth table of internal F/F
TC74HC161A TC74HC163A
D CK R Q Q D CK R Q Q
X X L L H X L L H
L H L H L H L H
H H H L H H H L
X H No Change L H No Change
X: Don’t care
(Note)
(Note)
(Note)
(Note)
TC74HC161,163AP/AF
2012-02-29
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Absolute Maximum Ratings (Note 1)
Characteristics Symbol Rating Unit
Supply voltage range VCC −0.5 to 7 V
DC input voltage VIN −0.5 to VCC + 0.5 V
DC output voltage VOUT −0.5 to VCC + 0.5 V
Input diode current IIK ±20 mA
Output diode current IOK ±20 mA
DC output current IOUT ±25 mA
DC VCC/ground current ICC ±50 mA
Power dissipation PD 500 (DIP) (Note 2)/180 (SOP) mW
Storage temperature Tstg −65 to 150 °C
Note 1: Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or
even destruction.
Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the
significant change in temperature, etc.) may cause this product to decrease in the reliability significantly
even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute
maximum ratings and the operating ranges.
Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook
(“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test
report and estimated failure rate, etc).
Note 2: 500 mW in the range of Ta = −40 to 65°C. From Ta = 65 to 85°C a derating factor of −10 mW/°C shall be
applied until 300 mW.
Operating Ranges (Note)
Characteristics Symbol Rating Unit
Supply voltage VCC 2 to 6 V
Input voltage VIN 0 to VCC V
Output voltage VOUT 0 to VCC V
Operating temperature Topr −40 to 85 °C
Input rise and fall time tr, tf
0 to 1000 (VCC = 2.0 V)
0 to 500 (VCC = 4.5 V)
0 to 400 (VCC = 6.0 V)
ns
Note: The operating ranges must be maintained to ensure the normal operation of the device.
Unused inputs must be tied to either VCC or GND.
TC74HC161,163AP/AF
2012-02-29
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Electrical Characteristics
DC Characteristics
Test Condition Ta = 25°C Ta =
−40 to 85°C
Characteristics Symbol
VCC (V) Min Typ. Max Min Max
Unit
High-level input
voltage VIH ⎯
2.0
4.5
6.0
1.50
3.15
4.20
⎯
⎯
⎯
⎯
⎯
⎯
1.50
3.15
4.20
⎯
⎯
⎯
V
Low-level input
voltage VIL ⎯
2.0
4.5
6.0
⎯
⎯
⎯
⎯
⎯
⎯
0.50
1.35
1.80
⎯
⎯
⎯
0.50
1.35
1.80
V
IOH = −20 μA
2.0
4.5
6.0
1.9
4.4
5.9
2.0
4.5
6.0
⎯
⎯
⎯
1.9
4.4
5.9
⎯
⎯
⎯
High-level output
voltage VOH VIN
= VIH or VIL
IOH = −4 mA
IOH = −5.2 mA
4.5
6.0
4.18
5.68
4.31
5.80
⎯
⎯
4.13
5.63
⎯
⎯
V
IOL = 20 μA
2.0
4.5
6.0
⎯
⎯
⎯
0.0
0.0
0.1
0.1
0.1
0.1
⎯
⎯
⎯
0.1
0.1
0.1
Low-level output
voltage VOL VIN
= VIH or VIL
IOL = 4 mA
IOL = 5.2 mA
4.5
6.0
⎯
⎯
0.17
0.18
0.26
0.26
⎯
⎯
0.33
0.33
V
Input leakage
current IIN V
IN = VCC or GND 6.0 ⎯ ⎯ ±0.1 ⎯ ±1.0 μA
Quiescent supply
current ICC V
IN = VCC or GND 6.0 ⎯ ⎯ 4.0 ⎯ 40.0 μA
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Timing Requirements (input: tr = tf = 6 ns)
Test Condition Ta = 25°C
Ta =
−40 to
85°C
Characteristics Symbol
V
CC (V) Typ. Limit Limit
Unit
Minimum pulse width
(CK)
tW (H)
tW (L) Figure 1
2.0
4.5
6.0
⎯
⎯
⎯
75
15
13
95
19
16
ns
Minimum pulse width
(CLR ) (Note 1)
tW (L) Figure 4
2.0
4.5
6.0
⎯
⎯
⎯
75
15
13
95
19
16
ns
Minimum set-up time
(LOAD , ENP, ENT) ts Figure 2, Figure 3
2.0
4.5
6.0
⎯
⎯
⎯
100
20
17
125
25
21
ns
Minimum set-up time
(A, B, C, D) ts Figure 2
2.0
4.5
6.0
⎯
⎯
⎯
75
15
13
95
19
16
ns
Minimum set-up time
(CLR ) (Note 2)
ts Figure 5
2.0
4.5
6.0
⎯
⎯
⎯
75
15
13
95
19
16
ns
Minimum hold time th Figure 2, Figure 3, Figure 5
2.0
4.5
6.0
⎯
⎯
⎯
0
0
0
0
0
0
ns
Minimum removal time
(CLR ) (Note 1)
trem Figure 4
2.0
4.5
6.0
⎯
⎯
⎯
50
10
9
65
13
11
ns
Clock frequency f ⎯
2.0
4.5
6.0
⎯
⎯
⎯
6
31
36
5
25
29
MHz
Note 1: For TC74HC161A only
Note 2: For TC74HC163A only
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AC Characteristics (CL = 15 pF, VCC = 5 V, Ta = 25°C, input: tr = tf = 6 ns)
Characteristics Symbol Test Condition Min Typ. Max Unit
Output transition time tTLH
tTHL
Figure 1 ⎯ 4 8 ns
Propagation delay time
(CK-Q)
tpLH
tpHL
Figure 1 ⎯ 13 21 ns
Propagation delay time
(CK-CO)
[count mode]
tpLH
tpHL
Figure 1 ⎯ 16 26 ns
tpLH ⎯ 18 30
Propagation delay time
(CK-CO)
[preset mode] tpHL
Figure 2
⎯ 20 35
ns
Propagation delay time
(ENT-CO)
tpLH
tpHL
Figure 6 ⎯ 10 17 ns
Propagation delay time
(CLR -Q) (Note)
tpHL Figure 4 ⎯ 17 26 ns
Propagation delay time
(CLR -CO) (Note)
tpHL Figure 4 ⎯ 20 35 ns
Maximum clock frequency fmax ⎯ 36 63 ⎯ MHz
Note: For TC74HC161A only
TC74HC161,163AP/AF
2012-02-29
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AC Characteristics (CL = 50 pF, input: tr = tf = 6 ns)
Test Condition Ta = 25°C Ta =
−40 to 85°C
Characteristics Symbol
VCC (V) Min Typ. Max Min Max
Unit
Output transition time tTLH
tTHL ⎯
2.0
4.5
6.0
⎯
⎯
⎯
25
7
6
75
15
13
⎯
⎯
⎯
95
19
16
ns
Propagation delay
time
(CK-Q)
tpLH
tpHL
Figure 1
2.0
4.5
6.0
⎯
⎯
⎯
48
16
14
125
25
21
⎯
⎯
⎯
155
31
26
ns
Propagation delay
time
(CK-CO)
[count mode]
tpLH
tpHL
Figure 1
2.0
4.5
6.0
⎯
⎯
⎯
57
19
16
150
30
26
⎯
⎯
⎯
190
38
33
ns
tpLH
2.0
4.5
6.0
⎯
⎯
⎯
66
22
19
175
35
30
⎯
⎯
⎯
220
44
37
Propagation delay
time
(CK-CO)
[preset mode] tpHL
Figure 2
2.0
4.5
6.0
⎯
⎯
⎯
72
24
20
200
40
34
⎯
⎯
⎯
250
50
43
ns
Propagation delay
time
(ENT-CO)
tpLH
tpHL
Figure 6
2.0
4.5
6.0
⎯
⎯
⎯
39
13
11
100
20
17
⎯
⎯
⎯
125
25
21
ns
Propagation delay
time
(CLR -Q) (Note 2)
tpHL Figure 4
2.0
4.5
6.0
⎯
⎯
⎯
60
20
17
150
30
26
⎯
⎯
⎯
190
38
33
ns
Propagation delay
time
(CLR -CO) (Note 2)
tpHL Figure 4
2.0
4.5
6.0
⎯
⎯
⎯
72
24
20
200
40
34
⎯
⎯
⎯
250
50
43
ns
Maximum clock
frequency fmax ⎯
2.0
4.5
6.0
6
31
36
18
53
62
⎯
⎯
⎯
5
25
29
⎯
⎯
⎯
MHz
Input capacitance CIN ⎯ ⎯ 5 10 ⎯ 10 pF
Power dissipation
capacitance
CPD
(Note 1) ⎯ ⎯ 34 ⎯ ⎯ ⎯ pF
Note 1: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating
current consumption without load.
Average operating current can be obtained by the equation:
ICC (opr) = CPD･VCC･fIN + ICC
When the outputs drive a capacitive load, total current consumption is the sum of CPD, and ΔICC which is
obtained from the following formula:
In case of TC74HC161A/163A:
)
16
C
16
C
8
C
4
C
2
C
(VfI CO
QDQCQBQA
CCCKCC ++++⋅=Δ
CQA~CQD and CCO are the capacitances at QA~QD and CO, respectively.
fCK is the input frequency of the CK.
Note 2: For TC74HC161A only
TC74HC161,163AP/AF
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Switching Characteristics Test Waveform
Count Mode Clear Mode (TC74HC161A)
Preset Mode Clear Mode (TC74HC163A)
Count Enable Mode Cascade Mode (fix maximum count)
Figure 3 Figure 6
Figure 2 Figure 5
Figure 1 Figure 4
TC74HC161,163AP/AF
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Typical Application
Parallel Carry N-Bit Counter
TC74HC161,163AP/AF
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Package Dimensions
Weight: 1.00 g (typ.)
TC74HC161,163AP/AF
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Package Dimensions
Weight: 0.18 g (typ.)
TC74HC161,163AP/AF
2012-02-29
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