TOSHIBA THLY648031BFG-80,-80L,-10,-10L TENTATIVE TOSHIBA HYBRID DIGITAL INTEGRATED CIRCUIT 8,388,608-WORD BY 64-BIT SYNCHRONOUS DRAM MODULE DESCRIPTION The THLY648031BFG is a 8,388,608-word by 64-bit synchronous dynamic RAM module consisting of eight TC59S6408BFT/BFTL DRAMs on a printed circuit board. FEATURES @ 8,388,608-word by 64-bit organization -80 -10 tek Clock Cycle Time (CL = 2) 10 ns 12 ns tras Active-to-Precharge Command 48 ns 60 ns Period (min) tac Access Time from CLK (CL = 2) 6ns 8ns tre Ref/Active-to-Ref/Active 68 ns 84 ns Command Period (min) PIN ASSIGNMENT Single power supply of 3.3 V + 0.3 V Pipeline architecture Auto-refresh and Self-refresh capability All inputs and outputs LVTTL-compatible 4096 refresh cycles per 64 ms Package: 144-pin small-outline DIMM (gold contacts) PIN NAMES FRONT 4 BACK 143 o1 59, 61 LUO LO TTT) COT) fT O02 60 62 1440 All 1 {/\N o 39 40 41 10 42 11 44 45| VDD VDD 47{0Q12 48/| DQ44 87 1 95] 0Q21 VDO 66] /CAS 96| 0Q53 99 101{ VDD 1 107 109} A9 111] A10 113] VDD 117 1 421 123 1 1 1 136 138 1 141 142 1431 VOD 144; VDD 961001EBA1 operatin @ The information contained herein is @ TOSHIBA is continually working to improve the quality and the reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified ranges as set forth in the most recent products specifications. Also, please keep in mind the precautions and conditions set forth in the TOSHIBA Semiconductor Reliability Handbook. @ The products described in this document are subject to foreign exchange and foreign trade control laws. resented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. @ The information contained herein is subject to change without notice. 1998-02-16 1/13TOSHIBA THLY648031BFG-80,-80L,-10,-10L Serial Presence Detect (Rev.1.2A) Naneor Function Described = 10 Entry Value Entry Entry Value Entry 0 muret bytes Written into Serial Memory at Module 128bytes 80h 128bytes Boh 1 Total # bytes of SPD Memory Device 256bytes 08h 256bytes 08h 2 (EM EDO. SDRAM Fires Appendix A SDRAM 04h SDRAM O4h 3 # Row Addresses on this Assembly RAOQ-RA11 OCh RAO-RA11 0Ch 4 # Column Addresses on this Assembly CA0-CA8 09h CA0-CA8 09h 5 # Module Banks on this Assembly 1Bank Oth 1Bank Oth 6 Data Width of this Assembly... x64 40h x64 40h 7 ..Data Width Continuation x64 00h x64 00h 8 Voltage Interface Standard of this Assembly LVTTL Oth LVTTL O1h 9 SORAM Cycle Time at Max. Supported CAS Latency (CL), CL = 3, 8.0ns 80h CL = 3, 10ns Ah 10 SDRAM Access from Clock @ Ct = X CL = 3, 6.0ns 60h CL = 3, 7.0ns 70h WW DIMM Configuration Type (Non-parity, Parity, ECC) Non-Parity 00h Non-Parity 00h 12 Refresh Rate/Type 15.625 ys/self 80h 15.625 ps/self 80h 13 SDRAM Width, Primary DRAM x8 08h x8 08h 14 Error Checking SDRAM Data Width N/A 00h N/A 00h 15 amu Clock Delay, Back to Back Random Column CLK Oth CLK Oth 16 Burst Lengths Supported 1,2,4,8 Full page 8Fh 1,2,4,8 Full page 8Fh 17 # Banks on each SDRAM Device 4Bank 04h 4Bank 04h 18 CAS # Latencies Supported 2,3 O6h 2,3 06h 19 cs # Latency Oth Oth 20 WE # Latency Oth O1h 21 SDRAM Module Attributes 00h 00h 22 SDRAM Device Attributes: General OEh OEh 23 Minimum Clock Cycle Time at CL- X-1 CL = 2, 10ns Ah CL = 2, 12 ns cOh 24 Maximum Data Access Time from Clock @ CL X-1 CL = 2, 6.0 ns 60h CL = 2, 8.0ns 80h 25 Minimum Clock Cycle Time at CL X-2 00h 00h 26 Maximum Data Access Time from Clock @ CL X-2 00h 00h 27 Minimum Row Precharge Time 20 ns 14h 24ns 18h 28 Minimum Row Active to Row Active Delay 20 ns 14h 20 ns 14h 29 Minimum RAS to CAS Delay 20 ns 14h 24ns 18h 30 Minimum RAS Pulse Width 48 ns 30h 60 ns 3Ch 31 Module/Bank Density 64MB 10h 64MB 10h 32 Command & Address signal Input Set-up Time 2ns 20h 2.5ns 25h 33 Command & Address signal Input Hold Time Ins 10h 1ns 10h 34 Data signal Input Set-up Time 2ns 20h 2.5 ns 25h 35 Data signal Input Hold Time Ins 10h Ins 10h 36-61 Superset information (may be used in future) FFh FFh 62 SPD Revision Rev.1.2A 12h Rev.1.2A 12h 63 Checksum for bytes 0-62 1EC9h C9h 1F57h 57h Option Manufacturers JEDEC ID Code per JEP-106E Manufacturing Location Manufacturer's Part Number Revision Code Manufacturing Date Assem Serial Number Manufacturer Data Reserved Intel Specification Intel Specification Reserved intel Specification Intel Specification 1998-02-16 2/13TOSHIBA BLOCK DIAGRAM CLKOo THLY6480318FG-80,-80L,-10,-10L pamso DQMB2 rain cs DQM =e cs0 9 oS OB F- peo vgieoJ or s 4S eee Bet ga 1 is RAS +t GAS VO3 DQ2 CAS HL voa - DpQ3.--:DQ19 OJ 1/04 rt CKE M1 vos [ Dod 0Q20 oO_} 1/05 M3 CKE HYy dt We vO6 F DQs 0Q210j 1/06 we Hh AO to 1 vO7 |- DQ6 0Q22{ 1/07 AO to 11 CLK aso,1 VOB F- 0Q7_- G23. O}_ 108 aso, CLK | | DQMB1 DQMB3 | | GS ORM Lf 0 bes pqzao or s WW Ht RAS vOo2 -o 099, 0923 o VO2 RAS He IW Ltt CAS 03 [2 o | CAS Hi V04 -O DQi1 DQ270} 1/04 prot CKE M2 vOS F _DQ12 Ba28 oO VvO5 M4 CKE Hiv WE VOB + DQ13. _0Qz90-J 1/06 WE Adto 1, "O72 F~2 0Q140Q30 O 7 N07 A0 to 11 CLK 80,1 | VOB FO DQIS 0Q31 OJ 1/08 350.1 CLK | pamB4 DQMBE | | cs ot fo 0932 paago] vor cs 1 RAS vO2 7? 0933 pQ49 OJ v2 RAS HK po CLK1 I CAS v03 [-- DQs0 OoJ A ane Hy CAS M5 vo4 }O _DQ35 Dost o{ 04 M7 CAS T71 try] CKE VO5 fF _0Q36 -0Q52 O_{_ 1/05 CKE F171 WE 106 } DQ37__DQs3 OJ 1/06 WE aoto 1, VO? FF 8 9938 0Q54. OF 07 AO to 11 cLK Bso,1 O8 F9 9Q39_ 0Qs5 oO | 08 BS0,1 CLK | | DQMBS5 DQMB7 2 | Cs DQM DQM =< CS io1 Po bao 0Q56}_/01 cs LaW4 1 RAS O2 F 0941 9Q57 0-4 1/02 RAS 14 r-wW Wt CAS 03 F? 0Q42 pass O-} 1/03 cas M6 VO4 -DQ43.- pqs9 OJ 1/04 Ms H+ CKE VO5 F2 0Q44 pQ0 OJ 1/05 CKE Fy44 WE VO6 T? DQ45_pgeg1 OJ 1/06 WE Adto 1, vO7 F? 0Q48 pgez OJ 107 AO to 11, CLK 8S0,1 v8 [- 0047 pQ3 O} 1/08 BS0,1 CLK RAS o CAS Keo | AO to 11, BAO,1 Vop @ Mito8 Vpop o > E2PROM V TC1 to 8 C9 to 16 C17 to 24 V F 025 SS Oo + + * > M1 to 8 35 6 + E2PROM 2 SCL o-4 SCL E2PROM SDA o SDA AO Al A2_ WC i__{ | f 777 1998-02-16 3/13TOSHIBA THLY648031BFG-80,-80L,-10,-10L ABSOLUTE MAXIMUM RATINGS SYMBOL ITEM RATING UNIT NOTES Vin Input Voltage -0.3 to Vcc + 0.3 Vv 1 Vout Output Voltage -0.3 to Vec + 0.3 Vv 1 Vpp Power Supply Voltage -0.3 to 4.6 Vv 1 Topr Operating Temperature 0 to 70 c 1 TstG Storage Temperature -55 to 125 C 1 Pp Power Dissipation 2.4 w 1 lout Short Circuit Output Current 50 mA 1 RECOMMENDED DC OPERATING CONDITIONS (Ta = 0 to 70C) SYMBOL PARAMETER MIN TYP. MAX UNIT NOTES Voo Supply Voltage 3.0 3.3 3.6 Vv 2 Vin LVTTL Input High Voltage 2.0 - Vpp + 0.3 Vv 2 Vic LVTTL Input Low Voltage -0.3 - 0.8 Vv 2 CAPACITANCE (Vcc = 3.3V,f = 1MHz, Ta = 0 to 70C) SYMBOL PARAMETER MIN MAX UNIT Cy Input Capacitance (AO to Al1) - T.B.D. pF Co Input Capacitance (RAS, CAS, WE) - T.B.D. pF C3 Input Capacitance (CLKO,1) - T.B.D. pF Ca Input Capacitance (CSO) - T.B.D. pF Cs Input Capacitance (DQMBO to 7) - T.B.D. pF Cog /O Capacitance (DQO to DQ63) - T.B.D. pF 1998-02-16 4/13TOSHIBA THLY648031BFG-80,-80L,-10,-10L DC CHARACTERISTICS (Vcc = 3.3V + 0.3V, Ta = 0 to 70C) -80 -10 SYMBOL ITEM UNIT | NOTES MIN MAX MIN MAX lec OPERATING CURRENT 1 | Active-Precharge Command Cycling . without Burst Operation 1-Bank Operation - 720 - 560 mA 3 lec1B (tex = tre min) STANDBY CURRENT oe KE=V ~ 400 - 320 lec2 (tek = min, CS = Vin: CKE lH mA 3 Vie = Vin (min) / Vy (max) CKE = Vip 8 8 lccap_ | Bank: Inactive State) (Power-down Mode) - - STANDBY CURRENT ae =V - 64 - 64 lec2zs_ | (CLK = Vu, CS = Vin, CKE = Vin nA Vint = Vin (min) / Vi (max) CKE = Vi 8 3 IccaPs._ | Bank: Inactive State) (Power-down Mode) - - lec3 NO OPERATING CURRENT CKE = Viy - 520 - 400 (tex = min, CS = Viy (min) CKE= Vi mA 3 Icc3p | Bank: Active State (2 Banks)) (Power-down Mode) - 64 - 64 BURST OPERATING CURRENT 1120 380 mA 3.4 cea (tc = min, CS = Vin (min) Read/Write Command Cycling) I AUTO-REFRESH CURRENT _ 1120 . 880 mA 3 ces (tex = min, Auto-Refresh Command Cycling) SELF-REFRESH CURRENT THLY648031BFG-80,-10 - 8 - 8 A 5 SS | (Self-Refresh Mode, CKE=0.2V) | riveqgostarc-ao.-1o; - | 36 | - | 36 INPUT LEAKAGE CURRENT -5 5 -5 5 WA Ww) (OV S Vin S Vpp, All Other Pins Not under Test = 0V) OUTPUT LEAKAGE CURRENT -5 5 5 5 WA OW | (Dour Is Disabled, 0 V S Vout S Vpn) Vv OUTPUT LEVEL 24 2A V OH | LVTTL Output H Level Voltage (lout = -2mA) , , Vv OUTPUT LEVEL 04 04 V ot LVTTL Output L Level Voltage (lout = 2 mA) , , 1998-02-16 5/13TOSHIBA THLY648031BFG-80,-80L,-10,-10L AC CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS (Vcc = 3.3V + 0.3V, Ta = 0 to 70C) -80 -10 SYMBOL PARAMETER MIN MAX MIN MAX UNIT | NOTES tre Ref/Active-Ref/Active Command Period 68 84 tras Active- Precharge Command Period 48 100000 60 100000 ns treo Active-Read/Write Command Delay Time 20 24 tecp Read/Write(a) ~Read/Write(b) 1 1 cycle 9 Command Period trp Precharge-Active Command Period 20 24 trrao Active(a)-Active(b) Command Period 20 20 twr Write Recovery Time CL* =2 10 12 CL* = 3 8 10 tex CLK Cycle Time CL* =2 10 1000 12 1000 CL* = 3 8 1000 10 1000 tou CLK High Level Width 3 3 10 te. CLK Low Level Width 3 3 tac Access Time from CLK CL* =2 6 8 CL* =3 6 7 ton Output Data Hold Time 3 3 tuz Output Data High Impedance Time 3 8 3 10 8 tiz Output Data Low Impedance Time 0 0 ns tsp Power-down Mode Entry Time 0 8 0 10 tr Transition Time of CLK (Rise and Fall) 0.5 10 0.5 10 tos Data-in Set-up Time 2 2.5 tou Data-in Hold Time 1 1 tas Address Set-up Time 2 2.5 tan Address Hold Time 1 | teks CKE Set-up Time 2 2.5 teKH CKE Hold Time 1 { tems Command Set-up Time 2 25 tem Command Hold Time 1 1 trer Refresh Time 64 64 ms trsc Mode Register Set Cycle Time 16 20 ns 9 * CL is CAS latency. 1998-02-16 6/13TOSHIBA THLY648031BFG-80,-80L,-10,-10L NOTES: 1, Conditions outside the limits listed under Absolute Maximum Ratings may cause permanent damage to the device. 2. All voltages are referenced to Vss. 3. These parameters depend on the cycle rate and their values are measured at the minimum cycle rate values tcx and trc. Input signals are changed once during tcx. 4, These parameters depend on the output loading. The specified values are obtained with the output open. 5. The power-up sequence is described in Note 11. 6. AC TEST CONDITIONS ence Level i 1.4V/1.4V Load See the di m for AC Test Load (B) below Input Signal Levels 2.4V/0.4V Transition Time (Rise and Fall) of Si 2ns I | 1.4V 3.3V 1.4V 1.2kQ g,, Q Output Output Tr 50 pF 8702 T 50 pF AC TEST LOAD (A) AC TEST LOAD (B) 7. Transition times are measured between the Vjy and Vyz, levels. Transition (rise and fall) of input signals has a fixed slope. 8. tyz, defines the time at which the outputs go open circuit and are not reference levels. 9. These parameters depend on the number of clock cycles and depend on the operating frequency of the clock as follows: Number of clock cycles = Specified value of timing /Clock period (Round up fractions to a whole number.) 1998-02-16 7/13TOSHIBA THLY648031BFG-80,-80L,-10,-10L 10, 11. tcH is the pulse width of CLK measured from the positive edge to the negative edge and referenced to Vi (min). tcy is the pulse width of CLK measured from the negative edge to the positive edge and referenced to Vyz, (max). Power-up Sequence Power-up must be performed in the following sequence. 1) Power must be applied to Vcc and VccQ (simultaneously) with all input signals held in the NOP state. The CLK signal must be started at the same time as power is applied. 2) After power-up a pause of at least 200 seconds is required. Then, DQM and CKE must be held High (at the Vcc level) to ensure that the DQ output is high-impedance. 3) Both banks must be precharged. 4) The Mode Register Set command must be asserted to initialize the Mode register, 5) An Auto-Refresh operation must consist of at least eight Auto-Refresh cycles. The order in which 4) and 5) are performed is interchangeable. 1998-02-16 8/13TOSHIBA THLY648031BFG-80,-80L,-10,-10L TIMING DIAGRAMS Read Timing lL / =| TZHH LM. 37 | VIM]: WY \ MVHC@ VM YA soa TX NY. Ld Ld VM La Vdd __ (Z. | = }> Burst Length 1998-02-16 9/13TOSHIBA THLY648031BFG-80,-80L,-10,-10L Command Input Timin tek ter 41 tcH CLK vn ~ \ f VF Vglh \Ey - f Lf teomu - t EE eee i MR TT LT MM IN. VEZ Yi 1 TUL: aC ate ULI texsl. tek = PKS Le tcKH map s _t 1998-02-16 10/13TOSHIBA THLY648031BFG-80,-80L,-10,-10L Control Timing for Input Data (Word Mask) cux f \ FVII". tomy tems | temy tems DQMBO0 to 7 f t \ | tos tou tos] tow tos| tox T ton tos <-> ~<-_-| VALID VALID VALID VALID DQO to 63 DATA-IN Yy DATA-IN DATA-IN DATA-IN (Clock Mask) af "7. tekH teks | teKH es CKE Y \ / i t tos] tox tos | ton tos] tou tos| ton }<-_-| A VALID 4 VALID Vy VALID VALID DQO to 63 DATA-IN DATA-IN fy DATA-IN DATA-IN Control Timing for Output Data (Output Enable) CLK _f VP VP, temy tems] temH tems y \ Te DQMBO to 7 ] Lt tac tac le tHz ton ton tou VALID VALID DQO to 63 DATA-OUT DATA-OUT (Clock Mask) CLK j teKH teks | teKH teks < <>|~<. |< CKE + t } < tac sy le tac < tac tac | ton ton |_. tou tou VALID . VALID DQO to 63 DATA-OUT VALID DATA-OUT DATA-OUT 1998-02-16 11/13TOSHIBA THLY648031BFG-80,-80L,-10,-10L Mode Register Set Cycle CLK } tems cs tems tase CMH -_f temH us ) WMMM|@ es Yd tems WI tomy Uy cS MMMMW@@, i Y//) tems} tema ; we Yp, VUUUEE00280. Wh, tas tan I | frre mi ty saan [oa rosea mo Y/Y... XT. Next Command AO Burst A2_ Ai AO al Interleave Al Burst Length << a aT) 1 0 0 1 2 A2 0 1 Oo 4 A3 | Addressing Mode 9 i 1 8 1 0 0 A4 1 0 1 Reserved __ 1 1 0 Reserved CAS Latenc AS y 1 1 1 Full AG A3 Addressing Mode A7 | 0 | (Test Mode) 0 Sequential 1 interleave A8 | 0 Reserved AS Ad @AS Lat AQ Write Mode 0 0 Reserved A10/ 0 1 2 BAO | o Reserved 1 3 0 4 BA1] 0 . . AY Single-Write Mode 0 Burst Read and Burst Write 1 Burst Read and Single Write 1998-02-16 12/13TOSHIBA THLY648031BFG-80,-80L,-10,-10L PACKAGE DIMENSIONS (THLY648031BFG) Unit: mm FRONT Le 67.60 + 0.13 3.80 MAX tT I j - ol cc z 2 oO - non = = + o | | = 2 2 Oo + oO vT0g N = 18) 8 oF Oba ofDa__ of" | | LAB = a(elele} |. Oo CI co . 14 1 3 | 2.50,| 3.30 + 0.13 L 23.20 1.00 + 0.10 2.00 + 0.13 | |. 63.60 REF BACK 3.70 + 0.13 210 TMM 2 : On 3 U CONTACT DIMENSIONS @THLY648031BFG FULL-R To. FRONT i -_ I o 1 ! x z +i = 2 g in v ! N A | y 1 ' 0.60 + 0.05 0.80 | > oso] 150+0.10 ; $j! 2.50 ons 460 *| Contacts: gold Weight: g (typ) 1998-02-16 13/13