W28F321BB70L - Winbond Electronics

W28F321BB/TB

32MBIT (2MBIT × 16)

PAGE MODE DUAL WORK FLASH MEMORY

Publication Release Date: February 17, 2003

- 1 - Revision A2

1. GENERAL DESCRIPTION

The W28F321, a 4-Plane Page Mode Dual Work (Simultaneous Read while Erase/Program) Flash

memory, is a low power, high density, cost efficiency, nonvolatile read/write storage solution for a wide

range of applications. The product can be operated at VDD = 2.7V to 3.6V and VPP = 1.65V to 3.6V or

11.7V to 12.3V. Its low voltage operation capability greatly extends battery life for portable

applications.

The W28F321 provides high performance asynchronous page mode. It allows code execution directly

from Flash, thus eliminating time-consuming wait states. Furthermore, its configurative partitioning

architecture allows flexible dual work operation.

The memory array block architecture utilizes Enhanced Data Protection features, and provides

separate Parameter and Main Blocks that provide maximum flexibility for safe nonvolatile code and

data storage.

Fast program capability is provided through the use of high speed Page Buffer Program. Special OTP

(One Time Program) block provides an area to store permanent code such as a unique number.

2. FEATURES

• 32M Density with 16 Bit I/O Interface

• High-Performance Reads

− 70/25 nS 8-Word Page Mode

• Configurative 4-Plane Dual Work

− Flexible Partitioning

− Read operations during Block Erase or (Page

Buffer) Program

− Status Register for Each Partition

• Low Power Operation

− 2.7V Read and Write Operations

− VDDQ for Input/Output Power Supply Isolation

− Automatic Power Savings Mode Reduces

ICCR in Static Mode

• Enhanced Code + Data Storage

− 5 µS Typical Erase/Program Suspends

• OTP (One Time Program) Block

− 4-Word Factory-Programmed Area

− 4-Word User-Programmable Area

• High Performance Program with Page Buffer

− 16-Word Page Buffer

− 5 µS/ Word (Typ.) at 12V VPP

• Operating Temperature

− -40°C to +85°C

• CMOS Process (P-type silicon substrate)

• Flexible Blocking Architecture

− Eight 4k-word Parameter Blocks

− Sixty-three 32k-word Main Blocks

− Top or Bottom Parameter Location

• Enhanced Data Protection Features

− Individual Block Lock and Block Lock-Down

with Zero-Latency

− All blocks are locked at power-up or device

reset

− Absolute Protection with VPP ≤ VPPLK

W28F321BB/TB

- 2 -

− Block Erase, Full Chip Erase, (Page Buffer)

Word Program Lockout during Power

Transitions

• Automated Erase/Program Algorithms

− 3.0V Low-Power 11 µS/ Word (Typ.)

Programming

− 12V No Glue Logic 9 µS/ Word (Typ.)

Production Programming and 0.5s Erase

(Typ.)

• Cross-Compatible Command Support

− Common Flash Interface (CFI)

− Basic Command Set

• Extended Cycling Capability

− Minimum 100,000 Block Erase Cycles

• Chip-Size Packaging

− 0.75 mm pitch 48-Ball TFBGA(7mm x 7mm)

• ETOX™ Flash Technology

• No designed or rated as radiation hardened

* ETOX is a trademark of Intel Corporation.

3. PIN CONFIGURATION

#CE

5432

#OE

A17

DQ0

DQ8

DQ9

DQ1

A18

A20

DQ2

DQ10

DQ11

DQ3

#WP

#WE #RESET

A19

DQ5

DQ12

VDDQ

DQ4

A10

A11

DQ7

DQ14

DQ13

DQ6

A13

A12

A14

A15

A16

DQ15 Vss

Vss VDD

VPP

0. 75mm pitch

48-Ball TFBGA

Pinout

7 x 7 mm

TOP VIEW

Figure 1. 0.75 mm pitch TFBGA 48-Ball Pinout

W28F321BB/TB

Publication Release Date: February 17, 2003

- 3 - Revision A2

Table 1. Pin Descriptions

SYMBOL TYPE NAME AND FUNCTION

A0 − A20 INPUT ADDRESS INPUTS: Inputs for addresses. 32M: A0 − A20.

DQ0 − DQ15 INPUT/

OUTPUT

DATA INPUT/OUTPUTS: Inputs data and commands during CUI (Command User

Interface) write cycles, outputs data during memory array, status register, query code,

identifier code and partition configuration register code reads. Data pins float to high

impedance (High Z) when the chip or outputs are deselected. Data is internally

latched during an erase or program cycle.

#CE INPUT

CHIP ENABLE: Activates the device’s control logic, input buffers, decoders and

sense amplifiers. #CE-high (VIH) deselects the device and reduces power

consumption to standby levels.

#RESET INPUT

RESET: When low (VIL), #RESET resets internal automation and inhibits write

operations, which provides data protection. #RESET-high (VIH) enables normal

operation. After power-up or reset mode, the device is automatically set to read array

mode. #RESET must be low during power-up/down.

#OE INPUT

OUTPUT ENABLE: Gates the device’s outputs during a read cycle.

#WE INPUT

WRITE ENABLE: Controls writes to the CUI and array blocks. Addresses and data

are latched on the rising edge of #CE or #WE (whichever goes high first).

#WP INPUT

WRITE PROTECT: When #WP is VIL, locked-down blocks cannot be unlocked. Erase

or program operation can be executed to the blocks which are not locked and locked-

down. When #WP is VIH, lock-down is disabled.

VPP INPUT

MONITORING POWER SUPPLY VOLTAGE: VPP is not used for power supply pin.

With VPP ≤ VPPLK, block erase, full chip erase, (page buffer) program or OTP program

cannot be executed and should not be attempted.

Applying 12V±0.3V to VPP provides fast erasing or fast programming mode. In this

mode, VPP is power supply pin. Applying 12V±0.3V to VPP during erase/program can

only be done for a maximum of 1,000 cycles on each block. VPP may be connected to

12V±0.3V for a total of 80 hours maximum. Use of this pin at 12V beyond these limits

may reduce block cycling capability or cause permanent damage.

VDD SUPPLY

DEVICE POWER SUPPLY (2.7V to 3.6V): With VDD ≤ VLKO, all write attempts to the

flash memory are inhibited. Device operations at invalid VDD voltage (see DC

Characteristics) produce spurious results and should not be attempted.

VDDQ SUPPLY

INPUT/OUTPUT POWER SUPPLY (2.7V to 3.6V): Power supply for all input/output

pins.

VSS SUPPLY

GROUND: Do not float any ground pins.

NO CONNECT: Lead is not internally connected; it may be driven or floated.

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Table 2. Simultaneous Operation Modes Allowed with Four Planes(1,2)

THEN THE MODES ALLOWED IN THE OTHER PARTITION IS:

IF ONE

PARTITION IS

Read

Array

Read

ID/OTP

Read

Status

Read

Query

Word

Program

Page

Buffer

Program

OTP

Program

Block

Erase

Full

Chip

Erase

Program

Suspend

Block

Erase

Suspend

Read Array X X X X X X X X X

Read ID/OTP X X X X X X X X X

Read Status X X X X X X X X X X X

Read Query X X X X X X X X X

Word Program X X X X X

Page Buffer

Program X X X X X

OTP Program X

Block Erase X X X X

Full Chip Erase X

Program

Suspend X X X X X

Block Erase

Suspend X X X X X X X

Notes:

1. "X" denotes the operation available.

2. Configurative Partition Dual Work Restrictions:

Status register reflects partition state, not WSM (Write State Machine) state - this allows a status register for each partition.

Only one partition can be erased or programmed at a time - no command queuing.

Commands must be written to an address within the block targeted by that command.

W28F321BB/TB

Publication Release Date: February 17, 2003

- 5 - Revision A2

BLOCK NUMBER ADDRESS RANGE

70 4K-WORD 1FF000h - 1FFFFFh

69 4K-WORD 1FE000h - 1FEFFFh

68 4K-WORD 1FD000h - 1FDFFFh

67 4K-WORD 1FC000h - 1FCFFFh

66 4K-WORD 1FB000h - 1FBFFFh

65 4K-WORD 1FA000h - 1FAFFFh

64 4K-WORD 1F9000h - 1F9FFFh

63 4K-WORD 1F8000h - 1F8FFFh

62 32K-WORD 1F0000h - 1F7FFFh

61 32K-WORD 1E8000h - 1EFFFFh

60 32K-WORD 1E0000h - 1E7FFFh

59 32K-WORD 1D8000h - 1DFFFFh

58 32K-WORD 1D0000h - 1D7FFFh

57 32K-WORD 1C8000h - 1CFFFFh

56 32K-WORD 1C0000h - 1C7FFFh

55 32K-WORD 1B8000h - 1BFFFFh

54 32K-WORD 1B0000h - 1B7FFFh

53 32K-WORD 1A8000h - 1AFFFFh

52 32K-WORD 1A0000h - 1A7FFFh

51 32K-WORD 198000h - 19FFFFh

50 32K-WORD 190000h - 197FFFh

49 32K-WORD 188000h - 18FFFFh

PLANE3 (PARAMETER PLANE)

48 32K-WORD 180000h - 187FFFh

47 32K-WORD 178000h - 17FFFFh

46 32K-WORD 170000h - 177FFFh

45 32K-WORD 168000h - 16FFFFh

44 32K-WORD 160000h - 167FFFh

43 32K-WORD 158000h - 15FFFFh

42 32K-WORD 150000h - 157FFFh

41 32K-WORD 148000h - 14FFFFh

40 32K-WORD 140000h - 147FFFh

39 32K-WORD 138000h - 13FFFFh

38 32K-WORD 130000h - 137FFFh

37 32K-WORD 128000h - 12FFFFh

36 32K-WORD 120000h - 127FFFh

35 32K-WORD 118000h - 11FFFFh

34 32K-WORD 110000h - 117FFFh

33 32K-WORD 108000h - 10FFFFh

PLANE2 (UNIFORM PLANE)

32 32K-WORD 100000h - 107FFFh

BLOCK NUMBER ADDRESS RANGE

31 32K-WORD 0F8000h - 0FFFFFh

30 32K-WORD 0F0000h - 0F7FFFh

29 32K-WORD 0E8000h - 0EFFFFh

28 32K-WORD 0E0000h - 0E7FFFh

27 32K-WORD 0D8000h - 0DFFFFh

26 32K-WORD 0D0000h - 0D7FFFh

25 32K-WORD 0C8000h - 0CFFFFh

24 32K-WORD 0C0000h - 0C7FFFh

23 32K-WORD 0B8000h - 0BFFFFh

22 32K-WORD 0B0000h - 0B7FFFh

21 32K-WORD 0A8000h - 0AFFFFh

20 32K-WORD 0A0000h - 0A7FFFh

19 32K-WORD 098000h - 09FFFFh

18 32K-WORD 090000h - 097FFFh

17 32K-WORD 088000h - 08FFFFh

PLANE1 (UNIFORM PLANE)

16 32K-WORD 080000h - 087FFFh

15 32K-WORD 078000h - 07FFFFh

14 32K-WORD 070000h - 077FFFh

13 32K-WORD 068000h - 06FFFFh

12 32K-WORD 060000h - 067FFFh

11 32K-WORD 058000h - 05FFFFh

10 32K-WORD 050000h - 057FFFh

9 32K-WORD 048000h - 04FFFFh

8 32K-WORD 040000h - 047FFFh

7 32K-WORD 038000h - 03FFFFh

6 32K-WORD 030000h - 037FFFh

5 32K-WORD 028000h - 02FFFFh

4 32K-WORD 020000h - 027FFFh

3 32K-WORD 018000h - 01FFFFh

2 32K-WORD 010000h - 017FFFh

1 32K-WORD 008000h - 00FFFFh

PLANE0 (UNIFORM PLANE)

0 32K-WORD 000000h - 007FFFh

Figure 2.1 Top Parameter Memory Map

W28F321BB/TB

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BLOCK NUMBER ADDRESS RANGE

70 32K-WORD 1F8000H - 1FFFFFH

69 32K-WORD 1F0000H - 1F7FFFH

68 32K-WORD 1E8000H - 1EFFFFH

67 32K-WORD 1E0000H - 1E7FFFH

66 32K-WORD 1D8000H - 1DFFFFH

65 32K-WORD 1D0000H - 1D7FFFH

64 32K-WORD 1C8000H - 1CFFFFH

63 32K-WORD 1C0000H - 1C7FFFH

62 32K-WORD 1B8000H - 1BFFFFH

61 32K-WORD 1B0000H - 1B7FFFH

60 32K-WORD 1A8000H - 1AFFFFH

59 32K-WORD 1A0000H - 1A7FFFH

58 32K-WORD 198000H - 19FFFFH

57 32K-WORD 190000H - 197FFFH

56 32K-WORD 188000H - 18FFFFH

PLANE3 (UNIFORM PLANE)

55 32K-WORD 180000H - 187FFFH

54 32K-WORD 178000H - 17FFFFH

53 32K-WORD 170000H - 177FFFH

52 32K-WORD 168000H - 16FFFFH

51 32K-WORD 160000H - 167FFFH

50 32K-WORD 158000H - 15FFFFH

49 32K-WORD 150000H - 157FFFH

48 32K-WORD 148000H - 14FFFFH

47 32K-WORD 140000H - 147FFFH

46 32K-WORD 138000H - 13FFFFH

45 32K-WORD 130000H - 137FFFH

44 32K-WORD 128000H - 12FFFFH

43 32K-WORD 120000H - 127FFFH

42 32K-WORD 118000H - 11FFFFH

41 32K-WORD 110000H - 117FFFH

40 32K-WORD 108000H - 10FFFFH

PLANE2 (UNIFORM PLANE)

39 32K-WORD 100000H - 107FFFH

BLOCK NUMBER ADDRESS RANGE

38 32K-WORD 0F8000H - 0FFFFFH

37 32K-WORD 0F0000H - 0F7FFFH

36 32K-WORD 0E8000H - 0EFFFFH

35 32K-WORD 0E0000H - 0E7FFFH

34 32K-WORD 0D8000H - 0DFFFFH

33 32K-WORD 0D0000H - 0D7FFFH

32 32K-WORD 0C8000H - 0CFFFFH

31 32K-WORD 0C0000H - 0C7FFFH

30 32K-WORD 0B8000H - 0BFFFFH

29 32K-WORD 0B0000H - 0B7FFFH

28 32K-WORD 0A8000H - 0AFFFFH

27 32K-WORD 0A0000H - 0A7FFFH

26 32K-WORD 098000H - 09FFFFH

25 32K-WORD 090000H - 097FFFH

24 32K-WORD 088000H - 08FFFFH

PLANE1 (UNIFORM PLANE)

23 32K-WORD 080000H - 087FFFH

22 32K-WORD 078000H - 07FFFFH

21 32K-WORD 070000H - 077FFFH

20 32K-WORD 068000H - 06FFFFH

19 32K-WORD 060000H - 067FFFH

18 32K-WORD 058000H - 05FFFFH

17 32K-WORD 050000H - 057FFFH

16 32K-WORD 048000H - 04FFFFH

15 32K-WORD 040000H - 047FFFH

14 32K-WORD 038000H - 03FFFFH

13 32K-WORD 030000H - 037FFFH

12 32K-WORD 028000H - 02FFFFH

11 32K-WORD 020000H - 027FFFH

10 32K-WORD 018000H - 01FFFFH

9 32K-WORD 010000H - 017FFFH

8 32K-WORD 008000H - 00FFFFH

7 4K-WORD 007000H - 007FFFH

6 4K-WORD 006000H - 006FFFH

5 4K-WORD 005000H - 005FFFH

4 4K-WORD 004000H - 004FFFH

3 4K-WORD 003000H - 003FFFH

2 4K-WORD 002000H - 002FFFH

1 4K-WORD 001000H - 001FFFH

PLANE0 (PARAMETER PLANE)

0 4K-WORD 000000H - 000FFFH

Figure 2.2 Bottom Parameter Memory Map

W28F321BB/TB

Publication Release Date: February 17, 2003

- 7 - Revision A2

Table 3. Identifier Codes and OTP Address for Read Operation

CODE

ADDRESS

[A15 − A0] (1)

DATA

[DQ15 − DQ0] NOTES

Manufacture Code Manufacture Code 0000H 00B0H

Top Parameter 00B4H 2

Device Code Bottom Parameter 0001H 00B5H 2

Block is Unlocked DQ0 = 0 3

Block is Locked DQ0 = 1 3

Block is not Locked-Down DQ1 = 0 3

Block Lock Configuration Code

Block is Locked-Down

Block Address

DQ1 = 1 3

Device Configuration Code Partition Configuration register 0006H PCRC 4

OTP Lock 0080H OTP-LK 5

OTP OTP 0081-0088H OTP 6

Notes:

1. The address A20 − A16 are shown in below table for reading the manufacturer, device, lock configuration, device

configuration code and OTP data.

2. Bottom parameter device has its parameter blocks in the plane0 (The lowest address).

Top parameter device has its parameter blocks in the plane3 (The highest address).

3. DQ15 − DQ2 are reserved for future implementation.

4. PCRC = Partition Configuration Register Code.

5. OTP − LK = OTP Block Lock configuration.

6. OTP = OTP Block data.

Table 4. Identifier Codes and OTP Address for Read Operation on Partition Configuration(1)

PARTITION CONFIGURATION

PCR.10 PCR.9 PCR.8

ADDRESS (32M-BIT DEVICE)

[A20 − A16]

0 0 0 00H

0 0 1 00H or 08H

0 1 0 00H or 10H

1 0 0 00H or 18H

0 1 1 00H or 08H or 10H

1 1 0 00H or 10H or 18H

1 0 1 00H or 08H or 18H

1 1 1 00H or 08H or 10H or 18H

Notes:

1. The address to read the identifier codes or OTP data is dependent on the partition which is selected when writing the Read

Identifier Codes/OTP command (90H).

2. Refer to Table 12 for the partition configuration register.

W28F321BB/TB

- 8 -

Figure 3. OTP Block Address Map for OTP Program (The area outside 80H − 88H cannot be used.)

Table 5. Bus Operations (1, 2)

MODE NOTE #RESET #CE #OE #WE ADDRESS VPP DQ0 − 15

Read Array 6 VIH VIL VIL VIH X X DOUT

Output Disable VIH VIL VIH VIH X X High Z

Standby VIH V

IH X X X X High Z

Reset 3 VIL X X X X X High Z

Read Identifier Codes/OTP 6 VIH V

IL VIL VIH See

Table 3, 4 X See

Table 3, 4

Read Query 6, 7 VIH V

IL VIL VIH See

Appendix X See

Appendix

Write 4, 5, 6 VIH V

IL V

IH V

IL X X DIN

Notes:

1. Refer to DC Characteristics. When VPP ≤ VPPLK, memory contents can be read, but cannot be altered.

2. X can be VIL or VIH for control pins and addresses, and VPPLK or VPPH1/2 for VPP. See DC Characteristics for VPPLK and VPPH1/2

voltages.

3. #RESET at VSS ±0.2V ensures the lowest power consumption.

4. Command writes involving block erase, (page buffer) program or OTP program are reliably executed when VPP = VPPH1/2 and

VDD = 2.7V to 3.6V.

Command writes involving full chip erase are reliably executed when VPP = VPPH1 and VDD = 2.7V to 3.6V.

5. Refer to Table 6 for valid DIN during a write operation.

6. Never hold #OE low and #WE low at the same timing.

7. Refer to Appendix for more information about query code.

Reserved for Future Implementation

(

−

)

Factory Programmed Area

Customer Programmable Area

Customer programmable Area Lock Bit (DQ1)

Factory programmed Area Lock Bit (DQ0)

[A20-A0]

000088H

000085H

000084H

000081H

000080H

W28F321BB/TB

Publication Release Date: February 17, 2003

- 9 - Revision A2

Table 6. Command Definitions(11)

FIRST BUS CYCLE SECOND BUS CYCLE

COMMAND

BUS

CYCLES

REQ’D.

NOTE Oper(1) Addr(2) Data(3) Oper(1) Addr(2) Data(3)

Read Array 1 2 Write PA FFH

Read Identifier Codes/OTP ≥ 2 2, 3, 4 Write PA 90H Read IA or OA ID or OD

Read Query ≥ 2 2, 3, 4 Write PA 98H Read QA QD

Read Status Register 2 2, 3 Write PA 70H Read PA SRD

Clear Status Register 1 2 Write PA 50H

Block Erase 2 2, 3, 5 Write BA 20H Write BA D0H

Full Chip Erase 2 2, 5, 9 Write X 30H Write X D0H

Program 2 2, 3, 5, 6 Write WA 40H or

10H Write WA WD

Page Buffer Program ≥ 4 2, 3, 5, 7 Write WA E8H Write WA N-1

Block Erase and (Page Buffer)

Program Suspend 1 2, 8, 9 Write PA B0H

Block Erase and (Page Buffer)

Program Resume 1 2, 8, 9 Write PA D0H

Set Block Lock Bit 2 2 Write BA 60H Write BA 01H

Clear Block Lock Bit 2 2, 10 Write BA 60H Write BA D0H

Set Block Lock-down Bit 2 2 Write BA 60H Write BA 2FH

OTP Program 2 2, 3, 9 Write OA C0H Write OA OD

Set Partition configuration

Notes:

1. Bus operations are defined in Table 5.

2. The address which is written at the first bus cycle should be the same as the address which is written at the second bus cycle.

X = Any valid address within the device.

PA = Address within the selected partition.

IA = Identifier codes address (See Table 3 and Table 4).

QA = Query codes address. Refer to Appendix for details.

BA = Address within the block being erased, set/cleared block lock bit or set block lock-down bit.

WA = Address of memory location for the Program command or the first address for the Page Buffer Program command.

OA = Address of OTP block to be read or programmed (See Figure 3).

PCRC = Partition configuration register code presented on the address A0 − A15.

3. ID = Data read from identifier codes. (See Table 3 and Table 4).

QD = Data read from query database. Refer to Appendix for details.

SRD = Data read from status register. See Table 10 and Table 11 for a description of the status register bits.

WD = Data to be programmed at location WA. Data is latched on the rising edge of #WE or #CE (whichever goes high first).

OD = Data to be programmed at location OA. Data is latched on the rising edge of #WE or #CE (whichever goes high first).

N-1 = N is the number of the words to be loaded into a page buffer.

4. Following the Read Identifier Codes/OTP command, read operations access manufacturer code, device code, block lock

configuration code, partition configuration register code and the data within OTP block (See Table 3 and Table 4). The Read

Query command is available for reading CFI (Common Flash Interface) information.

5. Block erase, full chip erase or (page buffer) program cannot be executed when the selected block is locked. Unlocked block

can be erased or programmed when #RESET is VIH.

6. Either 40H or 10H are recognized by the CUI (Command User Interface) as the program setup.

7. Following the third bus cycle, inputs the program sequential address and write data of "N" times. Finally, input the any valid

address within the target partition to be programmed and the confirm command (D0H). Refer to Appendix for details.

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8. If the program operation in one partition is suspended and the erase operation in other partition is also suspended, the

suspended program operation should be resumed first, and then the suspended erase operation should be resumed next.

9. Full chip erase and OTP program operations can not be suspended. The OTP Program command can not be accepted while

the block erase operation is being suspended.

10. Following the Clear Block Lock Bit command, block which is not locked-down is unlocked when #WP is VIL. When #WP is

VIH, lock-down bit is disabled and the selected block is unlocked regardless of lock-down configuration.

11. Commands other than those shown above are reserved by Winbond for future device implementations and should not be

used.

Table 7. Functions of Block Lock(5) and Block Lock-Down

CURRENT STATE

State #WP DQ1(1) DQ0(1) State Name Erase/Program Allowed(2)

[000] 0 0 0 Unlocked Yes

[001](3) 0 0 1 Locked No

[011] 0 1 1 Locked-down No

[100] 1 0 0 Unlocked Yes

[101](3) 1 0 1 Locked No

[110](4) 1 1 0 Lock-down Disable Yes

[111] 1 1 1 Lock-down Disable No

Notes:

1. DQ0 = 1: a block is locked; DQ0 = 0: a block is unlocked.

DQ1 = 1: a block is locked-down; DQ1 = 0: a block is not locked-down.

2. Erase and program are general terms, respectively, to express: block erase, full chip erase and (page buffer) program

operations.

3. At power-up or device reset, all blocks default to locked state and are not locked-down, that is, [001] (#WP = 0) or [101] (#WP

= 1), regardless of the states before power-off or reset operation.

4. When #WP is driven to VIL in [110] state, the state changes to [011] and the blocks are automatically locked.

5. OTP (One Time Program) block has the lock function, which is different from those described above.

Table 8. Block Locking State Transitions upon Command Write(4)

CURRENT STATE RESULT AFTER LOCK COMMAND WRITTEN (Next State)

State #WP DQ1 DQ0 Set Lock(1) Clear Lock(1) Set Lock-down(1)

[000] 0 0 0 [001] No Change [011](2)

[001] 0 0 1 No Change(3) [000] [011]

[011] 0 1 1 No Change No Change No Change

[100] 1 0 0 [101] No Change [111](2)

[101] 1 0 1 No Change [100] [111]

[110] 1 1 0 [111] No Change [111](2)

[111] 1 1 1 No Change [110] No Change

Notes:

1. "Set Lock" means Set Block Lock Bit command, "Clear Lock" means Clear Block Lock Bit command and "Set Lock-down"

means Set Block Lock-Down Bit command.

2. When the Set Block Lock-Down Bit command is written to the unlocked block (DQ0 = 0), the corresponding block is locked-

down and automatically locked at the same time.

3. "No Change" means that the state remains unchanged after the command written.

4. In this state transitions table, assumes that #WP is not changed and fixed VIL or VIH.

W28F321BB/TB

Publication Release Date: February 17, 2003

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Table 9. Block Locking State Transitions upon #WP Transition(4)

Current State Result after #WP Transition (Next State)

Previous State State #WP DQ1 DQ0

#WP = 0→1(1) #WP = 1→0(1)

- [000] 0 0 0 [100] -

- [001] 0 0 1 [101] -

[110](2) [110] -

Other than [110](2) [011] 0 1 1 [111] -

- [100] 1 0 0 - [000]

- [101] 1 0 1 - [001]

- [110] 1 1 0 - [011](3)

- [111] 1 1 1 - [011]

Notes:

1. "#WP = 0→1" means that #WP is driven to VIH and "#WP = 1→0" means that #WP is driven to VIL.

2. State transition from the current state [011] to the next state depends on the previous state.

3. When #WP is driven to VIL in [110] state, the state changes to [011] and the blocks are automatically locked.

4. In this state transitions table, assumes that lock configuration commands are not written in previous, current and next state.

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Table 10. Status Register Definition

R R R R R R R R

15 14 13 12 11 10 9 8

WSMS BESS BEFCES PBPOPS VPPS PBPSS DPS R

7 6 5 4 3 2 1 0

SR.15 - SR.8 = RESERVED FOR FUTURE

ENHANCEMENTS (R)

SR.7 = WRITE STATE MACHINE STATUS (WSMS)

1 = Ready

0 = Busy

SR.6 = BLOCK ERASE SUSPEND STATUS (BESS)

1 = Block Erase Suspended

0 = Block Erase in Progress/Completed

SR.5 = BLOCK ERASE AND FULL CHIP ERASE STATUS

(BEFCES)

1 = Error in Block Erase or Full Chip Erase

0 = Successful Block Erase or Full Chip Erase

SR.4 = (PAGE BUFFER) PROGRAM AND OTP PROGRAM

STATUS (PBPOPS)

1 = Error in (Page Buffer) Program or OTP Program

0 = Successful (Page Buffer) Program or OTP Program

SR.3 = VPP STATUS (VPPS)

1 = VPP LOW Detect, Operation Abort

0 = VPP OK

SR.2 = (PAGE BUFFER) PROGRAM SUSPEND STATUS

(PBPSS)

1 = (Page Buffer) Program Suspended

0 = (Page Buffer) Program in Progress/Completed

SR.1 = DEVICE PROTECT STATUS (DPS)

1 = Erase or Program Attempted on a Locked Block,

Operation Abort

0 = Unlocked

SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R)

NOTES:

Status Register indicates the status of the partition, not WSM

(Write State Machine). Even if the SR.7 is "1", the WSM may

be occupied by the other partition when the device is set to

2, 3 or 4 partitions configuration.

Check SR.7 to determine block erase, full chip erase, (page

buffer) program or OTP program completion. SR.6 − SR.1

are invalid while SR.7 = "0".

If both SR.5 and SR.4 are "1"s after a block erase, full chip

erase, (page buffer) program, set/clear block lock bit, set

block lock-down bit, set partition configuration register

attempt, an improper command sequence was entered.

SR.3 does not provide a continuous indication of VPP level.

The WSM interrogates and indicates the VPP level only after

Block Erase, Full Chip Erase, (Page Buffer) Program or OTP

Program command sequences. SR.3 is not guaranteed to

report accurate feedback when VPP ≠ VPPH1, VPPH2 or VPPLK.

SR.1 does not provide a continuous indication of block lock

bit. The WSM interrogates the block lock bit only after Block

Erase, Full Chip Erase, (Page Buffer) Program or OTP

Program command sequences. It informs the system,

depending on the attempted operation, if the block lock bit is

set. Reading the block lock configuration codes after writing

the Read Identifier Codes/OTP command indicates block

lock bit status.

SR.15 - SR.8 and SR.0 are reserved for future use and

should be masked out when polling the status register.

W28F321BB/TB

Publication Release Date: February 17, 2003

- 13 - Revision A2

Table 11. Extended Status Register Definition

R R R R R R R R

15 14 13 12 11 10 9 8

SMS R R R R R R R

7 6 5 4 3 2 1 0

XSR.15-8 = RESERVED FOR FUTURE ENHANCEMENTS (R)

XSR.7 = STATE MACHINE STATUS (SMS)

1 = Page Buffer Program available

0 = Page Buffer Program not available

XSR.6-0 = RESERVED FOR FUTURE ENHANCEMENTS (R)

NOTES:

After issue a Page Buffer Program command (E8H),

XSR.7="1" indicates that the entered command is

accepted. XSR.7 is "0", the command is not accepted and

a next Page Buffer Program command (E8H) should be

issued again to check if page buffer is available or not.

XSR.15-8 and XSR.6-0 are reserved for future use and

should be masked out when polling the extended status

W28F321BB/TB

- 14 -

Table 12. Partition Configuration Register Definition

R R R R R PC2 PC1 PC0

15 14 13 12 11 10 9 8

R R R R R R R R

7 6 5 4 3 2 1 0

PCR.150−11 = RESERVED FOR FUTURE ENHANCEMENTS (R)

PCR.10-8 = PARTITION CONFIGURATION (PC2 − 0)

000 = No partitioning. Dual Work is not allowed.

001 = Plane1 − 3 are merged into one partition.

(default in a bottom parameter device)

010 = Plane 0-1 and Plane2 − 3 are merged into one

partition respectively.

100 = Plane 0 − 2 are merged into one partition.

(default in a top parameter device)

011 = Plane 2 − 3 are merged into one partition.

There are three partitions in this configuration.

Dual work operation is available between any

two partitions.

110 = Plane 0 − 1 are merged into one partition.

There are three partitions in this configuration.

Dual work operation is available between any

two partitions.

101 = Plane 1 − 2 are merged into one partition.

There are three partitions in this configuration.

Dual work operation is available between any

two partitions.

111 = There are four partitions in this configuration.

Each plane corresponds to each partition

respectively.

Dual work operation is available between any two

partitions.

PCR.7 − 0 = RESERVED FOR FUTURE

ENHANCEMENTS (R)

NOTES:

After power-up or device reset, PCR10-8 (PC2 − 0) is set

to "001" in a bottom parameter device and "100" in a top

parameter device.

See Figure 4 for the detail on partition configuration.

PCR.15 − 11 and PCR.7 − 0 are reserved for future use

and should be masked out when polling the partition

configuration register.

PC2 PC1 PC0 PARTITIONING FOR DUAL WORK PC2 PC1 PC0 PARTITIONING FOR DUAL WORK

PARTITION0 PARTITION2 PARTITION1 PARTITION0

0 0 0

0 1 1

PARTITION1 PARTITION0 PARTITION2 PARTITION1 PARTITION0

0 0 1

1 1 0

PARTITION1 PARTITION0 PARTITION2 PARTITION1 PARTITION0

0 1 0

1 0 1

PARTITION1 PARTITION0 PARTITION3 PARTITION2 PARTITION1 PARTITION0

1 0 0

1 1 1

Figure 4. Partition Configuration

PLANE3

PLANE2

PLANE1

PLANE0

PLANE3

PLANE2

PLANE1

PLANE0

PLANE3

PLANE2

PLANE1

PLANE0

PLANE3

PLANE2

PLANE1

PLANE0

PLANE3

PLANE2

PLANE1

PLANE0

PLANE3

PLANE2

PLANE1

PLANE0

PLANE3

PLANE2

PLANE1

PLANE0

PLANE3

PLANE2

PLANE1

PLANE0

W28F321BB/TB

Publication Release Date: February 17, 2003

- 15 - Revision A2

4. ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings*

Operating Temperature

During Read, Erase and Program ..................................................................................... -40°C to +85°C(1)

Storage Temperature

During under Bias ................................................................................................................ -40°C to +85°C

During non Bias .............................. .................................................................................. .. -65°C to +125°C

Voltage On Any Pin

(except VDD and VPP) ......... .......................................................................................... -0.5V to VDD +0.5V(2)

VDD and VDDQ Supply Voltage................................................................................................. -0.2V to +3.9V(2)

VPP Supply Voltage..................................................................................................... .... -0.2V to +12.6V(2,3,4)

Output Short Circuit Current............. .............................................................................. ...................100 mA(5)

*WARNING: Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress

ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating

Conditions" may affect device reliability.

Notes:

1. Operating temperature is for extended temperature product defined by this specification.

2. All specified voltages are with respect to VSS. Minimum DC voltage is -0.5V on input/output pins and -0.2V on VDD and VPP

pins. During transitions, this level may undershoot to -2.0V for periods <20 nS. Maximum DC voltage on input/output pins and

VDD is VDD +0.5V, which, during transitions, may overshoot to VDD +2.0V for periods <20 nS.

3. Maximum DC voltage on VPP may overshoot to +13.0V for periods <20 nS.

4. VPP erase/program voltage is normally 2.7V to 3.6V. Applying 11.7V to 12.3V to VPP during erase/program can be done for a

maximum of 1,000 cycles on the main blocks and 1,000 cycles on the parameter blocks. VPP may be connected to 11.7V to

12.3V for a total of 80 hours maximum.

5. Output shorted for no more than one second. No more than one output shorted at a time.

Operating Conditions

PARAMETER SYM. MIN. TYP. MAX. UNIT NOTE

Operating Temperature TA -40 +25 +85 °C

VDD Supply Voltage VDD 2.7 3.0 3.6 V 1

I/O Supply Voltage VDDQ 2.7 3.0 3.6 V 1

VPP Voltage when Used as a Logic Control VPPH1 1.65 3.0 3.6 V 1

VPP Supply Voltage VPPH2 11.7 12 12.3 V 1, 2

Main Block Erase Cycling: VPP = 3.0V 100,000 Cycles

Parameter Block Erase Cycling: VPP = 3.0V 100,000 Cycles

Main Block Erase Cycling: VPP = 12V, 80 hrs. 1,000 Cycles

Parameter Block Erase Cycling: VPP = 12V, 80 hrs. 1,000 Cycles

Maximum VPP hours at 12V 80 Hours

Notes:

1. See DC Characteristics tables for voltage range-specific specification.

2. Applying VPP = 11.7V to 12.3V during an erase or program can be done for a maximum of 1,000 cycles on the main blocks

and 1,000 cycles on the parameter blocks. A permanent connection to VPP =11.7V to 12.3V is not allowed and can cause

damage to the device.

W28F321BB/TB

- 16 -

Capacitance(1)

TA = +25° C, f = 1 MHz

PARAMETER SYM. TYP. MAX. UNIT CONDITION

Input Capacitance CIN 6 8 pF VIN = 0.0V

Output Capacitance COUT 10 12 pF VOUT = 0.0V

Note: Sampled, not 100% tested.

AC Input/Output Test Conditions

VDDQ

0.0

INPUT VDDQ/2 OUTPUT

TEST POINTS VDDQ/2

AC test inputs are driven at VDD(min) for a Logic "1" and 0.0V for a Logic "0".

Input timing begins, and output timing ends at VDD/2. Input rise and fall times (10% to 90%) < 5 nS.

Worst case speed conditions are when VDD =VDD(min).

Figure 5. Transient Input/Output Reference Waveform for VDD =2.7V to 3.6V

VDDQ(min)/2

Includes Jig Capacitance

1N914

DEVICE

UNDER

TEST

OUT

=3.3K ohm

Figure 6. Transient Equivalent Testing Load Circuit

Table 13. Configuration Capacitance Loading Value

TEST CONFIGURATION CL(PF)

VDD = 2.7V to 3.6V 50

W28F321BB/TB

Publication Release Date: February 17, 2003

- 17 - Revision A2

DC Characteristics

VDD = 2.7V to 3.6V

PARAMETER SYM. TEST CONDITIONS

Min. Typ. Max.

UNIT

Input Load Current

(note 1) ILI -1.0 +1.0

µA

Output Leakage Current

(note1) ILO

VDD = VDD Max., VDDQ = VDDQ Max.,

VIN/VOUT = VDDQ or VSS -1.0 +1.0

µA

VDD Standby Current

(note 1) ICCS VDD = VDD Max. #CE = #RESET =

VDDQ ±0.2V, #WP = VDDQ or VSS 4 20

µA

VDD Automatic Power Saving

Current (note 1, 4) ICCAS VDD = VDD Max. #CE = VSS ±0.2V,

#WP = VDDQ or VSS 4 20

µA

VDD Reset Power-Down Current

(note 1) ICCD #RESET = VSS ±0.2V 4 20

µA

Average VDD Read

Current

Normal Mode (note1, 7)

15 25 mA

Average VDD Read

Current

Page Mode (note1, 7)

8 Word

Read

ICCR VDD = VDD Max.,

#CE = VIL, #OE = VIH, f = 5 MHz

5 10 mA

VPP = VPPH1 20 60 mA

VDD (Page Buffer) Program

Current (note 1, 5, 7)

ICCW VPP = VPPH2 10 20 mA

VPP = VPPH1 10 30 mA

VDD Block Erase, Full Chip Erase

Current (note 1, 5, 7) ICCE VPP = VPPH2 10 30 mA

VDD (Page Buffer) Program or

Block Erase Suspend Current

(note 1, 2, 7)

ICCWS

ICCES #CE = VIH 10 200

µA

VPP Standby or Read Current

(note 1, 6, 7)

IPPS

IPPR VPP ≤ VDD 2 5

µA

VPP = VPPH1 2 5

µA

VPP (Page Buffer) Program

Current (note 1, 5, 6, 7) IPPW

VPP = VPPH2 10 30 mA

VPP = VPPH1 2 5

µA

VPP Block Erase, Full Chip Erase

Current (note 1, 5, 6, 7) IPPE

VPP = VPPH2 5 15 mA

VPP = VPPH1 2 5

µA

VPP (Page Buffer) Program

Suspend Current (note 1, 6, 7) IPPWS VPP = VPPH2 10 200

µA

VPP = VPPH1 2 5

µA

VPP Block Erase Suspend Current

(note 1, 6, 7) IPPES

VPP = VPPH2 10 200

µA

W28F321BB/TB

- 18 -

DC Characteristics (continued)

VDD = 2.7V − 3.6V

PARAMETER SYM.

TEST

CONDITIONS Min. Typ. Max.

UNIT

Input Low Voltage (note 5) VIL -0.4 0.4 V

Input High Voltage (note 5) VIH

VDDQ

-0.4 VDDQ

+0.4 V

Output Low Voltage (note 5) VOL VDD = VDD Min., VDDQ =

VDDQ Min., IOL = 100 µA 0.2 V

Output High Voltage (note 5) VOH VDD = VDD Min., VDDQ =

VDDQ Min., IOH = -100 µA

VDDQ

-0.2 V

VPP Lockout during Normal Operations

(note 3, 5, 6) VPPLK 0.4 V

VPP during Block Erase, Full Chip Erase,

(Page Buffer) Program or OTP Program

Operations (note 6)

VPPH1 1.65 3.0 3.6 V

VPP during Block Erase, (Page Buffer)

Program or OTP Program Operations

(note 6)

VPPH2 11.7 12 12.3 V

VDD Lockout Voltage VLKO 1.5 V

Notes:

1. All currents are in RMS unless otherwise noted. Typical values are the reference values at VDD = 3.0V and TA = +25° C unless

VDD is specified.

2. ICCWS and ICCES are specified with the device de-selected. If read or (page buffer) program while in block erase suspend

mode, the device's current draw is the sum of ICCWS or ICCES and ICCR or ICCW, respectively.

3. Block erases, full chip erase, (page buffer) program and OTP program are inhibited when VPP ≤ VPPLK, and not guaranteed in

the range between VPPLK (max.) and VPPH1 (min.), between VPPH1 (max.) and VPPH2 (min.) and above VPPH2 (max.).

4. The Automatic Power Savings (APS) feature automatically places the device in power save mode after read cycle completion.

Standard address access timings (tAVQV) provide new data when address are changed.

5. Sampled, not 100% tested.

6. VPP is not used for power supply pin. With VPP ≤ VPPLK, block erase, full chip erase, (page buffer) program and OTP program

cannot be executed and should not be attempted.

Applying 12V±0.3V to V VPP provides fast erasing or fast programming mode. In this mode, VPP is power supply pin and

supplies the memory cell current for block erasing and (page buffer) programming. Use similar power supply trace widths and

layout considerations given to the VDD power bus.

Applying 12V±0.3V to VPP during erase/program can only be done for a maximum of 1,000 cycles on each block. VPP may be

connected to 12V±0.3V for a total of 80 hours maximum.

7. The operating current in dual work is the sum of the operating current (read, erase, program) in each plane.

W28F321BB/TB

Publication Release Date: February 17, 2003

- 19 - Revision A2

AC Characteristics - Read-only Operations(1)

VDD = 2.7V to 3.6V, TA = -40°C to +85°C

PARAMETER SYM. MIN. MAX. UNIT

Read Cycle Time tAVAV 70 nS

Address to Output Delay tAVQV 70 nS

#CE to Output Delay (note 3) tELQV 70 nS

Page Address Access Time TAPA 25 nS

#OE to Output Delay (note 3) tGLQV 20 nS

#RESET High to Output Delay TPHQV 150 nS

#CE or #OE to Output in High Z, whichever Occurs First (note 2) tEHQZ, tGHQZ, 20 nS

#CE to Output in Low Z (note 2) TELQX 0 nS

#OE to Output in Low Z (note 2) tGLQX 0 nS

Output Hold from first Occurring Address, #CE or #OE Change

(note 2) tOH 0 nS

Notes:

1. See AC Input/Output Reference Waveform for timing measurements and maximum allowable input slew rate.

2. Sampled, not 100% tested.

3. #OE may be delayed up to tELQV to tGLQV after the falling edge of #CE without impact to tELQV.

A20-0(A)

#OE(G)

#WE(W)

#CE(E)

Valid Address

DQ15-0 (D/Q)

#RESET(P)

HIGH Z

tGLQV

tELQX

tGLQX

tOH

Valid Output

tAVQV

tELQV

tPHQV

tGHQZ

tEHQZ

Figure 7. AC Waveform for Single Asynchronous Read Operations from Status Register,

Identifier codes, OTP Block or Query Code

W28F321BB/TB

- 20 -

#OE(G)

#WE(W)

#CE(E)

VIH

VIL

VIH

VIL

DQ15-0 (D/Q)

VOL

#RESET(P)

HIGH Z

tGLQV

tELQX

tGLQX

tOH

tAVQV

tELQV

tPHQV

A2-0(A)

VIH

VIL

Valid Address

tGHQZ

tEHQZ

A20-3(A)

VIH

VIL

Valid Address

Valid

Address

Valid

Address

Valid

Address

Valid

Address

Valid

Address

Valid

Address

Valid

Address

tAPA

Figure 8. AC Waveform for Asynchronous Page Mode Read Operations from Main Blocks or Parameter Blocks

W28F321BB/TB

Publication Release Date: February 17, 2003

- 21 - Revision A2

AC Characteristics - Write Operations(1,2)

VDD = 2.7V to 3.6V, TA = -40°C to +85°C

PARAMETER SYM. MIN. MAX. UNIT

Write Cycle Time tAVAV 70 nS

#RESET High Recovery to #WE(#CE) Going Low (note 3) tPHWL(tPHEL) 150 nS

#CE(#WE) Setup to #WE(#CE) Going Low (note 4) tELWL(tWLEL) 0 nS

#WE(#CE) Pulse Width (note 4) tWLWH(tELEH) 60 nS

Data Setup to #WE(#CE) Going High (note 8) tDVWH(tDVEH) 40 nS

Address Setup to #WE(#CE) Going High (note 8) tAVWH(tAVEH) 50 nS

#CE(#WE) Hold from #WE(#CE) High tWHEH(tEHWH) 0 nS

Data Hold from #WE(#CE) High tWHDX(tEHDX) 0 nS

Address Hold from #WE(#CE) High tWHAX(tEHAX) 0 nS

#WE(#CE) Pulse Width High (note 5) tWHWL(tEHEL) 30 nS

#WP High Setup to #WE(#CE) Going High (note 3) tSHWH(tSHEH) 0 nS

VPP Setup to #WE(#CE) Going High (note 3) tVVWH(tVVEH) 200 nS

Write Recovery before Read tWHGL(tEHGL) 30 nS

#WP High Hold from Valid SRD (note 3, 6) tQVSL 0 nS

VPP Hold from Valid SRD (note 3, 6) tQVVL 0 nS

#WE(#CE) High to SR.7 Going "0" (note 3, 7) tWHR0(tEHR0) tAVQV+40 nS

Notes:

1. The timing characteristics for reading the status register during block erase, full chip erase, (page buffer) program and OTP

program operations are the same as during read-only operations. Refer to AC Characteristics for read-only operations.

2. A write operation can be initiated and terminated with either #CE or #WE.

3. Sampled, not 100% tested.

4. Write pulse width (tWP) is defined from the falling edge of #CE or #WE (whichever goes low last) to the rising edge of #CE or

#WE (whichever goes high first). Hence, tWP = tWLWH = tELEH = tWLEH = tELWH.

5. Write pulse width high (tWPH) is defined from the rising edge of #CE or #WE (whichever goes high first) to the falling edge of

#CE or #WE (whichever goes low last). Hence, tWPH = tWHWL = tEHEL = tWHEL = tEHWL.

6. VPP should be held at VPP = VPPH1/2 until determination of block erase, (page buffer) program or OTP program success

(SR.1/3/4/5 = 0) and held at VPP = VPPH1 until determination of full chip erase success (SR.1/3/5 = 0).

7. tWHR0 (tEHR0) after the Read Query or Read Identifier Codes/OTP command=tAVQV+100ns.

8. Refer to Table 6 for valid address and data for block erase, full chip erase, (page buffer) program, OTP program or lock bit

configuration.

W28F321BB/TB

- 22 -

A21-0(A)

VIH

V IL

tAVAV

#WE(W)

V IH

VIL

DQ15-0(D/Q)

VIH

DIN Valid

SRD

VIL

("0")

#WP(S) IH

SR.7(R)

("1")

#RESET(P) IH

PPH1,2

PPLK

(V)

VPP

Note 1 Note 2 Note 3 Note 4 Note 5

#CE(E)

VIH

V IL

#OE(G)

V IH

VIL

Note 5,6

DIN

Note 5,6

VVWH

tVVEH

(t ) QVVL

SHWH

tSHEH

(t ) QVSL

WHR0

tEHR0

(t )

WHQV1,2,3

tEHQV1,2,3

(t )

DVWH

tDVEH

(t )

WHDX

tEHDX

(t )

WLWH

tELEH

(t )

PHWL

tPHEL (t )

WHWL

tEHEL

(t )

ELWL

tWLEL (t )

WHEH

tEHWH (t )

WHGL

tEHGL

(t )

WHAX

tEHAX

(t )

AVWH

tAVEH

Valid Address Valid Address Valid Address

Figure 9. AC Waveform for Write Operations

Notes:

1. VDD power-up and standby.

2. Write each first cycle command.

3. Write each second cycle command or valid address and data.

4. Automated erase or program delay.

5. Read status register data.

6. For read operation, #OE and #CE must be driven active, and #WE de-asserted.

W28F321BB/TB

Publication Release Date: February 17, 2003

- 23 - Revision A2

Reset Operations

#RESET(P)

High Z

PLRH

(C)#RESET Rising Timing

2VPH

#RESET(P)

PLPH

(A)Reset During Read Array Mode

DQ15-0(D/Q) OH

PHQV

Valid Output

#RESET(P)

PLPH

Abort

Complete

SR.7="1"

PHQV

(B)Reset During Erase or Program Mode

DQ15-0(D/Q) OH

High Z Valid Output

DQ15-0(D/Q) OH

High Z Valid Output

PHQV

DD(min)

Vss VHQV

Figure 10. AC Waveform for Reset Operation

Reset AC Specifications

VDD = 2.7V to 3.6V, TA = -40°C to +85°C

PARAMETER SYM. MIN. MAX. UNIT

#RESET Low to Reset during Read

(#RESET should be low during power-up.) (note 1, 2, 3) tPLPH 100 nS

#RESET Low to Reset during Erase or Program (note 1, 3, 4) tPLRH 22

µS

VDD 2.7V to #RESET High (note 1, 3, 5) t2VPH 100 nS

VDD 2.7V to Output Delay (note 3) tVHQV 1 mS

Notes:

1. A reset time, tPHQV, is required from the later of SR.7 going "1"(High Z) or #RESET going high until outputs are valid. Refer to

AC Characteristics - Read-Only Operations for tPHQV.

2. tPLPH is <100ns the device may still reset but this is not guaranteed.

3. Sampled, not 100% tested.

W28F321BB/TB

- 24 -

4. If #RESET asserted while a block erase, full chip erase, (page buffer) program or OTP program operation is not executing,

the reset will complete within 100ns.

5. When the device power-up, holding #RESET low minimum 100ns is required after VDD has been in predefined range and also

has been in stable there.

Block Erase, Full Chip Erase, (Page Buffer) Program and OTP Program

Performance(3)

VDD = 2.7V to 3.6V, TA = -40°C to +85°C

VPP = VPPH1

(IN SYSTEM)

VPP = VPPH2

(IN MANUFACTURING)

PARAMETER SYM.

PAGE BUFFER

COMMAND IS

USED OR NOT

USED MIN. TYP.(1) MAX.(2) MIN. TYP.(1) MAX.(2)

UNIT

Not Used 0.05 0.3 0.04 0.12 S

4K-Word Parameter Block

Program Time (note 2) tWPB Used 0.03 0.12 0.02 0.06 S

Not Used 0.38 2.4 0.31 1.0 S

32K-Word Main Block

Program Time (note 2) tWMB Used 0.24 1.0 0.17 0.5 S

Not Used 11 200 9 185 µS

Word Program Time (note 2) tWHQV1/

tEHQV1

Used 7 100 5 90

µS

OTP Program Time (note 2) tWHOV1/

tEHOV1

Not Used 36 400 27 185 µS

4K-Word Parameter Block

Erase Time (note 2)

tWHQV2/

tEHQV2

- 0.3 4 0.2 4 S

32K-Word Main Block Erase

Time (note 2)

tWHQV3/

tEHQV3

- 0.6 5 0.5 5 S

Full Chip Erase Time (note 2) 40 350 S

(Page Buffer) Program

Suspend Latency Time to

Read (note 4)

tWHRH1/

tEHRH1

- 5 10 5 10

µS

Block Erase Suspend Latency

Time to Read (note 4)

tWHRH2/

tEHRH2

- 5 20 5 20

µS

Latency Time from Block

Erase Resume Command to

Block Erase Suspend

Command (note 5)

tERES - 500 500

µS

Notes:

1. Typical values measured at VDD = 3.0V, VPP = 3.0V or 12V, and TA=+25°C. Assumes corresponding lock bits are not set.

Subject to change based on device characterization.

2. Excludes external system-level overhead.

3. Sampled, but not 100% tested.

4. A latency time is required from writing suspend command (#WE or #CE going high) until SR.7 going "1".

5. If the interval time from a Block Erase Resume command to a subsequent Block Erase Suspend command is shorter than

tERES and its sequence is repeated, the block erase operation may not be finished.

W28F321BB/TB

Publication Release Date: February 17, 2003

- 25 - Revision A2

5. ADDITIONAL INFORMATION

Recommended Operating Conditions

At Device Power-Up

AC timing illustrated in Figure A-1 is recommended for the supply voltages and the control signals at

device power-up. If the timing in the figure is ignored, the device may not operate correctly.

VIH

VIL

VIH

V IL

#OE

Valid Address

VDD

Vss

(min)

tVR t2VPH tPHQV

#RESET (p)

Vpp (V)

Vss

V PPH1/2

DDRESS

VIH

VIL

(A)

tRor Ft

tRor F

tAVQV

#CE (E)

tFtELQV

tGLQV

#WE (W)

(G)

tFtR

#WP (S)

DATA (D/Q)

OL Valid Output

HIGH Z

*1 To prevent the unwanted writes, system designers should consider the design, which applies VPP to 0V during read

operations and VPPH1/2 during write or erase operations.

Figure A-1. AC Timing at Device Power-up

For the AC specifications tVR, tR, tF in the figure, refer to the next page. See the “ELECTRICAL SPECIFICATIONS“ described in

specifications for the supply voltage range, the operating temperature and the AC specifications not shown in the next page.

W28F321BB/TB

- 26 -

Rise and Fall Time

PARAMETER SYMBOL MIN. MAX. UNIT

VDD Rise Time (note 1) tVR 0.5 30000

µS/ V

Input Signal Rise Time (note1, 2) tR 1

µS/ V

Input Signal Fall Time (note1, 2) tF 1

µS/ V

Notes:

1. Sampled, not 100% tested.

2. This specification is applied for not only the device power-up but also the normal operations.

Glitch Noises

Do not input the glitch noises which are below VIH (Min.) or above VIL (Max.) on address, data, reset,

and control signals, as shown in Figure A-2 (b). The acceptable glitch noises are illustrated in Figure

A-2 (a).

Input Singal

VIH(Min.)

Input Singal

VIH(Min.)

IL (Max.)

Input Singal

VIL (Max.)

Input Singal

(

)

Acce

table Glitch Noises (b) NOT Acceptable Glitch Noises

Figure A-2. Waveform for Glitch Noises

See the "DC CHARACTERISTICS" described in specifications for VIH (Min.) and VIL (Max.).

W28F321BB/TB

Publication Release Date: February 17, 2003

- 27 - Revision A2

6. ORDERING INFORMATION

PART NO.

ACCESS

TIME

(nS)

OPERATING

TEMPERATURE

(°C)

BOOT BLOCK PACKAGE

W28F321BB70L 70 -40º C to 85º C Bottom Boot 48-Ball TFBGA

W28F321TB70L 70 -40º C to 85º C Top Boot 48-Ball TFBGA

Notes:

1. Winbond reserves the right to make changes to its products without prior notice.

2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in

applications where personal injury might occur as a consequence of product failure.

7. PACKAGE DIMENSION

48-Ball TFBGA (7mm x 7mm) (measurements in millimeters)

SYMBOL

MILLIMETER

1.05

MIN. NOM. MAX.

0.20 0.25 0.30

5.25 BASIC

3.75 BASIC

0.10 BASIC

0.37 0.40 0.43

0.75 BASIC

INCH

0.042

MIN. NOM. MAX.

0.008 0.010 0.012

6.80 7.00 7.20 0.272 0.280 0.288

0.210

0.150 BASIC

0.004 BASIC

0.015 0.016 0.017

0.030 BASIC

CONTROL DIMENSIONS ARE IN MILLIMETERS

SEATING PLANE

6.80 7.00 7.20 0.272 0.280 0.288

1 2 3 4 5 6

W28F321BB/TB

- 28 -

8. VERSION HISTORY

VERSION DATE PAGE DESCRIPTION

A1 Jan. 3, 2003 - Initial Issued

A2 Feb. 17, 2003 27 Modify the package dimension drawing

Headquarters

No. 4, Creation Rd. III,

Science-Based Industrial Park,

Hsinchu, Taiwan

TEL: 886-3-5770066

FAX: 886-3-5665577

http://www.winbond.com.tw/

Taipei Office

TEL: 886-2-8177-7168

FAX: 886-2-8751-3579

Winbond Electronics Corporation America

2727 North First Street, San Jose,

CA 95134, U.S.A.

TEL: 1-408-9436666

FAX: 1-408-5441798

Winbond Electronics (H.K.) Ltd.

No. 378 Kwun Tong Rd.,

Kowloon, Hong Kong

FAX: 852-27552064

Unit 9-15, 22F, Millennium City,

TEL: 852-27513100

Please note that all data and specifications are subject to change without notice.

All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.

Winbond Electronics (Shanghai) Ltd.

200336 China

FAX: 86-21-62365998

27F, 2299 Yan An W. Rd. Shanghai,

TEL: 86-21-62365999

Winbond Electronics Corporation Japan

Shinyokohama Kohoku-ku,

Yokohama, 222-0033

FAX: 81-45-4781800

7F Daini-ueno BLDG, 3-7-18

TEL: 81-45-4781881

9F, No.480, Rueiguang Rd.,

Neihu District, Taipei, 114,

Taiwan, R.O.C.