MC33910G5AC/MC3433910G5AC Freescale Semiconductor Advance Information Document Number: MC33911 Rev. 8.0, 3/2010 LIN System Basis Chip with DC Motor Pre-driver 33911 The 33911G5/BAC is a Serial Peripheral Interface (SPI) controlled System Basis Chip (SBC), combining many frequently used functions in an MCU based system, plus a Local Interconnect Network (LIN) transceiver. The 33911 has a 5.0 V, 50 mA/60 mA low dropout regulator with full protection and reporting features. The device provides full SPI readable diagnostics and a selectable timing watchdog for detecting errant operation. The LIN Protocol Specification 2.0 and 2.1 compliant LIN transceiver has waveshaping circuitry that can be disabled for higher data rates. One 50 mA/60 mA high side switch and two 150 mA/160 mA low side switches with output protection are available. All outputs can be pulse-width modulated (PWM). Two high voltage inputs are available for use in contact monitoring, or as external wake-up inputs. These inputs can be used as high voltage Analog Inputs. The voltage on these pins is divided by a selectable ratio and available via an analog multiplexer. The 33911 has three main operating modes: Normal (all functions available), Sleep (VDD off, wake-up via LIN, wake-up inputs (L1, L2), cyclic sense and forced wake-up), and Stop (VDD on with limited current capability, wake-up via CS, LIN bus, wake-up inputs, cyclic sense, forced wake-up and external reset). The 33911 is compatible with LIN Protocol Specification 2.0, 2.1, and SAEJ2602-2. SYSTEM BASIS CHIP WITH LIN 2ND GENERATION AC SUFFIX (Pb-FREE) 98ASH70029A 32-PIN LQFP ORDERING INFORMATION Features * Full-duplex SPI interface at frequencies up to 4.0 MHz * LIN transceiver capable of up to 100 kbps with wave shaping * One 50 mA/60 mA high side and two 150 mA/60 mA low side protected switches * Two high voltage analog/logic Inputs * Configurable window watchdog * 5.0 V low drop regulator with fault detection and low voltage reset (LVR) circuitry * Pb-free packaging designated by suffix code AC Device Temperature Range (TA) MC33911G5AC/R2 - 40C to 125C MC34911G5AC/R2 -40C to 85C MC33911BAC/R2 - 40C to 125C MC34911BAC/R2 -40C to 85C * See Page 2 for Device Variations 33911 VBAT VSENSE HS1 VS1 VS2 LIN INTERFACE L1 L2 LIN VDD PWMIN ADOUT0 LS1 M MOSI MISO SCLK CS RXD TXD IRQ RST LS2 WDCONF LGND PGND AGND MCU Figure 1. 33911 Simplified Application Diagram * This document contains certain information on a new product. Specifications and information herein are subject to change without notice. (c) Freescale Semiconductor, Inc., 2009 - 2010. All rights reserved. Package 32-LQFP MC33911G5AC/MC3433911G5AC DEVICE VARIATIONS DEVICE VARIATIONS The 33911G5 data sheet is within MC33911G5 Product Specifications Pages 3 to 47 The 33911BAC data sheet is within MC33911BAC Product Specifications pages 48 to 88 Table 1. This specification support the following products Device MC33911G5AC Temperature Generation 1. Increase ESD GUN IEC61000-4-2 (gun test contact with 150 pF, 330 test conditions) performance to achieve 6.0 kV min on the LIN pin. - 40 to 125C 2.5 MC34911G5AC - 40 to 85C MC33911BAC/R2 - 40 to 125C MC34911BAC/R2 - 40 to 85C 2. Immunity against ISO7637 pulse 3b 3. Reduce EMC emission level on LIN 4. Improve EMC immunity against RF - target new specification including 3x68 pF 5. Comply with J2602 conformance test 2.0 Initial release 33911 2 Analog Integrated Circuit Device Data Freescale Semiconductor MC33911G5AC/MC3433911G5AC MC33911G5 PRODUCT SPECIFICATIONS PAGES 3 TO 47 MC33911G5 PRODUCT SPECIFICATIONS PAGES 3 TO 47 33911 Analog Integrated Circuit Device Data Freescale Semiconductor 3 MC33911G5AC/MC3433911G5AC INTERNAL BLOCK DIAGRAM INTERNAL BLOCK DIAGRAM RST IRQ INTERRUPT CONTROL MODULE LVI, HVI, ALL OT (VDD,HS,LS,LIN,SD) RESET CONTROL MODULE LVR, WD, EXT C VS1 INTERNAL BUS VS2 VDD AGND VOLTAGE REGULATOR LS1 LOW SIDE CONTROL MODULE WINDOW WATCHDOG MODULE LS2 PWMIN PGND VS2 MISO SCLK HS1 SPI & CONTROL ANALOG MULTIPLEXER MOSI HIGH SIDE CONTROL MODULE CS ADOUT0 WAKE-UP MODULE VBAT SENSE MODULE CHIP TEMPERATURE SENSE MODULE ANALOG INPUT MODULE DIGITAL INPUT MODULE RXD TXD VSENSE L1 L2 LIN PHYSICAL LAYER LIN LGND WDCONF Figure 2. 33911G5 Simplified Internal Block Diagram 33911 4 Analog Integrated Circuit Device Data Freescale Semiconductor MC33911G5AC/MC3433911G5AC PIN CONNECTIONS AGND VDD NC* VSENSE NC* VS1 VS2 HS1 32 31 30 29 28 27 26 25 PIN CONNECTIONS RXD 1 24 NC* TXD 2 23 L1 MISO 3 22 L2 MOSI 4 21 NC* SCLK 5 20 NC* CS 6 19 LS1 ADOUT0 7 18 PGND PWMIN 8 17 LS2 9 10 11 12 13 14 15 16 RST IRQ NC* WDCONF LIN LGND NC* NC* * See Recommendation in Table below Figure 3. 33911 Pin Connections Table 2. 33911 Pin Definitions A functional description of each pin can be found in the Functional Pin Description section beginning on page 24. Pin Pin Name Formal Name Definition 1 RXD Receiver Output This pin is the receiver output of the LIN interface which reports the state of the bus voltage to the MCU interface. 2 TXD Transmitter Input This pin is the transmitter input of the LIN interface which controls the state of the bus output. 3 MISO SPI Output SPI (Serial Peripheral Interface) data output. When CS is high, pin is in the high-impedance state. 4 MOSI SPI Input SPI (Serial Peripheral Interface) data input. 5 SCLK SPI Clock SPI (Serial Peripheral Interface) clock Input. 6 CS SPI Chip Select 7 ADOUT0 Analog Output Pin 0 8 PWMIN PWM Input 9 RST Internal Reset I/O Bidirectional Reset I/O pin - driven low when any internal reset source is asserted. RST is active low. 10 IRQ Internal Interrupt Output Interrupt output pin, indicating wake-up events from Stop mode or events from Normal and Normal request modes. IRQ is active low. 11 & 30 NC Not Connected SPI (Serial Peripheral Interface) chip select input pin. CS is active low. Analog Multiplexer Output. High Side and Low Side Pulse Width Modulation Input. This pin must not be connected. 33911 Analog Integrated Circuit Device Data Freescale Semiconductor 5 MC33911G5AC/MC3433911G5AC PIN CONNECTIONS Table 2. 33911 Pin Definitions A functional description of each pin can be found in the Functional Pin Description section beginning on page 24. Pin Pin Name Formal Name Definition 12 WDCONF Watchdog Configuration Pin 13 LIN LIN Bus 14 LGND LIN Ground Pin This pin is the device LIN ground connection. It is internally connected to the PGND pin. 15,16, 20 & 21 NC Not Connected This pin must not be connected or connected to ground. 17 LS2 19 LS1 18 PGND 22 L2 23 L1 24 This input pin is for configuration of the watchdog period and allows the disabling of the watchdog. This pin represents the single-wire bus transmitter and receiver. Low Side Outputs Relay drivers low side outputs. Power Ground Pin This pin is the device low side ground connection. It is internally connected to the LGND pin. Wake-up Inputs These pins are the wake-up capable digital inputs(1). In addition, all Lx inputs can be sensed analog via the analog multiplexer. NC Not Connected This pin must not be connected or connected to VS2. 25 HS1 High Side Output High side switch output. 26 VS2 27 VS1 Power Supply Pin These pins are device battery level power supply pins. VS2 is supplying the HS1 driver while VS1 supplies the remaining blocks.(2) 28 NC Not Connected This pin can be left opening or connected to any potential ground or power supply 29 VSENSE Voltage Sense Pin Battery voltage sense input.(3) 31 VDD Voltage Regulator Output +5.0 V main voltage regulator output pin.(4) 32 AGND Analog Ground Pin This pin is the device analog ground connection. Notes 1. When used as digital input, a series 33 k resistor must be used to protect against automotive transients. 2. Reverse battery protection series diodes must be used externally to protect the internal circuitry. 3. This pin can be connected directly to the battery line for voltage measurements. The pin is self protected against reverse battery connections. It is strongly recommended to connect a 10 k resistor in series with this pin for protection purposes. 4. External capacitor (2.0 F < C < 100 F; 0.1 < ESR < 10 ) required. 33911 6 Analog Integrated Circuit Device Data Freescale Semiconductor MC33911G5AC/MC3433911G5AC ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Table 3. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device. Ratings Symbol Value Unit Normal Operation (DC) VSUP(SS) -0.3 to 27 Transient Conditions (load dump) VSUP(PK) -0.3 to 40 VDD -0.3 to 5.5 VIN -0.3 to VDD +0.3 VIN(IRQ) -0.3 to 11 HS1 Pin Voltage (DC) VHS - 0.3 to VSUP +0.3 V LS1 and LS2 Pin Voltage (DC) VLS -0.3 to 45 V Normal Operation with a series 33k resistor (DC) VLxDC -18 to 40 Transient input voltage with external component (according to ISO7637-2) (See Figure 5, page 20) VLxTR 100 VVSENSE -27 to 40 Normal Operation (DC) VBUSDC -18 to 40 Transient input voltage with external component (according to ISO7637-2) (See Figure 4, page 20) VBUSTR -150 to 100 IVDD Internally Limited ELECTRICAL RATINGS Supply Voltage at VS1 and VS2 Supply Voltage at VDD Input / Output Pins Voltage V (5) CS, RST, SCLK, PWMIN, ADOUT0, MOSI, MISO, TXD, RXD Interrupt Pin (IRQ)(6) V L1 and L2 Pin Voltage VSENSE Pin Voltage (DC) V LIN Pin Voltage VDD Output Current V V V A Notes 5. Exceeding voltage limits on specified pins may cause a malfunction or permanent damage to the device. 6. Extended voltage range for programming purpose only. 33911 Analog Integrated Circuit Device Data Freescale Semiconductor 7 MC33911G5AC/MC3433911G5AC ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Table 3. Maximum Ratings (continued) All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device. Ratings Symbol Value ESD Capability Unit V AECQ100 Human Body Model - JESD22/A114 (CZAP = 100 pF, RZAP = 1500 ) 8.0k LIN Pin VESD1-1 L1 and L2 VESD1-2 6.0k all other Pins VESD1-3 2000 Corner Pins (Pins 1, 8, 9, 16, 17, 24, 25 and 32) VESD2-1 750 All other Pins (Pins 2-7, 10-15, 18-23, 26-31) VESD2-2 500 LIN pin with 220 pF VESD3-1 20k LIN pin without capacitor VESD3-2 11k VS1/VS2 (100 nF to ground) VESD3-3 > 12k Lx inputs (33 k serial resistor) VESD3-4 6000 LIN pin with 220 pF and without capacitor VESD4-1 8000 VS1/VS2 (100 nF to ground) VESD4-2 8000 VESD4-3 8000 Charge Device Model - JESD22/C101 (CZAP = 4.0 pF) According to LIN Conformance Test Specification / LIN EMC Test Specification, August 2004 (CZAP = 150 pF, RZAP = 330 ) Contact Discharge, Unpowered According to IEC 61000-4-2 (CZAP = 150 pF, RZAP = 330 ) Unpowered Lx inputs (33 k serial resistor) THERMAL RATINGS Operating Ambient Temperature (7) Operating Junction Temperature C TA 33911 -40 to 125 34911 -40 to 85 TJ -40 to 150 C Storage Temperature TSTG -55 to 150 C Thermal Resistance, Junction to Ambient RJA Natural Convection, Single Layer board (1s)(7), (8) Natural Convection, Four Layer board (2s2p)(7), (9) Thermal Resistance, Junction to Case(10) Peak Package Reflow Temperature During Reflow(11), (12) C/W 85 56 RJC 23 C/W TPPRT Note 12 C Notes 7. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 8. 9. 10. 11. Per JEDEC JESD51-2 with the single layer board (JESD51-3) horizontal. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. Freescale's Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics. 12. 33911 8 Analog Integrated Circuit Device Data Freescale Semiconductor MC33911G5AC/MC3433911G5AC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 4. Static Electrical Characteristics Characteristics noted under conditions 5.5 V VSUP 18 V, -40C TA 125C for the 33911 and -40C TA 85C for the 34911, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions, unless otherwise noted. Characteristic Symbol Min Typ Max Unit VSUP 5.5 - 18 V Functional Operating Voltage(13) VSUPOP - - 27 V Load Dump VSUPLD - - 40 V IRUN - 4.5 10 mA SUPPLY VOLTAGE RANGE (VS1, VS2) Nominal Operating Voltage SUPPLY CURRENT RANGE (VSUP = 13.5 V) Normal Mode (IOUT at VDD = 10 mA), LIN Recessive State(14) Stop Mode, VDD ON with IOUT = 100 A, LIN Recessive State (16) (17) , (14), (15), ISTOP A 5.5 V < VSUP < 12 V - 47 VSUP = 13.5 V - 62 90 13.5 V < VSUP < 18 V - 180 400 5.5 V < VSUP < 12 V - 27 35 VSUP = 13.5 V - 33 48 13.5 V VSUP < 18 V - 160 300 ICYCLIC - 10 - Threshold (measured on VS1)(18) VBATFAIL 1.5 3.0 3.9 Hysteresis (measured on VS1)(18) VBATFAIL_HYS - 0.9 - VSUV 5.55 6.0 6.6 VSUV_HYS - 0.2 - VSOV 18 19.25 20.5 - 1.0 - Sleep Mode, VDD OFF, LIN Recessive State(14), (16) Cyclic Sense Supply Current Adder(18) 80 ISLEEP A A SUPPLY UNDER/OVER-VOLTAGE DETECTIONS Power-On Reset (BATFAIL)(19) V VSUP under-voltage detection (VSUV Flag) (Normal and Normal Request Modes, Interrupt Generated) Threshold (measured on VS1) Hysteresis (measured on VS1) V VSUP over-voltage detection (VSOV Flag) (Normal and Normal Request Modes, Interrupt Generated) Threshold (measured on VS1) Hysteresis (measured on VS1) VSOV_HYS V Notes 13. Device is fully functional. All features are operating. 14. Total current (IVS1 + IVS2) measured at GND pins excluding all loads, cyclic sense disabled. 15. Total IDD current (including loads) below 100 A. 16. Stop and Sleep modes current will increase if VSUP exceeds13.5 V. 17. 18. 19. This parameter is guaranteed after 90 ms. This parameter is guaranteed by process monitoring but not production tested. The Flag is set during power up sequence. To clear the flag, a SPI read must be performed. 33911 Analog Integrated Circuit Device Data Freescale Semiconductor 9 MC33911G5AC/MC3433911G5AC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 4. Static Electrical Characteristics (continued) Characteristics noted under conditions 5.5 V VSUP 18 V, -40C TA 125C for the 33911 and -40C TA 85C for the 34911, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions, unless otherwise noted. Characteristic (20) VOLTAGE REGULATOR Symbol Min Typ Max 4.75 5.00 5.25 60 110 200 - 0.1 0.25 Unit (VDD) Normal Mode Output Voltage VDDRUN 1.0 mA < IVDD < 50 mA; 5.5 V < VSUP < 27 V Normal Mode Output Current Limitation IVDDRUN Dropout Voltage(21) VDDDROP IVDD = 50 mA Stop Mode Output Voltage V V VDDSTOP IVDD < 5.0 mA mA V 4.75 5.0 5.25 IVDDSTOP 6.0 13 36 Normal Mode, 5.5 V < VSUP < 18 V; IVDD = 10 mA LRRUN - - 25 Stop Mode, 5.5 V < VSUP < 18 V; IVDD = 1.0 mA LRSTOP - - 25 Normal Mode, 1.0 mA < IVDD < 50 mA LDRUN - - 80 Stop Mode, 0.1 mA < IVDD < 5.0 mA LDSTOP - - 50 90 115 140 TPRE_HYS - 13 - C TSD 150 170 190 C TSD_HYS - 13 - C VRSTTH 4.3 4.5 4.7 V 0.0 - 0.9 -150 -250 -350 Stop Mode Output Current Limitation Line Regulation mV Load Regulation Over-temperature Prewarning mA mV (Junction)(22) TPRE Interrupt generated, VDDOT Bit Set Over-temperature Prewarning Hysteresis(22) Over-temperature Shutdown Temperature (Junction)(22) (22) Over-temperature Shutdown Hysteresis C RST INPUT/OUTPUT PIN (RST) VDD Low Voltage Reset Threshold Low-state Output Voltage VOL IOUT = 1.5 mA; 3.5 V VSUP 27 V High-state Output Current (0 V < VOUT < 3.5 V) IOH Pull-down Current Limitation (internally limited) IPD_MAX VOUT = VDD Low-state Input Voltage High-state Input Voltage V A mA 1.5 - 8.0 VIL -0.3 - 0.3 x VDD V VIH 0.7 x VDD - VDD +0.3 V Notes 20. Specification with external capacitor 2.0 F < C < 100 F and 100 m ESR 10 . 21. Measured when voltage has dropped 250 mV below its nominal Value (5.0 V). 22. This parameter is guaranteed by process monitoring but not production tested. 33911 10 Analog Integrated Circuit Device Data Freescale Semiconductor MC33911G5AC/MC3433911G5AC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 4. Static Electrical Characteristics (continued) Characteristics noted under conditions 5.5 V VSUP 18 V, -40C TA 125C for the 33911 and -40C TA 85C for the 34911, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions, unless otherwise noted. Characteristic Symbol Min Typ Max 0.0 - 1.0 VDD -0.9 - VDD Unit MISO SPI OUTPUT PIN (MISO) Low-state Output Voltage VOL IOUT = 1.5 mA High-state Output Voltage VOH IOUT = -250 A Tri-state Leakage Current V V ITRIMISO 0 V VMISO VDD A -10 - 10 SPI INPUT PINS (MOSI, SCLK, CS) Low-state Input Voltage VIL -0.3 - 0.3 x VDD V High-state Input Voltage VIH 0.7 x VDD - VDD +0.3 V MOSI, SCLK Input Current IIN 0 V VIN VDD CS Pull-up Current A -10 - 10 IPUCS 0 V < VIN < 3.5 V A 10 20 30 0.0 - 0.8 VDD -0.8 - VDD INTERRUPT OUTPUT PIN (IRQ) Low-state Output Voltage VOL IOUT = 1.5 mA High-state Output Voltage VOH IOUT = -250 A Leakage Current V V IOUT VDD VOUT 10 V mA - - 2.0 PULSE WIDTH MODULATION INPUT PIN (PWMIN) Low-state Input Voltage VIL -0.3 - 0.3 x VDD V High-state Input Voltage VIH 0.7 x VDD - VDD +0.3 V 10 20 30 Pull-up current 0 V < VIN < 3.5 V IPUPWMIN A 33911 Analog Integrated Circuit Device Data Freescale Semiconductor 11 MC33911G5AC/MC3433911G5AC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 4. Static Electrical Characteristics (continued) Characteristics noted under conditions 5.5 V VSUP 18 V, -40C TA 125C for the 33911 and -40C TA 85C for the 34911, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions, unless otherwise noted. Characteristic Symbol Min Typ Max TJ = 25C, ILOAD = 50 mA; VSUP > 9.0 V - - 7.0 TJ = 150C, ILOAD = 50 mA; VSUP > 9.0 V(23) - - 10 TJ = 150C, ILOAD = 30 mA; 5.5 V < VSUP < 9.0 V(23) - - 14 60 90 250 - 5.0 7.5 - - 10 Unit HIGH SIDE OUTPUT HS1 PIN (HS1) Output Drain-to-Source On Resistance RDS(ON) Output Current Limitation(24) ILIMHS1 0 V < VOUT < VSUP - 2.0 V Open Load Current Detection(25) IOLHS1 Leakage Current ILEAK -0.2 V < VHS1 < VS2 + 0.2 V Short-circuit Detection Threshold(26) mA A VTHSC 5.5 V < VSUP < 27 V mA V VSUP -2.0 - - THSSD 140 160 180 C THSSD_HYS - 10 - C TJ = 25C, ILOAD = 150 mA, VSUP > 9.0 V - - 2.5 TJ = 125C, ILOAD = 150 mA, VSUP > 9.0 V - - 4.5 - - 10 160 275 350 - 7.5 12 Over-temperature Shutdown(27), (31) Over-temperature Shutdown Hysteresis(31) LOW SIDE OUTPUTS LS1 AND LS2 PINS (LS1, LS2) Output Drain-to-Source On Resistance RDS(ON) TJ = 125C, ILOAD = 120 mA, 5.5 V < VSUP < 9.0 V Output Current Limitation(28) ILIMLSX 2.0 V < VOUT < VSUP Open Load Current Detection(29) IOLLSX Leakage Current ILEAK -0.2 V < VOUT < VS1 Active Output Energy Clamp mA Short-circuit Detection Threshold(26) - - 10 VSUP +2.0 - VSUP +5.0 V VTHSC 5.5 V < VSUP < 27 V (30), (31) (31) Over-temperature Shutdown Hysteresis mA A VCLAMP IOUT = 150 mA Over-temperature Shutdown V 2.0 - - TLSSD 140 160 180 C TLSSD_HYS - 10 - C Notes 23. This parameter is production tested up to TA = 125C, and guaranteed by process monitoring up to TJ = 150C. 24. 25. 26. 27. 28. 29. 30. 31. When over-current occurs, the corresponding high side stays ON with limited current capability and the HS1CL flag is set in the HSSR. When open load occurs, the flag (HS1OP) is set in the HSSR. HS and LS automatically shutdown if HSOT or LSOT occurs or if the HVSE flag is enabled and an over-voltage occurs. When over-temperature shutdown occurs, the high side is turned off. All flags in HSSR are set. When over-current occurs, the corresponding low side stays ON with limited current capability and the LSxCL flag is set in the LSSR. When open load occurs, the flag (LSxOP) is set in the LSSR. When over-temperature shutdown occurs, both low sides are turned off. All flags in LSSR are set. Guaranteed by characterization but not production tested 33911 12 Analog Integrated Circuit Device Data Freescale Semiconductor MC33911G5AC/MC3433911G5AC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 4. Static Electrical Characteristics (continued) Characteristics noted under conditions 5.5 V VSUP 18 V, -40C TA 125C for the 33911 and -40C TA 85C for the 34911, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions, unless otherwise noted. Characteristic Symbol Min Typ Max Unit L1 AND L2 INPUT PINS (L1 AND L2) Low Detection Threshold(32) VTHL 5.5 V < VSUP < 27 V V 2.0 2.5 3.0 3.0 3.5 4.0 0.4 0.8 1.4 -10 - 10 800 1300 2000 LXDS (Lx Divider Select) = 0 0.95 1.0 1.05 LXDS (Lx Divider Select) = 1 3.42 3.6 3.78 High Detection Threshold (32) VTHH 5.5 V < VSUP < 27 V Hysteresis(32) VHYS 5.5 V < VSUP < 27 V Input Current(33) V IIN -0.2 V < VIN < VS1 Analog Input Impedance(34) RLXIN Analog Input Divider Ratio (RATIOLx = VLx / VADOUT0) A k RATIOLX Analog Output offset Ratio VRATIOLx- LXDS (Lx Divider Select) = 0 Analog Inputs Matching mV -80 6.0 80 -22 2.0 22 96 100 104 96 100 104 REXT 20 - 200 k WDACC -15 - 15 % OFFSET LXDS (Lx Divider Select) = 1 LXMATCHING LXDS (Lx Divider Select) = 0 LXDS (Lx Divider Select) = 1 WINDOW WATCHDOG CONFIGURATION PIN (WDCONF) V % (35) External Resistor Range Watchdog Period Accuracy with External Resistor (Excluding Resistor Accuracy)(36) ANALOG MULTIPLEXER Temperature Sense Analog Output Voltage VADOUT0_TEMP V TA = -40C 2.0 - 2.8 TA = 25C 2.8 3.0 3.6 TA = 125C 3.6 Temperature Sense Analog Output Voltage per characterization (37) VADOUT0_25 TA = 25C Internal Chip Temperature Sense Gain Internal Chip Temperature Sense Gain per characterization at 3 temperatures(37) See Figure 16, Temperature Sense Gain VSENSE Input Divider Ratio (RATIOVSENSE = VVSENSE / VADOUT0) 5.5 V < VSUP < 27 V Notes 32. 33. 34. 35. 4.6 V 3.1 3.15 3.2 STTOV 9.0 10.5 12 mV/K STTOV_3T 9.9 10.2 10.5 mV/K 5.0 5.25 5.5 RATIOVSENSE The unused Lx pins must be connected to ground. Analog multiplexer input disconnected from Lx input pin. Analog multiplexer input connected to Lx input pin. For VSUP 4.7 to 18 V 36. Watchdog timing period calculation formula: tPWD [ms] = [0.466 * (REXT - 20)] + 10 with (REXT in k) 37. These limits have been defined after laboratory characterization on 3 lots and 30 samples. These tighten limits could not be guaranteed by production test. 33911 Analog Integrated Circuit Device Data Freescale Semiconductor 13 MC33911G5AC/MC3433911G5AC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 4. Static Electrical Characteristics (continued) Characteristics noted under conditions 5.5 V VSUP 18 V, -40C TA 125C for the 33911 and -40C TA 85C for the 34911, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions, unless otherwise noted. Characteristic VSENSE Input Divider Ratio (RATIOVSENSE=Vsense/Vadout0) per characterization(38) Symbol VSENSE Output Related Offset per characterization(38) Typ Max 5.15 5.25 5.35 -30 -10 30 Unit RATIOVSENSECZ 5.5 <VSUP< 27 V VSENSE Output Related Offset Min OFFSETVSENSE mV OFFSETVSENSE_ CZ mV -30 -12.6 0 VDD -0.35 - VDD ANALOG OUTPUT (ADOUT0) Maximum Output Voltage VOUT_MAX -5.0 mA < IO < 5.0 mA Minimum Output Voltage V VOUT_MIN -5.0 mA < IO < 5.0 mA V 0.0 - 0.35 0.0 - 0.8 VDD -0.8 - VDD RXD OUTPUT PIN (LIN PHYSICAL LAYER) (RXD) Low-state Output Voltage VOL IOUT = 1.5 mA High-state Output Voltage VOH IOUT = -250 A V V TXD INPUT PIN (LIN PHYSICAL LAYER) (TXD) Low-state Input Voltage VIL -0.3 - 0.3 x VDD V High-state Input Voltage VIH 0.7 x VDD - VDD +0.3 V IPUIN 10 20 30 A Pin Pull-up Current, 0 V < VIN < 3.5 V LIN PHYSICAL LAYER WITH J2602 FEATURE ENABLED (BIT DIS_J2602 = 0) LIN Under Voltage threshold Positive and Negative threshold (VTHP, VTHN) Hysteresis (VTHP - VTHN) VTH_UNDER_ VOLTAGE VJ2602_DEG V 5.0 6.0 400 mV Notes 38. These limits have been defined after laboratory characterization on 3 lots and 30 samples. These tighten limits could not be guaranteed by production test. 33911 14 Analog Integrated Circuit Device Data Freescale Semiconductor MC33911G5AC/MC3433911G5AC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 4. Static Electrical Characteristics (continued) Characteristics noted under conditions 5.5 V VSUP 18 V, -40C TA 125C for the 33911 and -40C TA 85C for the 34911, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions, unless otherwise noted. Characteristic Symbol Min Operating Voltage Range VBAT Supply Voltage Range Typ Max Unit 8.0 18 V VSUP 7.0 18 V VSUP_NON_OP -0.3 40 V (39) LIN PHYSICAL LAYER, TRANSCEIVER (LIN) Voltage Range within which the device is not destroyed Current Limitation for Driver Dominant State IBUS_LIM Driver ON, VBUS = 18 V Input Leakage Current at the receiver mA 40 90 200 -1.0 - - - - 20 -1.0 - 1.0 - - 100 - - 0.4 0.6 - - IBUS_PAS_DOM Driver off; VBUS = 0 V; VBAT = 12 V Leakage Output Current to GND IBUS_PAS_REC Driver Off; 8.0 V < VBAT < 18 V; 8.0 V < VBUS < 18 V; VBUS VBAT Control unit disconnected from ground(40) A IBUS_NO_GND GNDDEVICE = VSUP; VBAT = 12 V; 0 < VBUS < 18 V VBAT Disconnected; VSUP_DEVICE = GND; 0 V < VBUS < 18 V(41) Receiver Dominant State mA IBUSNO_BAT A VBUSDOM Receiver Recessive State VSUP VBUSREC Receiver Threshold Center VSUP VBUS_CNT (VTH_DOM + VTH_REC)/2 Receiver Threshold Hysteresis VSUP 0.475 0.5 0.525 - - 0.175 VHYS (VTH_REC - VTH_DOM) mA VSUP Voltage Drop at the serial Diode in pull-up path VSERDIODE 0.4 1.0 V VBAT_SHIFT VSHIFT_BAT 0 11.5% VBAT VSHIFT_GND 0 11.5% VBAT 5.3 5.8 V GND_SHIFT LIN Wake-up threshold from Stop or Sleep Mode (42) LIN Pull-up Resistor to VSUP Over-temperature Shutdown(43) Over-temperature Shutdown Hysteresis VBUSWU RSLAVE 20 30 60 k TLINSD 140 160 180 C TLINSD_HYS - 10 - C Notes 39. Parameters guaranteed for 7.0 V VSUP 18 V. 40. 41. 42. 43. Loss of local ground must not affect communication in the residual network. Node has to sustain the current that can flow under this condition. Bus must remain operational under this condition. This parameter is 100% tested on an Automatic Tester. However, since it has not been monitored during reliability stresses, Freescale does not guarantee this parameter during the product's life time. When over-temperature shutdown occurs, the LIN bus goes in recessive state and the flag LINOT in LINSR is set. 33911 Analog Integrated Circuit Device Data Freescale Semiconductor 15 MC33911G5AC/MC3433911G5AC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 5. Dynamic Electrical Characteristics Characteristics noted under conditions 5.5 V VSUP 18 V, -40C TA 125C for the 33911 and -40C TA 85C for the 34911, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions, unless otherwise noted. Characteristic Symbol Min Typ Max Unit SPI Operating Frequency f SPIOP - - 4.0 MHz SCLK Clock Period SPI INTERFACE TIMING (SEE Figure 13, PAGE 23) tPSCLK 250 - N/A ns SCLK Clock High Time(44) tWSCLKH 110 - N/A ns SCLK Clock Low Time(44) tWSCLKL 110 - N/A ns Falling Edge of CS to Rising Edge of SCLK(44) tLEAD 100 - N/A ns Falling Edge of SCLK to CS Rising Edge(44) tLAG 100 - N/A ns MOSI to Falling Edge of SCLK(44) tSISU 40 - N/A ns Falling Edge of SCLK to MOSI(44) tSIH 40 - N/A ns MISO Rise Time(44) tRSO - 40 - CL = 220 pF MISO Fall Time(44) tFSO CL = 220 pF Time from Falling or Rising Edges of ns ns - 40 - CS to:(44) ns - MISO Low-impedance tSOEN 0.0 - 50 - MISO High-impedance tSODIS 0.0 - 50 Time from Rising Edge of SCLK to MISO Data Valid(44) tVALID 0.0 - 75 t RST 0.65 1.0 1.35 ms t RSTDF 350 480 900 ns 8.5 10 11.5 0.2 x VDD MISO 0.8 x VDD, CL = 100 pF ns RST OUTPUT PIN Reset Low-level Duration After VDD High (see Figure 12, page 23) Reset Deglitch Filter Time WINDOW WATCHDOG CONFIGURATION PIN (WDCONF) Watchdog Time Period(45) External Resistor REXT = 20 k (1%) t PWD ms External Resistor REXT = 200 k (1%) 79 94 108 Without External Resistor REXT (WDCONF Pin Open) 110 150 205 Notes 44. This parameter is guaranteed by process monitoring but not production tested. 45. Watchdog timing period calculation formula: tPWD [ms] = [0.466 * (REXT - 20)] + 10 with (REXT in k) 33911 16 Analog Integrated Circuit Device Data Freescale Semiconductor MC33911G5AC/MC3433911G5AC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 5. Dynamic Electrical Characteristics (continued) Characteristics noted under conditions 5.5 V VSUP 18 V, -40C TA 125C for the 33911 and -40C TA 85C for the 34911, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions, unless otherwise noted. Characteristic Symbol Min Typ Max Unit t WUF 8.0 20 38 s - - 5.0 t NR TOUT 110 150 205 ms TON 130 200 270 s +35 % L1 AND L2 INPUTS Lx Filter Time Deglitcher(46) STATE MACHINE TIMING Delay Between CS LOW-to-HIGH Transition (at End of SPI Stop Command) and Stop Mode Activation(46) Normal Request Mode Timeout (see Figure 12, page 23) Cyclic Sense ON Time from Stop and Sleep Mode(47) t STOP Cyclic Sense Accuracy(46) Delay Between SPI Command and HS /LS Turn On(48) -35 - - 10 s t S-OFF 9.0 V < VSUP < 27 V Delay Between Normal Request and Normal Mode After a Watchdog Trigger Command (Normal Request Mode)(46) s t S-ON 9.0 V < VSUP < 27 V Delay Between SPI Command and HS /LS Turn Off(48) s - - 10 - - 10 s t SNR2N Delay Between CS Wake-up (CS LOW to HIGH) in Stop Mode and: s Normal Request Mode, VDD ON and RST HIGH t WUCS 9.0 15 80 First Accepted SPI Command t WUSPI 90 -- N/A t 2CS 4.0 -- -- 35 50 70 Minimum Time Between Rising and Falling Edge on the CS s J2602 DEGLITCHER VSUP Deglitcher(49) (DIS_J2602 = 0) tJ2602_DEG s Notes 46. This parameter is guaranteed by process monitoring but not production tested. 47. This parameter is 100% tested on an Automatic Tester. However, since it has not been monitored during reliability stresses, Freescale does not guarantee this parameter during the product's life time. 48. Delay between turn on or off command (rising edge on CS) and HS or LS ON or OFF, excluding rise or fall time due to external load. 49. This parameter has not been monitoring during operating life test. 33911 Analog Integrated Circuit Device Data Freescale Semiconductor 17 MC33911G5AC/MC3433911G5AC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 5. Dynamic Electrical Characteristics (continued) Characteristics noted under conditions 5.5 V VSUP 18 V, -40C TA 125C for the 33911 and -40C TA 85C for the 34911, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions, unless otherwise noted. Characteristic Symbol Min Typ Max Unit LIN PHYSICAL LAYER: DRIVER CHARACTERISTICS FOR NORMAL SLEW RATE - 20.0KBIT/SEC ACCORDING TO LIN PHYSICAL LAYER SPECIFICATION(50), (51) Duty Cycle 1: D1 THREC(MAX) = 0.744 * VSUP THDOM(MAX) = 0.581 * VSUP D1 = tBUS_REC(MIN)/(2 x tBIT), tBIT = 50 s, 7.0 V VSUP 18 V Duty Cycle 2: 0.396 -- -- -- -- 0.581 D2 THREC(MIN) = 0.422 * VSUP THDOM(MIN) = 0.284 * VSUP D2 = tBUS_REC(MAX)/(2 x tBIT), tBIT = 50 s, 7.6 V VSUP 18 V LIN PHYSICAL LAYER: DRIVER CHARACTERISTICS FOR SLOW SLEW RATE - 10.4KBIT/SEC ACCORDING TO LIN PHYSICAL LAYER SPECIFICATION(50), (52) Duty Cycle 3: D3 THREC(MAX) = 0.778 * VSUP THDOM(MAX) = 0.616 * VSUP D3 = tBUS_REC(MIN)/(2 x tBIT), tBIT = 96 s, 7.0 V VSUP 18 V Duty Cycle 4: 0.417 -- -- -- -- 0.590 D4 THREC(MIN) = 0.389 * VSUP THDOM(MIN) = 0.251 * VSUP D4 = tBUS_REC(MAX)/(2 x tBIT), tBIT = 96 s, 7.6 V VSUP 18 V Notes 50. Bus load RBUS and CBUS 1.0 nF / 1.0 k, 6.8 nF / 660 , 10 nF / 500 . Measurement thresholds: 50% of TXD signal to LIN signal threshold defined at each parameter. See Figure 6, page 21. 51. See Figure 7, page 21. 52. See Figure 8, page 21. 33911 18 Analog Integrated Circuit Device Data Freescale Semiconductor MC33911G5AC/MC3433911G5AC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 5. Dynamic Electrical Characteristics (continued) Characteristics noted under conditions 5.5 V VSUP 18 V, -40C TA 125C for the 33911 and -40C TA 85C for the 34911, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions, unless otherwise noted. Characteristic Symbol Min Typ Max Unit SRFAST -- 20 -- V / s t REC_PD -- 4.2 6.0 t REC_SYM - 2.0 -- 2.0 t PROPWL 42 70 95 t WAKE_SLEEP -- -- 1500 t WAKE_STOP 9.0 27 35 t TXDDOM 0.65 1.0 1.35 LIN PHYSICAL LAYER: DRIVER CHARACTERISTICS FOR FAST SLEW RATE LIN Fast Slew Rate (Programming Mode) LIN PHYSICAL LAYER: CHARACTERISTICS AND WAKE-UP TIMINGS (53) Propagation Delay and Symmetry(54) s Propagation Delay of Receiver, tREC_PD=MAX (tREC_PDR, tREC_PDF) Symmetry of Receiver Propagation Delay, tREC_PDF - tREC_PDR Bus Wake-up Deglitcher (Sleep and Stop Modes)(55),(59), (56) Bus Wake-up Event Reported From Sleep Mode (57) From Stop Mode(58) TXD Permanent Dominant State Delay s s s PULSE WIDTH MODULATION INPUT PIN (PWMIN) PWMIN pin(59) Max. frequency to drive HS and LS output pins fPWMIN kHz 10 Notes 53. VSUP from 7.0 to 18 V, bus load RBUS and CBUS 1.0 nF / 1.0 k, 6.8 nF / 660 , 10 nF / 500 . Measurement thresholds: 50% of TXD signal to LIN signal threshold defined at each parameter. See Figure 6, page 21. 54. See Figure 9, page 22 55. See Figure 10, page 22 for Sleep and Figure 11, page 22 for Stop mode. 56. This parameter is tested on automatic tester but has not been monitoring during operating life test. 57. The measurement is done with 1.0 F capacitor and 0mA current load on VDD. The value takes into account the delay to charge the capacitor. The delay is measured between the bus wake-up threshold (VBUSWU) rising edge of the LIN bus and when VDD reaches 3.0 V. See Figure 10, page 22. The delay depends of the load and capacitor on VDD. 58. 59. In Stop mode, the delay is measured between the bus wake-up threshold (VBUSWU) and the falling edge of the IRQ pin. See Figure 11, page 22. This parameter is guaranteed by process monitoring but not production tested. 33911 Analog Integrated Circuit Device Data Freescale Semiconductor 19 MC33911G5AC/MC3433911G5AC ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS TIMING DIAGRAMS 33911 1.0 nF LIN TRANSIENT PULSE GENERATOR (NOTE) GND PGND LGND AGND Note Waveform per ISO 7637-2. Test Pulses 1, 2, 3a, 3b. Figure 4. Test Circuit for Transient Test Pulses (LIN) 33911 Transient Pulse Generator (Note) 1.0 nF L1, L2 10 k GND PGND LGND AGND Note Waveform per ISO 7637-2. Test Pulses 1, 2, 3a, 3b,. Figure 5. Test Circuit for Transient Test Pulses (Lx) VSUP TXD LIN R0 RXD C0 R0 AND C0 COMBINATIONS: * 1.0 K and 1.0 nF * 660 and 6.8 nF * 500 and 10 nF Figure 6. Test Circuit for LIN Timing Measurements 33911 20 Analog Integrated Circuit Device Data Freescale Semiconductor MC33911G5AC/MC3433911G5AC ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS TXD tBIT tBIT tBUS_DOM(MAX) VLIN_REC THREC(MAX) 74.4% VSUP THDOM(MAX) 58.1% VSUP tBUS_REC(MIN) Thresholds of receiving node 1 LIN THREC(MIN) THDOM(MIN) Thresholds of receiving node 2 42.2% VSUP 28.4% VSUP tBUS_DOM(MIN) tBUS_REC(MAX) RXD Output of receiving Node 1 tREC_PDF(1) tREC_PDR(1) RXD Output of receiving Node 2 tREC_PDF(2) tREC_PDR(2) Figure 7. LIN Timing Measurements for Normal Slew Rate TXD tBIT tBIT tBUS_DOM(MAX) VLIN_REC THREC(MAX) 77.8% VSUP THDOM(MAX) 61.6% VSUP tBUS_REC(MIN) Thresholds of receiving node 1 LIN THREC(MIN) THDOM(MIN) Thresholds of receiving node 2 38.9% VSUP 25.1% VSUP tBUS_DOM(MIN) tBUS_REC(MAX) RXD Output of receiving Node 1 tREC_PDF(1) tREC_PDR(1) RXD Output of receiving Node 2 tREC_PDR(2) tREC_PDF(2) Figure 8. LIN Timing Measurements for Slow Slew Rate 33911 Analog Integrated Circuit Device Data Freescale Semiconductor 21 MC33911G5AC/MC3433911G5AC ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS VLIN_REC VBUSREC 0.6% VSUP VBUSDOM 0.4% VSUP VSUP LIN BUS SIGNAL RXD tREC_PDF tREC_PDR Figure 9. LIN Receiver Timing VLIN_REC LIN 5.0 V VBUSWU DOMINANT LEVEL 3.0 V VDD tPROPWL tWAKE_SLEEP Figure 10. LIN Wake-up Sleep Mode Timing VLIN_REC LIN 5.0 V VBUSWU DOMINANT LEVEL IRQ tPROPWL tWAKE_STOP Figure 11. LIN Wake-up Stop Mode Timing 33911 22 Analog Integrated Circuit Device Data Freescale Semiconductor MC33911G5AC/MC3433911G5AC ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS VSUP VDD RST tNRTOUT tRST Figure 12. Power On Reset and Normal Request Timeout Timing tPSCLK CS tWSCLKH tLEAD tLAG SCLK tWSCLKL tSISU MOSI UNDEFINED D0 tSIH DON'T CARE D7 DON'T CARE tVALID tSODIS tSOEN MISO D0 DON'T CARE D7 Figure 13. SPI Timing Characteristics 33911 Analog Integrated Circuit Device Data Freescale Semiconductor 23 MC33911G5AC/MC3433911G5AC FUNCTIONAL DESCRIPTION INTRODUCTION FUNCTIONAL DESCRIPTION INTRODUCTION The 33911 was designed and developed as a highly integrated and cost-effective solution for automotive and industrial applications. For automotive body electronics, the 33911 is well suited to perform relay control in applications such as a window lift, sunroof, etc. via the LIN bus. Power switches are provided on the device configured as high side and low side outputs. Other ports are also provided, which include a current and voltage sense port and two wakeup capable pins. An internal voltage regulator provides power to a MCU device. Also included in this device is a LIN physical layer, which communicates using a single wire. This enables this device to be compatible with 3-wire bus systems, where one wire is used for communication, one for battery, and one for ground. FUNCTIONAL PIN DESCRIPTION See Figure 1, 33911 Simplified Application Diagram, page 1, for a graphic representation of the various pins referred to in the following paragraphs. Also, see the pin diagram on page 5 for a description of the pin locations in the package. MASTER OUT SLAVE IN PIN (MOSI) RECEIVER OUTPUT PIN (RXD) The MISO pin sends data to an SPI-enabled MCU. It is a digital tri-state output used to shift serial data to the microcontroller. Data on this output pin changes on the positive edge of the SCLK. When CS is High, this pin will remain in the high-impedance state. The RXD pin is a digital output. It is the receiver output of the LIN interface and reports the state of the bus voltage: RXD Low when LIN bus is dominant, RXD High when LIN bus is recessive. TRANSMITTER INPUT PIN (TXD) The TXD pin is a digital input. It is the transmitter input of the LIN interface and controls the state of the bus output (dominant when TXD is Low, recessive when TXD is High). This pin has an internal pull-up to force recessive state in case the input is left floating. LIN BUS PIN (LIN) The LIN pin represents the single-wire bus transmitter and receiver. It is suited for automotive bus systems and is compliant to the LIN bus specification 2.0, 2.1, and SAE J2602-2. The LIN interface is only active during Normal mode. See Table 6, Operating Modes Overview. The MOSI digital pin receives SPI data from the MCU. This data input is sampled on the negative edge of SCLK. MASTER IN SLAVE OUT PIN (MISO) CHIP SELECT PIN (CS) CS is an active low digital input. It must remain low during a valid SPI communication and allow for several devices to be connected in the same SPI bus without contention. A rising edge on CS signals the end of the transmission and the moment the data shifted in is latched. A valid transmission must consist of 8 bits only. While in STOP mode, a low-to-high level transition on this pin will generate a wake-up condition for the 33911. ANALOG MULTIPLEXER PIN (ADOUT0) The ADOUT0 pin can be configured via the SPI to allow the MCU A/D converter to read the several inputs of the Analog Multiplexer, including the VSENSE, L1, L2 input voltages, and the internal junction temperature. SERIAL DATA CLOCK PIN (SCLK) PWM INPUT CONTROL PIN (PWMIN) The SCLK pin is the SPI clock input. MISO data changes on the positive transition of the SCLK. MOSI is sampled on the negative edge of the SCLK. This digital input can control the high side and low sides drivers in Normal Request and Normal mode. To enable PWM control, the MCU must perform a write operation to the High Side Control Register (HSCR) or the Low Side Control Register (LSCR). This pin has an internal 20 A current pull-up. 33911 24 Analog Integrated Circuit Device Data Freescale Semiconductor MC33911G5AC/MC3433911G5AC FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION RESET PIN (RST) This bidirectional pin is used to reset the MCU in case the 33911 detects a reset condition, or to inform the 33911 that the MCU has just been reset. After release of the RST pin, Normal Request mode is entered. The RST pin is an active low filtered input and output formed by a weak pull-up and a switchable pull-down structure which allows this pin to be shorted either to VDD or to GND during software development, without the risk of destroying the driver. INTERRUPT PIN (IRQ) The IRQ pin is a digital output used to signal events or faults to the MCU while in Normal and Normal Request mode or to signal a wake-up from Stop mode. This active low output will transition to high only after the interrupt is acknowledged by a SPI read of the respective status bits. WATCHDOG CONFIGURATION PIN (WDCONF) The WDCONF pin is the configuration pin for the internal watchdog. A resistor can be connected to this pin to configure the window watchdog period. When connected directly to ground, the watchdog will be disabled. When this pin is left open, the watchdog period is fixed to its lower precision internal default value (150 ms typical). GROUND CONNECTION PINS (AGND, PGND, LGND) The AGND, PGND and LGND pins are the Analog and Power ground pins. The AGND pin is the ground reference of the voltage regulator. The PGND and LGND pins are used for high current load return as in the relay-drivers and LIN interface pin. Note: PGND, AGND and LGND pins must be connected together. LOW SIDE PINS (LS1 AND LS2) LS1 and LS2 are the low side driver outputs. Those outputs are short-circuit protected and include active clamp circuitry to drive inductive loads. Due to the energy clamp voltage on this pin, it can raise above the battery level when switched off. The switches are controlled through the SPI and can be configured to respond to a signal applied to the PWMIN input pin. Both low side switches are protected against overheating. In case of VS1 disconnection and the low sides are still supplied by VBAT through a load, both low sides will have a VDS voltage equal to the clamping value, as stated in the specification. DIGITAL/ANALOG PINS (L1 AND L2) The Lx pins are multi purpose inputs. They can be used as digital inputs, which can be sampled by reading the SPI and used for wake-up when 33911 is in low power mode or used as analog inputs for the analog multiplexer. When used to sense voltage outside the module, a 33 kohm series resistor must be used on each input. When used as wake-up inputs L1 and L2 can be configured to operate in cyclic-sense mode. In this mode the high side switch is configured to be periodically turned on and sample the wake-up inputs. If a state change is detected between two cycles a wake-up is initiated. The 33911 can also wake-up from Stop or Sleep by a simple state change on L1 and L2. When used as analog inputs, the voltage present on the Lx pins is scaled down by an selectable internal voltage divider and can be routed to the ADOUT0 output through the analog multiplexer. Note: If an Lx input is selected in the analog multiplexer, it will be disabled as a digital input and remains disabled in low power mode. No wake-up feature is available in that condition. When an Lx input is not selected in the analog multiplexer, the voltage divider is disconnected from that input. HIGH SIDE OUTPUT PIN (HS1) This high side switch is able to drive loads such as relays or lamps. Its structure is connected to the VS2 supply pin. The pin is short-circuit protected and also protected against overheating. HS1 is controlled by SPI and can respond to a signal applied to the PWMIN input pin. The HS1 output can also be used during low-power mode for the cyclic-sense of the wake inputs. POWER SUPPLY PINS (VS1 AND VS2) Those are the battery level voltage supply pins. In an application, VS1 and VS2 pins must be protected against reverse battery connection and negative transient voltages with external components. These pins sustain standard automotive voltage conditions such as a load dump at 40 V. The high side switch (HS1) is supplied by the VS2 pin. All other internal blocks are supplied by the VS1 pin. 33911 Analog Integrated Circuit Device Data Freescale Semiconductor 25 MC33911G5AC/MC3433911G5AC FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION VOLTAGE SENSE PIN (VSENSE) +5.0 V MAIN REGULATOR OUTPUT PIN (VDD) This input can be connected directly to the battery line. It is protected against battery reverse connection. The voltage present in this input is scaled down by an internal voltage divider, and can be routed to the ADOUT0 output pin and used by the MCU to read the battery voltage. The ESD structure on this pin allows for excursion up to +40 V and down to -27 V, allowing this pin to be connected directly to the battery line. It is strongly recommended to connect a 10 kohm resistor in series with this pin for protection purposes. An external capacitor has to be placed on the VDD pin to stabilize the regulated output voltage. The VDD pin is intended to supply a microcontroller. The pin is current limited against shorts to GND and over-temperature protected. During Stop mode, the voltage regulator does not operate with its full drive capabilities and the output current is limited. During Sleep mode, the regulator output is completely shut down. 33911 26 Analog Integrated Circuit Device Data Freescale Semiconductor MC33911G5AC/MC3433911G5AC FUNCTIONAL DEVICE OPERATIONS OPERATIONAL MODES FUNCTIONAL DEVICE OPERATIONS OPERATIONAL MODES INTRODUCTION The 33911 offers three main operating modes: Normal (Run), Stop, and Sleep (Low Power). In Normal mode, the device is active and is operating under normal application conditions. The Stop and Sleep modes are low power modes with wake-up capabilities. In Stop mode, the voltage regulator still supplies the MCU with VDD (limited current capability), while in Sleep mode the voltage regulator is turned off (VDD = 0 V). Wake-up from Stop mode is initiated by a wake-up interrupt. Wake-up from Sleep mode is done by a reset and the voltage regulator is turned back on. The selection of the different modes is controlled by the MOD1:2 bits in the Mode Control Register (MCR). Figure 14 describes how transitions are done between the different operating modes. Table 6, gives an overview of the operating modes. The VDD regulator is ON and delivers its full current capability. If an external resistor is connected between the WDCONF pin and the Ground, the window watchdog function will be enabled. The wake-up inputs (L1 and L2) can be read as digital inputs or have its voltage routed through the analogmultiplexer. The LIN interface has slew rate and timing compatible with the LIN protocol specification 2.0, 2.1 and SAEJ2602. The LIN bus can transmit and receive information. The high side and low side switches are active and have PWM capability according to the SPI configuration. The interrupts are generated to report failures for VSUP over/under-voltage, thermal shutdown, or thermal shutdown prewarning on the main regulator. SLEEP MODE RESET MODE The 33911 enters the Reset mode after a power up. In this mode, the RST pin is low for 1.0 ms (typical value). After this delay, it enters the Normal Request mode and the RST pin is driven high. The Reset mode is entered if a reset condition occurs (VDD low, watchdog trigger fail, after wake-up from Sleep mode, Normal Request mode timeout occurs). NORMAL REQUEST MODE This is a temporary mode automatically accessed by the device after the Reset mode, or after a wake-up from Stop mode. In Normal Request mode, the VDD regulator is ON, the RESET pin is High, and the LIN is operating in RX Only mode. As soon as the device enters in the Normal Request mode an internal timer is started for 150 ms (typical value). During these 150 ms, the MCU must configure the Timing Control Register (TIMCR) and the Mode Control Register (MCR) with MOD2 and MOD1 bits set = 0, to enter the Normal mode. If within the 150 ms timeout, the MCU does not command the 33911 to Normal mode, it will enter in Reset mode. If the WDCONF pin is grounded in order to disable the watchdog function, it goes directly in Normal mode after the Reset mode. NORMAL MODE In Normal mode, all 33911 functions are active and can be controlled by the SPI interface and the PWMIN pin. The Sleep mode is a low power mode. From Normal mode, the device enters into Sleep mode by sending one SPI command through the Mode Control Register (MCR), or (VDD low > 150 ms) with VSUV = 0. When in Reset mode, a VDD under-voltage condition with no VSUP under-voltage (VSUV = 0) will send the device to Sleep mode. All blocks are in their lowest power consumption condition. Only some wake-up sources (wake-up inputs with or without cyclic sense, forced wake-up and LIN receiver) are active. The 5.0 V regulator is OFF. The internal low-power oscillator may be active if the IC is configured for cyclic-sense. In this condition, the high side switch is turned on periodically and the wake-up inputs are sampled. Wake-up from Sleep mode is similar to a power-up. The device goes in Reset mode except that the SPI will report the wake-up source and the BATFAIL flag is not set. STOP MODE The Stop mode is the second low power mode, but in this case the 5.0 V regulator is ON with limited current drive capability. The application MCU is always supplied while the 33911 is operating in Stop mode. The device can enter into Stop mode only by sending the SPI command. When the application is in this mode, it can wake-up from the 33911 side (for example: cyclic sense, force wake-up, LIN bus, wake inputs) or the MCU side (CS, RST pins). Wake-up from Stop mode will transition the 33911 to Normal Request mode and generates an interrupt except if the wake-up event is a low to high transition on the CS pin or comes from the RST pin. 33911 Analog Integrated Circuit Device Data Freescale Semiconductor 27 MC33911G5AC/MC3433911G5AC FUNCTIONAL DEVICE OPERATIONS OPERATIONAL MODES Normal Request Timeout Expired (t NRTOUT ) Normal Request timeout expired (NR TOUT) VVDD Low DD Low VDD High and Normal Request VVDDLow Low DD VVDD LOW (>t NRTOUT ) expired) Expired DD Low (>NRTOUT andand VSUV =0 VSUV =0 Wake-up Wake-Up (Reset) (Reset) Sleep Command SLEEP Command Sleep Stop STOPCommand Command Normal WD Failed WD failed Wake-up (Interrupt) Wake-Up Interrupt Reset Reset Delay (t Delay VDD High and Reset RST) expired RST) (tExpired WD Disabled WD disabled Power Up WDtrigger Trigger WD Power Down Stop VDD VDD Low Low Legend WD: Watchdog Notes: WD Disabled: Watchdog disabled (WDCONF pin connected to GND) WD - meansisWatchdog WD Trigger: Watchdog triggered by SPI command WD means or Watchdog disabled (WDCONF terminal connected to GND) WD Failed: No disabled watchdog- trigger trigger occurs in closed window WD trigger - means Watchdog is triggered by SPI command Stop Command: Stop command sent via SPI WD failed - means no Watchdog trigger or trigger occurs in closed window Sleep Command: Sleep command sent via SPI STOP Command means STOP command via SPI Periodic wake-up, CS rising edge wake-up or RST wake-up. Wake-up from Stop mode: L1- or L2 state change, LIN sent bus wake-up, SLEEP Command SLEEP command via SPI Wake-up from Sleep mode: L1 -ormeans L2 state change, LIN bussend wake-up, Periodic wake-up. Wake-Up - means L1 or L2 state change or LIN bus wake up or SS rising edge Figure 14. Operating Modes and Transitions 33911 28 Analog Integrated Circuit Device Data Freescale Semiconductor MC33911G5AC/MC3433911G5AC FUNCTIONAL DEVICE OPERATIONS OPERATIONAL MODES Table 6. Operating Modes Overview Function VDD Reset Mode Normal Request Mode Normal Mode Stop Mode Sleep Mode Full Full Full Stop - - SPI/PWM(60) SPI/PWM - - HS1 - SPI/PWM(60) SPI/PWM Note(61) Note(62) Analog Mux - SPI SPI - - Lx - Inputs Inputs Wake-up Wake-up LIN - Rx-Only LSx Watchdog - 150 ms (typ.) timeout Voltage Monitoring VSUP/VDD VSUP/VDD Notes 60. 61. 62. 63. Full/Rx-Only Rx-Only/Wake-up Wake-up (63) - - VSUP/VDD VDD - On /Off Operation can be controlled by the PWMIN input. HS1 switch can be configured for cyclic sense operation in Stop mode. HS1 switch can be configured for cyclic sense operation in Sleep mode. Windowing operation when enabled by an external resistor. INTERRUPTS Low-voltage Interrupt: Interrupts are used to signal a microcontroller that a peripheral needs to be serviced. The interrupts which can be generated, change according to the operating mode. While in Normal and Normal Request modes, the 33911 signals through interrupts special conditions which may require a MCU software action. Interrupts are not generated until all pending wake-up sources are read in the Interrupt Source Register (ISR). While in Stop mode, interrupts are used to signal wake-up events. Sleep mode does not use interrupts. Wake-up is performed by powering-up the MCU. In Normal and Normal Request mode the wake-up source can be read by SPI. The interrupts are signaled to the MCU by a low logic level of the IRQ pin, which will remain low until the interrupt is acknowledged by a SPI read command of the ISR register. The IRQ pin will then be driven high. Interrupts are only asserted while in Normal, Normal Request and Stop mode. Interrupts are not generated while the RST pin is low. The following is a list of the interrupt sources in Normal and Normal Request modes. Some of these can be masked by writing to the SPI - Interrupt Mask Register (IMR). Signals when the supply line (VS1) voltage drops below the VSUV threshold (VSUV). High-voltage Interrupt: Signals when the supply line (VS1) voltage increases above the VSOV threshold (VSOV). Over-temperature Prewarning: Signals when the 33911 temperature has reached the preshutdown warning threshold. It is used to warn the MCU that an over-temperature shutdown in the main 5.0 V regulator is imminent. LIN Over-temperature Shutdown / TXD Stuck At Dominant / RXD Short-circuit: These signal fault conditions within the LIN interface will cause the LIN driver to be disabled. In order to restart the operation, the fault must be removed and TXD must go recessive. High Side Over-temperature Shutdown: Signals a shutdown in the high side output. Low Side Over-temperature Shutdown: Signals a shutdown in the low side outputs. 33911 Analog Integrated Circuit Device Data Freescale Semiconductor 29 MC33911G5AC/MC3433911G5AC FUNCTIONAL DEVICE OPERATIONS OPERATIONAL MODES RESET To reset a MCU the 33911 drives the RST pin low for the time the reset condition lasts. After the reset source is removed, the state machine will drive the RST output low for at least 1.0 ms (typical value) before driving it high. In the 33911, four main reset sources exist: 5.0 V Regulator Low-voltage-Reset (VRSTTH) The 5.0 V regulator output VDD is continuously monitored against brown outs. If the supply monitor detects that the voltage at the VDD pin has dropped below the reset threshold VRSTTH the 33911 will issue a reset. In case of overtemperature, the voltage regulator will be disabled and the voltage monitoring will issue a VDDOT Flag independently of the VDD voltage. In order to select and activate direct wake-up from Lx inputs, the Wake-up Control Register (WUCR) must be configured with appropriate LxWE inputs enabled or disabled. The wake-up input's state is read through the Wake-up Status Register (WUSR). Lx inputs are also used to perform cyclic-sense wake-up. Note: Selecting an Lx input in the analog multiplexer before entering low power mode will disable the wake-up capability of the Lx input Wake-up from Wake-up inputs (L1 and L2) with cyclic sense timer enabled During Sleep mode, the 5.0 V regulator is not active, hence all wake-up requests from Sleep mode require a power-up/reset sequence. The SBCLIN can wake-up at the end of a cyclic sense period if on one of the two wake-up input lines (L1-L2) a state change occurs. The HS1 switch can be activated in Sleep or Stop modes from an internal timer. Cyclic sense and force wake-up are exclusive. If cyclic sense is enabled, the force wake-up can not be enabled. In order to select and activate the cyclic sense wake-up from Lx inputs, before entering in low power modes (Stop or Sleep modes), the following SPI set-up has to be performed: In WUCR: select the Lx input to WU-enable. In HSCR: enable the desired HS1. * In TIMCR: select the CS/WD bit and determine the cyclic sense period with CYSTx bits. * Perform Go to Sleep/Stop command. External Reset Forced Wake-up The 33911 has a bidirectional reset pin which drives the device to a safe state (same as Reset mode) for as long as this pin is held low. The RST pin must be held low long enough to pass the internal glitch filter and get recognized by the internal reset circuit. This functionality is also active in Stop mode. After the RST pin is released, there is no extra t RST to be considered. The 33911 can wake-up automatically after a predetermined time spent in Sleep or Stop mode. Cyclic sense and Forced wake-up are exclusive. If Forced wake-up is enabled, the Cyclic Sense can not be enabled. To determine the wake-up period, the following SPI set-up has to be sent before entering in low power modes: * In TIMCR: select the CS/WD bit and determine the low power mode period with CYSTx bits. * In HSCR: The HS1 bit must be disabled. Window Watchdog Overflow If the watchdog counter is not properly serviced while its window is open, the 33911 will detect an MCU software runaway and will reset the microcontroller. Wake-up From Sleep Mode WAKE-UP CAPABILITIES Once entered into one of the low-power modes (Sleep or Stop) only wake-up sources can bring the device into Normal mode operation. In Stop mode, a wake-up is signaled to the MCU as an interrupt, while in Sleep mode the wake-up is performed by activating the 5.0 V regulator and resetting the MCU. In both cases the MCU can detect the wake-up source by accessing the SPI registers and reading the Interrupt Source Register. There is no specific SPI register bit to signal a CS wake-up or external reset. If necessary this condition is detected by excluding all other possible wake-up sources. Wake-up from Wake-up inputs (L1 and L2) with cyclic sense disabled CS Wake-up While in Stop mode, a rising edge on the CS will cause a wake-up. The CS wake-up does not generate an interrupt, and is not reported on SPI. LIN Wake-up While in the low-power mode, the 33911 monitors the activity on the LIN bus. A dominant pulse larger than t PROPWL followed by a dominant to recessive transition will cause a LIN wake-up. This behavior protects the system from a short to ground bus condition. The bit RXONLY = 1 from LINCR Register disables the LIN wake-up from Stop mode. The wake-up lines are dedicated to sense state changes of external switches and wake-up the MCU (in Sleep or Stop mode). 33911 30 Analog Integrated Circuit Device Data Freescale Semiconductor MC33911G5AC/MC3433911G5AC FUNCTIONAL DEVICE OPERATIONS OPERATIONAL MODES RST Wake-up While in Stop mode, the 33911 can wake-up when the RST pin is held low long enough to pass the internal glitch filter. Then, the 33911 will change to Normal Request or Normal modes depending on the WDCONF pin configuration. The RST wake-up does not generate an interrupt and is not reported via SPI. From Stop mode, the following wake-up events can be configured: * Wake-up from Lx inputs without cyclic sense * Cyclic sense wake-up inputs * Force wake-up * CS wake-up * LIN wake-up * RST wake-up From Sleep mode, the following wake-up events can be configured: * Wake-up from Lx inputs without cyclic sense * Cyclic sense wake-up inputs * Force wake-up * LIN wake-up WINDOW WATCHDOG The 33911 includes a configurable window watchdog which is active in Normal mode. The watchdog can be configured by an external resistor connected to the WDCONF pin. The resistor is used to achieve higher precision in the timebase used for the watchdog. SPI clears are performed by writing through the SPI in the MOD bits of the Mode Control Register (MCR). During the first half of the SPI timeout, watchdog clears are not allowed, but after the first half of the SPI timeout window, the clear operation opens. If a clear operation is performed outside the window, the 33911 will reset the MCU, in the same way as when the watchdog overflows. WINDOW CLOSED NO WATCHDOG CLEAR ALLOWED WD TIMING X 50% WINDOW OPEN FOR WATCHDOG CLEAR WD TIMING X 50% WD PERIOD (tPWD) WD TIMING SELECTED BY RESISTOR ON WDCONF PIN Figure 15. Window Watchdog Operation To disable the watchdog function in Normal mode the user must connect the WDCONF pin to ground. This measure effectively disables Normal Request mode. The WDOFF bit in the Watchdog Status Register (WDSR) will be set. This condition is only detected during Reset mode. If neither a resistor nor a connection to ground is detected, the watchdog falls back to the internal lower precision timebase of 150 ms (typ.) and signals the faulty condition through the Watchdog Status Register (WDSR). The watchdog timebase can be further divided by a prescaler which can be configured by the Timing Control Register (TIMCR). During Normal Request mode, the window watchdog is not active but there is a 150 ms (typ.) timeout for leaving the Normal Request mode. In case of a timeout, the 33911 will enter into Reset mode, resetting the microcontroller before entering again into Normal Request mode. FAULTS DETECTION MANAGEMENT The 33911 has the capability to detect faults like an over or under-voltage on VS1, TxD in permanent Dominant State, Over-temperature on HS, LIN. It is able to take corrective actions accordingly. Most of faults are monitoring through SPI and the Interrupt pin. The microcontroller can also take actions. The following table summarizes all fault sources the device is able to detect with associated conditions. The status for a device recovery and the SPI or pins monitoring are also described. 33911 Analog Integrated Circuit Device Data Freescale Semiconductor 31 MC33911G5AC/MC3433911G5AC FUNCTIONAL DEVICE OPERATIONS OPERATIONAL MODES Table 7. Fault Detection Management Conditions MONITORING(65) BLOCK FAULT BATTERY FAIL VSUP OVERVOLTAGE Power Supply MODE All modes Normal, Normal Request VSUP UNDERVOLTAGE VDD UNDERVOLTAGE CONDITION FALLOUT VSUP<3.0 V (typ) then power-up VSUP > 19.25 V (typ) In Normal mode, HS and LS shutdown if bit HVSE=1 (reg MCR) VSUP < 6.0 V (typ) All except Sleep VDD < 4.5 V (typ) RECOVERY REG (FLAG, BIT) INTERRUPT Condition gone VSR (BATFAIL, 0) - Condition gone, to re-enable HS or LS write to HSCR or LSCR registers VSR (VSOV,3) IRQ low + ISR (0101)(66) VSR (VSUV,2) IRQ low + ISR (0101) Reset (64) - - Condition gone VDD OVER-TEMP PREWARNING VDD OVERTEMPERATURE All except Low Power modes RXD PIN SHORT CIRCUIT LIN High Side TXD PIN PERMANENT DOMINANT RXD pin shorted to GND or 5 V LIN trans shutdown TXD pin low for more than 1s (typ) HIGH SIDE DRIVER OVERTEMPERATURE Temperature > 160C (typ) Normal, Normal Request LIN transmitter shutdown HS1 thermal shutdown Current through HS1 < 5.0 mA (typ) HS1 on with limited current capability 60 mA (min) LOW SIDE DRIVERS OVERTEMPERATURE Temperature > 160C (typ) Both LS thermal shutdown LS2 OPEN-LOAD LS2 OVER-CURRENT NORMAL REQUEST TIME-OUT EXPIRED Normal Request - IRQ low + ISR (0101) - LINSR, (RXSHORT,3) LIN transmitter reenabled once the condition is gone and TXD is high Condition gone, to re-enable HS1 write to HSCR reg - Current through HS1 tends to rise above the current limit 60 mA (min) Normal, Normal Request VSR (VDDOT,1) LINSR (TXDOM,2) IRQ low + ISR (0100)(66) LINSR (LINOT,1) HS1 OVERCURRENT LS1 OVER-CURRENT Watchdog VDD shutdown, Reset then Sleep Temperature > 160C (typ) HS1 OPEN-LOAD DETECTION - Temperature > 170C (typ) LIN DRIVER OVERTEMPERATURE LS1 OPEN-LOAD Low Side Normal, Normal Request Temperature > 115C (typ) All flags in HSSR are set IRQ low + ISR (0010) (66) HSSR (HS1OP,1) Condition gone HSSR (HS1CL,0) Condition gone, to re-enable LS write to LSCR reg All flags in LSSR are set IRQ low + ISR (0011) (66) LSSR (LS1OP,1) Current through LSx < 7.5 mA (typ) LSSR (LS2OP,3) - Current through LSx tends to rise above the current limit 160 mA (min) LSx on with limited current capability 160 mA (min) The MCU did not command the device to Normal mode within the 150 ms timeout after reset Reset LSSR (LS1CL,0) - LSSR (LS2CL,2) - WATCHDOG TIMEOUT Normal WD timeout or WD clear within the window closed Reset - WATCHDOG ERROR Normal WDCONF pin is floating WD internal lower precision timebase 150 ms (typ) WDSR (WDTO, 3) Connect WDCONF to a resistor or to GND WDSR (WDERR, 2) Notes 64. 65. 66. When in Reset mode a VDD under-voltage condition combined with no VSUP under-voltage (VSUV=0) will send the device to Sleep mode. Registers to be read when back in Normal Request or Normal mode depending on the fault. Interrupts only generated in Normal, Normal Request and Stop modes Unless masked, If masked IRQ remains high and the ISR flags are not set. 33911 32 Analog Integrated Circuit Device Data Freescale Semiconductor MC33911G5AC/MC3433911G5AC FUNCTIONAL DEVICE OPERATIONS OPERATIONAL MODES TEMPERATURE SENSE GAIN The analog multiplexer can be configured via SPI to allow the ADOUT0 pin to deliver the internal junction temperature of the device. The graph below illustrates the internal chip temp sense obtained per characterization at 3 temperatures with 3 different lots and 30 samples. Temperature Sense Analog Output Voltage 5 4.5 Vadout0 (V) 4 3.5 3 2.5 2 -50 0 50 100 150 Temperature (C) Figure 16. Temperature Sense Gain HIGH SIDE OUTPUT PINS HS1 This output is one high side driver intended to drive small resistive loads or LEDs incorporating the following features: * PWM capability (software maskable) * Open load detection * Current limitation * Over-temperature shutdown (with maskable interrupt) * High-voltage shutdown (software maskable) * Cyclic sense The high side switch is controlled by the bit HS1 in the High Side Control Register (HSCR). PWM Capability (direct access) The high side driver offers additional (to the SPI control) direct control via the PWMIN pin. If the bit HS1 and PWMHS1 are set in the High Side Control Register (HSCR), then the HS1 driver is turned on if the PWMIN pin is high and turned of if the PWMIN pin is low. 33911 Analog Integrated Circuit Device Data Freescale Semiconductor 33 MC33911G5AC/MC3433911G5AC FUNCTIONAL DEVICE OPERATIONS OPERATIONAL MODES Interrupt Control Module MOD1:2 HS1 HS1OP VDD VDD PWMIN High-Side Interrupt High Voltage Shutdown HVSE PWMHS1 VS2 on/off Control Status HS1CL High Side Driver charge pump open load detection current limitation over-temperture shutdown (interrupt maskable) high voltage shutdown (maskable) Cyclic Sense HS1 Wakeup Module Figure 17. High Side Drivers HS1 Open Load Detection The high side driver signals an open load condition if the current through the high side is below the open load current threshold. The open load condition is indicated with the bit HS1OP in the High Side Status Register (HSSR). Current Limitation The high side driver has an output current limitation. In combination with the over-temperature shutdown the highside driver is protected against over-current and short-circuit failures. When the driver operates in the current limitation area, it is indicated with the bit HS1CL in the HSSR. Note: If the driver is operating in current limitation mode, excessive power might be dissipated. Over-temperature Protection (HS Interrupt) The high side driver is protected against over-temperature. In case of an over-temperature condition, the high side driver is shut down and the event is latched in the Interrupt Control Module. The shutdown is indicated as HS Interrupt in the Interrupt Source Register (ISR). A thermal shutdown of the high side driver is indicated by setting the HS1OP and HS1CL bits simultaneously. If the bit HSM is set in the Interrupt Mask Register (IMR), then an interrupt (IRQ) is generated. A write to the High Side Control Register (HSCR), when the over-temperature condition is gone, will re-enable the high side driver. High-voltage Shutdown In case of a high voltage condition and if the high voltage shutdown is enabled (bit HVSE in the Mode Control Register (MCR) is set the high side driver is shut down. A write to the High Side Control Register (HSCR), when the high voltage condition is gone, will re-enable the high side driver. Sleep And Stop Mode The high side driver can be enabled to operate in Sleep and Stop mode for cyclic sensing. Also see Table 6, Operating Modes Overview. LOW SIDE OUTPUT PINS LS1 AND LS2 These outputs are two low side drivers intended to drive relays incorporating the following features: * PWM capability (software maskable) * Open load detection * Current limitation * Over-temperature shutdown (with maskable interrupt) * Active clamp (for driving relays) * High-voltage shutdown (software maskable) The low side switches are controlled by the bit LS1:2 in the Low Side Control Register (LSCR). 33911 34 Analog Integrated Circuit Device Data Freescale Semiconductor MC33911G5AC/MC3433911G5AC FUNCTIONAL DEVICE OPERATIONS OPERATIONAL MODES To protect the device against over-voltage when an inductive load (relay) is turned off. An active clamp will reenable the low side FET if the voltage on the LS1 or LS2 pin exceeds a certain level. If both the bits LS1 and PWMLS1 are set in the Low Side Control Register (LSCR), then the LS1 driver is turned on if the PWMIN pin is high and turned off if the PWMIN pin is low. The same applies to the LS2 and PWMLS2 bits for the LS2 driver. PWM Capability (direct access) Each low side driver offers additional (to the SPI control) direct control via the PWMIN pin. HVSE VDD Interrupt Control Module VDD MOD1:2 LSx LSxOP PWMLSx Low Side Interrupt High-voltage Shutdown PWMIN active clamp LSx on/off Control LSxCL Status Low Side Driver (active clamp) Open-load Detection Current Limitation Over-temperture Shutdown (interrupt maskable) High-voltage shutdown (maskable) PGND Figure 18. Low Side Drivers LS1 and LS2 Open Load Detection High-voltage Shutdown Each low side driver signals an open load condition if the current through the low side is below the open load current threshold. The open load condition is indicated with the bit LS1OP and LS2OP in the Low Side Status Register (LSSR). In case of a high-voltage condition and if the high-voltage shutdown is enabed (bit HVSE in the Mode Control Register (MCR) is set both low sides drivers are shut down. A write to the Low Side Control Register (LSCR), when the high-voltage condition is gone, will re-enable the low side drivers. Current Limitation Each low side driver has a current limitation. In combination with the over-temperature shutdown the low side drivers are protected against over-current and shortcircuit failures. When the drivers operate in current limitation, this is indicated with the bits LS1CL and LS2CL in the LSSR. Note: If the drivers are operating in current limitation mode excessive power might be dissipated. Over-temperature Protection (LS Interrupt) Both low side drivers are protected against overtemperature. In case of an over-temperature condition both low side drivers are shut down and the event is latched in the Interrupt Control Module. The shutdown is indicated as an LS Interrupt in the Interrupt Source Register (ISR). If the bit LSM is set in the Interrupt Mask Register (IMR) then an Interrupt (IRQ) is generated. A write to the Low Side Control Register (LSCR), when the over-temperature condition is gone, will re-enable the low side drivers. Sleep And Stop Mode The low side drivers are disabled in Sleep and Stop mode. Also see Table 6, Operating Modes Overview. LIN PHYSICAL LAYER The LIN bus pin provides a physical layer for single-wire communication in automotive applications. The LIN physical layer is designed to meet the LIN physical layer specification and has the following features: * LIN physical layer 2.0, 2.1 and SAEJ2602 compliant * Slew rate selection * Over-temperature shutdown * Advanced diagnostics The LIN driver is a low side MOSFET with thermal shutdown. An internal pull-up resistor with a serial diode structure is integrated, so no external pull-up components are required for the application in a slave node. The fall time from dominant to recessive and the rise time from recessive to dominant is controlled. The symmetry between both slopes is guaranteed. 33911 Analog Integrated Circuit Device Data Freescale Semiconductor 35 MC33911G5AC/MC3433911G5AC FUNCTIONAL DEVICE OPERATIONS OPERATIONAL MODES LIN Pin The LIN pin offers a high susceptibility immunity level from external disturbance, guaranteeing communication during external disturbance. WAKE-UP MODULE LIN Wake-up MOD1:2 LSR0:1 J2602 VS1 LIN DRIVER RXONLY Slope and Slew Rate Control RXSHORT Over-temperature Shutdown (interrupt maskable) TXDOM LINOT 30 K LIN TXD SLOPE CONTROL WAKE-UP FILTER LGND RXD RECEIVER Figure 19. LIN Interface Slew Rate Selection The slew rate can be selected for optimized operation at 10.4 and 20 kBit/s as well as a fast baud rate for test and programming. The slew rate can be adapted with the bits LSR1:0 in the LIN Control Register (LINCR). The initial slew rate is optimized for 20 kBit/s. J2602 Conformance To be compliant with the SAE J2602-2 specification, the J2602 feature has to be enabled in the LINCR Register (bit DIS_J2602 sets to 0). The LIN transmitter is disabled in case of a VSUP under-voltage condition occurs and TXD is in Recessive State: the LIN bus goes in Recessive State and RXD goes high. The LIN transmitter is not disabled if TXD is in Dominant State. A deglitcher on Vsup (tJ2602_DEG) is implemented to avoid false switching. If the (DIS_J2602) bit is set to 1, the J2602 feature is disabled and the communication TXD-LIN-RXD works for VSUP down to 4.6 V (typical value) and then the communication is interrupted. The (DIS_J2602) bit is set per default to 0. Over-temperature Shutdown (LIN Interrupt) The output low side FET is protected against overtemperature conditions. In case of an over-temperature condition, the transmitter will be shut down and the LINOT bit in the LIN Status Register (LINSR) is set. If the LINM bit is set in the Interrupt Mask Register (IMR), an Interrupt IRQ will be generated. The transmitter is automatically re-enabled once the condition is gone and TXD is high. RXD Short-circuit Detection (LIN Interrupt) The LIN transceiver has a short-circuit detection for the RXD output pin. If the device transmits and in case of a short- 33911 36 Analog Integrated Circuit Device Data Freescale Semiconductor MC33911G5AC/MC3433911G5AC FUNCTIONAL DEVICE OPERATIONS OPERATIONAL MODES circuit condition, either 5.0 V or Ground, the RXSHORT bit in the LIN Status Register (LINSR) is set and the transmitter is shut down. If the LINM bit is set in the Interrupt Mask Register (IMR), an Interrupt IRQ will be generated. The transmitter is automatically re-enabled once the condition is gone (transition on RXD) and TXD is high. A read of the LIN Status Register (LINSR) without the RXD pin short-circuit condition will clear the bit RXSHORT. TXD Dominant Detection (LIN Interrupt) The LIN transceiver monitors the TXD input pin to detect a stuck in dominant (0 V) condition. In case of a stuck condition (TXD pin 0 V for more than 1 second (typ.)), the transmitter is shut down and the TXDOM bit in the LIN Status Register (LINSR) is set. If the LINM bit is set in the IMR, an Interrupt IRQ will be generated. The transmitter is automatically re-enabled once TXD is high. A read of the LIN Status Register (LINSR) with the TXD pin at 5.0 V will clear the bit TXDOM. LIN Receiver Operation Only While in Normal mode, the activation of the RXONLY bit disables the LIN TXD driver. In case of a LIN error condition, this bit is automatically set. If Stop mode is selected with this bit set, the LIN wake-up functionality is disabled and the RXD pin will reflect the state of the LIN bus. STOP Mode And Wake-up Feature During Stop mode operation, the transmitter of the physical layer is disabled. The receiver is still active and able to detect wake-up events on the LIN bus line. A dominant level longer than TPROPWL followed by a rising edge will generate a wake-up interrupt, and will be reported in the Interrupt Source Register (ISR). Also see Figure 11. SLEEP Mode And Wake-up Feature During Sleep mode operation, the transmitter of the physical layer is disabled. The receiver must be active to detect wake-up events on the LIN bus line. A dominant level longer than TPROPWL followed by a rising edge will generate a system wake-up (Reset), and will be reported in the Interrupt Source Register (ISR). Also see Figure 10. 33911 Analog Integrated Circuit Device Data Freescale Semiconductor 37 MC33911G5AC/MC3433911G5AC FUNCTIONAL DEVICE OPERATIONS LOGIC COMMANDS AND REGISTERS LOGIC COMMANDS AND REGISTERS 33911 SPI INTERFACE AND CONFIGURATION * MISO -- Master-in Slave-out * SCLK-- Serial Clock A complete data transfer via the SPI consists of 1 byte. The master sends 4 bits of address (A3:A0) + 4 bits of control information (C3:C0) and the slave replies with 4 system status bits (VMS,LINS,HSS,LSS) + 4 bits of status information (S3:S0). The serial peripheral interface creates the communication link between a microcontroller (master) and the 33911. The interface consists of four pins (see Figure 20): * CS -- Chip Select * MOSI -- Master-out Slave-in CS Register Write Data MOSI A3 A2 A1 A0 C3 C2 C1 C0 S1 S0 Register Read Data MISO VMS LINS HSS LSS S3 S2 SCLK Read Data Latch Rising: 33911 changes MISO/ MCU changes MOSI Write Data Latch Falling: 33911 samples MOSI/ MCU samples MISO Figure 20. SPI Protocol During the inactive phase of the CS (HIGH), the new data The rising edge of the Chip Select CS indicates the end of transfer is prepared. the transfer and latches the write data (MOSI) into the register. The CS high forces MISO to the high-impedance The falling edge of the CS indicates the start of a new data state. transfer and puts the MISO in the low-impedance state and Register reset values are described along with the reset latches the analog status data (Register read data). condition. Reset condition is the condition causing the bit to With the rising edge of the SPI clock (SCLK), the data is be set to its reset value. The main reset conditions are: moved to MISO/MOSI pins. With the falling edge of the SPI - Power-On Reset (POR): the level at which the logic is clock (SCLK), the data is sampled by the receiver. reset and BATFAIL flag sets. The data transfer is only valid if exactly 8 sample clock - Reset mode edges are present during the active (low) phase of CS. - Reset done by the RST pin (ext_reset) 33911 38 Analog Integrated Circuit Device Data Freescale Semiconductor MC33911G5AC/MC3433911G5AC FUNCTIONAL DEVICE OPERATIONS LOGIC COMMANDS AND REGISTERS SPI REGISTER OVERVIEW Table 8. System Status Register Adress(A3:A0) $0 - $F BIT Register Name / Read / Write Information SYSSR - System Status Register R 7 6 5 4 VMS LINS HSS LSS Table 9 summarizes the SPI Register content for Control Information (C3:C0)=W and status information (S3:S0) = R. Table 9. SPI Register Overview Adress(A3:A0) BIT Register Name / Read / Write Information 3 2 1 0 MCR - Mode Control Register W HVSE 0 MOD2 MOD1 VSR - Voltage Status Register R VSOV VSUV VDDOT BATFAIL VSR - Voltage Status Register R VSOV VSUV VDDOT BATFAIL WUCR - Wake-up Control Register W 0 0 L2WE L1WE WUSR - Wake-up Status Register R - - L2 L1 WUSR - Wake-up Status Register R - - L2 L1 LINCR - LIN Control Register W DIS_J2602 RXONLY LSR1 LSR0 LINSR - LIN Status Register R RXSHORT TXDOM LINOT 0 LINSR - LIN Status Register R RXSHORT TXDOM LINOT 0 HSCR - High Side Control Register W 0 PWMHS1 0 HS1 HSSR - High Side Status Register R - - HS1OP HS1CL HSSR - High Side Status Register R - - HS1OP HS1CL LSCR - Low Side Control Register W PWMLS2 PWMLS1 LS2 LS1 LSSR - Low Side Status Register R LS2OP LS2CL LS1OP LS1CL LSSR - Low Side Status Register R LS2OP LS2CL LS1OP LS1CL TIMCR - Timing Control Register W CS/WD WD2 WD1 WD0 CYST2 CYST1 CYST0 WDSR - Watchdog Status Register R WDTO WDERR WDOFF WDWO $B WDSR - Watchdog Status Register R WDTO WDERR WDOFF WDWO $C AMUXCR - Analog Multiplexer Control Register W LXDS MX2 MX1 MX0 $D CFR - Configuration Register W 0 CYSX8 0 0 IMR - Interrupt Mask Register W HSM LSM LINM VMM ISR - Interrupt Source Register R ISR3 ISR2 ISR1 ISR0 ISR - Interrupt Source Register R ISR3 ISR2 ISR1 ISR0 $0 $1 $2 $3 $4 $5 $6 $7 $8 $9 $A $E $F 33911 Analog Integrated Circuit Device Data Freescale Semiconductor 39 MC33911G5AC/MC3433911G5AC FUNCTIONAL DEVICE OPERATIONS LOGIC COMMANDS AND REGISTERS REGISTER DEFINITIONS System Status Register - SYSSR HS1CL The System Status Register (SYSSR) is always transferred with every SPI transmission and gives a quick system status overview. It summarizes the status of the Voltage Monitor Status (VMS), LIN Status (LINS), High Side Status (HSS), and the Low Side Status (LSS). Table 10. System Status Register Read HSS HS1OP Figure 23. High Side Status LSS - Low Side Switch Status S7 S6 S5 S4 VMS LINS HSS LSS VMS - Voltage Monitor Status This read-only bit indicates that one or more bits in the LSSR are set. 1 = Low Side Status bit set 0 = None This read-only bit indicates that one or more bits in the VSR are set. 1 = Voltage Monitor bit set 0 = None LS1CL LS1OP LSS LS2CL LS2OP BATFAIL VDDOT VSUV Figure 24. Low Side Status VMS VSOV Figure 21. Voltage Monitor Status Mode Control Register - MCR The Mode Control Register (MCR) allows switching between the operation modes and to configure the 33911. Writing the MCR will return the VSR. Table 11. Mode Control Register - $0 LINS - LIN Status This read-only bit indicates that one or more bits in the LINSR are set. 1 = LIN Status bit set 0 = None C3 C2 C1 C0 Write HVSE 0 MOD2 MOD1 Reset Value 1 0 - - Reset Condition POR POR - - LINOT TXDOM LINS RXSHORT Figure 22. LIN Status HSS - High Side Switch Status This read-only bit indicates that one or more bits in the HSSR are set. 1 = High Side Status bit set 0 = None HVSE - High-Voltage Shutdown Enable This write-only bit enables/disables automatic shutdown of the high side and the low side drivers during a high-voltage VSOV condition. 1 = automatic shutdown enabled 0 = automatic shutdown disabled MOD2, MOD1 - Mode Control Bits These write-only bits select the operating mode and allow clearing the watchdog in accordance with Table 7 Mode Control Bits. 33911 40 Analog Integrated Circuit Device Data Freescale Semiconductor MC33911G5AC/MC3433911G5AC FUNCTIONAL DEVICE OPERATIONS LOGIC COMMANDS AND REGISTERS Wake-up Control Register - WUCR Table 12. Mode Control Bits This register is used to control the digital wake-up inputs. Writing the WUCR will return the Wake-up Status Register (WUSR). MOD2 MOD1 Description 0 0 Normal mode 0 1 Stop mode 1 0 Sleep mode 1 1 Normal mode + Watchdog Clear Table 14. Wake-up Control Register - $2 Voltage Status Register - VSR Returns the status of the several voltage monitors. This register is also returned when writing to the Mode Control Register (MCR). C3 C2 C1 C0 Write 0 0 L2WE L1WE Reset Value 1 1 1 1 Reset Condition POR, Reset mode or ext_reset Table 13. Voltage Status Register - $0/$1 Read S3 S2 S1 S0 VSOV VSUV VDDOT BATFAIL VSOV - VSUP Over-voltage This read-only bit indicates an over-voltage condition on the VS1 pin. 1 = Over-voltage condition. 0 = Normal condition. VSUV - VSUP Under-voltage This read-only bit indicates an under-voltage condition on the VS1 pin. 1 = Under-voltage condition. 0 = Normal condition. VDDOT - Main Voltage Regulator Over-temperature Warning This read-only bit indicates that the main voltage regulator temperature reached the Over-temperature Prewarning Threshold. 1 = Over-temperature Prewarning 0 = Normal BATFAIL - Battery Fail Flag. This read-only bit is set during power-up and indicates that the 33911 had a Power-On-Reset (POR). Any access to the MCR or VSR will clear the BATFAIL flag. 1 = POR Reset has occurred 0 = POR Reset has not occurred LxWE - Wake-up Input x Enable This write-only bit enables/disables which Lx inputs are enabled. In Stop and Sleep mode the LxWE bit determines which wake inputs are active for wake-up. If one of the Lx inputs is selected on the analog multiplexer, the corresponding LxWE is masked to 0. 1 = Wake-up Input x enabled. 0 = Wake-up Input x disabled. Wake-up Status Register - WUSR This register is used to monitor the digital wake-up inputs and is also returned when writing to the WUCR. Table 15. Wake-up Status Register - $2/$3 Read S3 S2 S1 S0 - - L2 L1 Lx - Wake-up input x This read-only bit indicates the status of the corresponding Lx input. If the Lx input is not enabled, then the according Wake-up status will return 0. After a wake-up from Stop or Sleep mode these bits also allow to determine which input has caused the wake-up, by first reading the Interrupt Status Register (ISR) and then reading the WUSR. The source of the wake-up is only reported on the first WUCR or WUSR access. 1 = Lx pin high, or Lx is the source of the wake-up. 0 = Lx pin low, disabled or selected as an analog input. LIN Control Register - LINCR This register controls the LIN physical interface block. Writing the LIN Control Register (LINCR) returns the LIN Status Register (LINSR). 33911 Analog Integrated Circuit Device Data Freescale Semiconductor 41 MC33911G5AC/MC3433911G5AC FUNCTIONAL DEVICE OPERATIONS LOGIC COMMANDS AND REGISTERS Table 18. LIN Status Register - $4/$5 Table 16. LIN Control Register - $4 C3 C2 C1 C0 Write DIS_J2602 RXONLY LSR1 LSR0 Reset Value 0 0 0 0 POR POR, Reset mode, ext_reset or LIN failure gone* Reset Condition POR * LIN failure gone: if LIN failure (overtemp, TXD/RXD short) was set, the flag resets automatically when the failure is gone. J2602 - LIN Dominant Voltage Select This write-only bit controls the J2602 circuitry. If the circuitry is enabled (bit sets to 0), the TXD-LIN-RXD communication works down to the battery under-voltage condition is detected. Below, the bus is in recessive state. If the circuitry is disabled (bit sets to 1), the communication TXD-LIN-RXD works down to 4.6 V (typical value). 0 = Enabled J2602 feature. 1 = Disabled J2602 feature. RXONLY - LIN Receiver Operation Only This write-only bit controls the behavior of the LIN transmitter. In Normal mode, the activation of the RXONLY bit disables the LIN transmitter. In case of a LIN error condition, this bit is automatically set. In Stop mode this bit disables the LIN wake-up functionality, and the RXD pin will reflect the state of the LIN bus. 1 = only LIN receiver active (Normal mode) or LIN wakeup disabled (Stop mode). 0 = LIN fully enabled. LSRx - LIN Slew-Rate This write-only bit controls the LIN driver slew-rate in accordance with Table 17. Table 17. LIN Slew Rate Control LSR1 LSR0 Description 0 0 Normal Slew Rate (up to 20 kb/s) 0 1 Slow Slew Rate (up to 10 kb/s) 1 0 Fast Slew Rate (up to 100 kb/s) 1 1 Reserved LIN Status Register - LINSR This register returns the status of the LIN physical interface block and is also returned when writing to the LINCR. Read S3 S2 S1 S0 RXSHORT TXDOM LINOT 0 RXSHORT - RXD Pin Short-circuit This read-only bit indicates a short-circuit condition on the RXD pin (shorted either to 5.0 V or to Ground). The shortcircuit delay must be a worst case of 8s to be detected and to shut down the driver. To clear this bit, it must be read after the condition is gone (transition detected on RXD pin). The LIN driver is automatically re-enabled once the condition is gone and TXD is high. 1 = RXD short-circuit condition. 0 = None. TXDOM - TXD Permanent Dominant This read-only bit signals the detection of a TXD pin stuck at dominant (Ground) condition and the resultant shutdown in the LIN transmitter. This condition is detected after the TXD pin remains in dominant state for more than 1 second (typical value). To clear this bit, it must be read after TXD has gone high. The LIN driver is automatically re-enabled once TXD goes High. 1 = TXD stuck at dominant fault detected. 0 = None. LINOT - LIN Driver Over-temperature This read-only bit signals that the LIN transceiver was shutdown due to over-temperature. The transmitter is automatically re-enabled after the over-temperature condition is gone and TXD is high. The LINOT bit is cleared after SPI read once the condition is gone. 1 = LIN over-temperature shutdown 0 = None High Side Control Register - HSCR This register controls the operation of the high side driver. Writing to this register returns the High Side Status Register (HSSR). Table 19. High Side Control Register - $6 C3 C2 C1 C0 Write 0 PWMHS1 0 HS1 Reset Value 0 0 0 0 Reset Condition POR POR, Reset mode, ext_reset, HS1 over-temp or (VSOV & HVSE) 33911 42 Analog Integrated Circuit Device Data Freescale Semiconductor MC33911G5AC/MC3433911G5AC FUNCTIONAL DEVICE OPERATIONS LOGIC COMMANDS AND REGISTERS PWMHS1 - PWM Input Control Enable. PWMLx - PWM input control enable. This write-only bit enables/disables the PWMIN input pin to control the high side switch. The high side switch must be enabled (HS1 bit). 1 = PWMIN input controls HS1 output. 0 = HS1 is controlled only by SPI. This write-only bit enables/disables the PWMIN input pin to control the respective low side switch. The corresponding low side switch must be enabled (LSx bit). 1 = PWMIN input controls LSx. 0 = LSx is controlled only by SPI. HS1 - HS1 Switch Control. LSx - LSx switch control. This write-only bit enables/disables the high side switch. 1 = HS1 switch on. 0 = HS1 switch off. This write-only bit enables/disables the corresponding low side switch. 1 = LSx switch on. 0 = LSx switch off. High Side Status Register - HSSR This register returns the status of the high side switch and is also returned when writing to the HSCR. Table 20. High Side Status Register - $6/$7 Read Low Side Status Register - LSSR This register returns the status of the low side switches and is also returned when writing to the LSCR. Table 22. Low Side Status Register - $8/$9 S3 S2 S1 S0 - - HS1OP HS1CL Read C3 C2 C1 C0 LS2OP LS2CL LS1OP LS1CL High Side thermal shutdown A thermal shutdown of the high side driver is indicated by setting the HS1OP and HS1CL bits simultaneously. Low Side thermal shutdown A thermal shutdown of the low side drivers is indicated by setting all LSxOP and LSxCL bits simultaneously. HS1OP - High Side Switch Open-Load Detection This read-only bit signals that the high side switch is conducting current below a certain threshold indicating possible load disconnection. 1 = HS1 Open Load detected (or thermal shutdown) 0 = Normal LSxOP - Low Side Switch Open-Load Detection This read-only bit signals that the low side switches are conducting current below a certain threshold indicating possible load disconnection. 1 = LSx Open Load detected (or thermal shutdown) 0 = Normal HS1CL - High Side Current Limitation This read-only bit indicates that the high side switch is operating in current limitation mode. 1 = HS1 in current limitation (or thermal shutdown) 0 = Normal LSxCL - Low Side Current Limitation This read-only bit indicates that the respective low side switch is operating in current limitation mode. 1 = LSx in current limitation (or thermal shutdown) 0 = Normal Low Side Control Register - LSCR This register controls the operation of the low side drivers. Writing the Low Side Control Register (LSCR) will also return the Low Side Status Register (LSSR). Table 21. Low Side Control Register - $8 C3 C2 C1 C0 Write PWMLS2 PWMLS1 LS2 LS1 Reset Value 0 0 0 0 Reset Condition POR Timing Control Register - TIMCR This register allows to configure the watchdog, the cyclic sense and Forced Wake-up periods. Writing to the Timing Control Register (TIMCR) will also return the Watchdog Status Register (WDSR). POR, Reset mode, ext_reset, LSx over-temp or (VSOV & HVSE) 33911 Analog Integrated Circuit Device Data Freescale Semiconductor 43 MC33911G5AC/MC3433911G5AC FUNCTIONAL DEVICE OPERATIONS LOGIC COMMANDS AND REGISTERS Table 25. Cyclic Sense and Force Wake-up Interval Table 23. Timing Control Register - $A CYSX8(67) CYST2 CYST1 CYST0 Interval X 0 0 0 No cyclic sense(68) 0 0 0 1 20 ms 0 0 1 0 40 ms 0 0 1 1 60 ms 0 1 0 0 80 ms 0 1 0 1 100 ms 0 1 1 0 120 ms CS/WD - Cyclic Sense or Watchdog prescaler select 0 1 1 1 140 ms This write-only bit selects which prescaler is being written to the Cyclic Sense/Forced Wake-up prescaler or the Watchdog prescaler. 1 = Cyclic Sense/Forced Wake-up Prescaler selected 0 = Watchdog Prescaler select 1 0 0 1 160 ms 1 0 1 0 320 ms 1 0 1 1 480 ms 1 1 0 0 640 ms 1 1 0 1 800 ms WDx - Watchdog Prescaler 1 1 1 0 960 ms 1 1 1 1 1120 ms C3 Write C2 C1 C0 WD2 WD1 WD0 CYST2 CYST1 CYST0 CS/WD Reset Value - Reset Condition 0 - 0 0 POR This write-only bits selects the divider for the watchdog prescaler and therefore selects the watchdog period in accordance with Table 24. This configuration is valid only if windowing watchdog is active. Notes 67. bit CYSX8 is located in Configuration Register (CFR) 68. No Cyclic Sense and no Force Wake up available. Table 24. Watchdog Prescaler Watchdog Status Register - WDSR This register returns the Watchdog status information and is also returned when writing to the TIMCR. WD2 WD1 WD0 Prescaler Divider 0 0 0 1 0 0 1 2 0 1 0 4 0 1 1 6 1 0 0 8 1 0 1 10 WDTO - Watchdog Timeout 1 1 0 12 1 1 1 14 This read-only bit signals the last reset was caused by either a watchdog timeout or by an attempt to clear the Watchdog within the window closed. Any access to this register or the Timing Control Register (TIMCR) will clear the WDTO bit. 1 = Last reset caused by watchdog timeout 0 = None CYSTx - Cyclic Sense Period Prescaler Select This write-only bits selects the interval for the wake-up cyclic sensing together with the bit CYSX8 in the Configuration Register (CFR) (see Configuration Register CFR on page 45). This option is only active if the high side switch is enabled when entering in Stop or Sleep mode. Otherwise a timed wake-up is performed after the period shown in Table 25. Table 26. Watchdog Status Register - $A/$B Read S3 S2 S1 S0 WDTO WDERR WDOFF WDWO WDERR - Watchdog Error This read-only bit signals the detection of a missing watchdog resistor. In this condition the watchdog is using the internal, lower precision timebase. The Windowing function is disabled. 1 = WDCONF pin resistor missing 0 = WDCONF pin resistor not floating 33911 44 Analog Integrated Circuit Device Data Freescale Semiconductor MC33911G5AC/MC3433911G5AC FUNCTIONAL DEVICE OPERATIONS LOGIC COMMANDS AND REGISTERS WDOFF - Watchdog Off Configuration Register - CFR This read-only bit signals that the watchdog pin connected to Ground and therefore disabled. In this case watchdog timeouts are disabled and the device automatically enters Normal mode out of Reset. This might be necessary for software debugging and for programming the Flash memory. 1 = Watchdog is disabled 0 = Watchdog is enabled WDWO - Watchdog Window Open This read-only bit signals when the watchdog window is open for clears. The purpose of this bit is for testing. Should be ignored in case WDERR is High. 1 = Watchdog window open 0 = Watchdog window closed Analog Multiplexer Control Register - MUXCR This register controls the analog multiplexer and selects the divider ration for the Lx input divider. Table 27. Analog Multiplexer Control Register -$C C3 C2 C1 C0 Write LXDS MX2 MX1 MX0 Reset Value 1 0 0 0 Reset Condition POR POR, Reset mode or ext_reset LXDS - Lx Analog Input Divider Select This write-only bit selects the resistor divider for the Lx analog inputs. Voltage is internally clamped to VDD. 0 = Lx Analog divider: 1 1 = Lx Analog divider: 3.6 (typ.) This register controls the cyclic sense timing multiplier. Table 29. Configuration Register - $D C3 C2 C1 C0 Write 0 CYSX8 0 0 Reset Value 0 0 0 0 Reset Condition POR, Reset mode or ext_reset POR POR POR CYSX8 - Cyclic Sense Timing x 8. This write-only bit influences the cyclic sense and Forced Wake-up period as shown in Table 25. 1 = Multiplier enabled 0 = None Interrupt Mask Register - IMR This register allows masking of some of the interrupt sources. No interrupt will be generated to the MCU and no flag will be set in the ISR register. The 5.0V Regulator overtemperature prewarning interrupt and Under-voltage (VSUV) interrupts can not be masked and will always cause an interrupt. Writing to the IMR will return the ISR. Table 30. Interrupt Mask Register - $E C3 C2 C1 C0 Write HSM LSM LINM VMM Reset Value 1 1 1 1 Reset Condition POR MXx - Analog Multiplexer Input Select These write-only bits selects which analog input is multiplexed to the ADOUT0 pin according to Table 28. When disabled or when in Stop or Sleep mode, the output buffer is not powered and the ADOUT0 output is left floating to achieve lower current consumption. Table 28. Analog Multiplexer Channel Select MX2 MX1 MX0 Meaning 0 0 0 Disabled 0 0 1 Reserved 0 1 0 Die Temperature Sensor 0 1 1 VSENSE input 1 0 0 L1 input 1 0 1 L2 input 1 1 0 Reserved 1 1 1 Reserved HSM - High Side Interrupt Mask This write-only bit enables/disables interrupts generated in the high side block. 1 = HS Interrupts Enabled 0 = HS Interrupts Disabled LSM - Low Side Interrupt Mask This write-only bit enables/disables interrupts generated in the low side block. 1 = LS Interrupts Enabled 0 = LS Interrupts Disabled LINM - LIN Interrupts Mask This write-only bit enables/disables interrupts generated in the LIN block. 1 = LIN Interrupts Enabled 0 = LIN Interrupts Disabled 33911 Analog Integrated Circuit Device Data Freescale Semiconductor 45 MC33911G5AC/MC3433911G5AC FUNCTIONAL DEVICE OPERATIONS LOGIC COMMANDS AND REGISTERS VMM - Voltage Monitor Interrupt Mask This register is also returned when writing to the Interrupt Mask Register (IMR). This write-only bit enables/disables interrupts generated in the Voltage Monitor block. The only maskable interrupt in the Voltage Monitor Block is the VSUP over-voltage interrupt. 1 = Interrupts Enabled 0 = Interrupts Disabled Table 31. Interrupt Source Register - $E/$F Read Interrupt Source Register - ISR S3 S2 S1 S0 ISR3 ISR2 ISR1 ISR0 ISRx - Interrupt Source Register This register allows the MCU to determine the source of the last interrupt or wake-up respectively. A read of the register acknowledges the interrupt and leads IRQ pin to high, in case there are no other pending interrupts. If there are pending interrupts, IRQ will be driven high for 10s and then be driven low again. These read-only bits indicate the interrupt source following Table 32. If no interrupt is pending then all bits are 0. In case more than one interrupt is pending, the interrupt sources are handled sequentially multiplex. Table 32. Interrupt Sources Interrupt Source ISR3 ISR2 ISR1 ISR0 Priority none maskable maskable no interrupt none highest 0 0 0 0 no interrupt 0 0 0 1 Lx Wake-up from Stop and Sleep mode - 0 0 1 0 - HS Interrupt (Over-temperature) 0 0 1 1 - LS Interrupt (Over-temperature) 0 1 0 0 LIN Wake-up LIN Interrupt (RXSHORT, TXDOM, LIN OT) 0 1 0 1 0 1 1 0 Voltage Monitor Interrupt Voltage Monitor Interrupt (Low Voltage and VDD over-temperature) (High Voltage) Forced Wake-up - lowest 33911 46 Analog Integrated Circuit Device Data Freescale Semiconductor MC33911G5AC/MC3433911G5AC TYPICAL APPLICATION TYPICAL APPLICATION The 33911 can be configured in several applications. The figure below shows the 33911 in the typical Slave Node Application. V BAT VS2 VS1 D1 C2 C1 C4 Interrupt Control Module LVI, HVI, HTI, OCI IRQ C3 Internal Bus VDD Voltage Regulator AGND VDD IRQ Reset Control Module LVR, HVR, HTR, WD, RST LS1 Low Side Control Module RST TIMER HB Type Relay PGND Window Watchdog Module PWMIN LS2 R1 Motor Output High Side Control Module HS1 MISO MOSI Chip Temp Sense Module SCLK Analog Multiplexer SPI & CONTROL SPI CS MCU VSENSE VBAT Sense Module L1 Analog Input Module A/D ADOUT0 L2 R2 R3 Wake Up Module Digital Input Module RXD LIN Physical Layer SCI LIN LIN TXD WDCONF LGND AGND PGND C5 Typical Component Values: C1 = 47 F; C2 = C4 = 100 nF; C3 = 10 F; C5 = 220 pF R1 = 10 k; R2 = R3 = 10 k; R4 = 20 k-200 k R4 Recommended Configuration of the not Connected Pins (NC): Pin 15, 16, 20, 21 = GND Pin 11, 30 = open (floating) Pin 24 = open (floating) or VS2 Pin 28 = this pin is not internally connected and may be used for PCB routing optimization. 33911 Analog Integrated Circuit Device Data Freescale Semiconductor 47 MC33911BAC / MC34911BAC MC33911BAC PRODUCT SPECIFICATIONS PAGES 48 TO 88 MC33911BAC PRODUCT SPECIFICATIONS PAGES 48 TO 88 33911 48 Analog Integrated Circuit Device Data Freescale Semiconductor MC33911BAC / MC34911BAC INTERNAL BLOCK DIAGRAM INTERNAL BLOCK DIAGRAM VS2 INTERRUPT CONTROL MODULE LVI, HVI, HTI, OCI VS1 INTERNAL BUS RST IRQ VDD AGND VOLTAGE REGULATOR RESET CONTROL MODULE LVR, HVR, HTR, WD LS1 LOW SIDE CONTROL MODULE WINDOW WATCHDOG MODULE LS2 PGND PWMIN VS2 HIGH SIDE CONTROL MODULE MISO SCLK SPI & CONTROL ANALOG MULTIPLEXER MOSI CS ADOUT0 WAKE-UP MODULE RXD TXD HS1 VBAT SENSE MODULE VSENSE CHIP TEMPERATURE SENSE MODULE ANALOG INPUT MODULE DIGITAL INPUT MODULE L1 L2 LIN PHYSICAL LAYER LIN LGND WDCONF Figure 25. 33911BAC Simplified Internal Block Diagram 33911 49 Analog Integrated Circuit Device Data Freescale Semiconductor MC33911BAC / MC34911BAC PIN CONNECTIONS AGND VDD NC* VSENSE NC VS1 VS2 HS1 32 31 30 29 28 27 26 25 PIN CONNECTIONS RXD 1 24 NC* TXD 2 23 L1 MISO 3 22 L2 MOSI 4 21 NC* SCLK 5 20 NC* CS 6 19 LS1 ADOUT0 7 18 PGND PWMIN 8 17 LS2 9 10 11 12 13 14 15 16 RST IRQ NC* WDCONF LIN LGND NC* NC* * Special Configuration Recommended / Mandatory for Marked NC Pins Figure 26. 33911 Pin Connections Table 33. 33911 Pin Definitions A functional description of each pin can be found in the Functional Pin Description section. Pin Pin Name Formal Name Definition 1 RXD Receiver Output This pin is the receiver output of the LIN interface which reports the state of the bus voltage to the MCU interface. 2 TXD Transmitter Input This pin is the transmitter input of the LIN interface which controls the state of the bus output. 3 MISO SPI Output SPI (Serial Peripheral Interface) data output. When CS is high, pin is in the high-impedance state. 4 MOSI SPI Input SPI (Serial Peripheral Interface) data input. 5 SCLK SPI Clock SPI (Serial Peripheral Interface) clock Input. 6 CS SPI Chip Select 7 ADOUT0 Analog Output Pin 0 8 PWMIN PWM Input 9 RST Internal Reset I/O Bidirectional reset I/O pin - driven low when any internal reset source is asserted. RST is active low. 10 IRQ Internal Interrupt Output Interrupt output pin, indicating wake-up events from Stop mode or events from Normal and Normal Request modes. IRQ is active low. SPI (Serial Peripheral Interface) chip select input pin. CS is active low. Analog Multiplexer Output. High side and low side pulse-width modulation input. 33911 Analog Integrated Circuit Device Data Freescale Semiconductor 50 MC33911BAC / MC34911BAC PIN CONNECTIONS Table 33. 33911 Pin Definitions A functional description of each pin can be found in the Functional Pin Description section. Pin Pin Name Formal Name 12 WDCONF Watchdog Configuration Pin 13 LIN LIN Bus 14 LGND LIN Ground Pin 17 LS2 19 LS1 18 PGND 22 L2 23 L1 25 HS1 26 VS2 27 VS1 29 Definition This input pin is for configuration of the watchdog period and allows the disabling of the watchdog. This pin represents the single-wire bus transmitter and receiver. This pin is the device LIN ground connection. It is internally connected to the PGND pin. Low Side Outputs Relay drivers low side outputs. Power Ground Pin This pin is the device low side ground connection. It is internally connected to the LGND pin. Wake-Up Inputs These pins are the wake-up capable digital inputs(69). In addition, all LX inputs can be sensed analog via the analog multiplexer. High Side Output High side switch output. Power Supply Pin These pins are device battery level power supply pins. VS2 is supplying the HS1 driver while VS1 supplies the remaining blocks.(70) VSENSE Voltage Sense Pin Battery voltage sense input. (71) 31 VDD Voltage Regulator Output +5.0V main voltage regulator output pin. (72) 32 AGND Analog Ground Pin This pin is the device analog ground connection. Notes 69. When used as a digital input, a series 33 k resistor must be used to protect against automotive transients. 70. Reverse battery protection series diodes must be used externally to protect the internal circuitry. 71. This pin can be connected directly to the battery line for voltage measurements. The pin is self-protected against reverse battery connections. It is strongly recommended to connect a 10 k resistor in series with this pin for protection purposes. 72. External capacitor (2.0 F < C < 100 F; 0.1 < ESR < 10 ) required. 33911 51 Analog Integrated Circuit Device Data Freescale Semiconductor MC33911BAC / MC34911BAC ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Table 34. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device. Ratings Symbol Value Unit Normal Operation (DC) VSUP(SS) -0.3 to 27 Transient Conditions (load dump) VSUP(PK) -0.3 to 40 VDD -0.3 to 5.5 VIN -0.3 to VDD +0.3 VIN(IRQ) -0.3 to 11 VHS1 - 0.3 to VSUP +0.3 V VLS -0.3 to 45 V Normal Operation with a series 33k resistor (DC) VLxDC -18 to 40 Transient input voltage with external component (according to ISO7637-2) (See Figure 28) VLxTR 100 VVSENSE -27 to 40 Normal Operation (DC) VBUSDC -18 to 40 Transient input voltage with external component (according to ISO7637-2) (See Figure ) VBUSTR -150 to 100 IVDD Internally Limited Human Body Model - LIN Pin(75) VESD1-1 8000 Human Body Model - all other Pins(75) VESD1-2 2000 VESD2 150 VESD3-1 750 VESD3-2 500 VNC Note 78 ELECTRICAL RATINGS Supply Voltage at VS1 and VS2 Supply Voltage at VDD Input / Output Pins Voltage V (73) CS, RST, SCLK, PWMIN, ADOUT0, MOSI, MISO, TXD, RXD V V Interrupt Pin (IRQ)(74) HS1 Pin Voltage (DC) LS1 and LS2 Pin Voltage (DC) L1 and L2 Pin Voltage VSENSE Pin Voltage (DC) V LIN Pin Voltage VDD output current V ESD Voltage Machine Model(76) Charge Device Model(77) Corner Pins (Pins 1, 8, 9, 16, 17, 24, 25 and 32) All other Pins (Pins 2-7, 10-15, 18-23, 26-31) NC Pin Voltage (NC pins 11, 15, 16, 20, 21, 24, 28 and 30)(78) V A V Notes 73. Exceeding voltage limits on specified pins may cause a malfunction or permanent damage to the device. 74. Extended voltage range for programming purpose only. 75. Testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 ), 76. Testing is performed in accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 ), 77. Testing is performed in accordance with the Charge Device Model, Robotic (CZAP = 4.0 pF). 78. Special configuration recommended / mandatory for marked NC pins. Please refer to the typical application shown on page 88. 33911 Analog Integrated Circuit Device Data Freescale Semiconductor 52 MC33911BAC / MC34911BAC ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Table 34. Maximum Ratings (continued) All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device. Ratings Symbol Value Unit THERMAL RATINGS Operating Ambient Temperature(79) C TA Operating Junction Temperature 33911 -40 to 125 34911 -40 to 85 TJ -40 to 150 C Storage Temperature TSTG -55 to 150 C Thermal Resistance, Junction to Ambient RJA Natural Convection, Single Layer board (1s)(80), (81) Natural Convection, Four Layer board (2s2p)(80), (82) (83) Thermal Resistance, Junction to Case Peak Package Reflow Temperature During Reflow(84), (85) C/W 85 56 RJC 23 C/W TPPRT Note 85 C Notes 79. The limiting factor is junction temperature; taking into account the power dissipation, thermal resistance, and heat sinking. 80. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 81. 82. 83. 84. Per JEDEC JESD51-2 with the single layer board (JESD51-3) horizontal. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. Freescale's Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics. 85. 33911 53 Analog Integrated Circuit Device Data Freescale Semiconductor MC33911BAC / MC34911BAC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 35. Static Electrical Characteristics Characteristics noted under conditions 5.5 V VSUP 18 V, -40C TA 125C for the 33911 and -40C TA 85C for the 34911, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions, unless otherwise noted. Characteristic Symbol Min Typ Max Unit VSUP 5.5 - 18 V Functional Operating Voltage(86) VSUPOP - - 27 V Load Dump VSUPLD - - 40 V IRUN - 4.5 10 mA - 48 80 - 58 90 - 27 35 - 37 48 ICYCLIC - 10 - VBATFAIL 1.5 3.0 3.9 VBATFAIL_HYS - 0.9 - VSUV 5.55 6.0 6.6 VSUV_HYS - 1.0 - VSOV 18 19.25 20.5 - 1.0 - SUPPLY VOLTAGE RANGE (VS1, VS2) Nominal Operating Voltage SUPPLY CURRENT RANGE (VSUP = 13.5 V) Normal Mode (IOUT at VDD = 10 mA), LIN Recessive State(87) Stop Mode, VDD ON with IOUT = 100 A, LIN Recessive State (87), (88), (89) ISTOP 5.5 V < VSUP < 12 V VSUP = 13.5 V Sleep Mode, VDD OFF, LIN Recessive State(87), (89) ISLEEP 5.5 V < VSUP < 12 V 12 V VSUP < 13.5 V Cyclic Sense Supply Current Adder(90) A A A SUPPLY UNDER/OVER VOLTAGE DETECTIONS Power-On Reset (BATFAIL)(91) Threshold (measured on VS1) V (90) Hysteresis (measured on VS1)(90) VSUP Under-voltage Detection (VSUV Flag) (Normal and Normal Request Modes, Interrupt Generated) Threshold (measured on VS1) Hysteresis (measured on VS1) V VSUP Over-voltage Detection (VSOV Flag) (Normal and Normal Request Modes, Interrupt Generated) Threshold (measured on VS1) Hysteresis (measured on VS1) VSOV_HYS V Notes 86. Device is fully functional. All features are operating. 87. Total current (IVS1 + IVS2) measured at GND pins excluding all loads, cyclic sense disabled. 88. Total IDD current (including loads) below 100 A. 89. Stop and Sleep modes current will increase if VSUP exceeds 13.5 V. 90. 91. This parameter is guaranteed by process monitoring but not production tested. The flag is set during power-up sequence. To clear the flag, a SPI read must be performed. 33911 Analog Integrated Circuit Device Data Freescale Semiconductor 54 MC33911BAC / MC34911BAC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 35. Static Electrical Characteristics (continued) Characteristics noted under conditions 5.5 V VSUP 18 V, -40C TA 125C for the 33911 and -40C TA 85C for the 34911, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions, unless otherwise noted. Characteristic (92) VOLTAGE REGULATOR Symbol Min Typ Max 4.75 5.00 5.25 60 110 200 - 0.1 0.25 Unit (VDD) Normal Mode Output Voltage VDDRUN 1.0 mA < IVDD < 50 mA; 5.5 V < VSUP < 27 V Normal Mode Output Current Limitation IVDDRUN Dropout Voltage(93) VDDDROP IVDD = 50 mA Stop Mode Output Voltage V V VDDSTOP IVDD < 5.0 mA mA V 4.75 5.0 5.25 IVDDSTOP 6.0 12 36 Normal Mode, 5.5 V < VSUP < 18 V; IVDD = 10 mA LRRUN - 20 25 Stop Mode, 5.5 V < VSUP < 18 V; IVDD = 1.0 mA LRSTOP - 5.0 25 Normal Mode, 1.0 mA < IVDD < 50 mA LDRUN - 15 80 Stop Mode, 0.1 mA < IVDD < 5.0 mA LDSTOP - 10 50 110 125 140 TPRE_HYS - 10 - C TSD 155 170 185 C TSD_HYS - 10 - C Stop Mode Output Current Limitation Line Regulation mV Load Regulation Over-temperature Prewarning mA mV (Junction)(94) TPRE Interrupt generated, Bit VDDOT Set Over-temperature Prewarning hysteresis(94) Over-temperature Shutdown Temperature (94) Over-temperature Shutdown hysteresis (Junction)(94) C Notes 92. Specification with external capacitor 2.0 F < C < 100 F and 100 m ESR 10 . 93. Measured when voltage has dropped 250 mV below its nominal Value (5.0 V). 94. This parameter is guaranteed by process monitoring but not production tested. 33911 55 Analog Integrated Circuit Device Data Freescale Semiconductor MC33911BAC / MC34911BAC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 35. Static Electrical Characteristics (continued) Characteristics noted under conditions 5.5 V VSUP 18 V, -40C TA 125C for the 33911 and -40C TA 85C for the 34911, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions, unless otherwise noted. Characteristic Symbol Min Typ Max Unit VRSTTH 4.3 4.5 4.7 V 0.0 - 0.9 -150 -250 -350 1.5 - 8.0 RST INPUT/OUTPUT PIN (RST) VDD Low-Voltage Reset Threshold Low-state Output Voltage VOL IOUT = 1.5 mA; 3.5 V VSUP 27 V High-state Output Current (0 < VOUT < 3.5 V) Pull-down Current Limitation (internally limited) IOH V IPD_MAX VOUT = VDD A mA Low-state Input Voltage VIL -0.3 - 0.3 x VDD V High-state Input Voltage VIH 0.7 x VDD - VDD +0.3 V 0.0 - 1.0 VDD -0.9 - VDD MISO SPI OUTPUT PIN (MISO) Low-state Output Voltage VOL IOUT = 1.5 mA High-state Output Voltage VOH IOUT = -250 A Tri-state Leakage Current V V ITRIMISO 0 V VMISO VDD A -10 - 10 SPI INPUT PINS (MOSI, SCLK, CS) Low-state Input Voltage VIL -0.3 - 0.3 x VDD V High-state Input Voltage VIH 0.7 x VDD - VDD +0.3 V MOSI, SCLK Input Current IIN 0 V VIN VDD CS Pull-up Current A -10 - 10 10 20 30 0.0 - 0.8 VDD -0.8 - VDD IPUCS 0 V < VIN < 3.5 V A INTERRUPT OUTPUT PIN (IRQ) Low-state Output Voltage VOL IOUT = 1.5 mA High-state Output Voltage VOH IOUT = -250 A Leakage Current V V VOH VDD VOUT 10 V mA - - 2.0 PULSE WIDTH MODULATION INPUT PIN (PWMIN) Low-state Input Voltage VIL -0.3 - 0.3 x VDD V High-state Input Voltage VIH 0.7 x VDD - VDD +0.3 V 10 20 30 Pull-up current 0 V < VIN < 3.5 V IPUPWMIN A 33911 Analog Integrated Circuit Device Data Freescale Semiconductor 56 MC33911BAC / MC34911BAC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 35. Static Electrical Characteristics (continued) Characteristics noted under conditions 5.5 V VSUP 18 V, -40C TA 125C for the 33911 and -40C TA 85C for the 34911, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions, unless otherwise noted. Characteristic Symbol Min Typ Max TJ = 25C, ILOAD = 50 mA; VSUP > 9.0 V - - 7.0 TJ = 150C, ILOAD = 50 mA; VSUP > 9.0 V(95) - - 10 TJ = 150C, ILOAD = 30 mA; 5.5 V < VSUP < 9.0 V(95) - - 14 Unit HIGH SIDE OUTPUT HS1 PIN (HS1) Output Drain-to-Source On resistance RDS(ON) Output Current Limitation(96) ILIMHS1 0 V < VOUT < VSUP - 2.0 V mA 60 120 250 - 5.0 7.5 - - 10 VSUP -2 - - THSSD 150 165 180 C THSSD_HYS - 10 - C TJ = 25C, ILOAD = 150 mA, VSUP > 9.0 V - - 2.5 TJ = 125C, ILOAD = 150 mA, VSUP > 9.0 V - - 4.5 - - 10 160 275 350 - 8.0 12 Open Load Current Detection (97) IOLHS1 Leakage Current ILEAK -0.2 V < VHS1 < VS2 + 0.2 V Short-circuit Detection Threshold(98) Over-temperature Shutdown(99), (104) Over-temperature Shutdown A VTHSC 5.5 V < VSUP < 27 V Hysteresis(104) mA V LOW SIDE OUTPUTS LS1 AND LS2 PINS (LS1, LS2) Output Drain-to-Source On resistance RDS(ON) TJ = 125C, ILOAD = 120 mA, 5.5 V < VSUP < 9.0 V Output Current Limitation (100) ILIMLSX 2.0 V < VOUT < VSUP Open Load Current Detection(101) IOLLSX Leakage Current ILEAK -0.2 V < VOUT < VS1 Active Output Energy Clamp mA A - - 10 VSUP +2 - VSUP +5 2.0 - - TLSSD 150 165 180 C TLSSD_HYS - 10 - C VCLAMP IOUT = 150 mA Short-circuit Detection Threshold(102) V VTHSC 5.5 V < VSUP < 27 V Over-temperature Shutdown(103), (104) (104) Over-temperature Shutdown Hysteresis mA V Notes 95. This parameter is production tested up to TA = 125C and guaranteed by process monitoring up to TJ = 150C. 96. 97. 98. 99. 100. 101. 102. 103. 104. When over-current occurs, the High Side stays ON with limited current capability and the HS1CL flag is set in the HSSR. When open Load occurs, the flag (HS1OP) is set in the HSSR. When short-circuit occurs and if the HVSE flag is enabled, HS1 automatically shut down. When over-temperature Shutdown occurs, the High Side is turned off. All flags in HSSR are set. When over-current occurs, the corresponding Low Side stays ON with limited current capability and the LSxCL flag is set in the LSSR. When open load occurs, the flag (LSxOP) is set in the LSSR. When short-circuit occurs and if the HVSE flag is enabled, both LS automatically shut down. When over-temperature shutdown occurs, both Low Sides are turned off. All flags in LSSR are set. Guaranteed by characterization but not production tested 33911 57 Analog Integrated Circuit Device Data Freescale Semiconductor MC33911BAC / MC34911BAC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 35. Static Electrical Characteristics (continued) Characteristics noted under conditions 5.5 V VSUP 18 V, -40C TA 125C for the 33911 and -40C TA 85C for the 34911, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions, unless otherwise noted. Characteristic Symbol Min Typ Max 2.0 2.5 3.0 3.0 3.5 4.0 0.5 1.0 1.5 -10 - 10 800 1550 - LXDS (Lx Divider Select) = 0 0.95 1.0 1.05 LXDS (Lx Divider Select) = 1 3.42 3.6 3.78 -80 0.0 80 -22 0.0 22 Unit L1 AND L2 INPUT PINS (L1, L2) Low Detection Threshold VTHL 5.5 V < VSUP < 27 V High Detection Threshold VTHH 5.5 V < VSUP < 27 V Hysteresis Analog Input Divider Ratio (RATIOLx = VLx / VADOUT0) Analog Output offset Ratio LXDS (Lx Divider Select) = 0 RLxIN A k RATIOLx VRATIOLxOFFSET LXDS (Lx Divider Select) = 1 Analog Inputs Matching V IIN -0.2 V < VIN < VS1 Analog Input Impedance(106) V VHYS 5.5 V < VSUP < 27 V Input Current(105) V mV LxMATCHING % LXDS (Lx Divider Select) = 0 96 100 104 LXDS (Lx Divider Select) = 1 96 100 104 REXT 20 - 200 k WDACC -15 - 15 % STTOV - 10.5 - mV/K 5.0 5.25 5.5 -30 - 30 -45 - 45 WINDOW WATCHDOG CONFIGURATION PIN (WDCONF) External Resistor Range Watchdog Period Accuracy with External Resistor (Excluding Resistor Accuracy)(107) ANALOG MULTIPLEXER Internal Chip Temperature Sense Gain VSENSE Input Divider Ratio (RATIOVSENSE = VVSENSE / VADOUT0) RATIOVSENSE 5.5 V < VSUP < 27 V VSENSE Output Related Offset OFFSETVSENSE -40C < TA < -20C mV ANALOG OUTPUT (ADOUT0) Maximum Output Voltage VOUT_MAX -5.0 mA < IO < 5.0 mA Minimum Output Voltage -5.0 mA < IO < 5.0 mA V VDD -0.35 - VDD 0.0 - 0.35 VOUT_MIN V Notes 105. Analog Multiplexer input disconnected from Lx input pin. 106. Analog Multiplexer input connected to Lx input pin. 107. Watchdog timing period calculation formula: tPWD [ms] = 0.466 * (REXT - 20) + 10 (REXT in k) 33911 Analog Integrated Circuit Device Data Freescale Semiconductor 58 MC33911BAC / MC34911BAC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 35. Static Electrical Characteristics (continued) Characteristics noted under conditions 5.5 V VSUP 18 V, -40C TA 125C for the 33911 and -40C TA 85C for the 34911, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions, unless otherwise noted. Characteristic Symbol Min Typ Max 0.0 - 0.8 VDD -0.8 - VDD Unit RXD OUTPUT PIN (LIN PHYSICAL LAYER) (RXD) Low-state Output Voltage VOL IOUT = 1.5 mA High-state Output Voltage VOH IOUT = -250 A V V TXD INPUT PIN (LIN PHYSICAL LAYER) (TXD) Low-state Input Voltage VIL -0.3 - 0.3 x VDD V High-state Input Voltage VIH 0.7 x VDD - VDD +0.3 V IPUIN 10 20 30 A 40 120 200 Pin Pull-up Current, 0 V < VIN < 3.5 V LIN PHYSICAL LAYER, TRANSCEIVER (LIN)(108) Output Current Limitation IBUSLIM Dominant State, VBUS = 18 V mA Leakage Output Current to GND Dominant State; VBUS = 0 V; VBAT = 12 V IBUS_PAS_DOM -1.0 - - mA Recessive State; 8.0 V < VBAT < 18 V; 8.0 V < VBUS < 18 V; VBUS VBAT IBUS_PAS_REC - - 20 A GND Disconnected; GNDDEVICE = VSUP; VBAT = 12 V; 0 V < VBUS < 18 V IBUS_NO_GND -1.0 - 1.0 mA IBUS - - 100 A VBAT Disconnected; VSUP_DEVICE = GND; 0 V < VBUS < 18 V Receiver Input Voltages VSUP Receiver Dominant State VBUSDOM - - Receiver Recessive State VBUSREC 0.6 - - Receiver Threshold Center (VTH_DOM + VTH_REC)/2 VBUS_CNT 0.475 0.5 0.525 Receiver Threshold Hysteresis (VTH_REC - VTH_DOM) VHYS - - 0.175 VLIN_REC VSUP-1 - - Dominant State, TXD LOW, 500 External Pull-up Resistor, LDVS = 0 VLIN_DOM_0 - 1.1 1.4 Dominant State, TXD LOW, 500 External Pull-up Resistor, LDVS = 1 VLIN_DOM_1 - 1.7 2 RSLAVE 20 30 60 k TLINSD 150 165 180 C TLINSD_HYS - 10 - C 0.4 LIN Transceiver Output Voltage Recessive State, TXD HIGH, IOUT = 1.0 A LIN Pull-up Resistor to VSUP Over-temperature Shutdown (109) Over-temperature Shutdown Hysteresis V Notes 108. Parameters guaranteed for 7.0 V VSUP 18 V. 109. When over-temperature shutdown occurs, the LIN bus goes into a recessive state and the flag LINOT in the LINSR is set. 33911 59 Analog Integrated Circuit Device Data Freescale Semiconductor MC33911BAC / MC34911BAC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 36. Dynamic Electrical Characteristics Characteristics noted under conditions 5.5 V VSUP 18 V, -40C TA 125C for the 33911 and -40C TA 85C for the 34911, otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions, unless otherwise noted. Characteristic Symbol Min Typ Max Unit SPI Operating Frequency f SPIOP - - 4.0 MHz SCLK Clock Period SPI INTERFACE TIMING (see Figure 36) tPSCLK 250 - N/A ns SCLK Clock High Time(110) tWSCLKH 110 - N/A ns SCLK Clock Low Time(110) tWSCLKL 110 - N/A ns Falling Edge of CS to Rising Edge of SCLK(110) tLEAD 100 - N/A ns Falling Edge of SCLK to CS Rising Edge(110) tLAG 100 - N/A ns MOSI to Falling Edge of SCLK(110) tSISU 40 - N/A ns Falling Edge of SCLK to MOSI(110) tSIH 40 - N/A ns MISO Rise Time(110) tRSO - 40 - CL = 220 pF MISO Fall Time(110) tFSO CL = 220 pF Time from Falling or Rising Edges of ns ns - 40 - CS to:(110) ns - MISO Low-impedance tSOEN 0.0 - 50 - MISO High -impedance tSODIS 0.0 - 50 Time from Rising Edge of SCLK to MISO Data Valid(110) tVALID 0.0 - 75 t RST 0.65 1.0 1.35 ms t RSTDF 350 600 900 ns 8.5 10 11.5 0.2 x VDD MISO 0.8 x VDD, CL = 100 pF ns RST OUTPUT PIN Reset Low-Level Duration after VDD High (see Figure 35) Reset Deglitch Filter Time WINDOW WATCHDOG CONFIGURATION PIN (WDCONF) Watchdog Time Period (111) External Resistor REXT = 20 k (1%) t PWD ms External Resistor REXT = 200 k (1%) 79 94 108 Without External Resistor REXT (WDCONF pin open) 110 150 205 Notes 110. This parameter is guaranteed by process monitoring but not production tested. 111. Watchdog timing period calculation formula: tPWD [ms] = 0.466 * (REXT - 20) + 10 (REXT in k) 33911 Analog Integrated Circuit Device Data Freescale Semiconductor 60 MC33911BAC / MC34911BAC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 36. Dynamic Electrical Characteristics (continued) Characteristics noted under conditions 5.5 V VSUP 18 V, -40C TA 125C for the 33911 and -40C TA 85C for the 34911, otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions, unless otherwise noted. Characteristic Symbol Min Typ Max Unit t WUF 8.0 20 38 s - - 5.0 110 150 205 - - 10 L1 AND L2 INPUTS Wake-up Filter Time STATE MACHINE TIMING Delay Between CS LOW-to-HIGH Transition (at the End of a SPI Stop Command) and Stop Mode Activation(112) Normal Request Mode Timeout (see Figure 35) Delay Between SPI Command and HS /LS Turn On(113) t NR TOUT Delay Between Normal Request and Normal Mode After a Watchdog Trigger Command (Normal Request Mode)(112) s t S-OFF 9.0 V < VSUP < 27 V - - 10 - - 10 s t SNR2N Delay Between CS Wake-Up (CS LOW to HIGH) in Stop Mode and: s Normal Request Mode, VDD ON and RST HIGH t WUCS 9.0 15 80 First Accepted SPI Command t WUSPI 90 -- N/A t 2CS 4.0 -- -- Minimum Time Between Rising and Falling Edge on the CS ms s t S-ON 9.0 V < VSUP < 27 V Delay Between SPI Command and HS /LS Turn Off(113) s t STOP s LIN PHYSICAL LAYER: DRIVER CHARACTERISTICS FOR NORMAL SLEW RATE - 20.0 KBIT/SEC(114), (115) Duty Cycle 1: D1 = tBUS_REC(MIN)/(2 x tBIT), tBIT = 50 s D1 7.0 V VSUP 18 V Duty Cycle 2: D2 = tBUS_REC(MAX)/(2 x tBIT), tBIT = 50 s LIN PHYSICAL LAYER: DRIVER CHARACTERISTICS FOR SLOW SLEW RATE - 10.4 7.6 V VSUP 18 V -- -- -- 0.581 KBIT/SEC(114), (116) s D3 7.0 V VSUP 18 V Duty Cycle 4: D4 = tBUS_REC(MAX)/(2 x tBIT), tBIT = 96 s -- D2 7.6 V VSUP 18 V Duty Cycle 3: D3 = tBUS_REC(MIN)/(2 x tBIT), tBIT = 96 s 0.396 0.417 -- -- -- -- 0.590 s D4 Notes 112. This parameter is guaranteed by process monitoring but not production tested. 113. Delay between turn on or off command (rising edge on CS) and HS or LS ON or OFF, excluding rise or fall time due to an external load. 114. Bus load RBUS and CBUS 1.0 nF / 1.0 k, 6.8nF / 660 , 10 nF / 500 . Measurement thresholds: 50% of TXD signal to LIN signal threshold defined at each parameter. See Figure 29. 115. See Figure 30. 116. See Figure 31. 33911 61 Analog Integrated Circuit Device Data Freescale Semiconductor MC33911BAC / MC34911BAC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 36. Dynamic Electrical Characteristics (continued) Characteristics noted under conditions 5.5 V VSUP 18 V, -40C TA 125C for the 33911 and -40C TA 85C for the 34911, otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions, unless otherwise noted. Characteristic Symbol Min Typ Max Unit SRFAST -- 20 -- V / s t REC_PD -- 3.0 6.0 t REC_SYM - 2.0 -- 2.0 t PROPWL 42 70 95 t WAKE -- -- 1500 t WAKE 9.0 13 17 t TXDDOM 0.65 1.0 1.35 LIN PHYSICAL LAYER: DRIVER CHARACTERISTICS FOR FAST SLEW RATE LIN Fast Slew Rate (Programming Mode) LIN PHYSICAL LAYER: CHARACTERISTICS AND WAKE-UP TIMINGS (117) Propagation Delay and Symmetry(118) s Propagation Delay Receiver, tREC_PD = max (tREC_PDR, tREC_PDF) Symmetry of Receiver Propagation Delay tREC_PDF - tREC_PDR Bus Wake-up Deglitcher (Sleep and Stop Modes)(119) Bus Wake-up Event Reported From Sleep Mode (120) From Stop Mode(121) TXD Permanent Dominant State Delay s s s PULSE WIDTH MODULATION INPUT PIN (PWMIN) PWMIN pin(122) fPWMIN Max. frequency to drive HS and LS output pins kHz 10 Notes 117. VSUP from 7.0 V to 18 V, bus load RBUS and CBUS 1.0 nF / 1.0 k, 6.8 nF / 660 , 10 nF / 500 . Measurement thresholds: 50% of TXD signal to LIN signal threshold defined at each parameter. See Figure 29. 118. See Figure 32. 119. See Figure 33 for Sleep and Figure 34 for Stop mode. 120. The measurement is done with 1.0 F capacitor and 0 mA current load on VDD. The value takes into account the delay to charge the capacitor. The delay is measured between the bus wake-up threshold (VBUSWU) rising edge of the LIN bus and when VDD reaches 3.0V. See Figure 33. The delay depends of the load and capacitor on VDD. 121. In Stop mode, the delay is measured between the bus wake-up threshold (VBUSWU) and the falling edge of the IRQ pin. See Figure 34. 122. This parameter is guaranteed by process monitoring but not production tested. 33911 Analog Integrated Circuit Device Data Freescale Semiconductor 62 MC33911BAC / MC34911BAC ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS TIMING DIAGRAMS 33911 1.0nF LIN TRANSIENT PULSE GENERATOR (NOTE) GND PGND LGND AGND Note Waveform per ISO 7637-2. Test Pulses 1, 2, 3a, 3b. Figure 27. Test Circuit for Transient Test Pulses (LIN) 33911 1.0nF L1, L2 10k PGND LGND TRANSIENT PULSE GENERATOR (NOTE) GND AGND NOTE: Waveform per ISO 7637-2. Test Pulses 1, 2, 3a, 3b. Figure 28. Test Circuit for Transient Test Pulses (Lx) VSUP TXD LIN R0 RXD C0 R0 AND C0 COMBINATIONS: * 1.0 K and 1.0 nF * 660 and 6.8 nF * 500 and 10 nF Figure 29. Test Circuit for LIN Timing Measurements 33911 63 Analog Integrated Circuit Device Data Freescale Semiconductor MC33911BAC / MC34911BAC ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS TXD tBIT tBIT tBUS_DOM (MAX) VLIN_REC tREC - MAX tDOM - MIN 74.4% VSUP tDOM - MIN 58.1% VSUP 40.0% VSUP LIN tBUS_REC (MIN) 60.0% VSUP 58.1% VSUP 40.0% VSUP 28.4% VSUP 28.4% VSUP 42.2% VSUP tREC - MIN tDOM - MAX tBUS_DOM (MIN) tBUS_REC (MAX) RXD tRDOM tRREC Figure 30. LIN Timing Measurements for Normal Slew Rate TXD tBIT tBIT tBUS_DOM (MAX) VLIN_REC tBUS_REC (MIN) tREC - MAX tDOM - MIN 61.6% VSUP 40.0% VSUP LIN tDOM - MIN 77.8% VSUP 60.0% VSUP 61.6% VSUP 40.0% VSUP 25.1% VSUP 25.1% VSUP 38.9% VSUP tREC - MIN tDOM - MAX tBUS_DOM (MIN) tBUS_REC (MAX) RXD tRDOM tRREC Figure 31. LIN Timing Measurements for Slow Slew Rate 33911 Analog Integrated Circuit Device Data Freescale Semiconductor 64 MC33911BAC / MC34911BAC ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS VLIN_REC VBUSrec VBUSdom VSUP LIN BUS SIGNAL RXD tRX_PDF tRX_PDR Figure 32. LIN Receiver Timing VLIN_REC LIN 0.4 VSUP DOMINANT LEVEL VDD tPROPWL tWAKE Figure 33. LIN Wake-up Sleep Mode Timing Vrec VLIN_REC LIN 0.4VSUP 0.4 VSUP Dominant Level Dominant level IRQ t PROPWL TpropWL t WAKE Twake Figure 34. LIN Wake-up Stop Mode Timing 33911 65 Analog Integrated Circuit Device Data Freescale Semiconductor MC33911BAC / MC34911BAC ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS VSUP VDD RST tNRTOUT tRST Figure 35. Power On Reset and Normal Request Timeout Timing tPSCLK CS tWSCLKH tLEAD tLAG SCLK tWSCLKL tSISU MOSI UNDEFINED D0 tSIH DON'T CARE D7 DON'T CARE tVALID tSODIS tSOEN MISO D0 DON'T CARE D7 Figure 36. SPI Timing Characteristics 33911 Analog Integrated Circuit Device Data Freescale Semiconductor 66 MC33911BAC / MC34911BAC FUNCTIONAL DESCRIPTION INTRODUCTION FUNCTIONAL DESCRIPTION INTRODUCTION The 33911 was designed and developed as a highly integrated and cost-effective solution for automotive and industrial applications. For automotive body electronics, the 33911 is well suited to perform relay control in applications like window lift, sunroof, etc. via a LIN bus. Power switches are provided on the device configured as high side and low side outputs. Other ports are also provided, which include a voltage sense port and two wake-up capable pins. An internal voltage regulator provides power to a MCU device. Also included in this device is a LIN physical layer, which communicates using a single wire. This enables this device to be compatible with 3-wire bus systems, where one wire is used for communication, one for battery, and one for ground. FUNCTIONAL PIN DESCRIPTION See Figure 1, 33911 Simplified Application Diagram, for a graphic representation of the various pins referred to in the following paragraphs. Also, see the 33911 Pin Connections diagram for a description of the pin locations in the package. RECEIVER OUTPUT (RXD) The RXD pin is a digital output. It is the receiver output of the LIN interface and reports the state of the bus voltage: RXD Low when LIN bus is dominant, RXD High when LIN bus is recessive. TRANSMITTER INPUT (TXD) The TXD pin is a digital input. It is the transmitter input of the LIN interface and controls the state of the bus output (dominant when TXD is Low, recessive when TXD is High). This pin has an internal pull-up to force recessive state in case the input is left floating. LIN BUS (LIN) The LIN pin represents the single-wire bus transmitter and receiver. It is suited for automotive bus systems and is compliant to the LIN bus specification 2.0. The LIN interface is only active during Normal and Normal Request modes. SERIAL DATA CLOCK (SCLK) The SCLK pin is the SPI clock input pin. MISO data changes on the negative transition of the SCLK. MOSI is sampled on the positive edge of the SCLK. MASTER OUT SLAVE IN (MOSI) The MOSI digital pin receives SPI data from the MCU. This data input is sampled on the positive edge of SCLK. MASTER IN SLAVE OUT (MISO) The MISO pin sends data to a SPI-enabled MCU. It is a digital tri-state output used to shift serial data to the microcontroller. Data on this output pin changes on the negative edge of the SCLK. When CS is High, this pin will remain in high-impedance state. CHIP SELECT (CS) CS is an active low digital input. It must remain low during a valid SPI communication and allow for several devices to be connected in the same SPI bus without contention. A rising edge on CS signals the end of the transmission and the moment the data shifted in is latched. A valid transmission must consist of 8 bits only. While in STOP mode a low-to-high level transition on this pin will generate a wake-up condition. ANALOG MULTIPLEXER (ADOUT0) The ADOUT0 pin can be configured via the SPI to allow the MCU A/D converter to read the several inputs of the Analog Multiplexer, including the VSENSE, L1, L2 input voltages and the internal junction temperature. PWM INPUT CONTROL (PWMIN) This digital input can control the high side and low side drivers in Normal Request and Normal mode. To enable PWM control, the MCU must perform a write operation to the High Side Control Register (HSCR), or the Low Side Control Register (LSCR). This pin has an internal 20 A current pull-up. RESET (RST) This bidirectional pin is used to reset the MCU in case the 33911 detects a reset condition, or to inform the 33911 that the MCU was just reset. After release of the RST pin Normal Request mode is entered. The RST pin is an active low filtered input and output formed by a weak pull-up and a switchable pull-down structure, which allows this pin to be shorted either to VDD or to GND during software development without the risk of destroying the driver. INTERRUPT (IRQ) The IRQ pin is a digital output used to signal events or faults to the MCU while in Normal and Normal Request mode or to signal a wake-up from Stop mode. This active low output 33911 67 Analog Integrated Circuit Device Data Freescale Semiconductor MC33911BAC / MC34911BAC FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION will transition high only after the interrupt is acknowledged by a SPI read of the respective status bits. WATCHDOG CONFIGURATION (WDCONF) The WDCONF pin is the configuration pin for the internal watchdog. A resistor can be connected to this pin to configure the window watchdog period. When connected directly to ground, the watchdog will be disabled. When this pin is left open, the watchdog period is fixed to its lower precision internal default value (150 ms, typical). GROUND CONNECTIONS (AGND, PGND, LGND) The AGND, PGND and LGND pins are the Analog and Power ground pins. The AGND pin is the ground reference of the voltage regulator. The PGND and LGND pins are used for high-current load return as in the relay-drivers and LIN interface pin. Note: PGND, AGND and LGND pins must be connected together. LOW SIDES (LS1 AND LS2) LS1 and LS2 are the low side driver outputs. Those outputs are short-circuit protected and include active clamp circuitry to drive inductive loads. Due to the energy clamp voltage on this pin, it can raise above the battery level when switched off. The switches are controlled through the SPI and can be configured to respond to a signal applied to the PWMIN input pin. Both low side switches are protected against overheating. DIGITAL/ANALOGS (L1 AND L2) The Lx pins are multi purpose inputs. They can be used as digital inputs, which can be sampled by reading the SPI and used for wake-up when 33911 is in low-power mode or used as analog inputs for the analog multiplexer. When used to sense voltage outside the module, a 33kohm series resistor must be used on each input. When used as wake-up inputs L1 and L2 can be configured to operate in cyclic sense mode. In this mode, the high side switch is configured to be periodically turned on and sample the wake-up inputs. If a state change is detected between two cycles, a wake-up is initiated. The 33911 can also wake-up from Stop or Sleep by a simple state change on L1 and L2. When used as an analog input, the voltage present on the Lx pins are scaled down by a selectable internal voltage divider and can be routed to the ADOUT0 output through the analog multiplexer. Note: If an Lx input is selected in the analog multiplexer, it will be disabled as a digital input and remains disabled in lowpower mode. No wake-up feature is available in that condition. When an Lx input is not selected in the analog multiplexer, the voltage divider is disconnected from that input. HIGH SIDE OUTPUT (HS1) This high side switch is able to drive loads such as relays or lamps. Its structure is connected to the VS2 supply pin. The pin is short-circuit protected and also protected against overheating. HS1 is controlled by SPI and can respond to a signal applied to the PWMIN input pin. The HS1 output can also be used during low-power mode for the cyclic-sense of the wake inputs. POWER SUPPLIES (VS1 AND VS2) These are the battery level voltage supply pins. In application, VS1 and VS2 pins must be protected against a reverse battery connection and negative transient voltages with external components. These pins sustain standard automotive voltage conditions such as a load dump at 40V. The high side switch (HS1) is supplied by the VS2 pin, all other internal blocks are supplied by the VS1 pin. VOLTAGE SENSE (VSENSE) This input can be connected directly to the battery line. It is protected against a battery reverse connection. The voltage present on this input is scaled down by an internal voltage divider, and can be routed to the ADOUT0 output pin and used by the MCU to read the battery voltage. The ESD structure on this pin allows for excursion up to +40 V and down to -27 V, allowing this pin to be connected directly to the battery line. It is strongly recommended to connect a 10kohm resistor in series with this pin for protection purposes. +5.0 V MAIN REGULATOR OUTPUT (VDD) An external capacitor must be placed on the VDD pin to stabilize the regulated output voltage. The VDD pin is intended to supply a microcontroller. The pin is current limited against shorts to GND and over-temperature protected. During Stop mode, the voltage regulator does not operate with its full drive capabilities and the output current is limited. During Sleep mode the regulator output is completely shut down. 33911 Analog Integrated Circuit Device Data Freescale Semiconductor 68 MC33911BAC / MC34911BAC FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION MC33911 - Functional Block Diagram Window Watchdog Digital / Analog Input High Side Drivers HS1 WakeUp Voltage & Temperature Sense Low Side Driver LS1 - LS2 SPI Interface Reset & IRQ Logic Voltage Regulator VDD LS/HS - PMW Control LIN Interface / Control LIN Physical Layer Interface LIN Analog Output 0 Analog Circutry MCU Interface and Output Control Drivers Figure 37. Functional Internal Block Diagram ANALOG CIRCUITRY MCU INTERFACE The 33911 is designed to operate under automotive operating conditions. A fully configurable window watchdog circuit will reset the connected MCU in case of an overflow. Two low-power modes are available with several different wake-up sources to reactivate the device. Two analog / digital inputs can be sensed or used as the wake-up source. The device is capable of sensing the supply voltage (VSENSE), the internal chip temperature (CTEMP) as well as the motor current using an external sense resistor.) The 33911 is providing its control and status information through a standard 8-Bit SPI interface. Critical system events such as low or high-voltage/temperature conditions as well as over-current conditions in any of the driver stages can be reported to the connected MCU via IRQ or RST. Both low side and both high side driver outputs can be controlled via the SPI register as well as PWMIN input. The integrated LIN physical layer interface can be configured via the SPI register and its communication is driven through the RXD and TXD device pin. All internal analog sources are multiplexed to the ANOUT0 pin. HIGH SIDE DRIVER One current and temperature protected high side driver with PWM capability is provided to drive small loads such as status LED's or small lamps. The driver can be configured for periodic sense during lowpower modes. LOW SIDE DRIVERS Two current and temperature protected low side drivers with PWM capability are provided to drive H-Bridge type relays for power motor applications. VOLTAGE REGULATOR OUTPUTS One voltage regulators is implemented on the 33911. The VDD main regulator output is designed to supply an MCU with a precise 5.0 V. LIN PHYSICAL LAYER INTERFACE The 33911 provides a LIN 2.0 compatible LIN physical layer interface with selectable slew rate and various diagnostic features. 33911 69 Analog Integrated Circuit Device Data Freescale Semiconductor MC33911BAC / MC34911BAC FUNCTIONAL DEVICE OPERATIONS OPERATIONAL MODES FUNCTIONAL DEVICE OPERATIONS OPERATIONAL MODES INTRODUCTION The 33911 offers three main operating modes: Normal (Run), Stop, and Sleep (Low-power). In Normal mode, the device is active and operating under normal application conditions. The Stop and Sleep modes are low-power modes with wake-up capabilities. In Stop mode, the voltage regulator still supplies the MCU with VDD (limited current capability), and in Sleep mode the voltage regulator is turned off (VDD = 0 V). Wake-up from Stop mode is initiated by a wake-up interrupt. Wake-up from Sleep mode is done by a reset and the voltage regulator is turned back on. The selection of the different modes is controlled by the MOD1:2 bits in the Mode Control Register (MCR). Figure 38 describes how transitions are done between the different operating modes, and Table 37, gives an overview of the operating modes. RESET MODE The 33911 enters the Reset mode after a power up. In this mode, the RST pin is low for 1.0 ms (typical value). After this delay, the 33911 enters the Normal Request mode and the RST pin is driven high. The Reset mode is entered if a reset condition occurs (VDD low, Watchdog trigger fail, after a wake-up from Sleep mode, or a Normal Request mode timeout). NORMAL REQUEST MODE This is a temporary mode automatically accessed by the device after the Reset mode, or after a wake-up from Stop mode. In Normal Request mode, the VDD regulator is ON, the Reset pin is high and the LIN is operating in RX Only mode. As soon as the device enters the Normal Request mode, an internal timer is started for 150 ms (typical value). During these 150 ms, the MCU must configure the Timing Control Register (TIMCR) and the MCR with MOD2 and MOD1 bits set = 0, to enter in Normal mode. If within the 150 ms timeout the MCU does not command the 33911 to Normal mode, it will enter in Reset mode. If the WDCONF pin is grounded in order to disable the watchdog function, the 33911 goes directly in Normal mode after the Reset mode. If the WDCONF pin is open, the 33911 stays typically for 150 ms in Normal Request before entering in Normal mode. The VDD regulator is ON and delivers its full current capability. If an external resistor is connected between the WDCONF pin and the Ground, the window watchdog function will be enabled. The wake-up inputs (L1 and L2) can be read as digital inputs or have its voltage routed through the analog multiplexer. The LIN interface has slew rate and timing compatible with the LIN protocol specification 2.0. The LIN bus can transmit and receive information. The high side and the low side switches are active and have PWM capability according to the SPI configuration. The interrupts are generated to report failures for VSUP over/under-voltage, thermal shutdown or thermal shutdown prewarning on the main regulator. SLEEP MODE The Sleep mode is a low-power mode. From Normal mode, the device enters the Sleep mode by sending one SPI command through the MCR. All blocks are in their lowest power consumption condition. Only some wake-up sources (wake-up inputs with or without cyclic sense, forced wake-up, and LIN receiver) are active. The 5.0 V regulator is OFF. The internal low-power oscillator may be active if the IC is configured for cyclic sense. In this condition, the high side switches are turned on periodically and the wake-up inputs are sampled. Wake-up from Sleep mode is similar to a power-up. The device goes into Reset mode except that the SPI will report the wake-up source, and the BATFAIL flag is not set. STOP MODE The Stop mode is the second low-power mode, but in this case the 5.0 V regulator is ON with limited current drive capability. The application MCU is always supplied while the 33911 is operating in Stop mode. The device can enter the Stop mode only by sending a SPI command. When the application is in this mode, it can wakeup from the 33911 side (for example: cyclic sense, force wake-up, LIN bus, wake inputs) or the MCU side (CS, RST pins). Wake-up from Stop mode will transition the 33911 to Normal Request mode and generate an interrupt, except if the wake-up event is a low to high transition on the CS pin or comes from the RST pin. NORMAL MODE In Normal mode, all 33911 functions are active and can be controlled by the SPI interface and the PWMIN pin. 33911 Analog Integrated Circuit Device Data Freescale Semiconductor 70 MC33911BAC / MC34911BAC FUNCTIONAL DEVICE OPERATIONS OPERATIONAL MODES Normal Request Timeout Expired (t NRTOUT) VDD LOW NORMAL REQUEST VDD LOW VDD LOW (>t NRTOUT) EXPIRED AND VSUV = 0 SLEEP COMMAND STOP COMMAND NORMAL WD FAILED WAKE-UP (INTERRUPT) RESET VDD HIGH AND RESET DELAY (t RST) EXPIRED WD DISABLED Power Up WD TRIGGER POWER DOWN WAKE-UP (RESET) SLEEP STOP VDD LOW Legend WD: Watchdog WD Disabled: Watchdog disabled (WDCONF pin connected to GND) WD Trigger: Watchdog is triggered by SPI command WD Failed: No watchdog trigger or trigger occurs in closed window Stop Command: Stop command sent via SPI Sleep Command: Sleep command sent via SPI wake-up from Stop mode: Lx state change, LIN bus wake-up, Periodic wake-up, CS rising edge wake-up or RST wake-up. wake-up from Sleep mode: Lx state change, LIN bus wake-up, Periodic wake-up. Figure 38. Operating Modes and Transitions 33911 71 Analog Integrated Circuit Device Data Freescale Semiconductor MC33911BAC / MC34911BAC FUNCTIONAL DEVICE OPERATIONS OPERATIONAL MODES Table 37. Operating Modes Overview Function Reset Mode Normal Request Mode Normal Mode Stop Mode VDD Full Full Full Stop - LSx - SPI/PWM(123) SPI/PWM - - HS1 - SPI/PWM(123) SPI/PWM Note(124) Note(125) Analog Mux - SPI SPI - - Lx - Inputs Inputs Wake-up Wake-up LIN - Rx-Only full/Rx-Only Rx-Only/Wake-up Wake-up Watchdog - 150 ms (typ.) timeout On(126)/Off - - VSENSE On On On VDD - Notes 123. 124. 125. 126. Sleep Mode Operation can be controlled by the PWMIN input. HS switch can be configured for cyclic sense operation in Stop mode. HS switch can be configured for cyclic sense operation in Sleep mode. Windowing operation when enabled by an external resistor. INTERRUPTS High-voltage Interrupt Interrupts are used to signal a microcontroller that a peripheral needs to be serviced. The interrupts which can be generated change according to the operating mode. While in Normal and Normal Request modes, the 33911 signals through interrupts special conditions which may require a MCU software action. Interrupts are not generated until all pending wake-up sources are read in the Interrupt Source Register (ISR). While in Stop mode, interrupts are used to signal wake-up events. Sleep mode does not use interrupts, wake-up is performed by powering-up the MCU. In Normal and Normal Request mode the wake-up source can be read by the SPI. The interrupts are signaled to the MCU by a low logic level of the IRQ pin, which will remain low until the interrupt is acknowledged by a SPI read. The IRQ pin will then be driven high. Interrupts are only asserted while in Normal, Normal Request and Stop mode. Interrupts are not generated while the RST pin is low. Following is a list of the interrupt sources in Normal and Normal Request modes, some of those can be masked by writing to the SPI-Interrupt Mask Register (IMR). The high-voltage interrupt signals when the supply line (VS1) voltage increases above the VSOV threshold (VSOV). Low-voltage Interrupt The low-voltage interrupt signals when the supply line (VS1) voltage drops below the VSUV threshold (VSUV). Over-temperature Prewarning Over-temperature prewarning signals when the 33911 temperature has reached the pre-shutdown warning threshold. It is used to warn the MCU that an overtemperature shutdown in the main 5.0 V regulator is imminent. LIN Over-current Shutdown / Over-temperature Shutdown / TXD Stuck At Dominant / RXD Short-Circuit These signal fault conditions within the LIN interface will cause the LIN driver to be disabled, except for the LIN overcurrent. In order to restart an operation, the fault must be removed and must be acknowledged by reading the SPI. The LINOC bit functionality in the LIN Status Register (LINSR) is to indicate that an LIN over-current occurred and the driver stays enabled. High Side Over-temperature Shutdown The high side over-temperature shutdown signals a shutdown in the high side output. Low Side Over-temperature Shutdown The low side over-temperature shutdown signals a shutdown in the low side outputs. 33911 Analog Integrated Circuit Device Data Freescale Semiconductor 72 MC33911BAC / MC34911BAC FUNCTIONAL DEVICE OPERATIONS OPERATIONAL MODES RESET To reset an MCU, the 33911 drives the RST pin low for the time the reset condition lasts. After the reset source has been removed, the state machine will drive the RST output low for at least 1ms (typical value) before driving it high. In the 33911 four main reset sources exist: 5.0 V Regulator Low-voltage-Reset (VRSTTH) The 5.0 V regulator output VDD is continuously monitored against brown outs. If the supply monitor detects that the voltage at the VDD pin has dropped below the reset threshold VRSTTH the 33911 will issue a reset. In case of an overtemperature, the voltage regulator will be disabled and the voltage monitoring will issue a VDDOT Flag independently of the VDD voltage. In order to select and activate direct wake-up from Lx inputs, the Wake-up Control Register (WUCR) must be configured with appropriate LxWE inputs enabled or disabled. The wake-up inputs state are read through the Wake-up Status Register (WUSR). Lx inputs are also used to perform cyclic sense wake-up. Note: Selecting an Lx input in the analog multiplexer before entering low-power mode will disable the wake-up capability of the Lx input. Wake-up from Wake-up inputs (L1-L2) with cyclic sense timer enabled During Sleep mode, the 5.0 V regulator is not active. Hence, all wake-up requests from Sleep mode require a power-up/reset sequence. The SBCLIN can wake-up at the end of a cyclic sense period if on one of the two wake-up input lines (L1-L2), a state change occurs. The HS1 switch is activated in Sleep or Stop modes from an internal timer. Cyclic sense and force wakeup are exclusive. If cyclic sense is enabled, the force wakeup can not be enabled. In order to select and activate the cyclic sense wake-up from Lx inputs, before entering in low-power modes (Stop or Sleep modes), the following SPI set-up has to be performed: * In WUCR: select the Lx input to WU-enable. * In HSCR: enable HS1. * In TIMCR: select the CS/WD bit and determine the cyclic sense period with CYSTx bits. * Perform Go to Sleep/Stop command. External Reset Forced Wake-up The 33911 has a bidirectional reset pin which drives the device to a safe state (same as Reset mode) for as long as this pin is held low. The RST pin must be held low long enough to pass the internal glitch filter and get recognized by the internal reset circuit. This functionality is also active in Stop mode. After the RST pin is released, there is no extra t RST to be considered. The 33911 can wake-up automatically after a predetermined time spent in Sleep or Stop mode. Cyclic sense and forced wake-up are exclusive. If forced wake-up is enabled, the cyclic sense can not be enabled. To determine the wake-up period, the following SPI set-up has to be sent before entering in low-power modes: * In TIMCR: select the CS/WD bit and determine the lowpower mode period with CYSTx bits. * In HSCR: the HS1 bit must be disabled. Window Watchdog Overflow If the watchdog counter is not properly serviced while its window is open, the 33911 will detect an MCU software runaway and will reset the microcontroller. Wake-Up From Sleep Mode WAKE-UP CAPABILITIES Once entered into one of the low-power modes (Sleep or Stop) only wake-up sources can bring the device into Normal mode operation. In Stop mode, a wake-up is signaled to the MCU as an interrupt, while in Sleep mode, the wake-up is performed by activating the 5.0 V regulator and resetting the MCU. In both cases, the MCU can detect the wake-up source by accessing the SPI registers. There is no specific SPI register bit to signal a CS wake-up or external reset. If necessary, this condition is detected by excluding all other possible wake-up sources. Wake-up from Wake-up inputs (L1-L2) with cyclic sense disabled CS Wake-up While in Stop mode, a rising edge on the CS will cause a wake-up. The CS wake-up does not generate an interrupt and is not reported on the SPI. LIN Wake-up While in the low-power mode the 33911 monitors the activity on the LIN bus. A dominant pulse larger than t PROPWL followed by a dominant to recessive transition will cause a LIN wake-up. This behavior protects the system from a shortto ground bus condition. The wake-up lines are dedicated to sense state changes of external switches, and wake-up the MCU (in Sleep or Stop mode). 33911 73 Analog Integrated Circuit Device Data Freescale Semiconductor MC33911BAC / MC34911BAC FUNCTIONAL DEVICE OPERATIONS OPERATIONAL MODES RST Wake-up While in Stop mode, the 33911 can wake-up when the RST pin is held low long enough to pass the internal glitch filter. Then, it will change to Normal Request or Normal modes depending on the WDCONF pin configuration. The RST wake-up does not generate an interrupt and is not reported via the SPI. From Stop mode, the following wake-up events can be configured: * Wake-up from Lx inputs without cyclic sense * Cyclic sense wake-up inputs * Force wake-up * CS wake-up * LIN wake-up * RST wake-up From Sleep mode, the following wake-up events can be configured: * Wake-up from Lx inputs without cyclic sense * Cyclic sense wake-up inputs * Force wake-up * LIN wake-up WINDOW WATCHDOG The 33911 includes a configurable window watchdog which is active in Normal mode. The watchdog can be configured by an external resistor connected to the WDCONF pin. The resistor is used to achieve higher precision in the timebase used for the watchdog. SPI clears are performed by writing through the SPI in the MOD bits of the Mode Control Register (MCR). During the first half of the SPI timeout, watchdog clears are not allowed, but after the first half of the SPI timeout window, the clear operation opens. If a clear operation is performed outside the window, the 33911 will reset the MCU, in the same way as when the watchdog overflows. WINDOW CLOSED NO WATCHDOG CLEAR ALLOWED WD TIMING X 50% WINDOW OPEN FOR WATCHDOG CLEAR WD TIMING X 50% WD PERIOD (tPWD) WD TIMING SELECTED BY REGISTER ON WDCONF PIN Figure 39. Window Watchdog Operation To disable the watchdog function in Normal mode, the user must connect the WDCONF pin to ground. This measure effectively disables Normal Request mode. The WDOFF bit in the Watchdog Status Register (WDSR) will be set. This condition is only detected during Reset mode. If neither a resistor nor a connection to ground is detected, the watchdog falls back to the internal lower precision timebase of 150 ms (typ.) and signals the faulty condition through the WDSR. The watchdog timebase can be further divided by a prescaler which can be configured by the Timing Control Register (TIMCR). During Normal Request mode, the window watchdog is not active but there is a 150 ms (typ.) timeout for leaving the Normal Request mode. In case of a timeout, the 33911 will enter into Reset mode, resetting the microcontroller before entering again into Normal Request mode. HIGH SIDE OUTPUT PIN HS1 This output is one high side driver intended to drive small resistive loads or LEDs incorporating the following features: * PWM capability (software maskable) * Open-load detection * Current limitation * Over-temperature shutdown (with maskable interrupt) * High-voltage shutdown (software maskable) * Cyclic sense The high side switch is controlled by the HS1 bit in the High Side Control Register (HSCR). PWM Capability (direct access) The high side driver offers additional (to the SPI control) direct control via the PWMIN pin. If the HS1 bit and PWMHS1 is set in the HSCR, then the HS1 driver is turned on if the PWMIN pin is high, and turned off if the PWMIN pin is low. 33911 Analog Integrated Circuit Device Data Freescale Semiconductor 74 MC33911BAC / MC34911BAC FUNCTIONAL DEVICE OPERATIONS OPERATIONAL MODES Interrupt Control Module MOD1:2 HS1 HS1OP VDD VDD PWMIN High-Side Interrupt High Voltage Shutdown HVSE PWMHS1 VS2 on/off Control Status HS1CL High Side - Driver charge pump open load detection current limitation overtemperture shutdown (interrupt maskable) high voltage shutdown (maskable) Cyclic Sense HS1 Wakeup Module Figure 40. High Side Driver HS1 Open Load Detection The high side driver signals an open-load condition if the current through the high side is below the open-load current threshold. The open-load condition is indicated with the HS1OP bits in the High Side Status Register (HSSR). Current Limitation The high side driver has an output current limitation. In combination with the over-temperature shutdown, the high side driver is protected against over-current and short-circuit failures. When the driver operates in the current limitation area, it is indicated with the bit HS1CL in the HSSR. Note: If the driver is operating in current limitation mode excessive power might be dissipated. Module. The shutdown is indicated as an HS Interrupt in the Interrupt Source Register (ISR). A thermal shutdown of the high side driver is indicated by setting the HS1OP and HS1CL bits simultaneously. If the bit HSM is set in the Interrupt Mask Register (IMR) than an interrupt (IRQ) is generated. A write to the High Side Control Register (HSCR), when the over-temperature condition is gone, will re-enable the high side driver. High-voltage Shutdown In case of a high-voltage condition, and if the high-voltage shutdown is enabled (bit HVSE in the Mode Control Register (MCR) is set), the high side driver is shut down. A write to the HSCR, when the high-voltage condition is gone, will re-enable the high side driver. Over-temperature Protection (HS Interrupt) Sleep And Stop Mode The high side driver is protected against over-temperature. In case of an over-temperature condition, the high side driver is shut down and the event is latched in the Interrupt Control The high side driver can be enabled to operate in Sleep and Stop mode for cyclic sensing. Also see Table 37, Operating Modes Overview. 33911 75 Analog Integrated Circuit Device Data Freescale Semiconductor MC33911BAC / MC34911BAC FUNCTIONAL DEVICE OPERATIONS OPERATIONAL MODES LOW SIDE OUTPUT PINS LS1 AND LS2 These outputs are two low side drivers intended to drive relays incorporating the following features: * PWM capability (software maskable) * Open load detection * Current limitation * Over-temperature shutdown (with maskable interrupt) * Active clamp (for driving relays) * High-voltage shutdown (software maskable) The low side switches are controlled by the bit LS1:2 in the Low Side Control Register (LSCR). HVSE To protect the device against over-voltage when an inductive load (relay) is turned off, an active clamp will reenable the low side FET if the voltage on the LS1 or LS2 pin exceeds a certain level. PWM Capability (direct access) Each low side driver offers additional (to the SPI control) direct control via the PWMIN pin. If both the LS1 and PWMLS1 bits are set in the LSCR, then the LS1 driver is turned on if the PWMIN pin is high, and turned off if the PWMIN pin is low. The same applies to the LS2 and PWMLS2 bits for the LS2 driver. VDD Interrupt Control Module VDD MOD1:2 LSx LSxOP PWMLSx Low Side Interrupt High-voltage Shutdown PWMIN active clamp LSx on/off Control LSxCL Status Low Side - Driver (active clamp) Open-load Detection Current Limitation Over-temperture Shutdown (interrupt maskable) High-voltage Shutdown (maskable) PGND Figure 41. Low Side Drivers LS1 and LS2 Open Load Detection Each low side driver signals an open-load condition if the current through the low side is below the open-load current threshold. The open-load condition is indicated with the bit LS1OP and LS2OP in the Low Side Status Register (LSSR). Current Limitation Each low side driver has a current limitation. In combination with the over-temperature shutdown, the low side drivers are protected against over-current and shortcircuit failures. When the drivers operate in current limitation, this is indicated with the LS1CL and LS2CL bits in the LSSR. Note: If the drivers are operating in current limitation mode excessive power might be dissipated. Over-temperature Protection (LS Interrupt) Both low side drivers are protected against overtemperature. In case of an over-temperature condition both low side drivers are shut down and the event is latched in the Interrupt Control Module. The shutdown is indicated as an LS Interrupt in the Interrupt Source Register (ISR). If the bit LSM is set in the Interrupt Mask Register (IMR), then an Interrupt (IRQ) is generated. A write to the Low Side Control Register (LSCR), when the over-temperature condition is gone, will re-enable the low side drivers. High-voltage Shutdown In case of a high voltage condition, and if the high-voltage shutdown is enabed (bit HVSE in the Mode Control Register (MCR) is set), both low side drivers are shut down. A write to the LSCR, when the high-voltage condition is gone, will re-enable the low side drivers. Sleep And Stop Mode The low side drivers are disabled in Sleep and Stop mode. Also see Table 37, Operating Modes Overview. 33911 Analog Integrated Circuit Device Data Freescale Semiconductor 76 MC33911BAC / MC34911BAC FUNCTIONAL DEVICE OPERATIONS OPERATIONAL MODES LIN PHYSICAL LAYER The LIN bus pin provides a physical layer for single-wire communication in automotive applications. The LIN physical layer is designed to meet the LIN physical layer specification and has the following features: * LIN physical layer 2.0 compliant * Slew rate selection * Over-current shutdown * Over-temperature shutdown * LIN pull-up disable in Stop and Sleep modes * Advanced diagnostics * LIN dominant voltage level selection The LIN driver is a low side MOSFET with over-current and thermal shutdown. An internal pull-up resistor with a serial diode structure is integrated, so no external pull-up components are required for the application in a slave node. The fall time from dominant to recessive and the rise time from recessive to dominant is controlled. The symmetry between both slopes is guaranteed. LIN Pin The LIN pin offers a high susceptibility immunity level from external disturbance, guaranteeing communication. INTERRUPT CONTROL MODULE High-voltage Shutdown High Side Interrupt WAKE-UP MODULE LIN Wake-up MOD1:2 LSR0:1 VS1 LINPE LIN - DRIVER LDVS RXONLY RXSHORT Slope and Slew Rate Control Over-current Shutdown (interrupt maskable) Over-temperature Shutdown (interrupt maskable) TXDOM LINOT LINOC 30K LIN TXD SLOPE CONTROL WAKE-UP FILTER LGND RXD RECEIVER Figure 42. LIN Interface Slew Rate Selection The slew rate can be selected for optimized operation at 10.4 and 20 kBit/s as well as a fast baud rate for test and programming. The slew rate can be adapted with the LSR1:0 bits in the LIN Control Register (LINCR). The initial slew rate is optimized for 20 kBit/s. LIN pin can be disconnected by clearing the LINPE bit in the Mode Control Register (MCR). The bit LINPE also changes the Bus wake-up threshold (VBUSWU). This feature will reduce the current consumption in STOP and SLEEP modes. It also improves performance and safe operation. LIN Pull-up Disable In Stop And Sleep Modes Current Limit (LIN Interrupt) In case of a LIN bus short to GND or LIN bus leakage during low-power mode, the internal pull-up resistor on the The output low side FET is protected against over-current conditions. If an over-current condition occurs (e.g. LIN bus 33911 77 Analog Integrated Circuit Device Data Freescale Semiconductor MC33911BAC / MC34911BAC FUNCTIONAL DEVICE OPERATIONS OPERATIONAL MODES short to VBAT), the transmitter will not be shut down. The bit LINOC in the LIN Status Register (LINSR) is set. If the LINM bit is set in the Interrupt Mask Register (IMR) an Interrupt IRQ will be generated. The transmitter is automatically re-enabled once TXD is high. A read of the LINSR with the TXD pin is high will clear the bit TXDOM. Over-temperature Shutdown (LIN Interrupt) LIN Dominant Voltage Level Selection The output low side FET is protected against overtemperature conditions. If an over-temperature condition occurs, the transmitter will be shut down and the LINOT bit in the LINSR is set. If the LINM bit is set in the IMR an Interrupt IRQ will be generated. The transmitter is automatically re-enabled once the condition is gone and TXD is high. A read of the LINSR with the TXD pin high will re-enable the transmitter. The LIN dominant voltage level can be selected by the LDVS bit in the LIN Control Register (LINCR). RXD Short-circuit Detection (LIN Interrupt) STOP Mode And Wake-up Feature The LIN transceiver has a short-circuit detection for the RXD output pin. In case of a short-circuit condition, either 5.0 V or Ground, the RXSHORT bit in the LINSR is set and the transmitter is shutdown. If the LINM bit is set in the IMR an Interrupt IRQ will be generated. The transmitter is automatically re-enabled once the condition is gone (transition on RXD) and TXD is high. A read of the LINSR without the RXD pin short-circuit condition will clear the RXSHORT bit. During Stop mode operation, the transmitter of the physical layer is disabled. If the LIN-PU bit was set in the Stop mode sequence, the internal pull-up resistor is disconnected from VSUP and a small current source keeps the LIN pin in the recessive state. The receiver is still active and able to detect wake-up events on the LIN bus line. A dominant level longer than tPROPWL followed by a rising edge will generate a wake-up interrupt and will be reported in the Interrupt Source Register (ISR). Also see Figure 34. TXD Dominant Detection (LIN Interrupt) The LIN transceiver monitors the TXD input pin to detect stuck-in-dominant (0 V) condition. If a stuck condition occurs (TXD pin 0V for more than 1 second (typ.), the transmitter is shut down and the TXDOM bit in the LINSR is set. If the bit LINM is set in the IMR an Interrupt IRQ will be generated. LIN Receiver Operation Only While in Normal mode, the activation of the RXONLY bit disables the LIN TXD driver. If a LIN error condition occurs, this bit is automatically set. If a low-power mode is selected with this bit set, the LIN wake-up functionality is disabled. Then in STOP mode, the RXD pin will reflect the state of the LIN bus. SLEEP Mode And Wake-up Feature During Sleep mode operation, the transmitter of the physical layer is disabled. If the LIN-PU bit was set in the Sleep mode sequence, the internal pull-up resistor is disconnected from VSUP and a small current source keeps the LIN pin in recessive state. The receiver must still active to detect wake-up events on the LIN bus line. A dominant level longer than tPROPWL followed by a rising edge will generate a system wake-up (Reset), and will be reported in the ISR. Also see Figure 33. 33911 Analog Integrated Circuit Device Data Freescale Semiconductor 78 MC33911BAC / MC34911BAC FUNCTIONAL DEVICE OPERATIONS LOGIC COMMANDS AND REGISTERS LOGIC COMMANDS AND REGISTERS 33911 SPI INTERFACE AND CONFIGURATION * MISO -- Master-In Slave-Out * SCLK-- Serial Clock A complete data transfer via the SPI consists of 1 byte. The master sends 4 bits of address (A3:A0) + 4 bits of control information (C3:C0) and the slave replies with 4 system status bits (VMS,LINS,HSS,LSS) + 4 bits of status information (S3:S0). The serial peripheral interface creates the communication link between a microcontroller (master) and the 33911. The interface consists of four pins (see Figure 43): * CS -- Chip Select * MOSI -- Master-Out Slave-In CS Register Write Data MOSI A3 A2 A1 A0 C3 C2 C1 C0 S1 S0 Register Read Data MISO VMS LINS HSS LSS S3 S2 SCLK Read Data Latch Rising Edge of SCLK Change MISO/MISO Output Write Data Latch Falling Edge of SCLK Sample MISO/MISO Input Figure 43. SPI Protocol During the inactive phase of the CS (HIGH), the new data The rising edge of the Chip Select (CS) indicates the end transfer is prepared. of the transfer and latches the write data (MOSI) into the register. The CS high forces MISO to the high-impedance The falling edge of the CS indicates the start of a new data state. transfer and puts the MISO in the low-impedance state and Register reset values are described along with the reset latches the analog status data (Register read data). condition. Reset condition is the condition causing the bit to With the rising edge of the SPI clock (SCLK), the data is be set to its reset value. The main reset conditions are: moved to MISO/MOSI pins. With the falling edge of the SPI - Power-On Reset (POR): level at which the logic is reset clock (SCLK), the data is sampled by the receiver. and BATFAIL flag sets. The data transfer is only valid if exactly 8 sample clock - Reset mode edges are present during the active (low) phase of CS. - Reset done by the RST pin (ext_reset) 33911 79 Analog Integrated Circuit Device Data Freescale Semiconductor MC33911BAC / MC34911BAC FUNCTIONAL DEVICE OPERATIONS LOGIC COMMANDS AND REGISTERS SPI REGISTER OVERVIEW Table 38. System Status Register Adress(A3:A0) $0 - $F BIT Register Name / Read / Write Information SYSSR - System Status Register R 7 6 5 4 VMS LINS HSS LSS Table 39 summarizes the SPI Register content for Control Information (C3:C0)=W and status information (S3:S0) = R. Table 39. SPI Register Overview Adress(A3:A0) BIT Register Name / Read / Write Information 3 2 1 0 MCR - Mode Control Register W HVSE LINPE MOD2 MOD1 VSR - Voltage Status Register R VSOV VSUV VDDOT BATFAIL VSR - Voltage Status Register R VSOV VSUV VDDOT BATFAIL WUCR - Wake-up Control Register W - - L2WE L1WE WUSR - Wake-up Status Register R - - L2 L1 WUSR - Wake-up Status Register R - - L2 L1 LINCR - LIN Control Register W LDVS RXONLY LSR1 LSR0 LINSR - LIN Status Register R RXSHORT TXDOM LINOT LINOC LINSR - LIN Status Register R RXSHORT TXDOM LINOT LINOC HSCR - High Side Control Register W - PWMHS1 - HS1 HSSR - High Side Status Register R - - HS1OP HS1CL HSSR - High Side Status Register R - - HS1OP HS1CL LSCR - Low Side Control Register W PWMLS2 PWMLS1 LS2 LS1 LSSR - Low Side Status Register R LS2OP LS2CL LS1OP LS1CL LSSR - Low Side Status Register R LS2OP LS2CL LS1OP LS1CL TIMCR - Timing Control Register W CS/WD WD2 WD1 WD0 CYST2 CYST1 CYST0 WDSR - Watchdog Status Register R WDTO WDERR WDOFF WDWO $B WDSR - Watchdog Status Register R WDTO WDERR WDOFF WDWO $C AMUXCR - Analog Multiplexer Control Register W LXDS MX2 MX1 MX0 $D CFR - Configuration Register W - CYSX8 - - IMR - Interrupt Mask Register W HSM LSM LINM VMM ISR - Interrupt Source Register R ISR3 ISR2 ISR1 ISR0 ISR - Interrupt Source Register R ISR3 ISR2 ISR1 ISR0 $0 $1 $2 $3 $4 $5 $6 $7 $8 $9 $A $E $F 33911 Analog Integrated Circuit Device Data Freescale Semiconductor 80 MC33911BAC / MC34911BAC FUNCTIONAL DEVICE OPERATIONS LOGIC COMMANDS AND REGISTERS REGISTER DEFINITIONS System Status Register - SYSSR HS1CL The System Status Register (SYSSR) is always transferred with every SPI transmission and gives a quick system status overview. It summarizes the status of the Voltage Status Register (VSR), LIN Status Register (LINSR), High Side Status Register (HSSR), and the Low Side Status Register (LSSR). HSS HS1OP Figure 46. High Side Status LSS - Low Side Switch Status Table 40. System Status Register Read S7 S6 S5 S4 VMS LINS HSS LSS This read-only bit indicates that one or more bits in the LSSR are set. 1 = Low Side Status bit set 0 = None VMS - Voltage Monitor Status This read-only bit indicates that one or more bits in the VSR are set. LS1CL LS1OP 1 = Voltage Monitor bit set 0 = None LS2OP Figure 47. Low Side Status BATFAIL VDDOT VSUV VMS Mode Control Register - MCR The Mode Control Register (MCR) allows to switch between the operation modes and to configure the 33911. Writing the MCR will return the VSR. VSOV Figure 44. Voltage Monitor Status Table 41. Mode Control Register - $0 LINS - LIN Status This read-only bit indicates that one or more bits in the LINSR are set. 1 = LIN Status bit set 0 = None TXDOM C3 C2 C1 C0 Write HVSE LINPE MOD2 MOD1 Reset Value 1 1 - - Reset Condition POR POR - - HVSE - High-Voltage Shutdown Enable LINOC LINOT LSS LS2CL LINS RXSHORT Figure 45. LIN Status HSS - High Side Switch Status This read-only bit indicates that one or more bits in the HSSR are set. 1 = High Side Status bit set 0 = None This write-only bit enables/disables automatic shutdown of the high side and the low side drivers during a high-voltage VSOV condition. 1 = automatic shutdown enabled 0 = automatic shutdown disabled LINPE - LIN pull-up enable. This write-only bit enables/disables the 30 k LIN pull-up resistor in STOP and SLEEP modes. This bit also controls the LIN bus wake-up threshold. 1 = LIN pull-up resistor enabled 0 = LIN pull-up resistor disabled 33911 81 Analog Integrated Circuit Device Data Freescale Semiconductor MC33911BAC / MC34911BAC FUNCTIONAL DEVICE OPERATIONS LOGIC COMMANDS AND REGISTERS MOD2, MOD1 - Mode Control Bits These write-only bits select the operating mode and allow to clear the watchdog in accordance with Table 42, Mode Control Bits. Any access to the MCR or Voltage Status Register (VSR) will clear the BATFAIL flag. 1 = POR Reset has occurred 0 = POR Reset has not occurred Table 42. Mode Control Bits Wake-up Control Register - WUCR MOD2 MOD1 Description 0 0 Normal Mode 0 1 Stop Mode 1 0 Sleep Mode 1 1 Normal Mode + watchdog Clear This register is used to control the digital wake-up inputs. Writing the Wake-up Control Register (WUCR) will return the Wake-up Status Register (WUSR). Table 44. Wake-up Control Register - $2 C3 C2 C1 C0 Write 0 0 L2WE L1WE Reset Value 1 1 1 1 Voltage Status Register - VSR Returns the status of the several voltage monitors. This register is also returned when writing to the Mode Control Register (MCR). Table 43. Voltage Status Register - $0/$1 Read S3 S2 S1 S0 VSOV VSUV VDDOT BATFAIL VSOV - VSUP Over-voltage This read-only bit indicates an over-voltage condition on the VS1 pin. 1 = Over-voltage condition. 0 = Normal condition. Reset Condition POR, Reset mode or ext_reset LxWE - Wake-up Input x Enable This write-only bit enables/disables which Lx inputs are enabled. In Stop and Sleep mode the LxWE bit determines which wake inputs are active for wake-up. If one of the Lx inputs is selected on the analog multiplexer, the corresponding LxWE is masked to 0. 1 = Wake-up Input x enabled. 0 = Wake-up Input x disabled. VSUV - VSUP Under-voltage Wake-up Status Register - WUSR This read-only bit indicates an under-voltage condition on the VS1 pin. 1 = Under-voltage condition. 0 = Normal condition. This register is used to monitor the digital wake-up inputs and is also returned when writing to the WUCR. VDDOT - Main Voltage Regulator Over-temperature Warning This read-only bit indicates that the main voltage regulator temperature reached the Over-temperature Prewarning Threshold. 1 = Over-temperature Prewarning 0 = Normal BATFAIL - Battery Fail Flag. This read-only bit is set during power-up and indicates that the 33911 had a Power On Reset (POR). Table 45. Wake-Up Status Register - $2/$3 Read S3 S2 S1 S0 - - L2 L1 Lx - Wake-up input x This read-only bit indicates the status of the corresponding Lx input. If the Lx input is not enabled then the according Wake-Up status will return 0. After a wake-up form Stop or Sleep mode these bits also allow to determine which input has caused the wake-up, by first reading the Interrupt Status Register (ISR) and then reading the WUSR. 1 = Lx Wake-up. 0 = Lx Wake-up disabled or selected as analog input. 33911 Analog Integrated Circuit Device Data Freescale Semiconductor 82 MC33911BAC / MC34911BAC FUNCTIONAL DEVICE OPERATIONS LOGIC COMMANDS AND REGISTERS LIN Control Register - LINCR LIN Status Register - LINSR This register controls the LIN physical interface block. Writing the LIN Control Register (LINCR) returns the LIN Status Register (LINSR). This register returns the status of the LIN physical interface block and is also returned when writing to the LIN Control Register (LINCR). Table 46. LIN Control Register - $4 Table 48. LIN Status Register - $4/$5 C3 C2 C1 C0 Write LDVS RXONLY LSR1 LSR0 Reset Value 0 0 0 0 Reset Condition POR, Reset mode or ext_reset POR, Reset mode, ext_reset or LIN failure gone* POR * LIN failure gone: if LIN failure (overtemp, TxD/RxD short) was set, the flag resets automatically when the failure is gone. LDVS - LIN Dominant Voltage Select This write-only bit controls the LIN Dominant voltage: 1 = LIN Dominant Voltage = VLIN_DOM_1 (1.7 V typ) 0 = LIN Dominant Voltage = VLIN_DOM_0 (1.1 V typ) RXONLY - LIN Receiver Operation Only. This write-only bit controls the behavior of the LIN transmitter. In Normal mode the activation of the RXONLY bit disables the LIN transmitter. In case of a LIN error condition this bit is automatically set. In Stop mode this bit disables the LIN wake-up functionality and the RXD pin will reflect the state of the LIN bus. 1 = only LIN receiver active (Normal mode) or LIN wakeup disabled (Stop mode). 0 = LIN fully enabled. LSRx - LIN Slew-rate This write-only bit controls the LIN driver slew-rate in accordance with Table 47. Table 47. LIN Slew-rate Control LSR1 LSR0 Description 0 0 Normal Slew-Rate (up to 20 kb/s) 0 1 Slow Slew-Rate (up to 10 kb/s) 1 0 Fast Slew-Rate (up to 100 kb/s) 1 1 Reserved Read S3 S2 S1 S0 RXSHORT TXDOM LINOT LINOC RXSHORT - RXD Short-circuit This read-only bit indicates a short-circuit condition on RXD (shorted either to 5.0V or to Ground). The short-circuit delay must be 8s worst case to be detected and to shutdown the driver. To clear this bit, it must be read after the condition is gone (transition detected on RXD). The LIN driver is automatically re-enabled once the condition is gone. 1 = RxD short-circuit condition. 0 = None. TXDOM - TXD Permanent Dominant This read-only bit signals the detection of a TXD pin stuck at dominant (Ground) condition and the resultant shutdown in the LIN transmitter. This condition is detected after the TXD pin remains in dominant state for more than 1 second typical value. To clear this bit, it must be read after TXD has gone high. The LIN driver is automatically re-enabled once TXD goes high. 1 = TXD stuck at dominant fault detected. 0 = None. LINOT - LIN Driver Over-temperature Shutdown This read-only bit signals that the LIN transceiver was shut-down due to over-temperature. The transmitter is automatically re-enabled after the over-temperature condition is gone and TXD is high. The LINOT bit is cleared after SPI read once the condition is gone. 1 = LIN over-temperature shutdown 0 = None LINOC - LIN Driver Over-current Shutdown This read-only bit signals an over-current condition occurred on the LIN pin. The LIN driver is not shut down but an IRQ is generated. To clear this bit, it must be read after the condition is gone. 1 = LIN over-current shutdown 0 = None 33911 83 Analog Integrated Circuit Device Data Freescale Semiconductor MC33911BAC / MC34911BAC FUNCTIONAL DEVICE OPERATIONS LOGIC COMMANDS AND REGISTERS High Side Control Register - HSCR Low Side Control Register - LSCR This register controls the operation of the high side driver. Writing to this register returns the High Side Status Register (HSSR). Table 49. High Side Control Register - $6 This register controls the operation of the low side drivers. Writing the Low Side Control Register (LSCR) will also return the Low Side Status Register (LSSR). C3 C2 C1 C0 Write 0 PWMHS1 0 HS1 Reset Value 0 0 0 0 Reset Condition POR, Reset mode, ext_reset, HS1 over-temp or (VSOV & HVSE) POR PWMHS1 - PWM Input Control Enable. This write-only bit enables/disables the PWMIN input pin to control the high side switch. The high side switch must be enabled (HS1 bit). 1 = PWMIN input controls HS1 output. 0 = HS1 is controlled only by SPI. HS1 - High Side Switch Control. This write-only bit enables/disables the high side switch. 1 = HS1 switch on. 0 = HS1 switch off. High Side Status Register - HSSR This register returns the status of the high side switch and is also returned when writing to the High Side Control Register (HSCR). Table 50. High Side Status Register - $6/$7 Read S3 S2 S1 S0 - - HS1OP HS1CL High Side thermal shutdown A thermal shutdown of the high side drivers is indicated by setting the HS1OP and HS1CL bits simultaneously. HS1OP - High Side Switch Open-Load Detection This read-only bit signals that the high side switch is conducting current below a certain threshold indicating possible load disconnection. 1 = HS1 Open Load detected (or thermal shutdown) 0 = Normal HS1CL - High Side Current Limitation This read-only bit indicates that the high side switch is operating in current limitation mode. 1 = HS1 in current limitation (or thermal shutdown) 0 = Normal Table 51. Low Side Control Register - $8 C3 C2 C1 C0 Write PWMLS2 PWMLS1 LS2 LS1 Reset Value 0 0 0 0 Reset Condition POR, Reset mode, ext_reset, LSx over-temp or (VSOV & HVSE) POR PWMLx - PWM input control enable. This write-only bit enables/disables the PWMIN input pin to control the respective low side switch. The corresponding low side switch must be enabled (LSx bit). 1 = PWMIN input controls LSx. 0 = LSx is controlled only by SPI. LSx - LSx switch control. This write-only bit enables/disables the corresponding low side switch. 1 = LSx switch on. 0 = LSx switch off. Low Side Status Register - LSSR This register returns the status of the low side switches and is also returned when writing to the LSCR. Table 52. Low Side Status Register - $8/$9 Read C3 C2 C1 C0 LS2OP LS2CL LS1OP LS1CL Low Side thermal shutdown A thermal shutdown of the low side drivers is indicated by setting all LSxOP and LSxCL bits simultaneously. LSxOP - Low Side Switch Open-Load Detection This read-only bit signals that the low side switches are conducting current below a certain threshold indicating possible load disconnection. 1 = LSx Open-load detected (or thermal shutdown) 0 = Normal LSxCL - Low Side Current Limitation This read-only bit indicates that the respective low side switch is operating in current limitation mode. 1 = LSx in current limitation (or thermal shutdown) 0 = Normal 33911 Analog Integrated Circuit Device Data Freescale Semiconductor 84 MC33911BAC / MC34911BAC FUNCTIONAL DEVICE OPERATIONS LOGIC COMMANDS AND REGISTERS Timing Control Register - TIMCR This register is a double purpose register which allows to configure the watchdog and the cyclic sense periods. Writing to the Timing Control Register (TIMCR) will also return the Watchdog Status Register (WDSR). Table 53. Timing Control Register - $A Configuration Register (CFR) (see Configuration Register CFR). This option is only active if the high side switch is enabled when entering in Stop or Sleep mode. Otherwise a timed wake-up is performed after the period shown in Table 55. Table 55. Cyclic Sense Interval CYSX8(127) CYST2 CYST1 CYST0 Interval X 0 0 0 No cyclic sense 0 0 0 1 20ms 0 0 1 0 40ms 0 0 1 1 60ms 0 1 0 0 80ms 0 1 0 1 100ms 0 1 1 0 120ms 0 1 1 1 140ms 1 0 0 1 160ms 1 0 1 0 320ms 1 0 1 1 480ms 1 1 0 0 640ms 1 1 0 1 800ms WDx - Watchdog Prescaler 1 1 1 0 960ms This write-only bits selects the divider for the watchdog prescaler and therefore selects the watchdog period in accordance with Table 54. This configuration is valid only if windowing watchdog is active. 1 1 1 1 1120ms C3 Write C2 C1 C0 WD2 WD1 WD0 CYST2 CYST1 CYST0 0 0 0 CS/WD Reset Value - Reset Condition - POR CS/WD - Cyclic Sense or Watchdog prescaler select. This write-only bit selects which prescaler is being written to, the Cyclic Sense prescaler or the watchdog prescaler. 1 = Cyclic Sense Prescaler selected 0 = watchdog Prescaler select Notes 127. bit CYSX8 is located in Configuration Register (CFR) Watchdog Status Register - WDSR Table 54. Watchdog Prescaler WD2 WD1 WD0 Prescaler Divider 0 0 0 1 0 0 1 2 0 1 0 4 0 1 1 6 1 0 0 8 1 0 1 10 1 1 0 12 1 1 1 14 CYSTx - Cyclic Sense Period Prescaler Select This write-only bits selects the interval for the wake-up cyclic sensing together with the bit CYSX8 in the This register returns the watchdog status information and is also returned when writing to the TIMCR. Table 56. Watchdog Status Register - $A/$B Read S3 S2 S1 S0 WDTO WDERR WDOFF WDWO WDTO - Watchdog Timeout This read-only bit signals the last reset was caused by either a watchdog timeout or by an attempt to clear the watchdog within the window closed. Any access to this register or the TIMCR will clear the WDTO bit. 1 = Last reset caused by watchdog timeout 0 = None 33911 85 Analog Integrated Circuit Device Data Freescale Semiconductor MC33911BAC / MC34911BAC FUNCTIONAL DEVICE OPERATIONS LOGIC COMMANDS AND REGISTERS WDERR - Watchdog Error MXx - Analog Multiplexer Input Select This read-only bit signals the detection of a missing watchdog resistor. In this condition the watchdog is using the internal, lower precision timebase. The Windowing function is disabled. 1 = WDCONF pin resistor missing 0 = WDCONF pin resistor not floating These write-only bits selects which analog input is multiplexed to the ADOUT0 pin according to Table 58. When disabled or when in Stop or Sleep mode, the output buffer is not powered and the ADOUT0 output is left floating to achieve lower current consumption. WDOFF - Watchdog Off This read-only bit signals that the watchdog pin connected to Ground and therefore disabled. In this case watchdog timeouts are disabled and the device automatically enters Normal mode out of Reset. This might be necessary for software debugging and for programming the Flash memory. 1 = Watchdog is disabled 0 = Watchdog is enabled WDWO - Watchdog Window Open This read-only bit signals when the watchdog window is open for clears. The purpose of this bit is for testing. Should be ignored in case WDERR is High. 1 = Watchdog window open 0 = Watchdog window closed Table 58. Analog Multiplexer Channel Select MX2 MX1 MX0 0 0 0 Disabled 0 0 1 Reserved 0 1 0 Die Temperature Sensor 0 1 1 VSENSE input 1 0 0 L1 input 1 0 1 L2 input 1 1 0 Reserved 1 1 1 Reserved Configuration Register - CFR This register controls the cyclic sense timing multiplier. Table 59. Configuration Register - $D C3 C2 C1 C0 Write 0 CYSX8 0 0 Reset Value 0 0 0 0 Reset Condition POR, Reset mode or ext_reset POR POR POR Analog Multiplexer Control Register - MUXCR This register controls the analog multiplexer and selects the divider ration for the Lx input divider. Table 57. Analog Multiplexer Control Register -$C C3 C2 C1 C0 Write LXDS MX2 MX1 MX0 Reset Value 1 0 0 0 Reset Condition POR POR, Reset mode or ext_reset LXDS - Lx Analog Input Divider Select Meaning CYSX8 - Cyclic Sense Timing x 8. This write-only bit influences the cyclic sense period as shown in Table 55. 1 = Multiplier enabled 0 = None This write-only bit selects the resistor divider for the Lx analog inputs. Voltage is internally clamped to VDD. 0 = Lx Analog divider: 1 1 = Lx Analog divider: 3.6 (typ.) 33911 Analog Integrated Circuit Device Data Freescale Semiconductor 86 MC33911BAC / MC34911BAC FUNCTIONAL DEVICE OPERATIONS LOGIC COMMANDS AND REGISTERS Interrupt Mask Register - IMR LINM - LIN Interrupts Mask This register allow to mask some of interrupt sources. The respective flags within the Interrupt Source Register (ISR) will continue to work but will not generate interrupts to the MCU. The 5.0 V Regulator over-temperature prewarning interrupt and Under Voltage (VSUV) interrupts can not be masked and will always cause an interrupt. This write-only bit enables/disables interrupts generated in the LIN block. 1 = LIN Interrupts Enabled 0 = LIN Interrupts Disabled VMM - Voltage Monitor Interrupt Mask Writing to the Interrupt Mask Register (IMR) will return the ISR. This write-only bit enables/disables interrupts generated in the Voltage Monitor block. The only maskable interrupt in the Voltage Monitor Block is the VSUP over-voltage interrupt. 1 = Interrupts Enabled 0 = Interrupts Disabled Table 60. Interrupt Mask Register - $E C3 C2 C1 C0 Write HSM LSM LINM VMM Reset Value 1 1 1 1 Reset Condition Interrupt Source Register - ISR This register allows the MCU to determine the source of the last interrupt or wake-up respectively. A read of the register acknowledges the interrupt and leads IRQ pin to high, in case there are no other pending interrupts. If there are pending interrupts, IRQ will be driven high for 10 s and then be driven low again. This register is also returned when writing to the IMR. POR HSM - High Side Interrupt Mask This write-only bit enables/disables interrupts generated in the high side block. 1 = HS Interrupts Enabled 0 = HS Interrupts Disabled Table 61. Interrupt Source Register - $E/$F Read LSM - Low Side Interrupt Mask This write-only bit enables/disables interrupts generated in the low side block. 1 = LS Interrupts Enabled 0 = LS Interrupts Disabled S3 S2 S1 S0 ISR3 ISR2 ISR1 ISR0 ISRx - Interrupt Source Register These read-only bits indicate the interrupt source following Table 62. If no interrupt is pending than all bits are 0. In case more than one interrupt is pending, than the interrupt sources are handled sequentially multiplex. Table 62. Interrupt Sources Interrupt Source ISR3 ISR2 ISR1 ISR0 none maskable maskable 0 0 0 0 0 0 0 1 0 0 1 0 - HS Interrupt (Over-temperature) 0 0 1 1 - LS Interrupt (Over-temperature) 0 1 0 0 0 1 0 1 0 1 1 0 no interrupt Priority no interrupt none Lx Wake-up from Stop mode- highest LIN Interrupt (RXSHORT, TXDOM, LIN OT, LIN OC) or LIN Wake-up Voltage Monitor Interrupt Voltage Monitor Interrupt (Low-voltage and VDD over-temperature) (High-voltage) - Forced Wake-up lowest 33911 87 Analog Integrated Circuit Device Data Freescale Semiconductor MC33911G5AC/MC3433911G5AC TYPICAL APPLICATION LOGIC COMMANDS AND REGISTERS TYPICAL APPLICATION The 33911 can be configured in several applications. The figure below shows the 33911 in the typical Slave Node Application. V BAT VS2 VS1 D1 C2 C1 C4 Interrupt Control Module LVI, HVI, HTI, OCI IRQ C3 Internal Bus VDD Voltage Regulator AGND VDD IRQ Reset Control Module LVR, HVR, HTR, WD, RST LS1 Low Side Control Module RST TIMER LS2 HB Type Relay PGND Window Watchdog Module PWMIN R1 Motor Output High Side Control Module HS1 MISO MOSI Chip Temp Sense Module SCLK Analog Multiplexer SPI & CONTROL SPI CS MCU VSENSE VBAT Sense Module L1 Analog Input Module A/D ADOUT0 L2 R2 R3 Wake Up Module Digital Input Module RXD LIN Physical Layer SCI LIN LIN TXD WDCONF LGND AGND PGND C5 R4 Typical Component Values: C1 = 47F; C2 = C4 = 100nF; C3 = 10F; C5 = 220pF R1 = 10k; R2 = R3 = 10k; R4 = 20k-200k Recommended Configuration of the not Connected Pins (NC): Pin 15, 16, 20, 21 = GND Pin 11, 30 = open (floating) Pin 24 = open (floating) or VS2 Pin 28 = this pin is not internally connected and may be used for PCB routing optimization. 33911 88 Analog Integrated Circuit Device Data Freescale Semiconductor MC33911G5AC/MC3433911G5AC PACKAGING PACKAGE DIMENSIONS PACKAGING PACKAGE DIMENSIONS Important For the most current revision of the package, visit www.Freescale.com and select Documentation, then under Available Documentation column select Packaging Information. AC SUFFIX (PB-FREE) 32-PIN LQFP 98ASH70029A REVISION D 33911 Analog Integrated Circuit Device Data Freescale Semiconductor 89 MC33911G5AC/MC3433911G5AC IMPORTANT FOR THE MOST CURRENT REVISION OF THE PACKAGE, VISIT WWW.FREESCALE.COM AND SELECT DOCUMENTA- AC SUFFIX (PB-FREE) 32-PIN LQFP 98ASH70029A REVISION D 33911 90 Analog Integrated Circuit Device Data Freescale Semiconductor MC33911G5AC/MC3433911G5AC REVISION HISTORY REVISION HISTORY Revision Date Description of Changes 1.0 5/2007 * Initial Release 2.0 9/2007 * * * * * Several textual corrections Page 11: "Analog Output offset Ratio" (LXDS=1) changed to "Analog Output offset" +/-22mV Page 11: VSENSE Input Divider Ratio adjusted to 5,0/5,25/5,5 Page 12: Common mode input impedance corrected to 75k Page 13/15: LIN PHYSICAL LAYER parameters adjusted to final LIN specification release 3.0 9/2007 * Revision number incremented at engineering request. 4.0 2/2008 * Changed Functional Block Diagram on page 24. 5.0 11/2008 * * * * Datasheet updated according to the Pass1.2 silicon version electrical parameters Add Maximum Rating on IBUS_NO_GND parameter Added L1 and L2, Temperature Sense Analog Output Voltage per characterization(37), Internal Chip Temperature Sense Gain per characterization at 3 temperatures(37) See Figure 16, Temperature Sense Gain, VSENSE Input Divider Ratio (RATIOVSENSE=Vsense/Vadout0) per characterization(38), and VSENSE Output Related Offset per characterization(38) parameters Added Temperature Sense Gain section Minor corrections to ESD Capability, (17), Cyclic Sense ON Time from Stop and Sleep Mode(47), Lin Bus Pin (LIN), Serial Data Clock Pin (SCLK), Master Out Slave In Pin (MOSI), Master In Slave Out Pin (MISO), Low Side Pins (LS1 and LS2), Digital/analog Pins (L1 and L2), Normal Request Mode, Sleep Mode, LIN Overtemperature Shutdown / TXD Stuck At Dominant / RXD Short-circuit:, Fault Detection Management Conditions, Lin Physical Layer, LIN Interface, Over-temperature Shutdown (LIN Interrupt), LIN Receiver Operation Only, SPI Protocol, Lx - Wake-up input x, LIN Control Register - LINCR, and RXSHORT - RXD Pin Short-circuit Updated Freescale form and style Added explanation for pins Not Connected (NC). * * 6.0 2/2009 * 7.0 3/2009 * Changed VBAT_SHIFT and GND_SHIFT maximum from 10% to 11.5% for both parameters on page 14. 3/2010 * Combined Complete Data sheet for Part Numbers MC33911BAC and MC34911BAC to the back of this data sheet. Changed ESD Voltage for Machine Model from 200 to 150 8.0 * 33911 Analog Integrated Circuit Device Data Freescale Semiconductor 91 How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. Technical Information Center, EL516 2100 East Elliot Road Tempe, Arizona 85284 1-800-521-6274 or +1-480-768-2130 www.freescale.com/support Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) www.freescale.com/support Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo 153-0064 Japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com Asia/Pacific: Freescale Semiconductor China Ltd. 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