© Semiconductor Components Industries, LLC, 2016
July, 2019 − Rev. 1
1Publication Order Number:
NCV8135/D
NCV8135
500 mA, Very Low Dropout
Bias Rail CMOS Voltage
Regulator
The NCV8135 is a 500 mA VLDO equipped with NMOS pass
transistor and a separate bias supply voltage (VBIAS). The device
provides very stable, accurate output voltage with low noise suitable
for space constrained, noise sensitive applications. In order to
optimize performance for battery operated portable applications, the
NCV8135 features low IQ consumption. The NCV8135 is offered in
WDFN6 2 mm x 2 mm package, wettable flanks option available for
Enhanced Optical Inspection.
Features
•Input Voltage Range: 0.4 V to 5.5 V
•Bias Voltage Range: 2.5 V to 5.5 V
•Fixed Output Voltage Versions Available
•±1% Accuracy over Temperature, 0.5% VOUT @ 25°C
•Ultra−Low Dropout: Typ. 53 mV at 500 mA
•Very Low Bias Input Current of Typ. 35 mA
•Logic Level Enable Input for ON/OFF Control
•Output Active Discharge Option Available
•Stable with a 10 mF Ceramic Capacitor
•NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
•These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Typical Applications
•Automotive, Consumer and Industrial Equipment Point of Load
Regulation
•Battery−powered Equipment
•Smartphones, Tablets
•Cameras, DVRs, STB and Camcorders
Figure 1. Typical Application Schematic
IN
BIAS
EN
OUT
GND
10 mF
VOUT
0.4 V up to 500 mA
VIN
VBIAS
VEN
0.1 mF
4.7 mFNCV8135
SNS
See detailed ordering, marking and shipping information on
page 8 of this data sheet.
ORDERING INFORMATION
MARKING
DIAGRAM
PIN CONNECTIONS
T
WDFN6
CASE 511BR
www.onsemi.com
XX = Specific Device Code
M = Date Code
XX M
1
(Top View)
Thermal
Pad
OUT
SNS
EN
IN
GND
BIAS
1
2
3
6
5
4
NCV8135
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PIN FUNCTION DESCRIPTION
Pin No. Pin Name Description
1 VIN Input Voltage Supply pin
2 GND Ground pin
3 VBIAS Bias voltage supply for internal control circuits. This pin is monitored by internal Under-Voltage
Lockout Circuit.
4 EN Enable pin. Driving this pin high enables the regulator. Driving this pin low puts the regulator into
shutdown mode.
5 SNS Output voltage Sensing Input. Connect to Output voltage node on the PCB.
6 VOUT Regulated Output Voltage pin
Pad Pad Should be soldered to the ground plane for increased thermal performance.
ABSOLUTE MAXIMUM RATINGS
Rating Symbol Value Unit
Input Voltage (Note 1) VIN −0.3 to 6 V
Output Voltage VOUT −0.3 to (VIN+0.3) ≤ 6 V
Chip Enable, Bias and SNS Input VEN, VBIAS, VSNS −0.3 to 6 V
Output Short Circuit Duration tSC unlimited s
Maximum Junction Temperature TJ125 °C
Storage Temperature TSTG −55 to 150 °C
ESD Capability, Human Body Model (Note 2) ESDHBM 2000 V
ESD Capability, Machine Model (Note 2) ESDMM 200 V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
2. This device series incorporates ESD protection (except OUT pin) and is tested by the following methods:
ESD Human Body Model tested per AEC−Q100−002
ESD Machine Model tested per AEC−Q100−003
Latchup Current Maximum Rating ± 100 mA per AEC−Q100−004.
THERMAL CHARACTERISTICS
Rating Symbol Value Unit
Thermal Characteristics, WDFN6 2 mm x 2 mm
Thermal Resistance, Junction−to−Air (Note 3)
RqJA 97 °C/W
3. This data was derived by thermal simulations based on the JEDEC JESD51 series standards methodology. Only a single device mounted
at the center of a high K (2s2p) 3 in x 3 in multilayer board with 1−ounce internal planes and 1−ounce copper on top and bottom. Top copper
layer has a dedicated 25 sq mm copper area.
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ELECTRICAL CHARACTERISTICS −40°C ≤ TJ ≤ 125°C; VBIAS = 2.7 V or (VOUT + 1.6 V), whichever is greater, VIN = VOUT(NOM) +
0.3 V, IOUT = 1 mA, VEN = 1 V, CIN = 4.7 mF, COUT = 10 mF, CBIAS = 1 mF, unless otherwise noted. Typical values are at TJ = +25°C.
Min/Max values are for −40°C ≤ TJ ≤ 125°C unless otherwise noted. (Note 4)
Parameter Test Conditions Symbol Min Typ Max Unit
Operating Input Voltage
Range
VIN VOUT +
VDO
5.5 V
Operating Bias Voltage
Range
VBIAS (VOUT +
1.50) ≥ 2.5
5.5 V
Undervoltage Lock−out VBIAS Rising
Hysteresis
UVLO 1.6
0.2
V
Output Voltage Accuracy VOUT ±0.5 %
Output Voltage Accuracy −40°C ≤ TJ ≤ 125°C, VOUT(NOM) + 0.3 V ≤ VIN
≤ VOUT(NOM) + 1.0 V, 2.7 V or (VOUT(NOM) +
1.6 V), whichever is greater < VBIAS < 5.5 V,
1 mA < IOUT < 500 mA
VOUT −1.0 +1.0 %
VIN Line Regulation VOUT(NOM) + 0.3 V ≤ VIN ≤ 5.0 V LineReg 0.01 %/V
VBIAS Line Regulation 2.7 V or (VOUT(NOM) + 1.6 V), whichever is
greater < VBIAS < 5.5 V
LineReg 0.01 %/V
Load Regulation IOUT = 1 mA to 500 mA LoadReg 0.5 mV
VIN Dropout Voltage IOUT = 500 mA (Note 5) VDO 53 100 mV
VBIAS Dropout Voltage IOUT = 500 mA, VIN = VBIAS (Notes 5, 6) VDO 1.1 1.5 V
Output Current Limit VOUT = 90% VOUT(NOM) ICL 600 820 1200 mA
SNS Pin Operating
Current
ISNS 0.01 0.5 mA
Bias Pin Quiescent
Current
VBIAS = 2.7 V, IOUT = 0 mA IBIASQ 35 55 mA
Bias Pin Disable Current VEN ≤ 0.4 V IBIAS(DIS) 0.2 1 mA
Vinput Pin Disable
Current
VEN ≤ 0.4 V IVIN(DIS) 0.01 1 mA
EN Pin Threshold Voltage EN Input Voltage “H” VEN(H) 0.9 V
EN Input Voltage “L” VEN(L) 0.4
EN Pull Down Current VEN = 5.5 V IEN 0.3 1 mA
Turn−On Time From assertion of VEN to VOUT =
98% VOUT(NOM) VOUT(NOM) = 0.4 V
VOUT(NOM) = 1.2 V
tON 150
275
ms
Power Supply Rejection
Ratio
VIN to VOUT
, f = 1 kHz, IOUT = 10 mA,
VIN ≥ VOUT +0.5 V, VOUT(NOM) = 0.4 V
PSRR(VIN) 73 dB
VBIAS to VOUT
, f = 1 kHz, IOUT = 10 mA,
VIN ≥ VOUT +0.5 V, VOUT(NOM) = 0.4 V
PSRR(VBIAS) 90 dB
Output Noise Voltage VIN = VOUT +0.5 V, f = 10 Hz to 100 kHz
VOUT(NOM) = 0.4 V
VOUT(NOM) = 1.2 V
VN28.7
40.3
mVRMS
Thermal Shutdown
Threshold
Temperature increasing 160 °C
Temperature decreasing 140
Output Discharge
Pull−Down
VEN ≤ 0.4 V, VOUT = 0.5 V, NCV8135A options
only
RDISCH 150 W
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Performance guaranteed over the indicated operating temperature range by design and/or characterization. Production tested at TA = 25°C.
Low duty cycle pulse techniques are used during the testing to maintain the junction temperature as close to ambient as possible.
5. Dropout voltage is characterized when VOUT falls 3% below VOUT(NOM).
6. For output voltages below 0.9 V, VBIAS dropout voltage does not apply due to a minimum Bias operating voltage of 2.5 V.
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TYPICAL CHARACTERISTICS
At TJ = +25°C, VIN = VOUT(NOM) + 0.3 V, VBIAS = 2.7 V, VEN = 1.0 V, VOUT(NOM) = 0.4 V, IOUT = 500 mA,
CIN = 1 mF, C BIAS = 0.1 mF, and COUT = 10 mF (effective capacitance value), unless otherwise noted.
Figure 3. VIN Dropout Voltage vs. IOUT and
Temperature TJ
Figure 4. VIN Dropout Voltage vs. (VBIAS −
VOUT) and Temperature TJ
IOUT
, OUTPUT CURRENT (mA) VBIAS − VOUT (V)
3002001000
0
10
20
30
40
50
60
4.03.53.02.52.01.5
0
5
10
20
25
VDO (VIN − VOUT) DROPOUT VOLTAGE (mV)
4.5
15
+125°C
+25°C−40°C
IOUT = 100 mA
VDO (VIN − VOUT) DROPOUT VOLTAGE (mV)
Figure 5. VIN Dropout Voltage vs. (VBIAS −
VOUT) and Temperature TJ
Figure 6. VIN Dropout Voltage vs. (VBIAS −
VOUT) and Temperature TJ
VBIAS − VOUT (V) VBIAS − VOUT (V)
4.03.53.02.52.01.5
60 100
VDO (VIN − VOUT) DROPOUT VOLTAGE (mV)
4.5
IOUT = 300 mA
VDO (VIN − VOUT) DROPOUT VOLTAGE (mV)
+125°C
+25°C
−40°C
70
80
90
100
+85°C
+85°C
+125°C
+25°C−40°C
+85°C
+125°C
+25°C
−40°C
+85°C
400 500 5.0 5.5
5.0 5.5
50
40
30
20
10
0
4.03.53.02.52.01.5 4.5 5.0 5.5
90
80
70
60
50
40
30
20
10
0
IOUT = 500 mA
Figure 7. Load Transient Response,
IOUT = 50 mA to 500 mA, COUT = 10 mF
50 ms/div
200 mA/div 50 mV/div
tR = tF = 1 ms
VOUT
IOUT
Figure 8. Load Transient Response,
IOUT = 50 mA to 500 mA, COUT = 22 mF
50 ms/div
200 mA/div 50 mV/div
tR = tF = 1 ms
VOUT
IOUT
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TYPICAL CHARACTERISTICS
At TJ = +25°C, VIN = VOUT(NOM) + 0.3 V, VBIAS = 2.7 V, VEN = 1.0 V, VOUT(NOM) = 0.4 V, IOUT = 500 mA,
CIN = 1 mF, C BIAS = 0.1 mF, and COUT = 10 mF (effective capacitance value), unless otherwise noted.
Figure 9. Load Transient Response,
IOUT = 1 mA to 500 mA, COUT = 10 mF
500 ms/div
200 mA/div 50 mV/div
tR = tF = 1 ms
VOUT
IOUT
Figure 10. Load Transient Response,
IOUT = 1 mA to 500 mA, COUT = 22 mF
500 ms/div
200 mA/div 50 mV/div
tR = tF = 1 ms
VOUT
IOUT
Figure 11. Load Transient Response,
IOUT = 1 mA to 20 mA, COUT = 10 mF
500 ms/div
10 mA/div 10 mV/div
tR = tF = 1 ms
VOUT
IOUT
Figure 12. Load Transient Response,
IOUT = 1 mA to 20 mA, COUT = 22 mF
500 ms/div
10 mA/div 10 mV/div
tR = tF = 1 ms
VOUT
IOUT
Figure 13. Enable Transient Response,
IOUT = 0 mA, COUT = 10 mF
100 ms/div
100 mV/div 500 mV/div
VOUT
VENABLE
Figure 14. Enable Transient Response, Output
Resistive Load 500 mA, COUT = 22 mF
100 ms/div
200 mA/div 500 mV/div
VOUT
IOUT
VENABLE
100 mV/div
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TYPICAL CHARACTERISTICS
At TJ = +25°C, VIN = VOUT(NOM) + 0.3 V, VBIAS = 2.7 V, VEN = 1.0 V, VOUT(NOM) = 0.4 V, IOUT = 500 mA,
CIN = 1 mF, C BIAS = 0.1 mF, and COUT = 10 mF (effective capacitance value), unless otherwise noted.
Figure 15. VIN Line Transient Response,
VIN = 0.7 V to 1.7 V, IOUT = 100 mA, CIN = 0,
COUT = 10 mF
50 ms/div
500 mV/div 20 mV/div
tR = tF = 5 ms
VOUT
VIN
Figure 16. VIN Line Transient Response,
VIN = 0.7 V to 1.7 V, IOUT = 100 mA, CIN = 0,
COUT = 22 mF
50 ms/div
500 mV/div 20 mV/div
tR = tF = 5 ms
VOUT
VIN
Figure 17. VIN Power Supply Rejection Ratio
vs. Frequency
Figure 18. VBIAS Power Supply Rejection Ratio
vs. Frequency
FREQUENCY (Hz) FREQUENCY (Hz)
10
Figure 19. Output Voltage Noise Spectral
Density
FREQUENCY (Hz)
100k10k1k10010
10000
OUTPUT NOISE (nV/
√
Hz)
1M
−120
100 mA, COUT = 10 mF
10M
PSSR (dB)
100 mA, COUT = 22 mF
10 mA, COUT = 10 mF
10 mA, COUT = 22 mF
VIN = 0.9 V, VBIAS = 2.7 V, COUT = MLCC 1206
−110
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
10
100 1k 10k 100k 1M 10M
−120
−110
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
10
10 mA, COUT = 22 mF
10 mA, COUT = 10 mF
100 mA, COUT = 10 mF
100 mA, COUT = 22 mF
VIN = 0.9 V, VBIAS = 2.7 V, COUT = MLCC 1206
PSSR (dB)
500 mA 22 mF
100 mA 22 mF
10 mA 22 mF
1 mA 22 mF
1 mA 10 mF
VIN = 0.9 V, VBIAS = 2.7 V, COUT = MLCC 1206
RMS Output Noise Voltage (mV)
27.54
27.28
35.49
44.87
54.04
28.67
28.19
36.23
45.44
54.54
10 mF
22 mF
22 mF
22 mF
22 mF
1 mA
1 mA
10 mA
100 mA
500 mA
IOUT COUT 10 Hz − 100 kHz 100 Hz − 100 kHz
10 100 1k 10k 100k 1M 10M
1000
100
10
1
NCV8135
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8
APPLICATIONS INFORMATION
The NCV8135 dual−rail very low dropout voltage
regulator is using NMOS pass transistor for output voltage
regulation from VIN voltage. All the low current internal
control circuitry is powered from the VBIAS voltage.
The use of an NMOS pass transistor offers several
advantages in applications. Unlike PMOS topology devices,
the output capacitor has reduced impact on loop stability. Vin
to Vout operating voltage difference can be very low compared
with standard PMOS regulators in very low Vin applications.
When enabled from Enable (EN) input, the NCV8135
offers smooth monotonic start-up. The controlled voltage
rising limits the inrush current.
The Enable (EN) input is equipped with internal
hysteresis.
Dropout Voltage
Because of two power supply inputs VIN and VBIAS and
one VOUT regulator output, there are two Dropout voltages
specified.
The first, the VIN Dropout voltage is the voltage
difference (VIN – VOUT) when VOUT starts to decrease by
percent specified in the Electrical Characteristics table.
VBIAS is high enough; specific value is published in the
Electrical Characteristics table.
The second, VBIAS dropout voltage is the voltage
difference (VBIAS – VOUT) when VIN and VBIAS pins are
joined together and VOUT starts to decrease.
Input and Output Capacitors
The device is designed to be stable for ceramic output
capacitors with Effective capacitance in the range from
10 mF to 22 mF. The device is also stable with multiple
capacitors in parallel, having the total effective capacitance
in the specified range.
In applications where no low input supplies impedance
available (PCB inductance in VIN and/or VBIAS inputs as
example), the recommended CIN = 1 mF and CBIAS = 0.1 mF
or greater. Ceramic capacitors are recommended. For the
best performance all the capacitors should be connected to
the NCV8135 respective pins directly in the device PCB
copper layer, not through vias having not negligible
impedance.
When using small ceramic capacitor, their capacitance is
not constant but varies with applied DC biasing voltage,
temperature and tolerance. The effective capacitance can be
much lower than their nominal capacitance value, most
importantly in negative temperatures and higher LDO
output voltages. That is why the recommended Output
capacitor capacitance value is specified as Effective value in
the specific application conditions.
Enable Operation
The enable pin will turn the regulator on or off. The
threshold limits are covered in the electrical characteristics
table in this data sheet. To get the full functionality of
soft−start, it is recommended to turn on the VIN and VBIAS
supply voltages first and activate the Enable pin no sooner
than when VIN and VBIAS are on their nominal levels. If the
enable function is not to be used then the pin should be
connected to VIN or VBIAS.
Current Limitation
The internal Current Limitation circuitry allows the
device to supply the full nominal current and surges but
protects the device against Current Overload or Short.
Thermal Protection
Internal thermal shutdown (TSD) circuitry is provided to
protect the integrated circuit in the event that the maximum
junction temperature is exceeded. When TSD activated, the
regulator output turns off. When cooling down under the low
temperature threshold, device output is activated again. This
TSD feature is provided to prevent failures from accidental
overheating.
Activation of the thermal protection circuit indicates
excessive power dissipation or inadequate heatsinking. For
reliable operation, junction temperature should be limited to
+125°C maximum.
ORDERING INFORMATION
Device Marking Voltage Option Package Shipping†
NCV8135AMT040TBG KA 0.4 V Output Active Discharge WDFN6
(Non−Wettable Flank)
(Pb−Free)
3000 / Tape & Reel
NCV8135BMT040TBG KC 0.4 V Non−Active Discharge
NCV8135AMT120TBG KE 1.2 V Output Active Discharge
NCV8135AMTW040TBG K2 0.4 V Output Active Discharge
WDFN6
(Wettable Flank)
(Pb−Free)
NCV8135BMTW040TBG K3 0.4 V Non−Active Discharge
NCV8135AMTW120TBG K4 1.2 V Output Active Discharge
NCV8135AMTW075TBG
(In Development)
KL 0.75 V Output Active Discharge
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Spe-
cifications Brochure, BRD8011/D.
To order other package and voltage variants, please contact your ON Semiconductor sales representative
ÍÍÍ
ÍÍÍ
ÍÍÍ
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL AND
IS MEASURED BETWEEN 0.15 AND 0.25 mm FROM
THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED PAD AS
WELL AS THE TERMINALS.
5. FOR DEVICES CONTAINING WETTABLE FLANK
OPTION, DETAIL A ALTERNATE CONSTRUCTION
A-2 AND DETAIL B ALTERNATE CONSTRUCTION
B-2 ARE NOT APPLICABLE.
SEATING
PLANE
D
E
0.10 C
A3
A
A1
0.10 C
WDFN6 2x2, 0.65P
CASE 511BR
ISSUE B
DATE 19 JAN 2016
SCALE 4:1
DIM
A
MIN MAX
MILLIMETERS
0.70 0.80
A1 0.00 0.05
A3 0.20 REF
b0.25 0.35
D2.00 BSC
D2 1.50 1.70
0.90 1.10
E2.00 BSC
E2
e0.65 BSC
0.20 0.40
L
PIN ONE
REFERENCE
0.05 C
0.05 C
NOTE 4
A0.10 C
NOTE 3
L
e
D2
E2
b
B
3
6
6X
1
4
0.05 C MOUNTING FOOTPRINT
GENERIC
MARKING DIAGRAM*
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
XX = Specific Device Code
M = Date Code
XX M
1
BOTTOM VIEW
RECOMMENDED
DIMENSIONS: MILLIMETERS
L1
DETAIL A
L
ALTERNATE
CONSTRUCTIONS
L
DETAIL A
DETAIL B
A
B
TOP VIEW
C
SIDE VIEW
--- 0.15
L1
6X
0.45
2.30
1.12
1.72
0.65
PITCH
6X 0.40
1
PACKAGE
OUTLINE
6X
M
M
ÉÉ
ÉÉ
ÇÇ
DETAIL B
MOLD CMPDEXPOSED Cu
ALTERNATE
CONSTRUCTIONS
ÉÉ
ÉÉ
ÇÇ
A1
A3
ALTERNATE B−2ALTERNATE B−1
ALTERNATE A−2ALTERNATE A−1
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
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