DS093 (v2.5) October 1, 2004 www.xilinx.com 1
Preliminary Product Specification 1-800-255-7778
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Features
• Optimized for 1.8V systems
- As fast as 4.5 ns pin-to-pin delays
- As low as 13 µA quiescent current
• Industry’s best 0.18 micron CMOS CPLD
- Optimized architecture for effective logic synthesis
- Multi-voltage I/O operation — 1.5V to 3.3V
• Available in multiple package options
- 100-pin VQFP with 80 user I/O
- 144-pin TQFP with 100 user I/O
- 132-ball CP (0.5mm) BGA with 100 user I/O
- Pb-free available for all packages
• Advanced system features
- Fastest in system programming
· 1.8V ISP using IEEE 1532 (JTAG) interface
- IEEE1149.1 JTAG Boundary Scan Test
- Optional Schmitt-trigger input (per pin)
- Unsurpassed low power management
· DataGATE enable (DGE) signal control
- Two separate output banks
- RealDigital 100% CMOS product term generation
- Flexible clocking modes
· Optional DualEDGE triggered registers
· Clock divider (divide by 2,4,6,8,10,12,14,16)
· CoolCLOCK
- Global signal options with macrocell control
· Multiple global clocks with phase selection per
macrocell
· Multiple global output enables
· Global set/reset
- Advanced design security
- Open-drain output option for Wired-OR and LED
drive
- PLA architecture
· Superior pinout retention
· 100% product term routability across function
block
- Optional bus-hold, 3-state or weak pull-up on
selected I/O pins
- Optional configurable grounds on unused I/Os
- Mixed I/O voltages compatible with 1.5V, 1.8V,
2.5V, and 3.3V logic levels
· SSTL2-1, SSTL3-1, and HSTL-1 I/O compatibility
- Hot plu gga ble
Refer to the CoolRunner™-II family data sheet for architec-
ture description.
Description
The CoolRunner-II 128-macrocell device is designed for
both high performance and low power applications. This
lends power savings to high-end communication equipment
and high speed to battery operated devices. Due to the low
power stand-by and dynamic operation, overall system reli-
ability is improved
This device consists of eight Function Blocks inter-con-
nected by a low power Advanced Interconnect Matrix (AIM).
The AIM feeds 40 true and complement inputs to each
Function Block. The F unction B locks consis t of a 40 by 56
P-term PLA and 16 macrocells which contain numerous
configurat ion bits that allow for combi national or regis tered
modes of operation.
Additionally, these registers can be globally reset or preset
and configured as a D or T flip-flop or as a D latch. There
are also multiple clock signals, both global and local product
term types, configured on a per macrocell basis. Output pin
configurations include slew rate limit, bus hold, pull-up,
open drain and programmable grounds. A Schmitt-trigger
input is available on a per input pin basis. In addition to stor-
ing macr ocel l ou tput s tates, th e ma cr oc ell r egi s ters m ay be
configur ed as direct input regis ters to store signals dir ectly
from input pins.
Clocking is available on a global or Function Block basis.
Three globa l clock s are avai lable for all Functi on Block s as
a synchronous clock source. Macrocell registers can be
individually configured to power up to the zero or one state.
A global s et/reset c ontrol line is als o availab le to asy nchro-
nously set or reset selected registers during operation.
Additional local clock, synchronous clock-enable, asynchro-
nous set/reset and output enable signals can be formed
using product terms on a per-macrocell or per-Function
Block basis.
A DualEDGE flip-flop feature is also available on a per mac-
rocell basis . T his fea tur e al lo ws hi gh per forma nc e sy nc hro-
nous operation based on lower frequency clocking to help
reduce the total power consumption of the device.
Circuitry has also been included to divide one externally
supplied global clock (GCK2) by eight different selections.
This yields divide by even and odd clock frequencies.
The use of the clock divide (division by 2) and DualEDGE
flip-flop gives the resultant CoolCLOCK feature.
DataGATE is a method to selectively disable inputs of the
CPLD that are not of interest during certain points in time.
0
XC2C128 CoolRunner-II CPLD
DS093 (v2.5 ) Octob er 1, 2004 00Preliminary Product Specification
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XC2C128 CoolRunner-II CPLD
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By mapping a signal to the DataGA TE function, lower power
can be achieved due to reduction in signal switching.
Another feature that eases voltage translation is output
banking. Two output banks are available on the
CoolRunner-II 128 macrocell device that permits easy inter-
facing to 3.3V, 2.5V, 1.8V, and 1.5V devices.
The CoolRunner-II 128 macrocell CPLD is I/O compatible
with various JEDEC I/O standards (see Table 1). This
device is also 1.5V I/O compatible with the use of
Schmitt-trigger inputs.
RealDigital Design Technology
Xilinx CoolRunner-II CPLDs are fabricated on a 0.18 micron
process technology which is derived from leading edge
FPGA pr odu ct d evelopment. Co ol Runn er-I I CPL Ds e mpl oy
RealDigital te chnology, a design techn ique that m akes use
of CMOS technology in both the fabrication and design
methodology. RealDigital technology employs a cascade of
CMOS gates to implement sum of products instead of tradi-
tional se nse amp lifie r methodol ogy. Due to thi s techn ology,
Xilinx CoolRunner-II CPLDs achieve both high-perfor-
mance and low power operation.
Supported I/O Standards
The CoolRunner-II 128 macrocell features LVCMOS,
LV TTL, SSTL an d HSTL I/O i mplementations. Se e Table 1
for I/O standard voltages. The LVTTL I/O standard is a gen-
eral purpose EIA/JEDEC standard for 3.3V applications that
use an LVTTL inpu t buffer and Pu sh -Pul l out put buffer. The
LV CMO S standar d is used in 3.3V, 2 .5V, 1.8V ap pli cati ons .
Both HSTL and SSTL make use of a VREF pin for JEDEC
compliance. CoolRunner-II CPLDs are also 1.5V I/O com-
patible with the use of Schmitt-trigger inputs.
Table 1: I/O Standards for XC2C128
I/O Types Output
VCCIO
Input
VCCIO
Input
VREF
Board
Termination
Voltage VTT
LVTTL 3.3 3.3 N/A N/A
LVCMOS33 3.3 3.3 N/A N/A
LVCMOS25 2.5 2.5 N/A N/A
LVCMOS18 1.8 1.8 N/A N/A
1.5V I/O 1.5 1.5 N/A N/A
HSTL-1 1.5 1.5 0.75 0.75
SSTL2-1 2.5 2.5 1.25 1.25
SSTL3-1 3.3 3.3 1.5 1.5
For information on assigning Vref pins, see XAPP399
Figure 1: ICC vs Frequency
Table 2: ICC vs Frequency (LVCMOS 1.8V TA = 25°C)(1)
Frequency (MHz)
0 25 50 75 100 150 175 200 225 250
Typical -4 ICC (mA)
Typical -6, -7 ICC (mA) 0.019 3.97 7.95 11.92 15.89 23.83 27.80 31.93 35.73 39.70
Notes:
1. 16-bit up/down, Resetable binary counter (one counter per function block).
Frequency (MHz)
DS093_050103
ICC (mA)
00
20
40
60
80
250200150100
50
XC2C128 CoolRunner-II CPLD
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Recommended Operating Conditions
DC Electrical Characteristics (Over Recommended Operating Conditions)
Absolute Maximum Ratings
Symbol Description Value Units
VCC Supply voltage relative to ground –0.5 to 2.0 V
VCCIO Supply voltage for output drivers –0.5 to 4.0 V
VJTAG(2) JTAG input voltage limits –0.5 to 4.0 V
VAUX JTAG input supply voltage –0.5 to 4.0 V
VIN(1) Input voltage relative to ground –0.5 to 4.0 V
VTS(1) Voltage applied to 3-state output –0.5 to 4.0 V
TSTG(3) Storage Temperature (ambient) –65 to +150 °C
TJJunction Temperature + 150 °C
Notes:
1. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easiest to achieve. During transitions,
the device pins ma y unde rshoot to –2.0 V or oversh oot t o +4.5V, provid ed this over or und ershoo t last s les s than 10 ns and wi th the
forcing current being limited to 200 mA.
2. Valid over commercial temperature range.
3. For soldering guidelines and thermal considerations, see the Device Packaging information on the Xilinx webs ite. For Pb-free
packages, see XAPP427.
Symbol Parameter Min Max Units
VCC Supply voltage for internal logic
and input buffers Commercial TA = 0°C to +70°C 1.7 1.9 V
Industrial TA = –40°C to +85°C 1.7 1.9 V
VCCIO Supply voltage for output drivers @ 3.3V operation 3.0 3.6 V
Supply voltage for output drivers @ 2.5V operation 2.3 2.7 V
Supply voltage for output drivers @ 1.8V operation 1.7 1.9 V
Supply voltage for output drivers @ 1.5V operation 1.4 1.6 V
VAUX Supply voltage for JTAG programming 1.7 3.6 V
Symbol Parameter Test Conditions Typical Max. Units
ICCSB Standby current (-4) VCC = 1.9V, VCCIO = 3.6V µA
ICCSB Standby current (-6, -7) VCC = 1.9V, VCCIO = 3.6V 30 80 µA
ICCSB Standby current (industrial) VCC = 1.9V, VCCIO = 3.6V 60 150 µA
ICC (1) Dynamic current (-4) f = 1 MHz - mA
f = 50 MHz - mA
ICC (1) Dynamic current (-6, -7) f = 1 MHz - 500 µA
f = 50 MHz - 10 mA
CJTAG JTAG input capacitance f = 1 MHz - 10 pF
CCLK Global clock input capacitance f = 1 MHz - 12 pF
CIO I/O capacitance f = 1 MHz - 10 pF
IIL(2) Input leakage current VIN = 0V or VCCIO to 3.9V –1 1 µA
IIH(2) I/O High-Z leakage VIN = 0V or VCCIO to 3.9V –1 1 µA
Notes:
1. 16-bit up/down, Resetable binary counter (one counter per function block).
2. See Quality and Reliability section in CoolRunner-II family data sheet for details.
XC2C128 CoolRunner-II CPLD
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LVCMOS and LVTTL 3.3V DC Voltage Specifications
LVCMOS 2.5 V DC Voltage Specifications
LVCMOS 1.8 V DC Voltage Specifications
1.5V DC Voltage Specifications(1)
Symbol Parameter Test Conditions Min. Max. Units
VCCIO Input source voltage 3.0 3.6 V
VIH High level input voltage 2.0 3.9 V
VIL Low level input voltage –0.3 0.8 V
VOH High level output voltage IOH = –8 mA, VCCIO = 3V VCCIO – 0.4V - V
IOH = –0.1 mA, VCCIO = 3V VCCIO – 0.2V - V
VOL Low level output voltage IOL = 8 mA, VCCIO = 3V - 0.4 V
IOL = 0.1 mA, VCCIO = 3V - 0.2 V
Symbol Parameter Test Conditions Min. Max. Units
VCCIO Input source voltage 2.3 2.7 V
VIH High level input voltage 1.7 3.9 V
VIL Low level input voltage –0.3 0.7 V
VOH High level output voltage IOH = –8 mA, VCCIO = 2.3V VCCIO –0.4V - V
IOH = –0.1 mA, VCCIO = 2.3V VCCIO – 0.2V - V
VOL Low level output voltage IOL = 8 mA, VCCIO = 2.3V - 0.4 V
IOL = 0.1 mA, VCCIO = 2.3V - 0.2 V
Symbol Parameter Test Conditions Min. Max. Units
VCCIO Input source voltage 1.7 1.9 V
VIH High level input voltage 0.65 x VCCIO 3.9 V
VIL Low level input voltage –0.3 0.35 x VCCIO V
VOH High level output voltage IOH = –8 mA, VCCIO = 1.7V VCCIO – 0.45 - V
IOH = –0.1 mA, VCCIO = 1.7V VCCIO – 0 .2 - V
VOL Low level output voltage IOL = 8 mA, VCCIO = 1.7V - 0.45 V
IOL = 0.1 mA, VCCIO = 1.7V - 0.2 V
Symbol Parameter Test Conditions Min. Max. Units
VCCIO Input source voltage 1.4 1.6 V
VT+ Input hysteresis threshold voltage 0.5 x VCCIO 0.8 x VCCIO V
VT- 0.2 x VCCIO 0.5 x VCCIO V
VOH High level output voltage IOH = –8 mA, VCCIO = 1.4V VCCIO – 0.45 V
IOH = –0.1 mA, VCCIO = 1.4V VCCIO – 0 .2 V
VOL Low level output voltage IOL = 8 mA, VCCIO = 1.4V 0.4 V
IOL = 0.1 mA, VCCIO = 1.4V 0.2 V
Notes:
1. Hysteresis used on 1.5V inputs.
XC2C128 CoolRunner-II CPLD
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Preliminary Product Specification 1-800-255-7778
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Schmitt Trigger Input DC Voltage Specifications
SSTL2-1 DC Voltage Specifications
SSTL3-1 DC Voltage Specifications
HSTL1 DC Voltage Sp ecifications
Symbol Parameter Test Conditions Min. Max. Units
VCCIO Input source voltage 1.4 3.9 V
VT+ Input hysteresis threshold voltage 0.5 x VCCIO 0.8 x VCCIO V
VT- 0.2 x VCCIO 0.5 x VCCIO V
Symbol Parameter Test Conditions Min. Typ. Max. Units
VCCIO Input source voltage 2.3 2.5 2.7 V
VREF(1) Input reference voltage 1.15 1.25 1.35 V
VTT(2) Termi nati on vo ltage V REF – 0.04 1.25 VREF + 0.04 V
VIH High level input voltage VREF + 0.18 - 3.9 V
VIL Low level input voltage –0.3 - VREF – 0.18 V
VOH High level output voltage IOH = –8 mA, VCCIO = 2.3V VCCIO – 0.62 - - V
VOL Low level output voltage IOL = 8 mA, VCCIO = 2.3V - - 0.54 V
Notes:
1. VREF should track the variations in VCCIO, also peak to peak ac noise on VREF may not exceed ±2% VREF.
2. VTT of transmitting device must track VREF of receiving devices.
Symbol Parameter Test Conditions Min. Typ. Max. Units
VCCIO Input source voltage 3.0 3.3 3.6 V
VREF(1) Input reference voltage 1.3 1.5 1.7 V
VTT(2) Termination voltage VREF – 0.05 1.5 VREF + 0.05 V
VIH High level input voltage VREF + 0.2 - VCCIO + 0.3 V
VIL Low level input voltage –0.3 - VREF – 0.2 V
VOH High level output voltage IOH = –8 mA, VCCIO = 3V V CCIO – 1.1 - - V
VOL Low level output voltage IOL = 8 mA, VCCIO = 3V - - 0.7 V
Notes:
1. VREF should track the variations in VCCIO, also peak to peak ac noise on VREF may not exceed ±2% VREF.
2. VTT of transmitting device must track VREF of receiving devices.
Symbol Parameter Test Conditions Min. Ty p. Max. Units
VCCIO Input source voltage 1.4 1.5 1.6 V
VREF(1) Input reference voltage 0.68 0.75 0.90 V
VTT(2) Termi nati on vo ltage VCCIO x 0.5 V
VIH High level input voltage VREF + 0.1 - 1.9 V
VIL Low level input voltage –0.3 - VREF – 0.1 V
VOH High level output voltage IOH = –8 mA, VCCIO = 1.7V VCCIO -0.4 - - V
VOL Low level output voltage IOL = 8 mA, VCCIO = 1.7V - - 0.4 V
Notes:
1. VREF should track the variations in VCCIO, also peak to peak ac noise on VREF may not exceed ±2% VREF.
2. VTT of transmitting device must track VREF of receiving devices.
XC2C128 CoolRunner-II CPLD
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AC Electrical Characteristics Over Recommended Operating Conditions
Symbol Parameter
-4(5) -6 -7 Unit
sMin. Max. Min. Max. Min. Max
.
TPD1 Propagation delay single p- term - 4.2 - 5.7 - 7.0 ns
TPD2 Propagation delay OR array - 4.5 - 6.0 - 7.5 ns
TSUD Direct input register set-up time 2.3 - 3.2 - 4.0 - ns
TSU1 Setup time fast (single p-term) 1.8 - 2.4 - 2.8 - ns
TSU2 Setup time (OR array) 2.1 - 2.7 - 3.3 - ns
THD Direct input register hold time 0.0 - 0.0 - 0.0 - ns
THHold time (Or array or p-term) 0.0 - 0.0 - 0.0 - ns
TCO Clock to output - 3.4 - 4.2 - 6.0 ns
FTOGGLE(1) Internal toggle rate - 500 - 450 - 300 MHz
FSYSTEM1(2) Maximum sy s tem freque nc y - 3 33 - 2 70 - 152 M Hz
FSYSTEM2(2) Maximum sy s tem freque nc y - 3 03 - 2 50 - 141 M Hz
FEXT1(3) Maximum ex ternal freq uency - 1 92 - 1 52 - 114 MHz
FEXT2(3) Maximum ex ter nal freq uency - 1 82 - 1 45 - 108 M Hz
TPSUD Direct input register p-term clock setup time 1.6 - 2.1 - 2.7 - ns
TPSU1 P-term clock setup time (single p-term) 1.1 - 1.3 - 1.5 - ns
TPSU2 P-term clock setup time (OR array) 1.4 - 1.6 - 2.0 - ns
TPHD Direct input register p-term clock hold time 0.0 - 0.2 - 0.2 - ns
TPH P-term clock hold 0.3 - 0.7 - 1.0 - ns
TPCO P-term clock to output - 4.1 - 5.3 - 7.3 ns
TOE/TOD Global OE to output enable/disable - 4.3 - 5.6 - 7.0 ns
TPOE/TPOD P-term OE to output enable/disable - 4.8 - 6.4 - 8.0 ns
TMOE/TMOD Macrocell driven OE to output enable/disable - 5.5 - 7.2 - 9.9 ns
TPAO P-term set/reset to output valid - 4.9 - 6.0 - 8.1 ns
TAO Global set/reset to output valid - 4.4 - 5.0 - 7.6 ns
TSUEC Register clock enable setup time 1.9 - 2.5 - 3.1 - ns
THEC Register clock enable hold time 0.0 - 0.0 - 0.0 - ns
TCW Global clock pulse width High or Low 0.9 - 1.1 - 1.6 - ns
TAPRPW Asynchronous preset/reset pulse width (High or Low) 4.5 - 6.0 - 7.5 - ns
TPCW P-term pulse width High or Low 4.5 - 6.0 - 7.5 - ns
TDGSU Set-up before DataGATE latch assertion 0.0 - 0.0 - 0.0 - ns
TDGH Hold to DataGATE latch assertion 5.0 - 4.0 - 6.0 - ns
TDGR DataGATE recovery to new data - 5.0 - 8.2 - 9.0 ns
TDGW DataGATE low pulse width 2.0 - 3.0 - 4.0 - ns
TCDRSU CDRST setup time before falling edge GCLK2 0.8 - 1.3 - 2.0 - ns
TCDRH Hold time CDRST after falling edge GCLK2 0.0 - 0.0 - 0.0 - ns
TCONFIG(4) Configuration time - 350 - 350 - 350 us
Notes:
1. FTOGGLE is the maximum clock frequency to which a T flip-flop can reliably toggle (see the CoolRunner-II family data sheet).
2. FSYSTEM1 is th e internal ope rating frequenc y for a devic e with 16-bit res etable bin ary counter th rough one p-term per macrocel l while
FSYSTEM2 is through the OR array (one counter per function block).
3. FEXT1 (1/TSU1+TCO) is the maximum external frequency using one p-term while FEXT2 is through the OR array.
4. Typical configuration current during TCONFIG is 10 mA.
5. The -4 speed grade is Advance Specification.
XC2C128 CoolRunner-II CPLD
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Preliminary Product Specification 1-800-255-7778
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Internal Timing Parameters
Symbol Parameter(1) -4(2) -6 -7 UnitsMin. Max. Min. Max. Min. Max.
Buffer Delays
TIN Input buffer delay - 1.6 - 2.0 - 2.6 ns
TDIN Direct data register input delay - 2.5 - 3.3 - 4.9 ns
TGCK Global Clock buffer delay - 1.4 - 1.5 - 2.7 ns
TGSR Global set/reset buffer delay - 1.5 - 1.6 - 3.5 ns
TGTS Global 3-state buffer delay - 1.6 - 1.8 - 3.0 ns
TOUT Output buffer delay - 1.8 - 2.3 - 2.6 ns
TEN Output buffer enable/disable delay - 2.7 - 3.8 - 4.0 ns
P-term Delays
TCT Control term delay - 0.5 - 0.6 - 1.4 ns
TLOGI1 Single P-term delay adder - 0.4 - 0.5 - 1.1 ns
TLOGI2 Multiple P-term delay adder - 0.3 - 0.3 - 0.5 ns
Macrocell Delay
TPDI Input to output valid - 0.4 - 0.9 - 0.7 ns
TLDI Setup before cloc k (tr an sparent
latch) - 1.2 - 2.1 - 2.5 ns
TSUI Setup before clock 1.2 - 1.4 - 1.8 - ns
THI Hold after clock 0.0 - 0.0 - 0.0 - ns
TECSU Enable clock setup time 1.2 - 1.4 - 1.8 - ns
TECHO Enable clock hold time 0.0 - 0.0 - 0.0 - ns
TCOI Clock to output valid - 0.2 - 0.4 - 0.7 ns
TAOI Set/reset to output valid - 1.0 - 1.1 - 1.5 ns
TCDBL Clock doubler delay - 0.0 - 0.0 - 0.0 ns
Feedback Delays
TFFeedback delay - 1.2 - 1.4 - 3.0 ns
TOEM Macrocell to global OE delay - 1.2 - 1.5 - 2.0 ns
I/O Standard Time Adder Delays 1.5V I/O
THYS15 Hysteresis input adder - 2.0 - 3.0 - 4.0 ns
TOUT15 Output adder - 0.5 - 0.8 - 1.0 ns
TSLEW15 Output slew rate adder - 2.0 - 4.0 - 4.0 ns
I/O Standard Time Adder Delays 1.8V CMOS
THYS18 Hysteresis input adder - 2.0 - 2.0 - 4.0 ns
TOUT18 Output adder - 0.0 - 0.0 - 0.0 ns
TSLEW Output slew rate adder - 2.0 - 2.0 - 4.0 ns
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Switching Characteristics
Figure 2: Derating Curve for TPD
Switching Test Conditions
Figure 3: AC Load Circuits
I/O Standard Time Adder Delays 2.5V CMOS
TIN25 Standard input adde r - 0.5 - 0.6 - 1.0 ns
THYS25 Hysteresis input adder - 1.5 - 1.5 - 3.0 ns
TOUT25 Output adder - 0.7 - 0.8 - 3.0 ns
TSLEW25 Output slew rate adder - 2.0 - 3.0 - 4.0 ns
I/O Standard Time Adder Delays 3.3V CMOS/TTL
TIN33 Standard input adde r - 0.4 - 0.5 - 2.0 ns
THYS33 Hysteresis input adder - 1.0 - 1.2 - 3.0 ns
TOUT33 Output adder - 1.0 - 1.2 - 3.0 ns
TSLEW33 Output slew rate adder - 2.0 - 3.0 - 4.0 ns
I/O Standard Time Adder Delays HSTL, SSTL
SSTL2-1 Input adder to TIN, TDIN, TGCK,
TGSR, TGTS
- 0.3 - 0.4 - 2.5 ns
Output adder to TOUT - -0.5 - -0.5 - 0.0 ns
SSTL3-1 Input adder to TIN, TDIN, TGCK,
TGSR, TGTS
- 0.3 - 0.4 - 2.5 ns
Output adder to TOUT - -0.5 - -0.5 - 0.0 ns
HSTL-1 Input adder to TIN, TDIN, TGCK,
TGSR, TGTS
- 0.5 - 0.6 - 2.5 ns
Output adder to TOUT - 0.0 - 0.0 - 0.0 ns
Notes:
1. 1.5 ns input pin signal rise/fall.
2. The -4 speed grade is Advance Specification.
Internal Timing Parameters (Continued)
Symbol Parameter(1) -4(2) -6 -7 UnitsMin. Max. Min. Max. Min. Max.
Number of Outputs Switching
12 4 8 16
4.0
4.4
4.8
VCC = VCCIO = 1.8V, 25
o
C
TPD2 (ns)
5.0
4.6
4.2
DS093_02_050103
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Preliminary Product Specification 1-800-255-7778
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Typical I/V Output Curves
11
Figure 4: Typical I/V Curves for XC2C128
VO (Output Volts)
XC128_IV_all_050703
IO (Output Current mA)
00
40
10
50
20
30
60
3.02.52.01.51.0.5 3
.5
3.3V
1.5V
1.8V
2.5V
Iol
Pin Descriptions
Function
Block Macro-
cell VQ100 CP132 TQ144 I/O
Bank
1 1 13 G1 17 2
12-F1162
1 3 12 F2 15 2
1411F3142
1 5 10 E1 13 2
169E2122
17----
18----
19----
110----
1118E3112
1127D1102
1136D292
114-C172
1(GTS1) 15 4 C2 6 2
1(GTS0) 16 3 C3 5 2
21-G2191
2 2 14 G3 21 1
2 3 15 H1 22 1
2 4 16 H2 23 1
2 5 17 H3 24 1
2 6 18 J1 25 1
27----
28----
29----
210----
21119J2261
212-K1281
2(GCK0) 13 22 K3 30 1
2(GCK1) 14 23 L2 32 1
2(CDRST) 15 24 M2 35 1
2(GCK2) 16 27 N2 38 1
Pin Descriptions (Continued)
Function
Block Macro-
cell VQ100 CP132 TQ144 I/O
Bank
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31-B142
3(GTS3) 2 2 B2 3 2
3(GTS2) 3 1 A1 2 2
3(GSR) 4 99 A3 143 2
3597B41402
3696A41382
3795C51362
38----
39----
310----
31194B51342
312 A51332
31393C61322
31492B61312
31591A61302
31690C71292
4(DGE) 1 28 P2 39 1
42-M3401
43-N3411
4 4 29 P3 43 1
4 5 30 M4 45 1
4 6 32 M5 49 1
4 7 33 N5 50 1
48----
49----
410----
41134P5511
41235M6521
41336N6531
41437P6541
41539N7561
41640M7571
Pin Descriptions (Continued)
Function
Block Macro-
cell VQ100 CP132 TQ144 I/O
Bank
5165G13942
5266G12952
5367F14962
54-F13972
5568F12982
56-E131002
5 7 70 E12 101 2
58----
59----
510----
51171D141022
51272D131032
51373D121042
51474C141052
51576B131102
5 16 - A13 111 2
6164H12921
6263H13911
6361J13881
6460J12871
6559K14861
6658K13851
67----
68----
69----
610----
6 11 - L14 83 1
6 12 56 L13 82 1
6 13 - L12 81 1
6 14 55 M14 80 1
615-M13791
6 16 54 M12 78 1
Pin Descriptions (Continued)
Function
Block Macro-
cell VQ100 CP132 TQ144 I/O
Bank
XC2C128 CoolRunner-II CPLD
DS093 (v2.5) October 1, 2004 www.xilinx.com 11
Preliminary Product Specification 1-800-255-7778
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XC2C128 JTAG, Power/Ground, No Connect Pins and To tal User I/O
7 1 77 C12 112 2
7 2 78 B12 113 2
73-A121152
7 4 79 C11 116 2
7 5 80 B11 117 2
7 6 81 A11 118 2
77-C101192
78----
79----
710----
71182A101202
712-C91212
71385A81242
71486B81252
71587C81262
71689B71282
Pin Descriptions (Continued)
Function
Block Macro-
cell VQ100 CP132 TQ144 I/O
Bank
8 1 - N14 77 1
8253N13761
8352P14741
8450P12711
85-M11701
8649N11691
87----
88----
89----
810----
811-P11681
8 12 46 P10 64 1
81344P9611
81443M8601
81542N8591
81641P8581
Notes:
1. GTS = global output enable, GSR = global reset/set, GCK =
global clock, CDRST = clock divide reset, DGE = DataGATE
enable.
Pin Descriptions (Continued)
Function
Block Macro-
cell VQ100 CP132 TQ144 I/O
Bank
Pin Type VQ100(1) CP132(1) TQ144(1)
TCK 48 M10 67
TDI 45 M9 63
TDO 83 B9 122
TMS 47 N10 65
VAUX (JTAG supply voltage) 5 D3 8
Power int ernal (VCC) 26, 57 P1, K12, A2 1, 37, 84
Power Bank 1 I/O (VCCIO1) 20, 38, 51 J3, P7, G14, P13 27, 55, 73, 93
Power Bank 2 I/O (VCCIO2) 88, 98 A14, C4, A7 109, 127, 141
Ground 21, 25, 31, 62, 69, 75,
84, 100 K2, N1, P4, N9, N12, J14,
H14, E14, B14, A9, B3 29, 36, 47, 62, 72, 89, 90,
99, 108, 123, 144
No connects - L1, L3, M1, N4, C13, B10 18, 20, 31, 33, 34, 42, 44,
46, 48, 66, 75, 106, 107,
114, 135, 137, 139, 142
Total user I/O (including dual function
pins) 80 100 100
Notes:
1. Pin compatible with all larger and smaller densities except where I/O banking is used.
XC2C128 CoolRunner-II CPLD
12 www.xilinx.com DS093 (v2.5) October 1, 2004
1-800-255-7778 Preliminary Product Specification
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Orderi ng Info r mat io n
Part Number Pin/Ball
Spacing θJA
(C/Watt) θJC
(C/Watt) Package Type Package Body
Dimensions I/O
Comm.
(C)
Ind. (I)(1)
XC2C128-4VQ100C(2) 0.5mm 47.5 12.5 V ery Thin Quad Flat
Pack 14mm x 14mm 80 C
XC2C128-6VQ100C 0.5mm 47.5 12.5 V ery Thin Quad Flat
Pack 14mm x 14mm 80 C
XC2C128-7VQ100C 0.5mm 47.5 12.5 V ery Thin Quad Flat
Pack 14mm x 14mm 80 C
XC2C128-4CP132C(2) 0.5mm 72.4 15.7 Chip Scale Package 8mm x 8mm 100 C
XC2C128-6CP132C 0.5mm 72.4 15.7 Chip Scale Package 8mm x 8mm 100 C
XC2C128-7CP132C 0.5mm 72.4 15.7 Chip Scale Package 8mm x 8mm 100 C
XC2C128-4TQ144C(2) 0.5mm 46.1 7.9 Thin Quad Flat Pack 20mm x 20mm 100 C
XC2C128-6TQ144C 0.5mm 46.1 7.9 Thin Quad Flat Pack 20mm x 20mm 100 C
XC2C128-7TQ144C 0.5mm 46.1 7.9 Thin Quad Flat Pack 20mm x 20mm 100 C
XC2C128-4VQG100C(2) 0.5mm 47.5 12.5 V ery Thin Quad Flat
Pack; Pb-free 14mm x 14mm 80 C
XC2C128-6VQG100C 0.5mm 47.5 12.5 V ery Thin Quad Flat
Pack; Pb-free 14mm x 14mm 80 C
XC2C128-7VQG100C 0.5mm 47.5 12.5 V ery Thin Quad Flat
Pack; Pb-free 14mm x 14mm 80 C
XC2C128-4CPG132C(2) 0.5mm 72.4 15.7 Chip Scale
Package; Pb-free 8mm x 8mm 100 C
XC2C128-6CPG132C 0.5mm 72.4 15.7 Chip Scale
Package; Pb-free 8mm x 8mm 100 C
XC2C128-7CPG132C 0.5mm 72.4 15.7 Chip Scale
Package; Pb-free 8mm x 8mm 100 C
XC2C128-4TQG144C(2) 0.5mm 46.1 7.9 Thin Quad Flat
Pack; Pb-free 20mm x 20mm 100 C
XC2C128-6TQG144C 0.5mm 46.1 7.9 Thin Quad Flat
Pack; Pb-free 20mm x 20mm 100 C
XC2C128-7TQG144C 0.5mm 46.1 7.9 Thin Quad Flat
Pack; Pb-free 20mm x 20mm 100 C
XC2C128-7VQ100I 0.5mm 47.5 12.5 V ery Thin Quad Flat
Pack 14mm x 14mm 80 I
XC2C128-7CP132I 0.5mm 72.4 15.7 Chip Scale Package 8mm x 8mm 100 I
XC2C128-7TQ144I 0.5mm 46.1 7.9 Thin Quad Flat Pack 20mm x 20mm 100 I
XC2C128-7VQG100I 0.5mm 47.5 12.5 V ery Thin Quad Flat
Pack; Pb-free 14mm x 14mm 80 I
XC2C128 CoolRunner-II CPLD
DS093 (v2.5) October 1, 2004 www.xilinx.com 13
Preliminary Product Specification 1-800-255-7778
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Device Part Marki ng
Note: Due to the small size of chip scale packages, the complete ordering part number cannot be included on the package
marking. Part marking on chip scale packages by line are:
• Line 1 = X (Xilinx logo) then truncated part number
• Line 2 = Not related to device part number
• Line 3 = Not related to device part number
• Line 4 = Package code, speed, operating temperature,
three digits not related to device part number. Package
codes: C5 = CP132, C6 = CPG132.
XC2C128-7CPG132I 0.5mm 72.4 15.7 Chip Scale
Package; Pb-free 8mm x 8mm 100 I
XC2C128-7TQG144I 0.5mm 46.1 7.9 Thin Quad Flat
Pack; Pb-free 20mm x 20mm 100 I
Notes:
1. C = Commercial (T A = 0° C to +70° C); I = Industrial (T A = –40° C to +85° C)
2. Inquire with your local sales representative for availability of this part.
Figure 5: Sample Package with Part Marking
Part Number Pin/Ball
Spacing θJA
(C/Watt) θJC
(C/Watt) Package Type Package Body
Dimensions I/O
Comm.
(C)
Ind. (I)(1)
Standard Example: XC2C128
Device
Speed Grade
Package Type
Number of Pins
Temperature Range
-4 TQ C144 Pb-Free Example:
XC2C128 TQ G 144 C
Device
Speed Grade
Package Type
Pb-Free
Number of Pins
-4
Temperature Range
XC2Cxxx
TQ144
7C
Device Type
Package
Speed
Operating Range
This line not
related to device
part number
Part Marking for all non chip scale packages
R
XC2C128 CoolRunner-II CPLD
14 www.xilinx.com DS093 (v2.5) October 1, 2004
1-800-255-7778 Preliminary Product Specification
R
Figure 6: VQ100 Very Thin Quad Flat Pack
VQ100
Top View
GND
I/O(3)
VCCIO2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCIO2
I/O
I/O
I/O
GND
TDO
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC
I/O(2)
I/O(5)
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
VCCIO1
I/O
I/O
I/O
I/O
I/O
I/O
TDI
I/O
TMS
TCK
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
I/O
VCCIO1
I/O(1)
I/O(1)
I/O(1)
I/O(1)
V
AUX
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCIO1
GND
I/O(2)
I/O(2)
I/O(4)
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
(1) - Global Output Enable
(2) - Global Clock
(3) - Global Set/Reset
(4) - Clock Divide Reset
(5) - Data Gate
XC2C128 CoolRunner-II CPLD
DS093 (v2.5) October 1, 2004 www.xilinx.com 15
Preliminary Product Specification 1-800-255-7778
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Figure 7: CP132 Chip Scale Package
CP132
Bottom View
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
VCC VCCIO1 VCCIO1
GNDI/O I/O I/O I/O I/O I/O I/O I/O I/O
I/O(5)
I/O I/O
VAUX I/O I/O
I/O
I/O I/O
I/O I/O I/O
I/O
I/O I/O
I/O I/O VCCIO1
I/O
I/O I/O
I/O I/O GND
I/O
I/O I/O
I/O I/O GND
I/O
I/O I/O
VCCIO1 I/O GND
I/O
I/O I/O
I/O(2) VCC I/O
GND
NC I/O
NC I/O I/O
I/O(2)
I/O(1) VCCIO2 I/O
I/OI/O(3) I/O I/O I/O GND I/O I/O I/O VCCIO2
VCC
I/O I/O I/O
I/OGND I/O I/O I/O TDO NC I/O I/O GND
I/O(1)
I/O I/O NC
VCCIO2I/O(1) I/O I/O I/O I/O I/O I/O I/O I/O
I/O(1)
NC I/O I/O
I/OI/O I/O I/O I/O TDI TCK I/O I/O I/O
I/O(4)
GND I/O I/O
NCI/O I/O I/O I/O GND TMS I/O GND I/O
I/O(2)
(1) - Global Output Enable
(2) - Global Clock
(3) - Global Set/Reset
(4) - Clock Divide Reset
(5) - DataGATE Enable
XC2C128 CoolRunner-II CPLD
16 www.xilinx.com DS093 (v2.5) October 1, 2004
1-800-255-7778 Preliminary Product Specification
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Additional Information
CoolRunner-II Data sheets and Application Notes Dev ice Pac kag e s
Figure 8: TQ144 Thi n Qua d Flat Pack
VCC
I/O(1)
I/O(1)
I/O
I/O(1)
I/O(1)
I/O
VAUX
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
VCCIO1
I/O
GND
I/O(2)
NC
I/O(2)
NC
NC
I/O(4)
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
TQ144
Top View
VCC
I/O(2)
I/O(5)
I/O
I/O
NC
I/O
NC
I/O
NC
GND
NC
I/O
I/O
I/O
I/O
I/O
I/O
VCCIO1
I/O
I/O
I/O
I/O
I/O
I/O
GND
TDI
I/O
TMS
NC
TCK
I/O
I/O
I/O
I/O
GND
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
GND
NC
NC
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
VCCIO1
I/O
I/O
GND
GND
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
VCCIO1
GND
I/O(3)
NC
VCCIO2
I/O
NC
I/O
NC
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCIO2
I/O
I/O
I/O
GND
TDO
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
I/O
I/O
I/O
VCCIO2
(1) - Global Output Enable
(2) - Global Clock
(3) - Global Set/Reset
(4) - Clock Divide Reset
(5) - DataGATE Enable
XC2C128 CoolRunner-II CPLD
DS093 (v2.5) October 1, 2004 www.xilinx.com 17
Preliminary Product Specification 1-800-255-7778
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Revision Hist ory
The following table shows the revision history for this document.
Date Version Revision
10/01/02 1.0 Initial Xilinx release.
5/19/03 2.0 Added bin 6, 7 characterization data.
8/25/03 2.1 Edit Package diagram, other minor formating edits.
01/26/04 2.2 Update links.
03/01/04 2.3 Fixed cropping on Figure 6.
7/30/04 2.4 Added Pb-free documentation.
10/01/04 2.5 Add Asynchronous Preset/Reset Pulse Width specification to AC Electrical Characteristics.
