KM616FR2000T-300 - Samsung Semiconductor Division

CMOS SRAMKM616FV2000, KM616FS2000, KM616FR2000 Family

Revision 1.0

1March 1998

ocument Title

128K x16 bit Super Low Power and Low Voltage Full CMOS Static RAM

Revision History

The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and

products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.

Revision No.

0.0

0.1

1.0

Remark

Advance

Preliminary

Final

History

Design target

Initial draft

- Add KM616FV2000 Family

- Erase KM616FU1000 Family and KM616FS1000 Family supprot

2.3~3.3V operating Vcc.

- Concept change high power version to low low power version

ISB1=10µA(Max)

- Add super low power version with special handling

ISB1=2.0µA(Max)

- Reduce Icc & Icc1

Write : 25mA to 20mA at Vcc=3.6V(Max)

Finalize

- Change datasheet format

- Erase reverse type package

Draft Date

October 2, 1996

December 1, 1996

March 4, 1998

CMOS SRAMKM616FV2000, KM616FS2000, KM616FR2000 Family

Revision 1.0

2March 1998

128Kx16 bit Super Low Power and Low Voltage Full CMOS Static RAM

GENERAL DESCRIPTION

The KM616FV2000, KM616FS2000 and KM616FR2000

families are fabricated by SAMSUNG′s advanced Full

CMOS process technology. The families support various

operating temperature ranges for user flexibility of system

design. The families also support low data retention voltage

for battery back-up operation with low data retention current.

FEATURES

• Process Technology : Full CMOS

• Organization : 128Kx16

• Power Supply Voltage

KM616FV2000 Family : 3.0V ~ 3.6V

KM616FS2000 Family : 2.3V ~ 3.3V

KM616FR2000 Family : 1.8V ~ 2.7V

• Low Data Retention Voltage : 1.5V(Min)

• Three state output status and TTL Compatible

• Package Type : 44-TSOP2-400F

PIN DESCRIPTION

Name Function Name Function

CS Chip Select Input LB Lower Byte(I/O1~8)

OE Output Enable Input UB Upper Byte(I/O9~16)

WE Write Enable Input Vcc Power

A0~A16 Address Inputs Vss Ground

I/O1~I/O16 Data Inputs/Outputs N.C. No Connection

PRODUCT FAMILY

1. The parameter is measured with 30pF test load.

2. Super low power product=2µA with special handling.

Product Family Operating Temperature Vcc Range Speed(ns) Power Dissipation PKG Type

Standby

(ISB1, Max) Operating

(ICC2, Max)

KM616FV2000

Commercial(0~70°C)

3.0~3.6V 701)/85@VCC=3.3±0.3V

10µA2)

80mA

44-TSOP2-

Forward

KM616FS2000 2.3~3.3V 85@VCC=3.0±0.3V 80mA

1201)/150@VCC=2.5±0.2V 50mA

KM616FR2000 1.8~2.7V 3001)@VCC=2.0±0.2V 20mA

KM616FV2000I

Industrial(-40~85°C)

3.0~3.6V 701)/85@VCC=3.3±0.3V 80mA

KM616FS2000I 2.3~3.3V 85@VCC=3.0±0.3V 80mA

1201)/150@VCC=2.5±0.2V 50mA

KM616FR2000I 1.8~2.7V 3001)@VCC=2.0±0.2V 20mA

FUNCTIONAL BLOCK DIAGRAM

I/OI

I/O2

I/O3

I/O4

Vcc

Vss

I/O5

I/O6

I/O7

I/O8

A16

A15

A14

A13

A12

I/O16

I/O15

I/O14

I/O13

Vss

Vcc

I/O12

I/O11

I/O10

I/O9

N.C

A10

A11

N.C

44-TSOP2

Forward

SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.

Precharge circuit.

Memory array

1024 rows

128×16 columns

I/O Circuit

Column select

Clk gen.

Row

select

A9 A8 A5 A6 A7 A11 A10

A16

A14

A15

I/O1~I/O8

A12

Data

cont

Data

cont

Data

cont

I/O9~I/O16

Vcc

Vss

A13

Control

logic

CMOS SRAMKM616FV2000, KM616FS2000, KM616FR2000 Family

Revision 1.0

3March 1998

PRODUCT LIST

Commercial Temperature Products(0~70°C) Industrial Temperature Products(-40~85°C)

Part Name Function Part Name Function

KM616FV2000T-7

KM616FV2000T-8

KM616FS2000T-12

KM616FS2000T-15

KM616FR2000T-30

44-TSOP2 F, 70ns, 3.3V, LL

44-TSOP2 F, 85ns, 3.3V, LL

44-TSOP2 F, 120/85ns, 2.5/3.0V, LL

44-TSOP2 F, 150/85ns, 2.5/3.0V, LL

44-TSOP2 F, 300ns, 2.0/2.5V, LL

KM616FV2000TI-7

KM616FV2000TI-8

KM616FS2000TI-12

KM616FS2000TI-15

KM616FR2000TI-30

44-TSOP2 F, 70ns, 3.3V, LL

44-TSOP2 F, 85ns, 3.3V, LL

44-TSOP2 F, 120/85ns, 2.5/3.0V, LL

44-TSOP2 F, 150/85ns, 2.5/3.0V, LL

44-TSOP2 F, 300ns, 2.0/2.5V, LL

ABSOLUTE MAXIMUM RATINGS1)

1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be

restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

2. VIN/VOUT=-0.2 to 3.9V for KM616FV2000 Family.

3. VCC=-0.2 to 4.6V for KM616FV2000 Family

Item Symbol Ratings Unit Remark

Voltage on any pin relative to Vss VIN,VOUT -0.2 to 3.6V2) V-

Voltage on Vcc supply relative to Vss VCC -0.2 to 4.0V3) V-

Power Dissipation PD1.0 W-

Storage temperature TSTG -55 to 150 °C-

Operating Temperature TA0 to 70 °CKM616FV2000, KM616FS2000, KM616FR2000

-40 to 85 °CKM616FV2000I, KM616FS2000I, KM616FR2000I

Soldering temperature and time TSOLDER 260°C, 5sec (Lead Only) - -

FUNCTIONAL DESCRIPTION

1. X means don′t care. (Must be in low or high state)

CS OE WE LB UB I/O1~8 I/O9~16 Mode Power

HX1) X1) X1) X1) High-Z High-Z Deselected Standby

LH H X1) X1) High-Z High-Z Output Disabled Active

LX1) X1) H H High-Z High-Z Output Disabled Active

L L HLHDout High-Z Lower Byte Read Active

L L H H LHigh-Z Dout Upper Byte Read Active

L L HL L Dout Dout Word Read Active

LX1) L L HDin High-Z Lower Byte Write Active

LX1) LHLHigh-Z Din Upper Byte Write Active

LX1) LLL Din Din Word Write Active

CMOS SRAMKM616FV2000, KM616FS2000, KM616FR2000 Family

Revision 1.0

4March 1998

RECOMMENDED DC OPERATING CONDITIONS1)

Note

1 Commercial Product : TA=0 to 70°C, unless otherwise specified

Industrial Product : TA=-40 to 85°C, unless otherwise specified

2. Overshoot : Vcc + 1.0V in case of pulse width ≤20ns

3. Undershoot : -1.0V in case of pulse width ≤20ns

4. Overshoot and undershoot are sampled, not 100% tested.

Item Symbol Product Min Typ Max Unit

Supply voltage Vcc KM616FV2000 Family 3.0 3.3 3.6 V

KM616FS2000 Family 2.3 2.5/3.0 3.3

KM616FR2000 Family 1.8 2.0/2.5 2.7

Ground Vss All Family 0 0 0 V

Input high voltage VIH

KM616FV2000 Family Vcc=3.3±0.3V 2.2

-Vcc+0.22) V

KM616FS2000 Family Vcc=3.0±0.3V 2.2

Vcc=2.5±0.2V 2.0

KM616FR2000 Family Vcc=2.5±0.2V 2.0

Vcc=2.0±0.2V 1.6

Input low voltage VIL All Family -0.23) -0.4 V

CAPACITANCE1) (f=1MHz, TA=25°C)

1. Capacitance is sampled, not 100% tested

Item Symbol Test Condition Min Max Unit

Input capacitance CIN VIN=0V -8pF

Input/Output capacitance CIO VIO=0V -10 pF

DC AND OPERATING CHARACTERISTICS

1. Super low power product=2µA with special handling.

Item Symbol Test Conditions Min Typ Max Unit

Input leakage current ILI VIN=Vss to Vcc -1 -1µA

Output leakage current ILO CS=VIH or OE=VIH or WE=VIL, VIO=Vss to Vcc -1 -1µA

Operating power supply current ICC IIO=0mA, CS=VIL, VIN=VIL or VIH, Read - - 3mA

Average operating current

ICC1 Cycle time=1µs, 100% duty, IIO=0mA,

CS≤0.2V, VIN≤0.2V or VIN≥VCC-0.2V Read - - 7mA

Write - - 20

ICC2 Cycle time=Min, 100% duty,

IIO=0mA, CS=VIL, VIN=VIL or VIH

Vcc=3.3V@70ns - - 70 mA

Vcc=2.7V@120ns - - 60

Vcc=2.2V@300ns - - 20

Output low voltage VOL IOL

2.1mA at Vcc=3.0/3.3V - - 0.4 V

0.5mA at Vcc=2.5V - - 0.4

0.33mA at Vcc=2.0V - - 0.4

Output high voltage VOH IOH

-1.0mA at Vcc=3.0/3.3V 2.4 - - V

-0.5mA at Vcc=2.5V 2.0 - -

-0.44mA at Vcc=2.0V 1.6 - -

Standby Current(TTL) ISB CS=VIH, Other inputs=VIL or VIH - - 0.3 mA

Standby Current(CMOS) ISB1 CS≥Vcc-0.2V, Other inputs=0~Vcc - - 101) µA

CMOS SRAMKM616FV2000, KM616FS2000, KM616FR2000 Family

Revision 1.0

5March 1998

AC OPERATING CONDITIONS

TEST CONDITIONS (Test Load and Test Input/Output Reference)

Input pulse level : 0.4 to 2.2V for Vcc=3.3V, 3.0V, 2.5V

0.4 to 1.8V for Vcc=2.0V

Input rising and falling time : 5ns

Input and output reference voltage : 1.5V for Vcc=3.3V, 3.0V

1.1V for Vcc=2.5V

0.9V for Vcc=2.0V

Output load (See right) : CL=100pF+1TTL

CL=30pF+1TTL

CL1)

1. Including scope and jig capacitance

R23)

R12)

VTM3)

2. R1=3070Ω, R2=3150Ω

3. VTM =2.8V for VCC=3.0/3.3V

=2.3V for VCC=2.5V

=1.8V for VCC=2.0V

AC CHARACTERISTICS (Commercial product :TA=0 to 70°C, Industrial product : TA=-40 to 85°C

KM616FV2000 Family : Vcc=3.0~3.6V, KM616FS2000 Family : Vcc=2.3~3.3V,

KM616FR2000 Family : Vcc=1.8~2.7V)

Parameter List Symbol

Speed Bins

Units

70ns 85ns 120ns 150ns 300ns

Min Max Min Max Min Max Min Max Min Max

Read

Read cycle time tRC 70 -85 -120 -150 -300 -ns

Address access time tAA -70 -85 -120 -150 -300 ns

Chip select to output tCO -70 -85 -120 -150 -300 ns

Output enable to valid output tOE -35 -45 -60 -75 -150 ns

UB, LB Access Time tBA -35 -45 -60 -75 -150 ns

Chip select to low-Z output tLZ 10 -10 -20 -20 -50 -ns

Output enable to low-Z output tOLZ, tBLZ 5-5-20 -20 -30 -ns

Chip disable to high-Z output tHZ 0 25 0 25 0 35 0 40 0 60 ns

Output disable to high-Z output tOHZ, tBHZ 0 25 0 25 0 35 0 40 0 60 ns

Output hold from address change tOH 10 -15 -15 -15 -30 -ns

Write

Write cycle time tWC 70 -85 -120 -150 -300 -ns

Chip select to end of write tCW 60 -70 -100 -120 -300 -ns

Address set-up time tAS 0-0-0-0-0-ns

Address valid to end of write tAW 65 -70 -100 -120 -300 -ns

Write pulse width tWP 55 -60 -80 -100 -200 -ns

UB, LB Valid to End of Write tBW 65 -70 -100 -120 -300 -ns

Write recovery time tWR 0-0-0-0-0-ns

Write to output high-Z tWHZ 0 25 0 25 0 35 0 40 0 60 ns

Data to write time overlap tDW 30 -35 -50 -60 -120 -ns

Data hold from write time tDH 0-0-0-0-0-ns

End write to output low-Z tOW 5-5-5-5-20 -ns

DATA RETENTION CHARACTERISTICS

1. Super low power product=2µA with special handling.

Item Symbol Test Condition Min Typ Max Unit

Vcc for data retention VDR CS≥Vcc-0.2V 1.5 -3.6 V

Data retention current IDR Vcc=3.0V, CS≥Vcc-0.2V - - 101) µA

Data retention set-up time tSDR See data retention waveform 0- - ns

Recovery time tRDR tRC - -

CMOS SRAMKM616FV2000, KM616FS2000, KM616FR2000 Family

Revision 1.0

6March 1998

Address

Data Out Previous Data Valid Data Valid

TIMMING DIAGRAMS

TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH, UB or/and LB=VIL)

TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)

Data Valid

High-Z

tRC

Address

UB, LB

Data out

tAA

tRC

tOH

tAA

tCO

tBA

tOE

tOLZ

tBLZ

tLZ tOHZ

tBHZ

tHZ

NOTES (READ CYCLE)

1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage

levels.

2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device

interconnection.

CMOS SRAMKM616FV2000, KM616FS2000, KM616FR2000 Family

Revision 1.0

7March 1998

TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)

Address

Data Undefined

UB, LB

Data in

Data out

TIMING WAVEFORM OF WRITE CYCLE(2) (CS Controlled)

Address

Data Valid

UB, LB

Data in

Data out High-Z High-Z

tWC

tCW(2) tWR(4)

tAWtBW

tWP(1)

tAS(3) tDH

tDW

tWHZ tOW

tWC

tCW(2)

tAW tBW

tWP(1)

tDH

tDW

tWR(4)

High-Z High-Z

Data Valid

tAS(3)

CMOS SRAMKM616FV2000, KM616FS2000, KM616FR2000 Family

Revision 1.0

8March 1998

Address

Data Valid

UB, LB

Data in

Data out High-Z High-Z

TIMING WAVEFORM OF WRITE CYCLE(3) (UB, LB Controlled)

NOTES (WRITE CYCLE)

1. A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB

or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transi-

tion when CS goes high and WE goes high. The tWP is measured from the beginning of write to the end of write.

2. tCW is measured from the CS going low to end of write.

3. tAS is measured from the address valid to the beginning of write.

4. tWR is measured from the end or write to the address change. tWR applied in case a write ends as CS or WE going high.

tWC

tCW(2)

tBW

tWP(1)

tDH

tDW

tWR(4)

tAW

DATA RETENTION WAVE FORM

CS controlled

VCC

3.0/2.7/2.3/1.8V

2.2V

VDR

GND

Data Retention Mode

CS≥VCC - 0.2V

tSDR tRDR

tAS(3)

CMOS SRAMKM616FV2000, KM616FS2000, KM616FR2000 Family

Revision 1.0

9March 1998

44 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400F)

Unit : millimeter(inch)

0.002

0.05

#22

#44 #23

0.35±0.10

0.014±0.004 0.80

0.0315

MIN.

0.047

1.20MAX.

0.741

18.81MAX.

18.41±.10

0.725±0.004

11.76±0.20

0.463±0.008

+ 0.10

- 0.05

0.50

+ 0.004

- 0.002

0.15

0.006

0.020

10.16

0.400

0.10

0.004

PACKAGE DIMENSIONS

0~8°

0.45 ~0.75

0.018 ~ 0.030

0.25

( )

0.010

( )

0.805

0.032

( )

MAX

1.00±0.10

0.039±0.004