General Description
The MAX1964/MAX1965 power-supply controllers are
designed to address cost-sensitive applications
demanding voltage sequencing/tracking, such as
cable modem consumer premise equipment (CPE),
xDSL CPE, and set-top boxes. Operating off a low-cost,
unregulated DC supply (such as a wall adapter output),
the MAX1964 generates three positive outputs and the
MAX1965 generates four positive outputs and one neg-
ative output to provide an inexpensive system power
supply.
The MAX1964 includes a current-mode synchronous
step-down controller and two positive regulator gain
blocks. The MAX1965 has one additional positive gain
block and one negative regulator gain block. The main
synchronous step-down controller generates a high-
current output that is preset to 3.3V or adjustable from
1.236V to 0.75 ✕VIN with an external resistive-divider.
The 200kHz operating frequency allows the use of low-
cost aluminum-electrolytic capacitors and low-cost
power magnetics. Additionally, the MAX1964/MAX1965
step-down controllers sense the voltage across the low-
side MOSFET’s on-resistance to efficiently provide the
current-limit signal, eliminating the need for costly cur-
rent-sense resistors.
The MAX1964/MAX1965 generate additional supply
rails at low cost. The positive regulator gain blocks use
an external PNP pass transistor to generate low voltage
rails directly from the main step-down converter (such
as 2.5V or 1.8V from the main 3.3V output) or higher
voltages using coupled windings from the step-down
converter (such as 5V, 12V, or 15V). The MAX1965’s
negative gain block uses an external NPN pass transis-
tor in conjunction with a coupled winding to generate
-5V, -12V, or -15V.
All output voltages are externally adjustable, providing
maximum flexibility. During startup, the MAX1964 fea-
tures voltage sequencing and the MAX1965 features
voltage tracking. Both controllers provide a power-
good output that monitors all of the output voltages.
Applications
xDSL, Cable, and ISDN Modems
Set-Top Boxes
Wireless Local Loop
Features
♦4.5V to 28V Input Voltage Range
♦Master DC-DC Step-Down Converter:
Preset 3.3V or Adjustable (1.236V to 0.75 x VIN)
Output Voltage
Fixed Frequency (200kHz) PWM Controller
No Current-Sense Resistor
Adjustable Current Limit
95% Efficient
Soft-Start
♦Two (MAX1964)/Four (MAX1965) Analog Gain
Blocks:
Positive Analog Blocks Drive Low-Cost PNP
Pass Transistors to Build Positive Linear
Regulators
Negative Analog Block (MAX1965) Drives a
Low-Cost NPN Pass Transistor to Build a
Negative Linear Regulator
♦Power-Good Indicator
♦Voltage Sequencing (MAX1964) or Tracking
(MAX1965)
MAX1964/MAX1965
Tracking/Sequencing Triple/Quintuple
Power-Supply Controllers
________________________________________________________________ Maxim Integrated Products 1
TOP VIEW
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
POK IN
VL
BST
DH
LX
DL
GND
ILIM
MAX1964
16-Pin QSOP
COMP
OUT
FB2
FB
B2
B3
FB3
IN
VL
BST
DH
LX
DL
GND
ILIM
POK
COMP
OUT
FB2
FB
B2
B3
FB3
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
12
11
9
10
FB5
B5FB4
B4
MAX1965
20-Pin QSOP
Pin Configurations
19-2084; Rev 0; 7/01
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Typical Operating Circuit appears at end of data sheet.
Ordering Information
PA RT TEMP.
RANGE
PIN-
PACKAGE
fOSC
(kHz)
MAX1964TEEE -40°C to +85°C16 QSOP 200
MAX1965TEEP -40°C to +85°C20 QSOP 200
MAX1964/MAX1965
Tracking/Sequencing Triple/Quintuple
Power-Supply Controllers
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
IN, B2, B3, B4 to GND............................................-0.3V to +30V
B5 to OUT...............................................................-20V to +0.3V
VL, POK, FB, FB2, FB3, FB4, FB5 to GND ...............-0.3V to +6V
LX to BST..................................................................-6V to +0.3V
BST to GND ............................................................-0.3V to +36V
DH to LX....................................................-0.3V to (VBST + 0.3V)
DL, OUT, COMP, ILIM to GND......................-0.3V to (VL+ 0.3V)
VL Output Current ...............................................................50mA
VL Short Circuit to GND..................................................≤100ms
Continuous Power Dissipation (TA= +70°C)
16-Pin QSOP (derate 8.3mW/°C above +70°C)...........666mW
20-Pin QSOP (derate 9.1mW/°C above +70°C)...........727mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
ELECTRICAL CHARACTERISTICS
(VIN = 12V, ILIM = FB = GND, VBST - VLX = 5V, TA= 0°C to +85°C. Typical values are at TA= +25°C, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
GENERAL
Operating Input Voltage Range
(Note 1) VIN 4.5 28 V
MAX1964 1.25 2.5
Quiescent Supply Current IIN
VFB = 0, VOUT = 4V,
VFB2 = VFB3 = VFB4 = 1.5V,
VFB5 = -0.1V MAX1965 1.5 3.0
mA
VL REGULATOR
Output Voltage VL 6V < VIN < 28V, 0.1mA < ILOAD <20mA 4.75 5.00 5.25 V
Line Regulation VIN = 6V to 28V 3.0 %
Undervoltage Lockout Trip Level VUVLO VL rising, 3% hysteresis (typ) 3.2 3.5 3.8 V
Minimum Bypass Capacitance CBYP
(
MIN
)
10mΩ < ESR < 500mΩ1µF
DC-DC CONTROLLER
Output Voltage (Preset Mode) VOUT FB = GND 3.272 3.34 3.355 V
Typical Output Voltage Range
(Adjustable Mode) (Note 2) VOUT VSET 0.75 ✕ VIN V
FB Set Voltage (Adjustable
Mode) VSET FB = COMP 1.221 1.236 1.252 V
FB Dual-Mode™ Threshold 50 100 150 mV
FB Input Leakage Current IFB VFB = 1.5V 0.01 100 nA
FB to COMP Transconductance gmFB = COMP, ICOMP = ±5µA 70 100 140 µS
Current-Sense Amplifier Voltage
Gain ALIM VIN - VLX = 250mV 4.46 4.9 5.44 V/V
Current-Limit Threshold
(Internal Mode) VVALLEY VILIM = 5.0V 190 250 310 mV
Current-Limit Threshold
(External Mode) VVALLEY VILIM = 2.5V 440 530 620 mV
Switching Frequency fOSC 160 200 240 kHz
Dual Mode is a trademark of Maxim Integrated Products, Inc.
MAX1964/MAX1965
Tracking/Sequencing Triple/Quintuple
Power-Supply Controllers
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS
(VIN = 12V, ILIM = FB = GND, VBST - VLX = 5V, TA= 0°C to +85°C. Typical values are at TA= +25°C, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Maximum Duty Cycle DMAX 77 82 90 %
Soft-Start Period tSOFT 1024 1/fOSC
Soft-Start Step Size VREF/64 V
FB Power-Up Sequence
Threshold MAX1964, FB rising, B2 turns on 1.145 V
DH Output Low Voltage ISINK = 10mA, measured from DH to LX 40 mV
DH Output High Voltage IS OU RC E
= 10m A, m easur ed fr om BS T to D H 40 mV
DL Output Low Voltage ISINK = 10mA, measured from DL to GND 20 mV
DL Output High Voltage IS OU RC E
= 10m A, m easur ed fr om D L to GN D VL - 0.1 V
DH On-Resistance High (DH to BST) and low (DH to LX) 1.5 4 Ω
High (DL to VL) 4.3 10
DL On-Resistance Low (DL to GND) 0.7 2 Ω
Output Drive Current Sourcing or sinking, VDH or VDL = VL/2 0.5 A
LX, BST Leakage Current VBST = VLX = VIN = 28V, VFB = 1.5V 0.04 10 µA
POSITIVE ANALOG GAIN BLOCKS
FB2, FB3, FB4 Regulation
Voltage
VB2 = VB3 = VB4 = 5V,
IB2 = IB3 = IB4 = 1mA (sink) 1.226 1.24 1.257 V
FB2 Power-Up Sequence
Threshold MAX1964, FB2 rising, B3 turns on 1.145 V
FB2, FB3, FB4 to B_
Transconductance Error ∆VFB_VB2 = VB3 = VB4 = 5V, IB2 = IB3 = IB4 =
0.5mA to 5mA (sink) 13 22 mV
Feedback Input Leakage
Current IFB_V
FB2 = VFB3 = VFB4 = 1.5V 0.01 100 nA
VB2 = VB3 = VB4 = 2.5V 10 21
Driver Sink Current IB_VFB2 = VFB3 =
VFB4 = 1.188V VB2 = VB3 = VB4 = 4.0V 24 mA
NEGATIVE ANALOG GAIN BLOCK
FB5 Regulation Voltage VB5 = VOUT - 2V, VOUT = 3.5V, IB5 = 1mA
(source) -20 -5 +10 mV
FB5 to B5 Tr anscond uctance E r r or ∆VFB5 VB5 = 0, IB5 = 0.5mA to 5mA (source) -13 -20 mV
Feedback Input Leakage Current IFB5 VFB5 = -100mV 0.01 100 nA
Driver Source Current IB5 VFB5 = 200mV, VB5 = VOUT - 2.0V, VOUT =
3.5V 10 25 mA
POWER GOOD (POK)
OUT Trip Level (Preset Mode) FB = GND, falling edge, 3% hysteresis (typ) 2.88 3.0 3.12 V
FB Trip Level (Adjustable Mode) Falling edge, 3% hysteresis (typ) 1.070 1.114 1.159 V
FB2, FB3, FB4 Trip Level Falling edge, 3% hysteresis (typ) 1.070 1.114 1.159 V
FB5 Trip Level Rising edge, 35mV hysteresis (typ) 368 530 632 mV
POK Output Low Level ISINK = 1mA 0.4 V
POK Output High Leakage VPOK = 5V 1 µA
MAX1964/MAX1965
Tracking/Sequencing Triple/Quintuple
Power-Supply Controllers
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS
(VIN = 12V, ILIM = FB = GND, VBST - VLX = 5V, TA= -40°C to +85°C, unless otherwise noted.) (Note 4)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
GENERAL
Operating Input Voltage Range
(Note 1) VIN 4.5 28 V
MAX1964 2.5
Quiescent Supply Current IIN
VFB = 0, VOUT = 4V,
VFB2 = VFB3 = VFB4 = 1.5V,
VFB5 = -0.1V MAX1965 3.0
mA
VL REGULATOR
Output Voltage VL 6V < VIN < 28V, 0.1mA < ILOAD <20mA 4.75 5.25 V
Line Regulation VIN = 6V to 28V 3.0 %
Undervoltage Lockout Trip Level VUVLO VL rising, 3% hysteresis (typ) 3.0 4.0 V
DC-DC CONTROLLER
Output Voltage (Preset Mode) VOUT FB = GND 3.247 3.38 V
Feedback Set Voltage
(Adjustable Mode) VSET FB = COMP 1.211 1.261 V
Current-Sense Amplifier Voltage
Gain ALIM VIN - VLX = 250mV 4.12 5.68 V/V
Current-Limit Threshold
(Internal Mode) VVALLEY VILIM = 5.0V 150 350 mV
Current-Limit Threshold
(External Mode) VVALLEY VILIM = 2.5V 400 660 mV
Switching Frequency fOSC 160 240 kHz
Maximum Duty Cycle DMAX 74 90 %
POSITIVE ANALOG GAIN BLOCKS
FB2, FB3, FB4 Regulation
Voltage
VB2 = VB3 = VB4 = 5V,
IB2 = IB3 = IB4 = 1mA (sink) 1.215 1.265 V
FB2, FB3, FB4 to B_
Transconductance Error ∆VFB_VB2 = VB3 = VB4 = 5V, IB2 = IB3 = IB4 =
0.5mA to 5mA (sink) 28 mV
ELECTRICAL CHARACTERISTICS (continued)
(VIN = 12V, ILIM = FB = GND, VBST - VLX = 5V, TA= 0°C to +85°C. Typical values are at TA= +25°C, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
THERMAL PROTECTION (NOTE 3)
Thermal Shutdown Rising temperature 160 °C
Thermal Shutdown Hysteresis 15 °C
MAX1964/MAX1965
Tracking/Sequencing Triple/Quintuple
Power-Supply Controllers
_______________________________________________________________________________________ 5
Note 1: Connect VL to IN for operation with VIN < 5V.
Note 2: See Output Voltage Selection section.
Note 3: The internal 5V linear regulator (VL) powers the thermal shutdown block. Shorting VL to GND disables thermal shutdown.
Note 4: Specifications to -40°C are guaranteed by design, not production tested.
ELECTRICAL CHARACTERISTICS (continued)
(VIN = 12V, ILIM = FB = GND, VBST - VLX = 5V, TA= -40°C to +85°C, unless otherwise noted.) (Note 4)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
NEGATIVE ANALOG GAIN BLOCK
FB5 Regulation Voltage VB5 = VOUT - 2V, VOUT = 3.5V,
IB5 = 1mA (source) -25 +10 mV
FB5 to B5 Tr anscond uctance E r r or ∆VFB5 VB5 = 0, IB5 = 0.5mA to 5mA (source) -30 mV
POWER GOOD (POK)
OUT Trip Level (Preset Mode) FB = GND, falling edge, 3% hysteresis (typ) 2.85 3.15 V
FB Trip Level (Adjustable Mode) Falling edge, 3% hysteresis (typ) 1.058 1.17 V
FB2, FB3, FB4 Trip Level Falling edge, 3% hysteresis (typ) 1.058 1.17 V
FB5 Trip Level Rising edge, 35mV hysteresis (typ) 325 675 mV
Typical Operating Characteristics
(Circuit of Figure 1, VIN = 12V, VOUT = 3.3V, TA= +25°C, unless otherwise noted.)
50
0.01 1010.1
EFFICIENCY vs. LOAD CURRENT
(PRESET MODE)
100
70
60
90
80
MAX1964/65 toc01
LOAD CURRENT (A)
EFFICIENCY (%)
VIN = 6.5V
VIN = 8V
VIN = 12V
VIN = 18V
VIN = 24V
VOUT = 3.3V
3.27
3.29
3.28
3.31
3.30
3.32
3.33
0 1.0 1.50.5 2.0 2.5 3.0
OUTPUT VOLTAGE vs. LOAD CURRENT
(PRESET MODE)
MAX1964/65 toc02
LOAD CURRENT (A)
OUTPUT VOLTAGE (V)
50
0.01 1010.1
EFFICIENCY vs. LOAD CURRENT
(ADJUSTABLE MODE)
100
70
60
90
80
MAX1964/65 toc03
LOAD CURRENT (A)
EFFICIENCY (%)
VIN = 6.5V
VIN = 8V
VIN = 12V
VIN = 18V
VIN = 24V
VOUT = +5.0V
MAX1964/MAX1965
Tracking/Sequencing Triple/Quintuple
Power-Supply Controllers
6 _______________________________________________________________________________________
Typical Operating Characteristics (continued)
(Circuit of Figure 1, VIN = 12V, VOUT = 3.3V, TA= +25°C, unless otherwise noted.)
1.00.50 1.5 2.0
OUPUT VOLTAGE vs. LOAD CURRENT
(ADJUSTABLE MODE)
MAX1964/65 toc04
LOAD CURRENT (A)
OUTPUT VOLTAGE (V)
4.97
4.99
5.01
4.95
5.03
5.05
4.95
4.97
4.99
5.01
5.03
5.05
0105 15202530
INTERNAL 5V LINEAR REGULATOR
vs. LOAD CURRENT
MAX1964/65 toc05
LOAD CURRENT (mA)
VL (V)
LOAD TRANSIENT
(STEP-DOWN CONVERTER)
MAX1964/65 toc06
5.0V
0
1A
A. VOUT = 5V, 100mV/div
B. IOUT = 10mA TO 1A, 500mA/div
VIN = 12V
B
A
40µs/div
SWITCHING WAVEFORMS
(STEP-DOWN CONVERTER)
MAX1964/65 toc07
5.00V
A. VOUT = 5.0V, 50mV/div
B. VLX,10V/div
C. INDUCTOR CURRENT, 500mA/div
VIN = 12V, ROUT1 = 5V
B
A
40µs/div
C
4.95V
12V
0
1A
0.5A
SOFT-START
(STEP-DOWN CONVERTER)
MAX1964/65 toc08
5V
A. VL = 5V, 5V/div
B. VOUT1 = 5V (ADJ),2V/div
C. INDUCTOR CURRENT, 1A/div
VIN = STEPPED FROM 0 TO 12V, ROUT1 = 10Ω
B
A
1ms/div
C
0
5V
0
1A
0
MAX1964 STARTUP WAVEFORM
(VOLTAGE SEQUENCING)
MAX1964/65 toc09
5V
A. VOUT1 = 5V (ADJ), 2V/div
B. VOUT2 = 1.8V, 1V/div
C. VOUT3 = 3.3V, 2V/div
D. VPOK, 5V/div
VIN = STEPPED FROM 0 TO 12V, ROUT1 = 5Ω
B
A
200µs/div
C
1.8V
3.3V
D
MAX1964/MAX1965
Tracking/Sequencing Triple/Quintuple
Power-Supply Controllers
_______________________________________________________________________________________ 7
2.42
2.44
2.46
2.48
2.50
243 5678
POSITIVE LINEAR REGULATOR
OUTPUT VOLTAGE vs. SUPPLY VOLTAGE
(QLDO = 2N3905)
MAX1964/65 toc13
SUPPLY VOLTAGE (V)
OUTPUT VOLTAGE (V)
IOUT2 = 1mA
IOUT2 = 100mA
80
70
60
50
40
30
20
10
0
0.1 10 10011000
POSITIVE LINEAR REGULATOR
POWER-SUPPLY REJECTION RATIO
(QLDO = 2N3905)
MAX1964/65 toc14
FREQUENCY (kHz)
PSRR (dB)
IOUT2 = 50mA
POSITIVE LINEAR REGULATOR
LOAD TRANSIENT
(QLDO = 2N3905)
MAX1964/65 toc15
100mA
2.457V
2.467V
A. IOUTZ = 1mA TO 100mA, 50mA/div
B. VOUTZ = 2.5V, 5mV/div
CLDO(POS) = 10µF CERAMIC, VSUP(POS) = 3.3V
CIRCUIT OF FIGURE 1
0
B
A
10µs/div
Typical Operating Characteristics (continued)
(Circuit of Figure 1, VIN = 12V, VOUT = 3.3V, TA= +25°C, unless otherwise noted.)
MAX1965 STARTUP WAVEFORM
(VOLTAGE TRACKING)
MAX1964/65 toc10
4V
A. VOUT4 = 5.0V, 2V/div D. VOUT3 = 1.8V/div
B. VOUT1 = 3.3V, 2V/div E. VOUT5 = -5.0V, 2V/div
C. VOUT2 = 2.5V, 2V/div F. VPOK, 5V/div
VIN = STEPPED FROM 0 TO 12V,
ROUT1 = 6.6Ω
CIRCUIT OF FIGURE 6
B
A
400µs/div
C
2V
0
D
E
F
-2V
-4V
5V
0
0
5
10
15
20
25
30
35
40
0246810
POSITIVE LINEAR REGULATOR BASE-
DRIVE CURRENT vs. BASE-DRIVE VOLTAGE
MAX1964/65 toc11
BASE VOLTAGE (V)
BASE-DRIVE SINK CURRENT (mA)
VFB_ = 1.0V
VFB_ = 0.96VREF
B2, B3 AND B4
(MAX1965) ONLY
2.50
0.01 10.1 100
POSITIVE LINEAR REGULATOR
OUTPUT VOLTAGE vs. LOAD CURRENT
(QLDO = 2N3905)
2.42
2.44
2.46
2.48
MAX1964/65 toc12
LOAD CURRENT (mA)
OUTPUT VOLTAGE (V)
10 1000
VSUP(POS) = 5.0V
VSUP(POS) = 3.3V
MAX1964/MAX1965
Tracking/Sequencing Triple/Quintuple
Power-Supply Controllers
8 _______________________________________________________________________________________
Typical Operating Characteristics (continued)
(Circuit of Figure 1, VIN = 12V, VOUT = 3.3V, TA= +25°C, unless otherwise noted.)
2.42
2.44
2.46
2.48
2.50
2 4 6 8 10 12
POSITIVE LINEAR REGULATOR
OUTPUT VOLTAGE vs. SUPPLY VOLTAGE
(QLDO = TIP30)
MAX1964/65 toc17
SUPPLY VOLTAGE (V)
OUTPUT VOLTAGE (V)
IOUT2 = 1mA
IOUT2 = 100mA
80
70
60
50
40
30
20
10
0
0.1 10 1001 1000
POSITIVE LINEAR REGULATOR
POWER-SUPPLY REJECTION RATIO
(QLDO = TIP30)
MAX1964/65 toc18
FREQUENCY (kHz)
PSRR (dB)
IOUT2 = 150mA
POSITIVE LINEAR REGULATOR
LOAD TRANSIENT
(QLDO = TIP30)
MAX1964/65 toc19
250mA
2.453V
2.473V
A. IOUT2 = 10mA TO 250mA, 200mA/div
B. VOUT2 = 2.5V, 10mV/div
CLDO(POS) = 10µF CERAMIC, VSUP(POS) = 3.3V
CIRCUIT OF FIGURE 1
0
B
A
10µs
0
10
5
25
20
15
40
35
30
45
0426810
NEGATIVE LINEAR REGULATOR BASE-
DRIVE CURRENT vs. BASE-DRIVE VOLTAGE
MAX1964/65 toc20
VOUT - VB5 (V)
BASE-DRIVE SOURCE CURRENT (mA)
VFB5 = 250mV
VFB5 = 50mV
VOUT = 5.0V
VOUT = 3.3V
B5 (MAX1965) ONLY
-12.00
-12.06
-12.12
-12.18
-12.24
0.01 1 10 1000.1 1000
NEGATIVE LINEAR REGULATOR
OUTPUT VOLTAGE vs. LOAD CURRENT
(QLDO = TIP29)
MAX1964/65 toc21
LOAD CURRENT (mA)
OUTPUT VOLTAGE (V)
VSUP(NEG) = -15V
VOUT3 = 5V
MAX1964/MAX1965
Tracking/Sequencing Triple/Quintuple
Power-Supply Controllers
_______________________________________________________________________________________ 9
-12.24
-12.18
-12.12
-12.06
-12.00
-20 -18 -16 -14 -12 -10
NEGATIVE LINEAR REGULATOR
OUTPUT VOLTAGE vs. SUPPLY VOLTAGE
(QLDO = TIP29)
MAX1964/65 toc22
SUPPLY VOLTAGE (V)
OUTPUT VOLTAGE (V)
ILDO(NEG) = 100mA
ILDO(NEG) = 1mA
Pin Description
PIN
MAX1964 MAX1965 NAME FUNCTION
1 1 POK
Open-Drain Power-Good Output. POK is low when any output voltage is more than
10% below its regulation point. POK is high impedance when all the outputs are in
regulation. Connect a resistor between POK and VL for logic-level voltages.
2 2 COMP Compensation Pin. Connect the compensation network to GND to compensate the
control loop.
3 3 OUT Regulated Output Voltage High-Impedance Sense Input. Internally connected to a
resistive-divider and negative gain block (MAX1965).
44FB
Dual-Mode Switching-Regulator Feedback Input. Connect to GND for the preset 3.3V
output. Connect to a resistive-divider from the output to FB to GND to adjust the output
voltage between 1.236V and 0.75 ✕ VIN. The feedback set point is 1.236V.
55B2
Open-Drain Output PNP Transistor Driver (Regulator 2). Internally connected to the
drain of a DMOS. B2 connects to the base of an external PNP pass transistor to form a
positive linear regulator.
6 6 FB2
Analog Gain Block Feedback Input (Regulator 2). Connect to a resistive-divider
between the positive linear regulator’s output and GND to adjust the output voltage.
The feedback set point is 1.24V.
Typical Operating Characteristics (continued)
(Circuit of Figure 1, VIN = 12V, VOUT - 3.3V, TA= +25°C, unless otherwise noted.)
MAX1964/MAX1965
Tracking/Sequencing Triple/Quintuple
Power-Supply Controllers
10 ______________________________________________________________________________________
Pin Description (continued)
PIN
MAX1964 MAX1965 NAME FUNCTION
77B3
Open-Drain Output PNP Transistor Driver (Regulator 3). Internally connected to the
drain of a DMOS. B3 connects to the base of an external PNP pass transistor to form a
positive linear regulator.
8 8 FB3
Analog Gain Block Feedback Input (Regulator 3). Connect to a resistive-divider
between the positive linear regulator’s output and GND to adjust the output voltage.
The feedback set point is 1.24V.
—9B4
Open-Drain Output PNP Transistor Driver (Regulator 4). Internally connected to the
drain of a DMOS. B4 connects to the base of an external PNP pass transistor to form a
positive linear regulator.
—10 FB4
Analog Gain Block Feedback Input (Regulator 4). Connect to a resistive-divider
between the positive linear regulator’s output and GND to adjust the output voltage.
The feedback set point is 1.24V.
—11 B5
Open-Drain Output NPN Transistor Driver (Regulator 5). Internally connected to the
drain of a P-channel MOSFET. B5 connects to the base of an external NPN pass
transistor to form a negative linear regulator.
—12 FB5
Analog Gain Block Feedback Input (Regulator 5). Connect to a resistive-divider
between the negative linear regulator’s output and a positive reference voltage,
typically one of the positive linear regulator outputs, to adjust the output voltage. The
feedback set point is at GND.
9 13 ILIM
Dual-Mode Current-Limit Adjustment Input. Connect to VL for the default 250mV
current-limit threshold. In adjustable mode, the current-limit threshold voltage is 1/5 th
the voltage present at ILIM. Connect to a resistive-divider between VL and GND to
adjust VILIM between 500mV and 2.5V. The logic threshold for switchover to the 250mV
default value is approximately VL - 1V.
10 14 GND Ground
11 15 DL Low-Side Gate-Driver Output. DL swings between GND and VL.
12 16 LX Inductor Connection. Used for current-sense between IN and LX, and used for current-
limit between LX and GND.
13 17 DH High-Side Gate-Driver Output. DH swings between LX and BST.
14 18 BST Boost Flying Capacitor Connection. Connect BST to the external boost diode and
capacitor as shown in the Standard Application Circuit.
15 19 VL
Internal 5V Linear Regulator Output. Supplies the IC and powers the DL low-side gate
driver and external boost diode and capacitor. Bypass with a 1µF or greater ceramic
capacitor to GND.
16 20 IN Input Supply Voltage. 4.5V to 28V. Bypass to GND with a 1µF or greater ceramic
capacitor close to the IC.
MAX1964/MAX1965
Tracking/Sequencing Triple/Quintuple
Power-Supply Controllers
______________________________________________________________________________________ 11
Detailed Description
The MAX1964/MAX1965 power-supply controllers pro-
vide system power for cable and xDSL modems. The
main step-down DC-DC controller operates in a cur-
rent-mode pulse-width-modulation (PWM) control
scheme to ease compensation requirements and pro-
vide excellent load and line transient response.
The MAX1964 includes two analog gain blocks to regu-
late two additional positive auxiliary output voltages,
and the MAX1965 includes four analog gain blocks to
regulate three additional positive and one negative aux-
iliary output voltages. The positive regulator gain blocks
can be used to generate low voltage rails directly from
the main step-down converter or higher voltages using
coupled windings from the step-down converter. The
Figure 1. MAX1964 Standard Application Circuit
BST
C1
1µF
D1
CENTRAL CMPSH-3
C2
1µF
NH
NL
CBST
0.1µF
RPOK
100kΩ
CCOMP1
470pF
CCOMP2
47pF
COUT
1000µF
CIN
470µF
DH
LX
VOUT1
5V AT 1A
INPUT
9V TO 18V
DL
OUT
GND
TO LOGIC
IN
VL
ILIM
POK
COMP
MAX1964
FB
RCOMP
5MΩ
RGATE(NH)
10Ω
L1
33µH
RGATE(NL)
10Ω
RBE2
220Ω
C3
1µF
Q1
TIP30
R3
4.64kΩ
R1
30kΩ
R2
10kΩ
VOUT2
1.8V AT 300mA
C4
10µF
R4
10kΩ
B2
FB2
B3
FB3
CBE2
2200pF
INTERNATIONAL
RECTIFIER
IRF7101
RBE3
220Ω
C5
1µF
Q2
TIP32
POWER GROUND
ANALOG GROUNDCOUT : 1000µF, 10V SANYO (CZ SERIES)
R5
4.99kΩVOUT3
3.3V AT 750mA
C6
10µF
R4
3.0kΩ
CBE3
1000pF
MAX1964/MAX1965
negative gain block can be used in conjunction with a
coupled winding to generate -5V, -12V, or -15V.
DC-DC Controller
The MAX1964/MAX1965 step-down converters use a
pulse-width-modulated (PWM) current-mode control
scheme (Figure 2). An internal transconductance ampli-
fier establishes an integrated error voltage at the COMP
pin. The heart of the current-mode PWM controller is an
open-loop comparator that compares the integrated
voltage-feedback signal against the amplified current-
sense signal plus the slope compensation ramp. At
each rising edge of the internal clock, the high-side
MOSFET turns on until the PWM comparator trips or the
maximum duty cycle is reached. During this on-time,
current ramps up through the inductor, sourcing current
to the output and storing energy in a magnetic field.
The current-mode feedback system regulates the peak
inductor current as a function of the output voltage error
signal. Since the average inductor current is nearly the
same as the peak inductor current (assuming that the
inductor value is relatively high to minimize ripple cur-
rent), the circuit acts as a switch-mode transconduc-
tance amplifier. It pushes the output LC filter pole,
normally found in a voltage-mode PWM, to a higher fre-
quency. To preserve inner-loop stability and eliminate
inductor stair casing, a slope-compensation ramp is
summed into the main PWM comparator.
During the second-half of the cycle, the high-side MOS-
FET turns off and the low-side N-Channel MOSFET
turns on. Now the inductor releases the stored energy
as its current ramps down, providing current to the out-
put. Therefore, the output capacitor stores charge when
the inductor current exceeds the load current, and dis-
charges when the inductor current is lower, smoothing
the voltage across the load. Under overload conditions
when the inductor current exceeds the selected cur-
rent-limit (see the Current Limit section), the high-side
MOSFET is not turned on at the rising edge of the clock
and the low-side MOSFET remains on to let the inductor
current ramp down.
The MAX1964/MAX1965 operate in a forced-PWM
mode, so even under light loads, the controller main-
tains a constant switching frequency to minimize cross-
regulation errors in applications that use a transformer.
So the low-side gate-drive waveform is the complement
of the high-side gate-drive waveform, which causes the
inductor current to reverse under light loads.
Current-Sense Amplifier
The one MAX1964/MAX1965’s one current-sense circuit
amplifies (AV= 4.9) the current-sense voltage
generated by the high-side MOSFET’s on resistance
(RDS(ON) ✕IINDUCTOR). This amplified current-sense
signal and the internal slope compensation signal are
summed together (VSUM) and fed into the PWM com-
parator’s inverting input. The PWM comparator turns off
the high-side MOSFET when the VSUM exceeds the
integrated feedback voltage (VCOMP). Place the high-
side MOSFET no further than 5mm from the controller
and connect IN and LX to the MOSFET using Kelvin
sense connections to guarantee current-sense accura-
cy and improve stability.
Current-Limit Circuit
The current-limit circuit employs a unique “valley” cur-
rent-limiting algorithm that uses the low-side MOSFET’s
on-resistance as a sensing element (Figure 3). If the
voltage across the low-side MOSFET (RDS(ON) ✕
IINDUCTOR) exceeds the current-limit threshold at the
beginning of a new oscillator cycle, the MAX1964/
MAX1965 will not turn on the high-side MOSFET. The
actual peak current is greater than the current-limit
threshold by an amount equal to the inductor ripple cur-
rent. Therefore, the exact current-limit characteristic
and maximum load capability are a function of the low-
side MOSFET on-resistance, inductor value, input volt-
age, and output voltage. The reward for this uncertainty
is robust, lossless overcurrent limiting.
In adjustable mode, the current-limit threshold voltage is
approximately one-fifth the voltage seen at ILIM (IVALLEY
= 0.2 ✕VILIM). Adjust the current-limit threshold by con-
necting a resistive-divider from VL to ILIM to GND. The
current-limit threshold can be set from 106mV to
530mV, which corresponds to ILIM input voltages of
500mV to 2.5V. This adjustable current limit accommo-
dates MOSFETs with a wide range of on-resistance
characteristics (see the Design Procedure section). The
current-limit threshold defaults to 250mV when ILIM is
connected to VL. The logic threshold for switchover to
the 250mV default value is approximately VL - 1V.
Carefully observe the PC board layout guidelines to
ensure that noise and DC errors don’t corrupt the cur-
rent-sense signals seen by LX and GND. The IC must
be mounted close to the low-side MOSFET with short
(less than 5mm), direct traces making a Kelvin sense
connection.
Synchronous Rectifier Driver (DL)
Synchronous rectification reduces conduction losses in
the rectifier by replacing the normal Schottky catch
diode with a low-resistance MOSFET switch. The
MAX1964/MAX1965 also use the synchronous rectifier
to ensure proper startup of the boost gate-driver circuit
and to provide the current-limit signal.
Tracking/Sequencing Triple/Quintuple
Power-Supply Controllers
12 ______________________________________________________________________________________
MAX1964/MAX1965
Tracking/Sequencing Triple/Quintuple
Power-Supply Controllers
______________________________________________________________________________________ 13
Figure 2a. MAX1964 Functional Diagram
∑
BIAS
OK
VREF
1.114V
THERMAL
SHDN
3.5V
IN
VL LDO
5V
VL
BST
DH
LX
DL
GND
100kΩ
400kΩ
ILIM
0.9VL
POK
ENABLE
250mV
AV = 5
0.9VREF
0.9VREF
0.9VREF
B2
FB2
100mV
FB
OUT
COMP
SOFT-
START
VREF
1.24V
CLK
SLOPE
COMP
AV = 4.9
ENABLE
MAX1964
FB3
B3
MAX1964/MAX1965
Tracking/Sequencing Triple/Quintuple
Power-Supply Controllers
14 ______________________________________________________________________________________
Figure 2b. MAX1965 Functional Diagram
∑
BIAS
OK
VREF
1.114V
THERMAL
SHDN
3.5V
IN
VL LDO
5V
VL
BST
DH
LX
DL
GND
100kΩ
400kΩ
ILIM
0.9VL
POK
ENABLE
250mV
AV = 5
0.9VREF
0.9VREF
B_
FB_
100mV
FB
OUT
COMP
SOFT-
START
VREF
1.24V
CLK
SLOPE
COMP
AV = 4.9
ENABLE
MAX1965
500mV
FB5
B5 OUT
The DL low-side drive waveform is always the comple-
ment of the DH high-side drive waveform (with con-
trolled dead time to prevent cross-conduction or
“shoot-through”). A dead-time circuit monitors the DL
output and prevents the high-side FET from turning on
until DL is fully off. In order for the dead-time circuit to
work properly, there must be a low-resistance, low-
inductance path from the DL driver to the MOSFET
gate. Otherwise, the sense circuitry in the MAX1964/
MAX1965 will interpret the MOSFET gate as “off” when
gate charge actually remains. Use very short, wide
traces (50mils to 100mils wide if the MOSFET is 1 inch
from the device). The dead time at the other edge (DH
turning off) is determined by a fixed internal delay.
High-Side Gate-Drive Supply (BST)
Gate-drive voltage for the high-side N-channel switch is
generated by a flying-capacitor boost circuit (Figure 1).
The capacitor between BST and LX is alternately
charged from the VL supply and placed parallel to the
high-side MOSFET’s gate and source terminals.
On startup, the synchronous rectifier (low-side MOS-
FET) forces LX to ground and charges the boost
capacitor to 5V. On the second half-cycle, the switch-
mode power supply turns on the high-side MOSFET by
closing an internal switch between BST and DH. This
provides the necessary gate-to-source voltage to turn
on the high-side switch, an action that boosts the 5V
gate-drive signal above the input voltage.
Internal 5V Linear Regulator (VL)
All MAX1964/MAX1965 functions, except the current-
sense amplifier, are internally powered from the on-
chip, low-dropout 5V regulator. The maximum regulator
input voltage (VIN) is 28V. Bypass the regulator’s output
(VL) with a ceramic capacitor of at least 1µF to GND.
The VIN-to-VL dropout voltage is typically 200mV, so
when VIN is less than 5.2V, VL is typically VIN - 200mV.
The internal linear regulator can source up to 20mA to
supply the IC, power the low-side gate driver, charge
the external boost capacitor, and supply small external
loads. When driving particularly large FETs, little or no
regulator current may be available for external loads.
For example, when switched at 200kHz, a large FET
with 40nC total gate charge requires 40nC x 200kHz, or
8mA.
Undervoltage Lockout
If VL drops below 3.5V, the MAX1964/MAX1965
assumes that the supply voltage is too low to make
valid decisions, so the undervoltage lockout (UVLO)
circuitry inhibits switching, forces POK low, and forces
the DL and DH gate drivers low. After VL rises above
3.5V, the controller powers up the outputs (see Startup
section).
Startup
Externally, the MAX1964/MAX1965 start switching when
VL rises above the 3.5V undervoltage lockout thresh-
old. However, the controller is not enabled unless all
four conditions are met: 1) VL exceeds the 3.5V under-
voltage lockout threshold, 2) the internal reference
exceeds 92% of its nominal value (VREF > 1.145V), 3)
the internal bias circuitry powers up, and 4) the thermal
limit is not exceeded. Once the MAX1964/MAX1965
assert the internal enable signal, the step-down con-
troller starts switching and enables soft-start.
The soft-start circuitry gradually ramps up to the refer-
ence voltage in order to control the rate of rise of the
step-down controller and reduce input surge currents
MAX1964/MAX1965
Tracking/Sequencing Triple/Quintuple
Power-Supply Controllers
______________________________________________________________________________________ 15
Figure 3. “Valley” Current-Limit Threshold Point
INDUCTOR CURRENT
IVALLEY
ILOAD
[()
]
TIME
-IPEAK
L
VOUT
VINƒOSC
(VIN - VOUT)
IPEAK = IVALLEY +
MAX1964/MAX1965
during startup. The soft-start period is 1024 clock
cycles (1024/fOSC), and the internal soft-start DAC
ramps up the voltage in 64 steps. The output reaches
regulation when soft-start is completed, regardless of
output capacitance and load.
Output Voltage Sequencing (MAX1964)
After the reference powers up, the controller begins a
startup sequence. First, the main DC-DC step-down
converter powers up with soft-start enabled. Once the
step-down converter reaches 92% of its nominal value
(VFB > 1.145V) and soft-start is completed, the con-
troller powers up the first positive linear regulator. Once
the first linear regulator reaches 92% of its nominal
value (VFB2 > 1.145V), the second linear regulator pow-
ers up. Once all three output voltages exceed 92% of
their nominal values, the active-high ready signal (POK)
goes high (see Power-Good Output section).
Output Voltage Tracking (MAX1965)
After the reference powers up, the controller simultane-
ously powers up all five output voltages. The main DC-
DC step-down converter powers up with soft-start
enabled while the linear regulators are fully activated.
However, the linear regulators’ inputs are typically con-
nected to or derived from the step-down converter out-
put voltage. Since the linear regulators are fully active,
the pass transistors immediately saturate, allowing
these output voltages to track the step-down convert-
er’s slow rising output voltage (see Typical Operating
Characteristics). Once all five output voltages exceed
92% of their nominal values, the active-high ready sig-
nal (POK) goes high (see Power-Good Output section).
Power-Good Output (POK)
POK is an open-drain output. The MOSFET turns on
and pulls POK low when any output falls below 90% of
its nominal regulation voltage. Once all of the outputs
exceed 92% of their nominal regulation voltages and
soft-start is completed, POK goes high impedance. To
obtain a logic voltage output, connect a pullup resistor
from POK to VL. A 100kΩresistor works well for most
applications. If unused, leave POK grounded or uncon-
nected.
Thermal overload Protection
Thermal overload protection limits total power dissipa-
tion in the MAX1964/MAX1965. When the junction tem-
perature exceeds TJ= +160°C, a thermal sensor shuts
down the device, forcing DL and DH low, allowing the
IC to cool. The thermal sensor turns the part on again
after the junction temperature cools by 15°C, resulting
in a pulsed output during continuous thermal overload
conditions. If the VL output is short-circuited, thermal
overload protection is disabled.
During a thermal event, the main step-down converter
and the linear regulators are turned off, POK goes low,
and soft-start is reset.
Design Procedure
DC-DC Step-Down Converter
Output Voltage Selection
The step-down controller’s feedback input features dual
mode operation. Connect the output to OUT and con-
nect FB to GND for the preset 3.3V output voltage.
Alternatively, the MAX1964/MAX1965 output voltage
may be adjusted by connecting a voltage-divider from
the output to FB to GND (Figure 4). Select R2 in the
5kΩto 50kΩrange. Calculate R1 with the following
equation:
where VSET = 1.236V and VOUT may range from 1.236V
to approximately 0.75 ✕VIN (up to 20V). If VOUT > 5.5V,
connect OUT to GND (MAX1964) or to one of the posi-
tive linear regulators (MAX1965) with an output voltage
between 2V and 5V.
Inductor Value
Three key inductor parameters must be specified:
inductance value (L), peak current (IPEAK), and DC
resistance (RDC). The following equation includes a
constant LIR, which is the ratio of inductor peak-to-peak
AC current to DC load current. A higher LIR value
allows smaller inductance, but results in higher losses
and higher output ripple. A good compromise between
size and losses is a 30% ripple-current to load-current
ratio (LIR = 0.3). The switching frequency, input volt-
age, output voltage, selected LIR determine the induc-
tor value as follows:
where fSW is 200kHz. The exact inductor value is not
critical and can be adjusted in order to make trade-offs
among size, cost, and efficiency. Lower inductor values
minimize size and cost, but they also increase the out-
put ripple and reduce the efficiency due to higher peak
currents. On the other hand, higher inductor values
increase efficiency, but at some point resistive losses
due to extra turns of wire will exceed the benefit gained
from lower AC current levels.
LVVV
VI LIR
OUT IN OUT
IN SW LOAD MAX
=
()
ƒ
-
()
RR V
V
OUT
SET
12 1=
-
Tracking/Sequencing Triple/Quintuple
Power-Supply Controllers
16 ______________________________________________________________________________________
Find a low-loss inductor having the lowest possible DC
resistance that fits in the allotted dimensions. Ferrite
cores are often the best choice, although powdered
iron is inexpensive and can work well at 200kHz. The
chosen inductor’s saturation rating must exceed the
peak inductor current:
Setting the Current Limit
The minimum current-limit threshold must be high
enough to support the maximum load current at the
minimum tolerance level of the current-limit circuit. The
valley of the inductor current occurs at ILOAD(MAX)
minus half of the ripple current:
where RDS(ON) is the on-resistance of the low-side
MOSFET (NL). For the MAX1964/MAX1965, the mini-
mum current-limit threshold is 190mV (for the typical
250mV default setting). Use the worst-case maximum
value for RDS(ON) from the MOSFET NLdata sheet, and
add some margin for the rise in RDS(ON) over tempera-
ture. A good general rule is to allow 0.5% additional
resistance for each °C of the MOSFET junction temper-
ature rise.
Connect ILIM to VL for the default 250mV (typ) current-
limit threshold. For an adjustable threshold, connect a
resistive-divider from VL to ILIM to GND. The external
adjustment range of 500mV to 2.5V corresponds to a
current-limit threshold of 106mV to 530mV. When
adjusting the current limit, use 1% tolerance resistors
and a 10µA divider current to prevent a significant
increase in the current-limit tolerance.
MOSFET Selection
The MAX1964/MAX1965’s step-down controller drives
two external logic-level N-channel MOSFETs as the cir-
cuit switch elements. The key selection parameters are:
1. On-resistance (RDS(ON))
2. Maximum drain-to-source voltage (VDS(MAX))
3. Minimum threshold voltage (VTH(MIN))
4. Total gate charge (Qg)
5. Reverse transfer capacitance (CRSS)
The high-side N-channel MOSFET must be a logic-level
type with guaranteed on-resistance specifications at
VGS ≤4.5V. Select the high-side MOSFET’s on-resis-
tance (RDS(ON)) so IPEAK ✕RDS(ON) ≤225mV for the
V
RILIR I
VALLEY LOW
DS ON LOAD MAX LOAD MAX
()
() () ()
>−
2
II LIR I
PEAK LOAD MAX LOAD MAX
=+
() ()
2
MAX1964/MAX1965
Tracking/Sequencing Triple/Quintuple
Power-Supply Controllers
______________________________________________________________________________________ 17
Figure 4. Adjustable Output Voltage
BST
C1
D1
C2
R2
R1
NH
NL
CBST
RPOK
RCOMP
CCOMP1
COUT
CIN
DH
LX
LOUTPUT
1.25V TO 5V*
INPUT
4.5V TO 28V
DL
OUT
GND
FB
IN
VL
ILIM
POK
COMP
MAX1964
MAX1965
CCOMP2
* FOR OUTPUT VOLTAGES > 5V, SEE "OUTPUT VOLTAGE SELECTION."
MAX1964/MAX1965
current-sense range. For a good compromise between
efficiency and cost, choose a high-side MOSFET (NH)
that has conduction losses equal to the switching loss-
es at the optimum input voltage. Check to ensure that
the conduction losses at minimum input voltage don’t
exceed the package thermal limits or violate the overall
thermal budget. Check to ensure that the conduction
losses plus switching losses at the maximum input volt-
age don’t exceed package ratings or violate the overall
thermal budget.
The low-side MOSFET (NL) provides the current-limit
signal, so choose a MOSFET with an RDS(ON) large
enough to provide adequate circuit protection (see the
Setting the Current-Limit section):
Use the worst-case maximum value for RDS(ON) from
the MOSFET NL data sheet, and add some margin for
the rise in RDS(ON) over temperature. A good general
rule is to allow 0.5% additional resistance for each °C of
the MOSFET junction temperature rise. Ensure that the
MAX1964/MAX1965 DL gate drivers can drive NL; in
other words, check that the dv/dt caused by NHturning
on does not pull up the NLgate due to drain-to-gate
capacitance, causing cross-conduction problems.
MOSFET package power dissipation often becomes a
dominant design factor. I2R power losses are the great-
est heat contributor for both high-side and low-side
MOSFETs. I2R losses are distributed between NHand
NLaccording to duty factor as shown in the equations
below. Generally, switching losses affect only the high-
side MOSFET, since the low-side MOSFET is a zero-
voltage switched device when used in the buck
topology.
Gate-charge losses are dissipated by the driver and do
not heat the MOSFET. Calculate the temperature rise
according to package thermal-resistance specifications
to ensure that both MOSFETs are within their maximum
junction temperature at high ambient temperature. The
worst-case dissipation for the high-side MOSFET (PNH)
occurs at both extremes of input voltage, and the worst-
case dissipation for the low-side MOSFET (PNL) occurs
at maximum input voltage.
IGATE is the average DH driver output current capability
determined by:
where RDS(ON)DH is the high-side MOSFET driver’s on-
resistance (4Ωmax), and RGATE is any resistance
placed between DH and the high-side MOSFET’s gate
(Figure 5).
To reduce EMI caused by switching noise, add a 0.1µF
ceramic capacitor from the high-side switch drain to the
low-side switch source or add resistors (max 47Ω) in
series with DL and DH to increase the switches’ turn-on
and turn-off times (Figure 5).
The minimum load current should exceed the high-side
MOSFET’s maximum leakage current over temperature
if fault conditions are expected.
Input Capacitor
The input filter capacitor reduces peak currents drawn
from the power source and reduces noise and voltage
ripple on the input caused by the circuit’s switching.
The input capacitor must meet the ripple current
requirement (IRMS) imposed by the switching currents
defined by the following equation:
PIR
V
V
PP P
PI R V
V
NH CONDUCTION LOAD DS ON NH OUT
IN
NH TOTAL NH SWITCHING NH CONDUCTION
NL LOAD DS ON NL OUT
IN
()()
()( )( )
()
=
=+
=
2
21-
IVL
RR
GATE
DS ON DH GATE
=+
()
2()
PVI
QQ
I
NH SWITCHING IN LOAD OSC GS GD
GATE
()
=ƒ +
RV
I
DS ON VALLEY
VALLEY
()
=
Tracking/Sequencing Triple/Quintuple
Power-Supply Controllers
18 ______________________________________________________________________________________
Figure 5. Reducing the Switching EMI
BST
NH
RGATE
(OPTIONAL)
NL
RGATE
(OPTIONAL)
CBST
DH
LX L
TO VL
DH
GND
MAX1964
MAX1965
IRMS has a maximum value when the input voltage
equals twice the output voltage (VIN = 2VOUT), so
IRMS(MAX) = ILOAD/2. For most applications, nontanta-
lum capacitors (ceramic, aluminum, polymer, or OS-
CON) are preferred due to their robustness with high
inrush currents typical of systems with low impedance
inputs. Additionally, two (or more) smaller value low-
ESR capacitors can be connected in parallel for lower
cost. Choose an input capacitor that exhibits less than
+10°C temperature rise at the RMS input current for
optimal circuit long-term reliability.
Output Capacitor
The key selection parameters for the output capacitor
are the actual capacitance value, the equivalent series
resistance (ESR), and voltage-rating requirements
which affect the overall stability, output ripple voltage,
and transient response.
The output ripple has two components: variations in the
charge stored in the output capacitor, and the voltage
drop across the capacitor’s equivalent series resis-
tance (ESR) caused by the current into and out of the
capacitor.
VRIPPLE =V
RIPPLE(ESR) + VRIPPLE(C)
The output voltage ripple as a consequence of the ESR
and output capacitance is:
where Ip-p is the peak-to-peak inductor current (see
Inductor Selection section). These equations are suit-
able for initial capacitor selection, but final values
should be set by testing a prototype or evaluation cir-
cuit. As a general rule, a smaller ripple current results in
less output ripple. Since the inductor ripple current is a
factor of the inductor value and input voltage, the out-
put voltage ripple decreases with larger inductance,
but increases with lower input voltages.
With low-cost aluminum electrolytic capacitors, the
ESR-induced ripple can be larger than that caused by
the charge into and out of the capacitor. Consequently,
high quality low-ESR aluminum-electrolytic, tantalum,
polymer, or ceramic filter capacitors are required to
minimize output ripple. Best results at reasonable cost
are typically achieved with an aluminum-electrolytic
capacitor in the 470µF range, in parallel with a 0.1µF
ceramic capacitor.
Since the MAX1964/MAX1965 use a current-mode con-
trol scheme, the output capacitor forms a pole that
affects circuit stability (see Compensation Design).
Furthermore, the output capacitor’s ESR also forms a
zero.
The MAX1964/MAX1965’s response to a load transient
depends on the selected output capacitor. After a load
transient, the output instantly changes by ESR x
∆ILOAD. Before the controller can respond, the output
will sag further depending on the inductor and output
capacitor values. After a short period of time (see
Typical Operating Characteristics), the controller
responds by regulating the output voltage back to its
nominal state. For applications that have strict transient
requirements, low-ESR high-capacitance electrolytic
capacitors are recommended to minimize the transient
voltage swing.
Do not exceed the capacitor’s voltage or ripple-current
ratings.
Compensation Design
The MAX1964/MAX1965 controllers use an internal
transconductance error amplifier whose output allows
compensation of the control loop. Connect a series
resistor and capacitor between COMP and GND to
form a pole-zero pair, and connect a second parallel
capacitor between COMP and GND to form another
pole. The external inductor, high-side MOSFET, output
capacitor, compensation resistor, and compensation
capacitors determine the loop stability. The inductor
and output capacitor are chosen based on perfor-
mance, size, and cost, while the compensation resistor
and capacitors are selected to optimize control-loop
stability. The component values shown in the Standard
Application Circuit (Figures 1 and 6) yield stable opera-
tion over a broad range of input-to-output voltages.
The controller uses a current-mode control scheme that
regulates the output voltage by forcing the required
current through the external inductor, so the
MAX1964/MAX1965 use the voltage across the high-
side MOSFET’s on-resistance (RDS(ON)) to sense the
inductor current. Using the current-sense amplifier’s
output signal and the amplified feedback voltage, the
control loop determines the peak inductor current by:
V I ESR
VI
C
IVV
L
V
V
RIPPLE ESR P P
RIPPLE C PP
OUT SW
PP IN OUT
SW
OUT
IN
()
()
=
=ƒ
=ƒ
-
-
-
-
8
II VVV
V
RMS LOAD
OUT IN OUT
IN
=
()
−
MAX1964/MAX1965
Tracking/Sequencing Triple/Quintuple
Power-Supply Controllers
______________________________________________________________________________________ 19
MAX1964/MAX1965
where VREF = 1.24V, AVCS is the current-sense amplifi-
er’s gain (4.9 typ), AVEA is the DC gain of the transcon-
ductance error amplifier (2000 typ) set by its DC output
resistance, and VOUT(NOMINAL) is the output voltage
set by the feedback resistive-divider (internal or exter-
nal). Since the output voltage is a function of the load
current and load resistance, the total DC loop gain
(AV(DC)) is approximately:
The first compensation capacitor (CCOMP1) creates the
dominant pole. Due to the current-mode control
scheme, the output capacitor also creates a pole in the
system which is a function of the load resistance. As
the load resistance increases, the frequency of the out-
put capacitor’s pole decreases. However, the DC loop
gain increases with larger load resistance, so the unity-
gain bandwidth remains fixed. Additionally, the com-
pensation resistor and the output capacitor’s ESR both
generate zeros which must be canceled out by corre-
sponding poles. Therefore, in order to achieve stable
operation, use the following procedure to properly com-
pensate the system:
1) The crossover frequency (the frequency at which
unity gain occurs) must be less than 1/5th the
switching frequency:
2) Determine the series compensation capacitor
(CCOMP1) required to set the desired crossover fre-
quency:
where the error amplifier’s transconductance (gm)
is 100µS (see Electrical Characteristics) and AV(DC)
is the total DC loop gain defined above.
3) Before crossover occurs, the output capacitor and
the load resistor generate a second pole:
4) The series compensation resistor and capacitor
provide a zero which can be used to cancel the
second pole in order to ensure stability:
5) For most applications using electrolytic capacitors,
the output capacitor’s ESR forms a second zero
that occurs before crossover. Applications using
low-ESR capacitors (e.g., polymer, OS-CON) may
have ESR zeros that occur after crossover.
Therefore, verify the frequency of the output capaci-
tor’s ESR zero:
6) Finally, if the output capacitor’s ESR zero occurs
before crossover, add the parallel compensation
capacitor (CCOMP2) to form a third pole to cancel
this second zero:
For example, the MAX1964 Standard Application
Circuit shown in Figure 1 requires a 5V output that sup-
ports up to 2A. Using the above compensation guide-
lines, we can determine the proper component values:
•First, select the crossover frequency to be 1/5th the
200kHz switching frequency.
•Next, determine the total DC loop gain (AV(DC)) so
you can calculate the series compensation capaci-
tance (CCOMP1). Since the applications circuit uses
the International Rectifier IRF7101 with an RDS(ON)
of 100mΩ, the DC loop gain approximately equals
2480 and CCOMP1 must be approximately 490pF.
Select the closest standard capacitor value of
470pF.
•Determine the location of the output pole
(fPOLE(OUT)). With a 5V output supplying 2A and a
1000µF electrolytic capacitor, the output pole
occurs at 64Hz.
CC
RC f
Cf
ff
COMP COMP
COMP COMP ZERO ESR
COMP POLE OUT
ZERO ESR POLE OUT
21
1
1
21
≈
()
≈
()
π()
()
() ( )
-
-
fCR
ZERO ESR OUT ESR
()
≈1
2π
RCf
COMP COMP POLE OUT
≥1
21
π()
fCR
I
CV
POLE OUT OUT LOAD
LOAD MAX
OUT OUT
() ()
==
1
22ππ
CgA
f
COMP
mVDC
C
1
1
2 2000
≥
π
()
ff
CSW
≤5
AI
I
VR A
VRA
VR
VR
VDC PEAK
LOAD
REF LOAD VEA
OUT NOMINAL DS ON VCS
REF LOAD
OUT NOMINAL DS ON
() ()()
()()
≈≈
≈×400
IVVA
VRA
PEAK OUT REF VEA
OUT NOMINAL DS ON VCS
=
()()
Tracking/Sequencing Triple/Quintuple
Power-Supply Controllers
20 ______________________________________________________________________________________
•With the output pole’s frequency and series com-
pensation capacitor values, the required series
resistance can be determined. Based on the above
equation, select RCOMP = 5.1MΩ.
•Now we must determine if the selected output
capacitor’s ESR generates a second zero before
crossover—the circuit shown in Figure 1 uses a
1000µF 10V Sanyo CZ-series electrolytic capacitor
with an ESR rating of 0.2Ω, so the zero occurs at
800Hz. Since crossover occurs at 40kHz, add the
second parallel compensation capacitor.
•Finally, the second compensation capacitor value
must be approximately 43pF. Select the closest
standard capacitor value of 47pF.
Boost-Supply Diode
A signal diode, such as the 1N4148, works well in most
applications. If the input voltage goes below 6V, use a
small 20mA Schottky diode for slightly improved effi-
ciency and dropout characteristics. Do not use large
power diodes, such as the 1N5817 or 1N4001, since
high junction capacitance can charge up VL to exces-
sive voltages.
Linear Regulator Controllers
Positive Output Voltage Selection
The MAX1964/MAX1965’s positive linear regulator out-
put voltages are set by connecting a voltage divider
from the output to FB_ to GND (Figure 6). Select R4 in
the 1kΩto 50kΩrange. Calculate R3 with the following
equation:
where VFB = 1.24V and VOUT may range from 1.24V to
30V.
Negative Output Voltage Selection (MAX1965)
The MAX1965’s negative output voltage is set by con-
necting a voltage divider from the output to FB5 to a
positive voltage reference (Figure 6). Select R6 in the
1kΩto 50kΩrange. Calculate R5 with the following
equation:
where VREF is the positive reference voltage used and
VOUT may be set between 0 and -20V.
If the negative regulator is used, the OUT pin must be
connected to a voltage supply between 2V and 5V that
can source at least 25mA. Typically, the OUT pin is
connected to the step-down converter’s output.
However, if the step-down converter’s output voltage is
set higher than 5V, OUT must be connected to one of
the positive linear regulators with an output voltage
between 2V and 5V.
Transistor Selection
The pass transistors must meet specifications for cur-
rent gain (hFE), input capacitance, collector-emitter sat-
uration voltage, and power dissipation. The transistor’s
current gain limits the guaranteed maximum output cur-
rent to:
where IDRV is the minimum 10mA base drive current
and RBE (220Ω) is the pullup resistor connected
between the transistor’s base and emitter. Furthermore,
the transistor’s current gain increases the linear regula-
tor’s DC loop gain (see Stability Requirements), so
excessive gain will destabilize the output. Therefore,
transistors with current gain over 100 at the maximum
output current, such as Darlington transistors, are not
recommended. The transistor’s input capacitance and
input resistance also create a second pole, which
could be low enough to destabilize the output when
heavily loaded.
The transistor’s saturation voltage at the maximum out-
put current determines the minimum input-to-output
voltage differential that the linear regulator will support.
Alternatively, the package’s power dissipation could
limit the useable maximum input-to-output voltage dif-
ferential. The maximum power dissipation capability of
the transistor’s package and mounting must exceed the
actual power dissipation in the device. The power dissi-
pated equals the maximum load current times the maxi-
mum input-to-output voltage differential:
P = ILOAD(MAX)(VLDOIN - VOUT) = ILOAD(MAX) VCE
Stability Requirements
The MAX1964/MAX1965 linear regulators use an inter-
nal transconductance amplifier to drive an external
pass transistor. The transconductance amplifier, pass
transistor’s specifications, the base-emitter resistor,
and the output capacitor determine the loop stability. If
the output capacitor and pass transistor are not proper-
ly selected, the linear regulator will be unstable.
The transconductance amplifier regulates the output
voltage by controlling the pass transistor’s base cur-
rent. Since the output voltage is a function of the load
II
V
Rh
LOAD MAX DRV BE
BE FE MIN() ()
=
-
RR
V
V
OUT
REF
56=
RR V
V
OUT
FB
34 1=
-
MAX1964/MAX1965
Tracking/Sequencing Triple/Quintuple
Power-Supply Controllers
______________________________________________________________________________________ 21
MAX1964/MAX1965
Tracking/Sequencing Triple/Quintuple
Power-Supply Controllers
22 ______________________________________________________________________________________
Figure 6. MAX1965 Application Circuit
BST
C1
1µF
C2
1µF
D1
CENTRAL CMPSH-3
NH
NL
NP = 1
T1
CBST
0.1µF
RPOK
100kΩ
COUT
470µF
10V SANYO
(MV-AX SERIES)
CIN
470µF
DH
LX
VOUT1
3.3V AT 1.4A
INPUT
9V TO 18V
DL
OUT
GND
TO LOGIC
IN
VL
ILIM
POK
COMP
MAX1965
D2
NIHON
EP05Q03L
C10
47µF
C11
1µF
C8
47µF
FB
RGATE(NH)
10Ω
RGATE(NL)
10Ω
RBE2
220Ω
C3
1µF
Q1
TIP30
Q4
TIP29
R1
10kΩVOUT2
2.5V AT 200mA
C4
10µF
C6
10µF
R2
10kΩ
B2
B5
FB5
FB2
B3
FB3
CBE2
2200pF
FAIRCHILD
FDS6912A
D3
NIHON
EC10QS10
RBE5
220Ω
VOUT5
-5V AT 50mA
CONNECT
TO VOUT2
C5
10µF
R7
15kΩ
R8
30kΩ
CBE5
2200pF
RBE3
220Ω
C5
1µF
Q2
TIP32
R3
1.3kΩVOUT3
1.8V AT 500mA
R4
3.0kΩ
CBE3
2200pF
C9
10µF
B3
FB3
RBE4
220Ω
C7
1µF
Q3
2N3905
R5
30kΩVOUT3
5V AT 100mA
R6
10kΩ
CBE4
4700pF
POWER GROUND
ANALOG GROUND
NOTE: ALL T1 TRANSFORMER
WINDINGS ARE ON THE SAME CORE
NS(POS) = 1 T1
NS(NEG) = 2
T1
CCOMP1
1500pF
CCOMP2
68pF
RCOMP
412kΩ
current and load resistance, the total DC loop gain
(AV(LDO)) is approximately:
where VTis 26mV, and IBIAS is the current through the
base-to-emitter resistor (RBE). This bias resistor is typi-
cally 220Ω, providing approximately 3.2mA of bias cur-
rent.
The output capacitor creates the dominant pole.
However, the pass transistor’s input capacitance creates
a second pole in the system. Additionally, the output
capacitor’s ESR generate a zero, which may be used to
cancel the second pole if necessary. Therefore, in order
to achieve stable operation, use the following equations
to verify that the linear regulator is properly compensat-
ed:
1) First, determine the dominant pole set by the linear
regulator’s output capacitor and the load resistor:
unity-gain crossover = AV(LDO) ƒPOLE(CLDO)
2) Next, determine the second pole set by the base-to-
emitter capacitance (including the transistor’s input
capacitance), the transistor’s input resistance, and
the base-to-emitter pullup resistor:
3) A third pole is set by the linear regulator’s feedback
resistance and the capacitance between FB_ and
GND (including 20pF stray capacitance).
4) If the second and third pole occur well after unity-
gain crossover, the linear regulator will remain stable:
ƒPOLE(FB) and ƒPOLE(CBE) >
2ƒPOLE(CLDO) AV(LDO)
However, if the ESR zero occurs before unity-gain
crossover, cancel the zero with fPOLE(FB) by changing
circuit components such that:
Do not use output capacitors with more than 200mΩof
ESR. Typically, more output capacitance provides the
best solution, since this also reduces the output voltage
drop immediately after a load transient.
Linear Regulator Output Capacitors
Connect at least 1µF capacitor between the linear regu-
lator’s output and ground, as close to the MAX1964/
MAX1965 and external pass transistors as possible.
Depending on the selected pass transistor, larger
capacitor values may be required for stability (see
Stability Requirements). Furthermore, the output capac-
itor’s equivalent series resistance (ESR) affects stability,
providing a zero that may be necessary to cancel the
second pole. Use output capacitors with an ESR less
than 200mΩto ensure stability and optimum transient
response.
Once the minimum capacitor value for stability is deter-
mined, verify that the linear regulator’s output does not
contain excessive noise. Although adequate for stabili-
ty, small capacitor values may provide too much band-
width, making the linear regulator sensitive to noise.
Larger capacitor values reduce the bandwidth, thereby
reducing the regulator’s noise sensitivity.
For the negative linear regulator, if noise on the ground
reference causes the design to be marginally stable,
bypass the negative output back to its reference volt-
age (VREF, Figure 7). This technique reduces the differ-
ential noise on the output.
Base-Drive Noise Reduction
The high-impedance base driver is susceptible to sys-
tem noise, especially when the linear regulator is lightly
loaded. Capacitively coupled switching noise or induc-
tively coupled EMI onto the base drive causes fluctua-
tions in the base current, which appear as noise on the
linear regulator’s output. Keep the base-drive traces
away from the step-down converter and as short as
possible to minimize noise coupling. Resistors in series
with the gate drivers (DH and DL) reduce the LX
switching noise generated by the step-down converter
(Figure 5). Additionally, a bypass capacitor may be
placed across the base-to-emitter resistor (Figure 7).
This bypass capacitor, in addition to the transistor’s
input capacitance, could bring in a second pole that
will destabilize the linear regulator (see Stability
Requirements). Therefore, the stability requirements
determine the maximum base-to-emitter capacitance:
ƒ≈
POLE FB OUT ESR
CR
()
1
π
ƒ=
()
POLE FB
FB
CRR
()
1
212π
ƒ=
()
=+
POLE CBE
BE BE IN BJT
BE LOAD T FE
BE BE T FE
CRR
RI Vh
CRVh
()
()
1
2
2
π
π
ƒ= =
POLE CLDO LDO LOAD
LOAD MAX
LDO LDO
CR
I
CV
() ()
1
22ππ
AV
Ih
IV
V LDO T
BIAS FE
LOAD REF()
.
≈
+
55 1
MAX1964/MAX1965
Tracking/Sequencing Triple/Quintuple
Power-Supply Controllers
______________________________________________________________________________________ 23
MAX1964/MAX1965
where CIN(Q) is the transistor’s input capacitance, and
fPOLE(CBE) is the second pole required for stability.
Transformer Selection
In systems where the step-down controller’s output is
not the highest voltage, a transformer may be used to
provide additional post-regulated, high-voltage outputs.
The transformer generates unregulated, high-voltage
supplies which power the positive and negative linear
regulators. These unregulated supply voltages are
dependent on the transformer’s turns ratio – number of
secondary turns (NS) divided by the number of primary
turns (NP). So the transformer must be selected to pro-
vide supply voltages high enough to keep the pass
transistors from saturating. For positive output voltages,
connect the transformer as shown in Figure 6 where the
minimum turns ratio (NPOS = NS(POS)/NP) is determined
by:
where VSAT is the pass transistor’s saturation voltage
under full load. For negative output voltages (MAX1965
only), connect the transformer as shown in Figure 6
where the minimum turns ratio (NNEG = NS(NEG)/NP) is
determined by:
Since power transfer occurs when the low-side MOS-
FET is on (DL = high), the transformer cannot support
heavy loads with high duty cycles.
Snubber Design
The MAX1964/MAX1965 use current-mode control
schemes that sense the current across the high-side
MOSFET (NH). Immediately after the high-side MOSFET
turns on, the MAX1964/MAX1965 use a 60ns current-
sense blanking period to minimize noise sensitivity.
However, when the MOSFET turns on, the transformer’s
secondary inductance and the diode’s parasitic capac-
itance form a resonant circuit that causes ringing.
Reflected back through the transformer to the primary
side, these oscillations appear across the high-side
MOSFET may last longer than the blanking period. As
NVVV
V
NEG
LDO NEG SAT DIODE
OUT
≥++
()
NVVV
V
POS LDO POS SAT DIODE
OUT
≥++
() -1
CRI Vh
RVh C
BE POLE CBE
BE LOAD T FE
BE T FE IN Q
≤ƒ
+
1
2π() ()
-
Tracking/Sequencing Triple/Quintuple
Power-Supply Controllers
24 ______________________________________________________________________________________
Figure 7. Base-Drive Noise Reduction
CBYP
VNEG
VSUP
QPASS
CLDO
RBE
CBE
R1
R2
B_
a) POSITIVE OUTPUT VOLTAGE
b) NEGATIVE OUTPUT VOLTAGE (MAX1965 ONLY)
FB_
MAX1964
MAX1965
VPOS
CBYP
VREF
VSUP
QPASS
CNEG
RBE
CBE
R4
R3
BF5
B5
MAX1965
shown in Figure 8, a series RC snubber circuit at the
diode increases the damping factor, allowing the ring-
ing to settle quickly. Applications with multiple trans-
former windings require only one snubber circuit on the
highest output voltage.
The diode’s parasitic capacitance can be estimated
using the diode’s reverse voltage rating (VRRM), current
capability (IO), and recovery time (tRR). A rough
approximation is:
For the EC10QS10 Nihon diode used in Figure 8, the
capacitance is roughly 15pF. The output snubber only
needs to dampen the ringing, so the initial turn-on spike
that occurs during the blanking period is still present. A
100pF capacitor works well in most applications.
Larger capacitance values require more charge, there-
by increasing the power dissipation.
The snubber’s time constant (tSNUB) must be smaller
than the 60ns blanking time. A typical RC time constant
of approximately 30ns was chosen for Figure 8:
Minimum Load Requirements (Linear Regulators)
Under no-load conditions, leakage currents from the
pass transistors supply the output capacitor, even
when the transistor is off. Generally, this is not a prob-
lem since the feedback resistors’ current drain the
excess charge. However, charge may build up on the
output capacitor over temperature, making VLDO rise
above its set point. Care must be taken to ensure that
the feedback resistors’ current exceeds the pass tran-
sistor’s leakage current over the entire temperature
range.
Applications Information
PC Board Layout Guidelines
Careful PC board layout is critical to achieve low
switching losses and clean, stable operation. The
switching power stage requires particular attention.
Follow these guidelines for good PC board layout:
1) Place the power components first, with ground ter-
minals adjacent (NL source, CIN, COUT). If possi-
ble, make all these connections on the top layer
with wide, copper-filled areas. Keep these high-cur-
rent paths short, especially at ground terminals.
2) Mount the MAX1964/MAX1965 adjacent to the
switching MOSFETs in order to keep IN-LX current-
sense lines, LX-GND current-limit sense lines, and
the driver lines (DL and DH) short and wide. The
current-sense amplifier inputs are connected
between IN and LX, so these pins must be connect-
ed as close as possible to the high-side MOSFET.
The current-limit comparator inputs are connected
between LX and GND, but accuracy is not as
important, so give priority to the high-side MOSFET
connections. The IN, LX, and GND connections to
the MOSFETs must be made using Kelvin sense
connections to guarantee current-sense and cur-
rent-limit accuracy.
3) Group the gate-drive components (BST diode and
capacitor, IN bypass capacitor) together near the
MAX1964/MAX1965.
4) All analog grounding must be done to a separate
solid copper ground plane, which connects to the
MAX1964/MAX1965 at the GND pin. This includes
the VL bypass capacitor, feedback resistors, com-
pensation components (RCOMP, CCOMP), and
adjustable current-limit threshold resistors connect-
ed to ILIM.
5) Ensure all feedback connections are short and
direct. Place the feedback resistors as close to the
MAX1964/MAX1965 as possible.
6) When trade-offs in trace lengths must be made, it’s
preferable to allow the inductor charging path to be
made longer than the discharge path. For example,
it is better to allow some extra distance between the
input capacitors and the high-side MOSFET than to
allow distance between the inductor and low-side
MOSFET.
7) Route high-speed switching nodes away from sen-
sitive analog areas (B_, FB_, COMP, ILIM).
Regulating High Voltage
The linear regulator controllers can be configured to
regulate high output voltages by adding a cascode
transistor to buffer the base-drive output. For example,
to generate an output voltage between 30V and 60V,
add a 2N5550 high-voltage NPN transistor as shown in
Figure 9A where VBIAS is a DC voltage between 3V
and 20V that can source at least 1mA. RDROP protects
the cascode transistor by decreasing the voltage
across the transistor when the pass transistor saturates.
Similarly, to regulate a negative output voltage between
-20V and -120V, add a 2N5401 high-voltage PNP tran-
sistor as shown in Figure 9B.
Rt
C
ns
C
SNUB SNUB
SNUB SNUB
==
30
CIt
V
DIODE RR
RRM
=×
0
MAX1964/MAX1965
Tracking/Sequencing Triple/Quintuple
Power-Supply Controllers
______________________________________________________________________________________ 25
MAX1964/MAX1965
Output Filtering for Analog Circuits
Some applications need to generate analog and power
outputs at the same voltage. By adding an LC filter to
filter the noise present on an analog output (Figure 10),
one output voltage can provide both analog and power
outputs. The LC filter provides approximately
40dB/decade of attenuation. Select the LC corner fre-
quency (1/2 π√LC) to provide desired attenuation. For
stable operation, the filter inductor (LFILTER) and output
filter capacitor (CFILTER) used to generate the filter
must be selected to provide an overdamped response
to output transients:
RRC
L
DCR ESR FILTER
FILTER
+
()
≥
2
41
Tracking/Sequencing Triple/Quintuple
Power-Supply Controllers
26 ______________________________________________________________________________________
Figure 8. MAX1964 High-Voltage Application Requires Snubber Circuit
BST
C1
1µF
D1
CENTRAL CMPSH-3
C2
1µF
NH
NL
1
T1
CBST
0.1µF
RPOK
100kΩ
CCOMP
8.2nF
COUT
470µF
CIN
470µF
DH
LX
VOUT1
3.3V AT 1A
INPUT
9V TO 18V
DL
OUT
GND
TO LOGIC
IN
VL
ILIM
POK
COMP
MAX1964
D2
NIHON
EP05Q03L
COUT
470µF
FB
RCOMP
200kΩ
RGATE(NH)
10Ω
RSNUB
300Ω
RGATE(NL)
10Ω
RBE2
220Ω
C3
10µF
Q1
2N3905
R3
30kΩVOUT2
5V AT 100mA
C5
10µF
R4
10kΩ
B2
FB2
B3
FB3
CBE2
4700pF
FAIRCHILD
FDS6912A
D3
NIHON
EC10QS10
C7
470µF
RBE3
220Ω
C6
10µF
Q2
TIP30
R5
86.6kΩVOUT3
12V AT 100mA
C8
10µF
R6
10kΩ
CSNUB
100pF
CBE3
2200pF
R7
470Ω
POWER GROUND
ANALOG GROUND
C9
10nF
1
T1
2
T1
where the RDCR is the inductor’s DC resistance and
RESR is the output filter capacitor’s effective series
resistance (ESR). Inductors with high DC resistance will
provide poor load regulation but allow the use of small-
er filter capacitors:
VOUT(FILTER) = VOUT(NOMINAL) - RDCRIOUT
Therefore, power chokes are ideal for these applica-
tions due to their high inductance values, high satura-
tion current ratings, and low resistance.
Chip Information
TRANSISTOR COUNT: 1617
PROCESS: BiCMOS
MAX1964/MAX1965
Tracking/Sequencing Triple/Quintuple
Power-Supply Controllers
______________________________________________________________________________________ 27
Figure 9. High-Voltage Linear Regulation
CBYP
VNEG
VSUP
QPASS
QCASCODE
QCASCODE
CPOS
RBE
RDROP
CDROP
RDROP
CDROP
R1
R2
B_
a) POSITIVE OUTPUT VOLTAGE WITH CASCODED BASE DRIVE
b) NEGATIVE OUTPUT VOLTAGE (MAX1965 ONLY)
WITH CASCODED BASE DRIVE
FB_
MAX1964
MAX1965
VBIAS
VPOS
CBYP
VREF
VSUP
QPASS
CNEG
RBE
R4
R3
FB5
B5
MAX1965
MAX1964/MAX1965
Tracking/Sequencing Triple/Quintuple
Power-Supply Controllers
28 ______________________________________________________________________________________
Figure 10. Filtered Output for Analog Circuits
BST
C1
D1
C2
TO LOGIC
LFILTER
NH
NL
CBST
RPOK
COUT
CFILTER
CIN
DH
LX
LPOWER
OUTPUT
ANALOG
OUTPUT
INPUT
9V TO 18V
DL
OUT
GND
FB
IN
VL
ILIM
POK
COMP
MAX1964
MAX1965
CCOMP1 CCOMP2
RCOMP
POWER GROUND
ANALOG GROUND
Table 1. Component Suppliers
SUPPLIER PHONE FAX WEBSITE
INDUCTORS & TRANSFORMERS
Coilcraft 847-639-6400 847-639-1469 www.coilcraft.com
Coiltronics 561-241-7876 561-241-9339 www.coiltronics.com
ICE Components 800-729-2099 800-729-2099 www.icecomponents.com
Sumida USA 847-956-0666 847-956-0702 www.sumida.com
Toko 847-297-0070 847-699-1194 www.tokoam.com
CAPACITORS
AVX 803-946-0690 803-626-3123 www.avxcorp.com
Kemet 408-986-0424 408-986-1442 www.kemet.com
Panasonic 847-468-5624 847-468-5815 www.panasonic.com
Sanyo 619-661-6835 619-661-1055 www.secc.co.jp
Taiyo Yuden 408-573-4150 408-573-4159 www.t-yuden.com
DIODES
Central Semiconductor 516-435-1110 516-435-1824 www.centralsemi.com
International Rectifier 310-322-3331 310-322-3332 www.irf.com
Nihon 847-843-7500 847-843-2798 www.niec.co.jp
On Semiconductor 602-303-5454 602-994-6430 www.onsemi.com
Zetex 516-543-7100 516-864-7630 www.zetex.com
MAX1964/MAX1965
Tracking/Sequencing Triple/Quintuple
Power-Supply Controllers
______________________________________________________________________________________ 29
BST
DH
LX
MAIN
OUTPUT
INPUT
DL
OUT
GND
IN
VL
ILIM
POK
COMP
MAX1964
MAX1965
FB
OUT #2
B2
FB2
Typical Operating Circuit
Package Information
QSOP.EPS
MAX1964/MAX1965
Tracking/Sequencing Triple/Quintuple
Power-Supply Controllers
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
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