Sandpoint III Sandpoint System Documentation Covering Sandpoint and Associated MPPMC Processor Mezzanine Cards Rev 1 2001 Feb 16 Contents User's Manual Schematics Errata List SP3 Talos (603/740/745) Configuration Guide Schematics Errata List TALOS Unity (8240/8245) Configuration Guide Schematics Errata List Altimus (75x/7400/7410) Configuration Guide Schematics Errata List ALTIM Valis (7450) Configuration Guide Schematics Errata List VALIS UNITY Sandpoint III SP3 TALOS UNITY Sandpoint III ALTIM VALIS Order Number: SP3UM/A Rev. 0.2, 2/2001 Semiconductor Products Sector ***** * * Sandpoint III User's Manual Welcome to Sandpoint, Motorola's PowerPC development platform. Using Sandpoint you can evaluate current and future PowerPC devices using MPPMC (Motorola Processor PCI Mezzanine Cards). These cards are interchangable and one Sandpoint platform can support numerous processor-specific PPMC cards (but just one at a time). This User's Manual covers the following issues: Topic Section 1, "Introduction" Section 2, "Setup" Section 3, "Configuration" Section 4, "Programmers Model" Section 5, "Development Issues" Section 6, "Troubleshooting" Section 7, "FAQ" Page page 2 page 4 page 6 page 15 page 21 page 24 page 27 To locate any published errata or updates for this document, refer to the website at http://www.mot.com/ SPS/PowerPC/. This document contains information on a new product under development by Motorola. Motorola reserves the right to change or discontinue this product without notice. (c) Motorola, Inc., 2001. All rights reserved. PRELIMINARY-- SUBJECT TO CHANGE WITHOUT NOTICE User's Manual 1 Introduction The Sandpoint III motherboard, or "SP3" for short, is an evaluation baseboard which accepts one Motorola Processor PMC (MPPMC) or PrPMC card, as well as up to four PCI cards, and supplies typical PC-I/O peripherals. Sandpoint provides a flexible base for the evaluation of new PowerPC devices, and for early software design for customer project using PowerPC processors. Figure 1-1 shows a block diagram of the Sandpoint III system. PCI Slots KBD Winbond SuperIO COM1 PAR COM2 FLP MSE NVRM IDE ROM1 IDE ROM2 Motorola MPPMC Board SPF100 Figure 1-1. Sandpoint III Block Diagram 1.1 Features SP3 has the following features: * 2 One MPPMC slot for a processor board (PrPMC compatible with PCI arbitration extensions). User's Manual PRELIMINARY-- SUBJECT TO CHANGE WITHOUT NOTICE User's Manual * * * * * * * * * * * * * Two 32-bit PCI slots (5V) Two 32/64-bit PCI slots (5V) PMC and PCI slots auto-sense/auto-select 33 or 66 MHz operation. Two standard 16650-compatible ESD-protected serial ports. IEEE 1284 parallel port. Floppy disk port. Two ATA33 bus-master IDE ports. PS/2 mouse and keyboard connectors. BBVRAM; 1K bytes Real-Time Clock. Switch-selectable operating modes. Advanced Power Controller ("soft on/off"). LED monitors for critical functions. The I/O subsystem is identical to that of the Sandpoint 2 and the "EC" version of the older Yellowknife development platform. When properly configured, software written for these platforms should operate identically when executed on a Sandpoint 3. User's Manual PRELIMINARY-- SUBJECT TO CHANGE WITHOUT NOTICE 3 User's Manual 2 Setup Sandpoint 3 is shipped ready to run the DINK debugger software. If you will be running other operating systems, refer to the respective installation and setup instructions. Many OSes will communicate using the same serial port DINK does, so the following setup may apply as well. To setup your system, you will need the following material: * * * Sandpoint 3 system Mac, PC or workstation running a terminal program. Null-modem cable. 1 COM1 DINK32>> go 900 1 COM2 COM1 COM2 Figure 2-1. Sandpoint III Setup Diagram STEP 1 Connect the Sandpoint to a 120 VAC source using the supplied AC power code. For international operation at 240 VAC, replace the connector with an appropriately-keyed power cable. STEP 2 Turn the power supply on using the switch at the back of the Sandpoint chassis near the power cord. The system will not turn on at this time. STEP 3 Attach a null-modem cable between the Sandpoint COM1 port (top-most as shown in Figure 2-1) to the PC (or workstation) serial port (usually COM1). STEP 4 Startup a terminal emulator program. Common terminal emulators include "Hyperterminal", available for free with most Windows PCs, and many commercial programs such as Hayes "SmartComm". Setup the PCs terminal program to use the following settings: * * * 4 9600 Baud 8 Bits No Parity User's Manual PRELIMINARY-- SUBJECT TO CHANGE WITHOUT NOTICE User's Manual * * * 1 Stop Bit No Handshaking Terminal Emulation: any STEP 5 Turn on the Sandpoint by pushing the power switch on the front of the chassis. DINK will start and print a banner: ###### ### # # # # ##### # # # ## # # # # # # # # # # # # # # # # # # # # ## ##### # # # # # # # # # # # # # ## # # # # ###### ### # # # # ##### ( ( ( ( (AltiVec) ) ) Version Released Written by System Processor Memory : : : : : : ##### # # # ##### # # ####### ) ) 12.2, Metaware Build Jan 31, 2001 Motorola's RISC Applications Group, Austin, TX Sandpoint with Altimus/Talos (MPPMC60x/7xx/74xx) MPC7400 V2.8 @ 500 MHz, Memory @ 100 MHz Map B (CHRP), 00000000...03FFFFFF Copyright Motorola Inc. 1993-2001 Refer to history.c' for release info, changes, errata and fixes. DINK32_MAX >> At this point, DINK is ready to accept user commands such as downloading and starting code or assembling user programs. Refer to the DINK User's Manual for more details on using DINK. If you are using another ROM, such as for an OS, follow the instructions for the ROM. 2.1 Null Modem Cable Since both Sandpoint 3 and the PC or workstation it communicates with are computers and therefore are DTEs (Data Terminal Equipments), a special serial cable known as a null-modem cable is required. These cables are readily available from computer supply stores. In addition, it is simple to make, as shown in Figure 2-2. 5 4 3 2 9 8 7 6 5 4 3 2 9 8 7 6 1 1 DB9 Female Back View DB9 Female Back View Figure 2-2. Null Modem Diagram Once the cable is available or constructed, attach one end to the Sandpoint COM1 port and the other to the PC/Workstation. Either end will work with either computer. User's Manual PRELIMINARY-- SUBJECT TO CHANGE WITHOUT NOTICE 5 User's Manual 3 Configuration Sandpoint 3 is shipped ready to run the DINK firmware by default. The following configuration options are preset: * * MPPMC is the PCI arbiter. MPPMC is the interrupt controller using Serial-EPIC. Occasionally, however, software will require other configurations, which Sandpoint supports to a limited extent. This is often done to make a Sandpoint more closely resemble the target development platform. Configurable features include: * * * Using an external PCI arbiter instead of the PMC-resident arbiter. Using the 8259 PIC in the Winbond instead of the PMC interrupt controller. PnP (Plug-and-Play) PC I/O devices can remain uninitialized and `virtually'disappear. Another reason to change the configuration is to use the legacy modes for Sandpoint 2 compatibility. Refer to Appendix A for details on legacy configurations. All options on Sandpoint 3 are set via two `DIP' switches, as shown in Figure 3-1. POWER SUPPLY WINBOND SW2 POWER SWITCH WINBOND SW1 Figure 3-1: Sandpoint 3 in an ATX Chassis The switches have the same orientation; with the system standing vertically, the switches operate as shown 6 User's Manual PRELIMINARY-- SUBJECT TO CHANGE WITHOUT NOTICE User's Manual in Figure 3-2 ON 1 2 3 4 RIGHT = ON LEFT = OFF 5 6 7 8 Figure 3-2: Sandpoint 3 SW1/SW2 Configuration Switches All configuration switches should be changed with the power off; changes only take effect on a system power-on reset. The system pushbutton reset is not necessarily sufficient. 3.1 SW1 Options SW1 is located near the bottom of the Sandpoint 3 board, near the end of the fourth PCI slot. It controls the features shown in Table 3-1: Table 3-1. Sandpoint 3 SW1 Options Switch Name Definition 1 ROMSEL ROM Selection 2 ROM1WP ROM1 Write Protect 3 reserved reserved 4 FRCPCI33 Force PCI to 33MHz 5 EXTCLK Use external clock 6 SSCLK Spread-Spectrum Clock Default User's Manual PRELIMINARY-- SUBJECT TO CHANGE WITHOUT NOTICE 7 User's Manual Table 3-1. Sandpoint 3 SW1 Options Switch Name Definition 7 SSRNG Spread-Spectrum Range 8 PSON Force Power Supply ON Default 3.1.1 ROMSEL The "ROMSEL" switch may be used to select between the primary and secondary flash device (if any) on the Sandpoint 3. Table 3-2. Sandpoint 3 ROMSEL Option ROMSEL Definition Notes SW1-1 On (right) Primary ROM (29F040) is used for PCI boot option. Off (left) Secondary ROM (28F800) is used for PCI boot option. Normal mode. NOTE: Not all Sandpoint 3's have a secondary flash. NOTE: The RMODE switch (see Section 3.2.4) overrides this switch. 3.1.2 ROM1WP The "ROM1WP" switch may be used to write-protect the secondary (backup) PCI-hosted boot ROM, if any. This primary ROM normally contains the DINK debugger, but with the backup ROM protected, users may overwrite the boot ROMs with development code and still return to DINK as a backup measure. Table 3-3. Sandpoint 3 ROM1WP Switch ROM1WP Definition Notes SW1-2 On (right) ROM1 may be read to or written from. Off (left) ROM1 is write-protected. Use to store OS code. NOTE: Not all Sandpoint 3's have a secondary flash. 3.1.3 Reserved Switch SW2-3 is reserved and has no function. 3.1.4 FRCPCI33 The "FRCPCI33" switch may be used to cause the PCI bus to operate at 33 MHz regardless of the status of the M66EN signal, which normally allows the PCI bus to automatically select 66 MHz PCI. This switch is normally enabled, forcing only 33 MHz operation since the Winbond component does not support 66 MHz 8 User's Manual PRELIMINARY-- SUBJECT TO CHANGE WITHOUT NOTICE User's Manual operation. Table 3-4. Sandpoint 3 FRCPCI33 Switch Force PCI33 Definition Notes SW1-4 On (right) Force 33 MHz PCI only. Normal mode. Off (left) Allow automatic 33/66 MHz PCI. Experimental purposes only. It may be possible to operate the PCI bus at 66 MHz if software does not use the Winbond or the ISA bus. 3.1.5 EXTCLK The "EXTCLK" switch allows the user to switch from the standard, on-board 33/66 MHz PCI bus clock generator, from which all other clocks are derived, to an externally-supplied clock signal. This allows testing the system at different frequencies other than the standard 33 MHz or 66 MHz frequencies supported. Table 3-5. Sandpoint 3 EXTCLK Switch EXTCLK Definition Notes SW1-5 On (right) Normal clock mode Normal mode. Off (left) Accept clock from SMA connector. Use for testing. The clock source must be attached to the coaxial SMA connector on the board, and the clock signal supplied must meet the requirements listed in Table 3-6. Table 3-6. Sandpoint 3 External Clock Requirements Parameter Value ZIN 50 VIN 3V NOTE: Care must be used that the devices receiving the clock are capable of and are configured to operate at the new clock speed. In particular, PowerPC devices have internal PLLs which require a minimum clock input to operate properly. NOTE: The external clock source must be on before power is applied to the Sandpoint. 3.1.6 SSCLK The spread-spectrum enable ("SSCLK") switch allows the user to enable and evaluate the spread-spectrum clock generator (SSCG) option. If enabled, the SSCG modulates the PCI base clock frequency by a selectable amount (see Section 3.1.7). Table 3-7. Sandpoint 3 SSCLK Switch SSCLK Definition Notes SW1-6 On (right) PCI clocks are modulated by -1.25% or -3.75%. Use for testing. Off (left) Normal PCI clocks. Normal mode. NOTE: The Sandpoint system is not guaranteed to operate if the SSCLK switch is set; this is for testing purposes only. User's Manual PRELIMINARY-- SUBJECT TO CHANGE WITHOUT NOTICE 9 User's Manual 3.1.7 SSRNG The spread-spectrum range ("SSRNG") switch allows the user to change the amount of modulation applied to the PCI clock signals if the SSCG is enabled (see Section 3.1.6). Table 3-8. Sandpoint 3 SSRNG Switch SSRNG Definition Notes SW1-7 On (right) Off (left) Normal mode. -3.75% modulation: 66 MHz PCI: 33 MHz PCI: 63.5 ... 66.0 MHz 31.8 ... 33.0 MHz -1.25% modulation: 66 MHz PCI: 33 MHz PCI: 65.2 ... 66.0 MHz 32.6 ... 33.0 MHz 3.1.8 PSON The "PSON" switch allows the user to force the system to power up whenever AC power is applied to the system power supply. Normally, the system power is controlled with the APC in the SuperIO chip, and power is controlled through the chassis switch, motherboard pushbutton, or APC under software control. If PSON is selected, the system remains on until external power is removed. Table 3-9. Sandpoint 3 PSON Switch PSON Definition Notes SW1-8 On (right) Force power on always. Off (left) Normal power control mode Normal mode. 3.2 SW2 Options SW2 is located near the top of the Sandpoint 3 board, near the socketed flash ROM socket, between the PMC and the floppy connector. This switch controls the features shown in Table 3-10: Table 3-10. Sandpoint 3 SW2 Options 10 Switch Name Definition 1&2 AMODE PCI Arbiter Architecture 3 ILEGACY Interrupt Legacy Modes 4&5 IMODE Interrupt Architecture Default User's Manual PRELIMINARY-- SUBJECT TO CHANGE WITHOUT NOTICE User's Manual Table 3-10. Sandpoint 3 SW2 Options Switch Name Definition 6 RMODE ROM Mode 7&8 USER User Options Default 3.2.1 AMODE The AMODE switches are used to configure the PCI arbitration connections. Table 3-11. Sandpoint 3 AMode Switches AMODE[0:1] Definition SW2-1 SW2-2 On (right) On (right) Full On (right) Off (left) Partial Off (left) On (right) Winbond Off (left) Off (left) reserved Notes Default PCI arbitration mode. 3.2.1.1 AMODE FULL When AMODE is set such that the FULL option is selected, the MPPMC and the SPF100 work in tandem to provide arbitration handling for all possible PCI devices. Requests are assigned as follows: PMC_REQ(0) = WB_REQ(0) or SLOT_REQ(1) PMC_REQ(1) = WB_REQ(1) PMC_REQ(2) = SLOT_REQ(2) or SLOT_REQ(3) PMC_REQ(3) = SLOT_REQ(4) And grants are handled correspondingly. 3.2.1.2 AMODE PARTIAL When AMODE is set such that the PARTIAL option is selected, the MPPMC provides arbitration handling for four PCI devices (the maximum permitted by the MPPMC/PrPMC spec). Requests are assigned as follows: PMC_REQ(0) = WB_REQ(0) PMC_REQ(1) = WB_REQ(1) PMC_REQ(2) = SLOT_REQ(3) PMC_REQ(3) = SLOT_REQ(4) And grants are handled correspondingly. 3.2.1.3 AMODE WINBOND When AMODE is set such that the Winbond is selected as the system arbiter, the arbiter on the MPPMC is disabled and the Winbond is enabled. Thereafter, requests are assigned as follows: WB_REQ(0) = PMC_REQ(0) WB_REQ(1) = SLOT_REQ(1) User's Manual PRELIMINARY-- SUBJECT TO CHANGE WITHOUT NOTICE 11 User's Manual WB_REQ(2) = SLOT_REQ(2) WB_REQ(3) = SLOT_REQ(3) WB_REQ(4) = SLOT_REQ(4) And grants are handled correspondingly. 3.2.2 ILEGACY The ILEGACY switch is used to select between standard SP3 interrupt connections and support for legacy interrupt connections. Table 3-12. Sandpoint 3 ILEGACY Switches ILEGACY Definition Notes SW2-3 On (right) Standard SP3 Interrupt Modes Off (left) Legacy Sandpoint 1/2 Interrupt Modes Default See Appendix B 3.2.3 IMODE The IMODE switches are connected to the SPF FPGA to configure the PCI interrupt connections. Table 3-13. Sandpoint 3 IMode Switches IMODE[0:1] Definition SW2-4 SW2-5 On (right) On (right) Serial On (right) Off (left) Wire-OR Off (left) On (right) reserved Off (left) Off (left) reserved Notes Default. 3.2.3.1 IMODE Serial When AMODE is set such that Serial is selected, the SPF100 enables an internal serial multiplexer that works with the serial demultiplexer in the EPIC portion of the MPC107 or MPC824X on MPPMC cards. This allows many interrupts to be conveyed to the MPPMC than would normally be possible with the four allocated pins. shows the serial `slot'corresponding to each external interrupt Table 3-14. Sandpoint 3 Serial Interrupt Slot Assignment Slot 12 Interrupt Source Note 0 SIOINT Inverted, so active low 1 SLOT #1 2 SLOT #2 3 SLOT #3 See technical summary for details on PCI cards with multiple interrupt outputs. 4 SLOT #4 5 WinBond INTA# 6 WinBond INTB# 7 WinBond INTC# IDE Interrupt 8 WinBond INTD# IDE Interrupt User's Manual PRELIMINARY-- SUBJECT TO CHANGE WITHOUT NOTICE User's Manual Table 3-14. Sandpoint 3 Serial Interrupt Slot Assignment Slot Interrupt Source Note 9 10 11 12 reserved 13 14 15 3.2.3.2 IMODE WireOR When IMODE is set such that the WireOR option is selected, the MPPMC will merge all interrupt inputs into one, and the SPF100 work in tandem to provide arbitration handling for all possible PCI devices. Requests are assigned as follows: PMC_INT(0) = SLOT_INT(1) OR SLOT_INT(2) OR SLOT_INT(3) OR SLOT_INT(4) OR SIOINT (inverted). The other MPPMC interrupt pins (1 to 3) are not asserted. Software must generally poll known devices to clear the interrupt status, so Wire-OR is a very weak architecture but it is effective in checking that interrupt signalling is setup properly, and suitable for embedded systems with minimal interrupt requirements. 3.2.4 RMODE The RMODE switch is used to select an alternate method of addressing the dual flash devices. Table 3-15. Sandpoint 3 RMode Switches RMODE Definition Notes SW2-6 On (right) ROMSEL governs ROM/Flash access Off (left) Primary ROM: 0xFFF0_0000 ... 0xFFFF_FFFF Secondary ROM: 0xFF80_0000 ... 0xFFFF_FFFF Default NOTE: This switch overrides the ROMSEL switch (see Section 3.1.1). NOTE: Not all Sandpoint 3's have a secondary flash. 3.2.5 USER The USER switches are connected to the SuperIO GPIO port #1, bits 2 and 3, respectively. Sandpoint 3 User's Manual PRELIMINARY-- SUBJECT TO CHANGE WITHOUT NOTICE 13 User's Manual makes no use of these switch settings, they are provided for user-defined functions. Table 3-16. Sandpoint 3 USER Switches USER[0:1] Definition SW2-7 SW2-8 On (right) On (right) GPIO1 = "XXXX00XX" On (right) Off (left) GPIO1 = "XXXX01XX" Off (left) On (right) GPIO1 = "XXXX10XX" Off (left) Off (left) GPIO1 = "XXXX11XX" Notes Default See Section 4 for details on reading the GPIO port. 14 User's Manual PRELIMINARY-- SUBJECT TO CHANGE WITHOUT NOTICE User's Manual 4 Programmers Model This section describes support information which may be useful to hardware or software designers who are using Sandpoint 3. 4.1 Address Map Table 4-1shows the general address map of the Sandpoint 3, and Table 4-2 shows the specific location of ISA/PCI I/O addresses. Both tables assume Map "B" (CHRP), which is the default and officially encouraged standard. Table 4-1. Global Address Map START END Definition Notes 0000_0000 3FFF_FFFF SDRAM 4000_0000 77FF_FFFF reserved 7800_0000 7BFF_FFFF RCS3 ROM space 2 7C00_0000 7FFF_FFFF RCS2 ROM space 2 8000_0000 FCFF_FFFF PCI memory 3 FD00_0000 FDFF_FFFF PCI/ISA memory FE00_0000 FEBF_FFFF PCI/ISA I/O space FEC0_0000 FEDF_FFFF PCI configuration address register FEE0_0000 FEEF_FFFF PCI configuration data register FEF0_0000 FEFF_FFFF Interrupt Acknowledge FF00_0000 FF7F_FFFF RCS1 ROM space FF80_0000 FFFF_FFFF RCS0 ROM space (Boot ROM) 1 4 NOTES: 1. Requires memory control registers to be properly programmed (MCCR[1:4], MS[E]AR[1:2], ME[E]AR[1:2], MBEN). 2. MPC107 or MPC8245 only. 3. Only software-enabled PCI devices appear in this space. 4. Only software-enabled PCI/ISA I/O devices appear in this space. The detailed address map in Table 4-2 assumes that the PnP devices have not been changed from the default locations. Table 4-2: Detailed ISA I/O Address Map Start End Mode Device Register FE00_0000 --- R/W WB DMA Channel 0 Base/Current Address FE00_0001 --- R/W WB DMA Channel 0 Base/Current Word FE00_0002 --- R/W WB DMA Channel 1 Base/Current Address FE00_0003 --- R/W WB DMA Channel 1 Base/Current Word FE00_0004 --- R/W WB DMA Channel 2 Base/Current Address FE00_0005 --- R/W WB DMA Channel 2 Base/Current Word FE00_0006 --- R/W WB DMA Channel 3 Base/Current Address User's Manual PRELIMINARY-- SUBJECT TO CHANGE WITHOUT NOTICE Notes 15 User's Manual Table 4-2: Detailed ISA I/O Address Map Start End Mode Device FE00_0007 --- R/W WB DMA Channel 3 Base/Current Word FE00_0008 --- R WB DMA Controller 1 Status W --- W WB DMA Controller 1 Request FE00_000A --- W WB DMA Controller 1 Mask FE00_000B --- W WB DMA Controller 1 Mode FE00_000C --- W WB DMA Controller 1 Clear Byte Pointer FE00_000D --- W WB DMA Controller 1 Master Clear FE00_000E --- W WB DMA Controller 1 Clear Mask FE00_000F --- W WB DMA Controller 1 Write All Mask FE00_0010 FE00_001F FE00_0020 --- R/W WB PIC 1 Command FE00_0021 --- R/W WB PIC 1 Command FE00_0022 FE00_003F FE00_0040 --- R/W WB Counter 0 FE00_0041 --- R/W WB Counter 1 FE00_0042 --- R/W WB Counter 2 FE00_0043 --- W WB Timer/Counter Control FE00_0044 FE00_005F FE00_0060 --- R/W SIO Keyboard Controller Data R/W WB NMI Status/Control FE00_0061 --- FE00_0062 FE00_0063 FE00_0064 --- FE00_0065 FE00_006F Notes DMA Controller 1 Command FE00_0009 FE00_0070 16 Register unassigned unassigned unassigned 1 unassigned R/W SIO Keyboard Controller Command 1 unassigned --- R/W SIO RTC/APC Index "--- W WB RTC Index (shadow) 1 FE00_0071 FE00_0077 unassigned FE00_0078 FF80_0079 R/W WB BIOS Timer FE00_007A FF80_007B R/W WB BIOS Timer Reserved FE00_007C FE00_007F FE00_0080 --- - WB DMA Reserved Page FE00_0081 --- R/W WB DMA Memory Page 2 FE00_0082 --- R/W WB DMA Memory Page 3 FE00_0083 --- R/W WB DMA Memory Page 1 FE00_0084 FF80_0086 - WB DMA Reserved Page FE00_0087 --- R/W WB DMA Memory Page 0 FE00_0088 --- - WB DMA Reserved Page FE00_0089 --- R/W WB DMA Memory Page 6 FE00_008A --- R/W WB DMA Memory Page 7 FE00_008B --- R/W WB DMA Memory Page 5 FE00_008C FF80_008E - WB DMA Reserved Page unassigned User's Manual PRELIMINARY-- SUBJECT TO CHANGE WITHOUT NOTICE User's Manual Table 4-2: Detailed ISA I/O Address Map Start End Mode Device R/W WB Register FE00_008F FE00_0091 FE00_0092 --- FE00_0093 FE00_009F FE00_00A0 --- R/W WB PIC 2 Command FE00_00A1 --- R/W WB PIC 2 Command FE00_00A2 FE00_00BF FE00_00C0 --- R/W WB DMA Channel 4 Base/Current Address FE00_00C1 --- R/W WB DMA Channel 4 Base/Current Word FE00_00C2 FE00_00C3 FE00_00C4 --- R/W WB DMA Channel 5 Base/Current Address unassigned Port 92: System Reset unassigned unassigned unassigned FE00_00C5 FE00_00C6 unassigned --- R/W WB DMA Channel 5 Base/Current Word --- R/W WB DMA Channel 6 Base/Current Address unassigned FE00_00C7 FE00_00C8 FE00_00C9 FE00_00CA unassigned --- R/W WB DMA Channel 6 Base/Current Word --- R/W WB DMA Channel 7 Base/Current Address FE00_00CB FE00_00CC unassigned FE00_00CD FE00_00CE unassigned --- R/W WB DMA Channel 7 Base/Current Word R WB DMA Controller 2 Status "W WB DMA Controller 2 Command FE00_00CF unassigned FE00_00D0 FE00_00D3 FE00_00D2 unassigned --- W WB DMA Controller 2 Request FE00_00D3 FE00_00D4 unassigned --- W WB DMA Controller 2 Mask FE00_00D5 FE00_00D6 unassigned --- W WB DMA Controller 2 Mode W FE00_00D7 FE00_00D8 unassigned --- W WB DMA Controller 2 Clear Byte Pointer FE00_00D9 FE00_00DA unassigned --- W WB DMA Controller 2 Master Clear FE00_00DB FE00_00DC Notes unassigned --- W WB DMA Controller 2 Clear Mask FE00_00DD unassigned FE00_00DE --- FE00_00DF FE00_00EF FE00_00F0 --- FE00_00F1 FE00_015B FE00_015C --- W WB DMA Controller 2 Write All Mask unassigned W WB Coprocessor Error unassigned R/W SIO PnP Index Register User's Manual PRELIMINARY-- SUBJECT TO CHANGE WITHOUT NOTICE 17 User's Manual Table 4-2: Detailed ISA I/O Address Map Start End Mode Device FE00_015D --- R/W SIO FE00_015E FE00_016F FE00_0170 FE00_0177 FE00_0178 FE00_01EF FE00_01F0 FE00_01F7 FE00_01F8 FE00_0277 FE00_0278 FE00_027F FE00_0280 FE00_02F7 FE00_02F8 FE00_02FF FE00_0300 FE00_0375 FE00_0376 --- FE00_0377 FE00_03F1 FE00_03F2 FE00_03F3 FE00_03F4 FE00_03F5 FE00_03F6 --- Notes PnP Data Register unassigned R/W WB IDE Channel 2 Primary unassigned R/W WB IDE Channel 1 Primary unassigned R/W SIO Parallel Port Registers 1 unassigned R/W SIO COM2 UART Registers 1 unassigned R/W WB IDE Channel 2 Secondary unassigned R/W SIO FDC Floppy Registers 1 unassigned R/W WB FE00_03F7 IDE Channel 1 Secondary unassigned FE00_03F8 FE00_03FF FE00_0400 FE00_0409 R/W SIO COM1 UART Registers FE00_040A --- R WB DMA Scatter/Gather Interrupt Status FE00_040B --- W WB DMA Controller 1 Extended Mode FE00_040C FE00_0414 FE00_0415 --- W WB DMA Scatter/Gather Channel 5 Command FE00_0416 --- W WB DMA Scatter/Gather Channel 6 Command FE00_0417 --- W WB DMA Scatter/Gather Channel 7 Command unassigned unassigned FE00_0418 FE00_041C FE00_041D --- R WB DMA Scatter/Gather Channel 5 Status unassigned FE00_041E --- R WB DMA Scatter/Gather Channel 6 Status FE00_041F --- R WB DMA Scatter/Gather Channel 7 Status FE00_0420 FE00_0433 FE00_0434 FE00_0437 R/W WB DMA Scatter/Gather Channel 5 Table Pointer unassigned FE00_0438 FE00_043B R/W WB DMA Scatter/Gather Channel 6 Table Pointer FE00_043C FE00_043F R/W WB DMA Scatter/Gather Channel 7 Table Pointer FE00_0440 FE00_0480 FE00_0481 --- R/W WB DMA Page Register 2 unassigned FE00_0482 --- R/W WB DMA Page Register 3 FE00_0483 --- R/W WB DMA Page Register 1 FE00_0484 FE00_0486 FE00_0487 --- R/W WB DMA Page Register 0 unassigned FE00_0488 18 Register unassigned FE00_0489 --- R/W WB DMA Page Register 6 FE00_048A --- R/W WB DMA Page Register 7 User's Manual PRELIMINARY-- SUBJECT TO CHANGE WITHOUT NOTICE 1 User's Manual Table 4-2: Detailed ISA I/O Address Map Start End Mode Device Register Notes FE00_048B --- R/W WB FE00_048C FE00_04CF FE00_04D0 --- R/W WB PIC 1 Interrupt Control FE00_04D1 --- R/W WB PIC 2 Interrupt Control FE00_04D2 FE00_06FF FE00_0700 --- R/W SIO GPIO Port #0: Data 2 FE00_0701 --- R/W SIO GPIO Port #0: Direction 2 FE00_0702 FE00_080F FE00_0810 --- W WB RTC CMOS RAM Protect 1 FE00_0812 --- W WB RTC CMOS RAM Protect 2 FE00_0813 FEBF_FFFF DMA Page Register 5 unassigned unassigned unassigned unassigned NOTES: 1. Requires that the indicated device in the SIO has been enabled through the PnP (Plug-and-Play) enumeration port (PnP Index/Data registers). 2. This register is programmable; shown is the DINK debugger default value. 4.2 Initializing Sandpoint A typical start-up sequence includes the following: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. Initialize CPU (all CPUs recognized) Initialize BATs Initialize Cache Initialize Bridge Chip (MPC107 or 842X) Setup stack pointer Initialize Winbond PCI/ISA bridge Initialize SuperIO Initialize Serial IO Bus speed detection Size memory Setup decrementer and timers Initialize EPIC and enable exceptions Begin User Code (perhaps more, perhaps less). These functions are too detailed to go into in this document, so instead refer to the DINK source code. Table 4-3. Dink Functions Step Functions Source file Notes 1 CPU setup except2.s starting at "system_reset:" 2 BAT setup except2.s starting at "mmu_setup:" 3 Cache setup except2.s cache.s starting at "init_L2backside_cache" all of "cache.s" 4 MPC107/MPC8240 setup mpc107.s or kahlua.s All or both User's Manual PRELIMINARY-- SUBJECT TO CHANGE WITHOUT NOTICE 19 User's Manual Table 4-3. Dink Functions Step Functions Source file 5 Stack setup except2.s 6 Winbond setup yk.c winbond_initialize() 7 Super IO yk.c ns308_defaults() 8 Serial Init yk.c CommInit() 9 Bus speed detection pmc.c 10 Size memory meminfo.c meminfo(), memcheck() EH500S 11 Decrementer except2.s 12 Initialize EPIC and exceptions drivers/epic/epic1.c Notes init_global_cont: GetBusPeriod() IDProcessor() all Starting with DINK release 12.3 and later, a demonstration Sandpoint initialization file "spinit.s" will be available. 20 User's Manual PRELIMINARY-- SUBJECT TO CHANGE WITHOUT NOTICE User's Manual 5 Development Issues The following sections cover a few issues related to developing software on the Sandpoint platform. 5.1 Code Development Software can generally be developed on a Unix workstation or PC and downloaded to the Sandpoint using assemblers or compilers from a variety of third-party resources. Refer to: http://www.mot.com/SPS/PowerPC/3rdparty/index.html for further details. Issues regarding code development on Sandpoint were covered in Section 4. Once the code has been developed, it is generally transferred to the Sandpoint by one method or another for testing. There are several ways of doing this, depending on the 5.2 Speeding Up Code Downloading DINK currently only supports loading program images through the S-record download command ("dl"). To speed up the process, the baud rate should generally be set to 38,400 baud. DINK32_MAX >> sb -k 38400 DINK32_MAX >> dl -k -o 90000 12000 lines transferred. DINK32_MAX >> In addition, DINK supports a binary download feature which is about 150% faster again. To use this facility, the `srec2bin' utility in the DINK source code must be compiled, and the resulting program is used to translate your program's S-Record file to binary. Then, the DINK command: DINK32_MAX >> dl -k -b -o 90000 436 bytes transferred. DINK32_MAX >> will initiate a binary download. After issuing the "dl" command, use your terminal emulation program to send the file as-is (no translation, padding or flow control). DINK stops accepting characters from the terminal program after 5 seconds of inactivity. NOTE: The basic "Hyperterminal" program on a PC inserts NULLs every 32K or so, so it is not generally usable with this facility. The facility for transferring binary files must be completely `transparent' and not alter any characters sent or received. This is sometimes referred to as `8-bit clean'. 5.3 Instant Code Downloading An alternate way of debugging boot code is to use a ROM emulator, such as the PromJET from Emulation Technologies ( http://www.emutec.com/pjetmain.html). The Sandpoint has a 32-pin, 5V socketed flash device which can be removed and replaced with an in-circuit emulator. Though limited to 512K, this can be a very fast method of code checkout. Equivalent solutions are available for the TSOP48-packaged flash on the MPPMC boards, but this requires desoldering and replacing the flash with a special cable. 5.4 Running Code Under DINK Once the program has been downloaded into memory, it can be execute by entering `go 90000' (or other starting address). DINK will preset all the registers (integer, floating and special-purpose) to the default values, and then execute the program. The code can return to DINK by ending with a `blr'instruction, or by setting a breakpoint. Changing the SPR registers using DINK can help with measuring program operation under varying User's Manual PRELIMINARY-- SUBJECT TO CHANGE WITHOUT NOTICE 21 User's Manual conditions; for example, if a program has been downloaded to address 0x90000, the following sequence: DINK32_MPC755 >> rm -e l2cr L2CR = 0x00000000 New Value ? 0x00000000 DINK32_MPC755 >> go 90000 (measure performance) User code returned to DINK. DINK32_MPC755 >> rm l2cr L2CR = 0x00000000 New Value ? 0x3D014000 DINK32_MPC755 >> go 90000 (measure performance) User code returned to DINK. DINK32_MPC755 >> By enabling or disabling the L2, the user code effectively emulates running on an MPC755 (w/L2 cache) or an MPC745 (w/no L2 cache). 5.5 Saving User Code in Flash DINK has the capability of saving user code to the ROM on the Sandpoint motherboard (but this overwrites DINK itself) or to one of the two flashes on most MPPMC cards. The "fupdate" command can be used for this purpose: 1. Download the code to memory dl -k -o 100000 and download your program as usual. 2. Make sure the PROGMODE switch on the MPPMC card is on (see the configuration guides for the corresponding MPPMC card for switch location). 3. Issue the command: fu -l 100000 ff000000 100000 (you can reduce the last argument to the actual size of your program). 4. Decide if you want to boot directly into your code (your code initializes the entire platform): Turn the PROGMODE switch OFF Set the ROMLOC switch to "RSC0 on local bus" Press the reset button -- DINK will boot directly into your code. or if you want DINK to do the init. Leave the PROGMODE switch ON To run your code, use the command "go ff000000" (assuming your code started at the offset 0; otherwise use a different offset). To automatically run your code upon reset, enter the command: "ENV BOOT=0xFF000000" 5.6 Compatibility Issues With the use of the MPPMC standard for evaluation processor modules, it is relatively easy to swap out the processor card in a Sandpoint with another CPU. This allows evaluating code for a variety of PowerPC devices, and each PMC card has the ability to change the operating speed to further adjust Sandpoint to resemble the target platform. 22 User's Manual PRELIMINARY-- SUBJECT TO CHANGE WITHOUT NOTICE User's Manual SP3 supports, and is shipped with, one of the following MPPMC cards. Table 5-1. Supported MPPMC Cards MPPMC Board MPPMC603 MPPMC740 Processor MPC740 MPC745 MPPMC750 MPC750 MPPMC7400 SDRAM MCP107 64MB SODIMM MPC603r Talos X1 MPPMC745 MPPMC755 Bridge Altimus X3 MPPMC7410 MPC755 MPC7400 MCP107 64MB discrete Notes SODIMM memory (no parity/ECC) (2) 1MB flash ECC/Parity support (2) 1MB flash MPC7410 MPPMC7450 Valis X1 MPC750 MCP107 64MB discrete MPPMC8240 Unity X4 MPC8240 - 64MB SODIMM ECC/Parity support (2) 1MB flash SODIMM memory (no parity/ECC) (2) 1MB flash Note: Due to the evolution between the Motorola's MPPMC specification and the changes made to it by VITA as part of their standardization process for the PrPMC standard, Motorola cannot guarantee that MPPMC cards will necessarily work outside the SP3 environment, nor that PrPMC cards will work in VITA-PrPMC systems. An option switch on some MPPMC cards attempts to mitigate this, but for this reason and others MPPMC cards are not sold except with an attached MPPMC card. For information on changing the operating speeds of an individual MPPMC cards, refer to the "configuration guide" included in the bound documentation, or on the Sandpoint website (see Appendix C). 5.7 Upgrading DINK Occasionally, DINK is upgraded with new facilities and bug fixes. DINK 12.1 or later has the ability to update itself using the "fupdate" command. To update DINK with a new version, follow this sequence: 1. Consider making a safety copy of the current DINK first by saving it to the flash on the MPPMC: Set the PROGMODE switch and enter fu -l fff00000 ff000000 7ff00 2. Obtain the DINK S-record file for Yellowknife/Sandpoint. The latest version is at: http://www.mot.com/SPS/PowerPC/teksupport/tools/DINK32/dinkindex.htm 3. Download the S-record file to the Sandpoint platform using the command: dl -k -o 100000 with the terminal program, in the usual manner. You can also convert it to binary for faster download, as described in Section 5.2). 4. Issue the command: fu -h 100000 fff00000 7ff00 Restart, and the new version of DINK should activate. If an error occurs, DINK will not work and the flash will need to be externally re-programmed on a PROM programmer. If the safety copy was made in step 1 above, just set the ROMLOC switch to boot from the local flash instead of PCI. User's Manual PRELIMINARY-- SUBJECT TO CHANGE WITHOUT NOTICE 23 User's Manual 6 Troubleshooting If you are having trouble with 6.1 DINK Does Not Start Up * * * Make sure the switch under the power cord is on. If there is AC power switched on at the power supply, the green LED labelled "STANDBY POWER" will be on (you must open the cover to see it). If STANDBY POWER is on, but the board will no power up Table 6-1. Troubleshooting SP3 Problem What to Check Verify DINK will not start Make sure power cord is plugged in. If AC power is active, the green Make sure power supply switch is ON (switch is under the "STANDBY POWER" LED on the SP3 power cord at the back) motherboard will be on (open the chassis to verify). If the standby power is now active, press the POWER switch on the front of the chassis. If STANDBY POWER is on but the front panel power switch does not start DINK,. Open the chassis and press the red POWER switch at the bottom right corner (second from the bottom). If power is now available (MAIN POWER is on), the chassis power switch may be disconnected. Make sure the cabled connecter labelled "POWER SW" or equivalent is connected to the chassis header (J29) on the pins labelled "PWR SW" (pins 24 and 26). If STANDBY POWER is on but neither the front panel power switch nor the internal red button will start DINK, set the PSON switch (see Section 3.1.8). If power is now available (MAIN POWER is on), the APC unit is not functioning. Make sure that the battery is installed and is not discharged (replace if necessary). Sandpoint will work without the APC but power must be turned on and off with the power supply switch. 24 If STANDBY POWER and MAIN POWER are both on, press the red reset button inside (bottom right corner). If DINK starts, the front-panel reset switch may be disconnected. Insure that the cable labelled "RESET" or equivalent is connected to the chassis header J26 pins 2/ 4/6/8. If power is on and the reset button does not start DINK, check the activity of the MPPMC LEDs and the SP3 LEDs. If all MPPMC LEDs do not activate while the Reset button is pressed and held, the MPPMC card is not installed or not functioning. Insure card is firmly seated and re-try. User's Manual PRELIMINARY-- SUBJECT TO CHANGE WITHOUT NOTICE User's Manual Table 6-1. Troubleshooting SP3 Problem What to Check If power is on and LEDs are active while reset pressed, release reset and monitor PCI bus activity. Verify If the PCI LED on the SP3 motherboard is not active (flickering), DINK is not running from the ROM. This can be caused by: 1. Improper configuration of the MPPMC card (review configuration guide) 2. Improper configuration of the SP3 board (refer to this document). 3. Socketed SDRAM loose (reseat). Reseat socketed devices, and/or restore the system to factory defaults (shaded settings on MPPMC configuration guides and as stated in this document). If power is on, LEDs are active, system is in default configuration. If the PCI LED flickers momentarily and then stops, the cause could be the PCI boot ROM: 1. A mis-programmed flash (user code) 2. Broken ROM socket (common with mishandled PromJETs). Restore or replace the DINK ROM and retry. Also consider trying the ROM in a second Sandpoint or verifying it on an external programming system. If power is on, LEDs are active, system is in default configuration, and the PCI LED is active continuously: DINK is running. Check the serial port connections. 1. Make sure you are using a null-modem cable. A standard cable will not work. 2. Make sure the cable is in COM1 on the Sandpoint system (nearest the power cord). 3. Make sure you're using the COM port your terminal expects (try the other one). If power is on, LEDs are active, system is in default DINK is running. Check the terminal setup: configuration, and the PCI LED is active continuously, and 1. Check that the terminal is setup for nothe connections are correct. handshaking: Remove the cable from the Sandpoint and connect a wire or piece of metal between pins 2 and 3. There are no dangerous voltages present. If you can type on the terminal, the handshaking is correct. If power is on, LEDs are active, system is in default Contact Motorola technical support. configuration, and the PCI LED is active continuously, and the connections and handshaking are correct. DINK writes characters to the screen, but they're illegible. Make sure the terminal program is set to 9600 baud, 8N1, no handshaking. Check settings. Make sure the DINK baud rate has not been changed with the ENV command. Press the backspace key and hold it down while pressing RESET. If DINK comes up, enter the command "ENV -c" User's Manual PRELIMINARY-- SUBJECT TO CHANGE WITHOUT NOTICE 25 User's Manual Table 6-1. Troubleshooting SP3 Problem What to Check Verify DINK prints "DUART Make sure DINK is not trying to setup an invalid L2/L3 setting (if appropriate) or other configuration. Initialized..." then hangs. Press the backspace key and hold it down while pressing RESET. If DINK comes up, enter the command "ENV -c" Open the chassis and make sure the heat sink, especially DINK runs fine for a while, then hangs until those with a fan, is firmly attached and that the fan is connected to a power source and is turning. it cools down. Reseat the heatsink if necessary and turn it gently to tighten. 26 Check fan power connections. User's Manual PRELIMINARY-- SUBJECT TO CHANGE WITHOUT NOTICE User's Manual 7 FAQ These questions are frequently asked. 1. What mode should I use if my software was running fine on Sandpoint 2? Use AMODE=00, ILEGACY=1 and IMODE=00 or 01 (this are equivalent to modes 0 and 1 on SP2). 2. What mode should I use if I am developing new software for Sandpoint 2? Use the defaults: AMODE=00, ILEGACY=0 and IMODE=00 -- these give better performance and enable all features of the system. 3. How can I write to the serial port? It doesn't seem to be at the address shown. Like any plug-and-play device, ISA IO devices need to be plugged and played. DINK includes setup for the serial port in the file "yk.c" for both the SuperIO and the COM ports. 4. How do I access/configure the PCI devices. This depends to some extent on the MPPMC card present. If it supports Map "B" (CHRP), then the configuration cycles are performed by writing the configuration address (0x8000_0000 with the appropriate bit set for the device number) to the PCI configuration address register (0xFEC0_0000) and reading/writing from the PCI configuration data register (0xFEE0_0000). See the file "pciLib.c" in the DINK source code for examples. 5. How can I control the STAT and FAIL LEDs? To do this the GPIO port in the SuperIO needs to be enabled. Use the code in "yk.c:ns308defaults()" as a starting point. This file sets the GPIO programmable address decoder to an ISA address of 0x0700, making the IO registers available at 0xFE00_0700. Elsewhere in "yk.c" the IO port direction is set to output for bits 1 and 0. Thereafter, writing a `0'to that port activates the LED, and writing a `1'deactivates it. 7.1 Detecting Sandpoint 3 The Sandpoint 3 motherboard has a loopback connection between GPIO pins 7 and 6. If software needs to know which platform it is operating on, the following sequence will work: 1. 2. 3. 4. 5. 6. Enable the GPIO port on the SuperIO. Program GPIO pin 7 to output. Program GPIO pin 6 to input. Write 1 to GPIO pin 7; read GPIO pin 6. Write 0 to GPIO pin 7; read GPIO pin 6. If read values are "[1, 0]", then the motherboard is 3; else it is 2. User's Manual PRELIMINARY-- SUBJECT TO CHANGE WITHOUT NOTICE 27 User's Manual Appendix A:Sandpoint 3 Changes There are several differences between Sandpoint 2 and Sandpoint 3. Table 7-1 lists them, as well as any likely effect on software. Table 7-1. Sandpoint 3 Changes Change Effect on Software IDSEL disconnected for MPPMC slot. None, but software no longer has to avoid sending configuration cycles to device #12 (IDSEL addr = AD12). Secondary, larger, PCI-hosted ROM. None as long as standard addresses are used (0xFFF0_0000 to 0xFFF7_FFFF). On-board spread-spectrum clock generator. None, spread-spectrum is disabled by default. IDE interface corrected. None, 2 was rewired. IDE PCI interrupts connected properly. Software may use PCI interrupts instead of 8259 interrupts. On-board reset controller for more reliable resetting, particularly None. from COP. Cabled battery replaced with standard socketed coin. None. All PCI bus devices (PMC and PCI slots plus the Winbond) can be configured for 5V or 3V operation (as a build option). None. PCI slots are correctly numbered in order. None. Might affect any installation instructions, though if so, they could only get clearer and less confusing. Test clock input enable works. None. 28 User's Manual PRELIMINARY-- SUBJECT TO CHANGE WITHOUT NOTICE User's Manual Appendix B: Legacy Interrupt Support Sandpoint 2 had an "interesting" interrupt architecture, mostly an attempt to funnel seven interrupts into the four available MPPMC interrupts with little logic support. SP3 solves this by using the "SPF100" logic in conjunction with the serial interrupt EPIC device avaiable on Motorola MPPMC cards. However, for backward compatibility purposes, SP3 supports the SP 1/2 interrupt scheme. For more details on the interconnections, refer to the SPX2TS (Sandpoint 2 Technical Summary), available on the Motorola Website. To enable Legacy-mode interrupt connections, set the ILEGACY switch OFF (SW2-3 to the left). Then select one of the interrupt connections according to Table 7-2. Table 7-2. Legacy Interrupt Connections SW2-5 SW2-5 Sandpoint 2 Modes Interrupt Connections PMC_INT0 = Winbond INTC# 0 On (right) On (right) inverted interrupt share SLOT2 PMC_INT1 = Winbond INTD# or SIOINT Notes Winbond IDE can output to INTC#/INTD# SIOINT is inverted PMC_INT2 = SLOT3 INTA# PMC_INT3 = SLOT4 INTA# PMC_INT0 = Winbond INTC# 0 On (right) Off (left) normal interrupt share SLOT2 PMC_INT1 = Winbond INTD# or SIOINT Winbond IDE can output to INTC#/INTD# SIOINT is not inverted PMC_INT2 = SLOT3 INTA# PMC_INT3 = SLOT4 INTA# PMC_INT0 = Winbond INTC# 0 Off (left) On (right) PMC_INT1 = Winbond INTD# inverted interrupt PMC_INT2 = SLOT3 INTA# or share SLOT3 Winbond IDE can output to INTC#/INTD# SIOINT is inverted SIOINT PMC_INT3 = SLOT4 INTA# PMC_INT0 = Winbond INTC# 0 Off (left) Off (left) PMC_INT1 = Winbond INTD# normal interrupt PMC_INT2 = SLOT3 INTA# or share SLOT3 SIOINT Winbond IDE can output to INTC#/INTD# SIOINT is not inverted PMC_INT3 = SLOT4 INTA# Note: This SP3 supports legacy mode in the manner SP2 should have; namely, supporting IDE interrupt from the Winbond on INTC#/INTD# (SP3) instead of INTA#/INTB# (SP2); there's not much point emulating SP2 bugs. Using the standard modes is highly encouraged, as nothing like this will be supported on future Sandpoint platform or any other platform. User's Manual PRELIMINARY-- SUBJECT TO CHANGE WITHOUT NOTICE 29 User's Manual Appendix C: Reference Documentation Table 7-3 describes reference documentation which may be useful for understanding the operation of the Sandpoint or an attached MPPMC card: Table 7-3. Reference Documentation Document Number/Reference Sandpoint 3 Technical Summary Schematics Errata http://www.mot.com/SPS/PowerPC/teksupport/ refdesigns/sandpoint.html MPPMC Schematics Documentation Errata http://www.mot.com/SPS/PowerPC/teksupport/ refdesigns/sandpoint.html MPC8240 User's Manual http://e-www.motorola.com/brdata/PDFDB/ MICROPROCESSORS/32_BIT/POWERPC/ MPC82XX/MPC8240UM.pdf MPC107 User's Manual http://e-www.motorola.com/brdata/PDFDB/ MICROPROCESSORS/32_BIT/POWERPC/ MPC1XX/MPC107UM.pdf DINK User's Manual and code updates http://www.mot.com/SPS/PowerPC/teksupport/ tools/DINK32/dinkindex.htm Draft Standard Physical and Environmental Layers for Processor PCI Mezzanine Cards: PrPMC http://www.vita.com/vso/ PCI 2.1 Specification http://www.pcisig.com Draft Standard Physical and Environmental Layers for PCI Mezzanine Cards: PMC IEEE P1386.1/Draft 2.0 04-APR-1995 Draft Standard for a Common Mezzanine Card Family: CMC IEEE P1386/Draft 2.0 04-APR-1995 Winbond W83C553 Datasheet http://www.winbond.com.tw/sheet/w83c553f.pdf or http:///www.winbond.com.tw/ National Semi. PC87307/97307 Datasheet http://www.national.com/pf/PC/PC97307.html or http:///www.national.com/design/ Appendix D: Glossary Table 7-4 explains some terminology used in this document: Table 7-4. Terminology Term 30 Definition ATA AT (PC format) Attach - protocol for communicating over IDE bus. ATX Form factor for chassis. User's Manual PRELIMINARY-- SUBJECT TO CHANGE WITHOUT NOTICE User's Manual Table 7-4. Terminology Term Definition BBRAM Battery-Backed Random Access Memory IDE Integrated Device Electronics -- common disk interface signalling. MPPMC Motorola Processor PCI Mezzanine Card -- an superset of the VITA PrPMC specification proposal which adds PCI arbitration. PCI Peripheral Connect Interface PMC PCI Mezzanine Card -- a small form-factor PCI-2.0 compliant daughtercard standard. PPMC Processor PCI Mezzanine Card -- an early name for PrPMC; no longer used. PrPMC Processor PCI Mezzanine Card -- an extension to the IEEE1386 PMC standard adding hostrelated functions and PCI-2.1 compatibility (was formerly called PPMC). RAM Are you kidding? RTC Real Time Clock SIO System I/O (or SuperIO) - National Semi. PC-I/O device. WB WinBond, manufacturer of the ISA/IDE interface. User's Manual PRELIMINARY-- SUBJECT TO CHANGE WITHOUT NOTICE 31 ***** * Sandpoint This schematic is provided for reference purposes only. All information is subject to change without notice. No warranty, expressed or applied, is made as to the accuracy of the information contained herein. Contact Motorola Sale/FAEs to obtain the latest information on this product. ** * * * *** * *** * Supporting MPPMC603 - Talos MPPMC740 - Talos MPPMC745 - Talos MPPMC8240 - Unity MPPMC8245 - Unity MPPMC8260 - Cygnus MPPMC750 - Altimus MPPMC755 - Altimus MPPMC7400 - Altimus MPPMC7410 - Altimus MPPMC7450 - Valis ...tbd... *Digital DNA from Motorola GARY MILLIORN Schematic Notes 1. 2. Integrated circuits have default connections to power and ground unless explicitly shown otherwise. Global power connections are: GND VCC_3.3V VCC_5V 3. Part numbers used are for reference only; compatible parts may be used; refer to the bill of materials. 4. Motorola and the Motorola logo are registered trademarks of Motorola. PowerPC is a trademark of IBM. Other trademarks are the respective property of their respective copyright holders. Diane, I am holding in my hand a box of small, chocolate bunnies. All rights reserved. 5. The sheet-to-sheet cross reference format is: Sheet "-" VertZoneLetter HorizZoneNumber Components with the property "no_stuff" are not to be installed by default; they are for test or manufacturing purposes only. 6. Page Unless otherwise specified: All resistors are SMD0603, in ohms, 0.1W, +/-5% All capacitors are SMD0603, in microfarads (uF), +/-20%. All inductances are in microhenries (uH). All ferrites are Z=50 ohms at 100 MHz. All fuses are self-resetting polyswitch (PTC) devices. Board impedance is 50-60 ohms. 7. All buses follow big-endian bit numbering order (bit 0 is the most-significant bit), except where industry standards apply (i.e. PCI). Little-endian numbering is noted at the source component. Team Sandpoint * Sandpoint Cindy Black Ivan Erickson Gary Milliorn Tony Saucedo Joey Tsai Gary Wojcik PCB CAD Program Mgr. Designer Components Documentation Imperial Poobah Contents 01 Cover Page 02 03 General Information Block Diagram 04 05 Routing and Layout Information Power Supply 06 07 Clock Generation Processor PMC Socket 08 09 64-bit PCI PMC Connector PCI/ISA Bridge 10 11 IDE Connectors Super I/O Controller 12 13 Floppy, PC I/O Connectors Serial Ports 14 15 PCI Slots #1, #2 PCI Slots #3, #4 16 17 PCI Boot ROMs, NVRAM SPF100 - Arbiter/Interrupt Controller 18 19 Configuration Switches; Monitor LEDs Pullups CHANGES REV DATE X1 98MAR23 Original X2 X3 98DEC11 00JUL26 Connector orientation; crosspoint tweaks. Many changes PMC Connector 32/64 bit PPMC Extensions 66 MHz Extensions <07-08> Power Supply ATX Chassis Header <05> 32-bit/64-bit 33/66 MHz PCI Bus System Clocks PCI: 33 or 66 MHz PC Clocks. <06> IDE Connectors Southbridge (2) 33/66-MHz ATAPI PCI Slots Winbond W53C55x <10> (2) 32-bit 5V PCI slots (2) 64-bit 5V PCI slots <14,15> <09> Reset Logic Chassis Headers <05> ISA Bus Interrupt Routing Non-Volatile RAM <17> Super I/O Controller 8K bytes APC/RTC Power Supply National 87307 <16> 1) 512KB 2) 8MB <11> Arbitration Routing PC I/O Ports <17> PS/2 Keyboard & Mouse Parallel Port & Floppy Serial Ports Boot Flash Rom <12,13> <16> GARY MILLIORN Layout/Routing Instructions 06 Keep series termination resistors near the output pins. Route all PCI clock lengths to equal the WBCLK trace less 2.5" Use heavy traces for power path through filter: +3.3V => VCCO pins & Rxxx/Rxxx Combo => VCCI Pin. Surround MPC972 with 4-6 0.1uF caps to provide good ground-return paths. Keep XTAL1 pin and jumper insanely close. 07 Place PMC at top side of ATX board. 08 " 09 Use equal-length traces on nets DAK(2:0) from WinBond to 'F138. 10 Place series termination resistors near socket. 11 Use very short traces from 32kHz crystal to SuperI/O and to connected components. Allow no other traces to enter or cross the crystal oscillator area. Use 12 mil traces for VBAT and VSTDBY. 12 Place EMI filtering caps and ferrite beads very close to DIN6 and DB25 connectors. Place series resistors for parallel port near DB25 connector. 13 Keep traces very short between RS232 drivers (U1, U2) and DB9 connectors. Use 12 mil traces for +12V and -12V. 14 Place IDSEL resistor near IDSEL pin. STDBY LED PWR SW SPKR DISK LED ON CHASSIS PWR LED IR Port Use split power planes for 5V and 3.3V power. Place header in lower-left hand corner of the board (I/O connectors would be in the upper right. Allow clearance around header to allow for silkscreen legends. Label pin groups as shown. RESET SWITCH 05 15 Place IDSEL resistor near IDSEL pin. 16 Use 12 mil traces between battery connector and diodes (before and after). 17 No special restrictions. 18 No special restrictions. 19 Recommended placement for status LEDs is under the disk tray area. Place LEDs in order and label with indicated text. Follow ATX chassis specs for ATX mounting hole sizes and plated area allowance. 20 Distribute capacitors as shown, unless otherwise specified. 21 Keep traces as short as possible. Pin swapping within and without of a package is encouraged in order to minimize trace length. i i i i Local Reset Switch ATX Chassis Cable Header Place in lower-left hand corner of board for cable connection. i Local Power Switch ATX Chassis Mounting Holes NVRAM SOURCING Select VSTDBY or battery as available. i TEST CLOCK INPUT Select CLKOFF to select external 50ohm clock source. i CLOCK EQUALIZATION Route indicated clocks to match WBCLK less 2.5 inches per PCI and PMC specifications. i PCI VIO SELECT Select 3.3V or 5V VIO option. Default: 5V i PRIMARY IDE i SECONDARY IDE i 32kHz Oscillator Keep all traces extremely short. Route no traces through that area. i i PS/2 Keyboard i PS/2 Mouse i Floppy connector Parallel Port Right-angle PCB mount i i Serial Port #1 Serial Port #2 i PCI Slot #1 IDSEL AD13 Closest to PMC. i PCI Slot #2 IDSEL AD14 Next-closest to PMC. i PCI Slot #3 IDSEL AD15 Third from PMC. i PCI Slot #4 IDSEL AD16 Furthest from PMC. i Diagnostic LEDs Place in visible area. Sandpoint Errata Page 1 /5 Sandpoint Reference Platform Errata c Board Revision Level X3 Errata Revision Level A Copyright 2001 by Motorola Incorporated. All rights reserved. Motorola Inc. Unrestricted Distribution Permitted 01 Feb 16 Sandpoint Errata Page 2 /5 Revision History Version A Date 2001 Jan 31 2001 Feb 16 Changes Initial errata. Changed method for errata #7. Motorola Inc. Unrestricted Distribution Permitted 01 Feb 16 Sandpoint Errata Page 3 /5 Table 1: Summary of Sandpoint Errata # 1 2 Type Problem Design Clocks not working. Design Soft-power inoperative. Cause Work-Around Affects Rev W185 enables are tied low; should be tied high. 1. Cut trace between U1 pin 18 and ground via. X3 A EN1 and EN2 should be connected to +3.3V. Only EN1 is required. 2. Connect U1 pin 18 to U1 pin 16 (+3.3V). VBAT needs to be ~3.0V. If CR2032 Coin Battery used: X3 A X3 A X3 A X3 A Coin cells are 3V, cabled batteries are 4.5V. R44 values must be selected based upon battery used. For X4: Connect pin 18 of U1 to +3.3V. 1. Remove 0 ohm resistor on half of dualresistor component R44 nearest ATX power header. If Rayovac Cabled Battery used: 1. Install 100K ohm resistor on portion of R44 nearest National SuperIO. 2. Install 27K ohm resistor on portion of R44 nearest ATX header. For X4: Use two discrete resistors; standardize on coin cell. 3 Design Soft power not working. No pullup allowed on PS_ON. 1. Cut trace between RN72 pin 5 and via connecting to VCC3.3. For X4: Delete pullup. 4 Design PCI arbiter not working. No pullups on SLOT_REQ(1:4) Connect (4) 4.7K ohm resistors between SLOT1/SLOT2/SLOT3/SLOT4 pins B18 and B19 on the bottom of the board. For X4: SLOT_INT(1:4) on page 19 should be for SLOT_REQ(1:4). 5 Design None. SLOT_INT(1:4) pulled up twice. None. For X4: Remove redundant pullups. Motorola Inc. Unrestricted Distribution Permitted 01 Feb 16 Sandpoint Errata Page 4 /5 Table 1: Summary of Sandpoint Errata # 6 Type Design Problem None. Cause WB_GNT(0:4) pulled up twice. Work-Around None. Affects Rev X3 A X3 A For X4: Remove redundant pullups. 7 Design Slot 3 interrupt not responding. Slot 3 INTA/INTB pins connected incorrectly. 1. Remove all solder on SLOT3 pin A6. 2. Cover pin with Teflon or equiv. insulating sleeve. 3. Connect SLOT3 pin A6 to SLOT3 pin B7. For X4: Connect INTA# to SLOT_INT(3), INTB# to SLOT_INT(4). Motorola Inc. Unrestricted Distribution Permitted 01 Feb 16 Sandpoint Errata Page 5 /5 Errata 7: SLOT3 Interrupt Connection OVERVIEW The SLOT #3 INTA# and INTB# interrupts are wired incorrectly. WORKAROUND The work-around corrects INTA# only. A multi-interrupt card should not be used in SLOT 3. 1. Remove all solder on SLOT3 pin A6. Place Teflon sleeve over pin. 2. Connect SLOT3 pin A6 to SLOT3 pin B7 SLOT 2 SLOT 3 A1 SLOT 4 R21 B7 A6 Motorola Inc. Unrestricted Distribution Permitted 01 Feb 16 SP3 TALOS Talos UNITY ALTIM VALIS Talos X1 (PrPMC60x/PrPMC7x5) Configuration Guide NAME DEF ROMLOC n=1 e=0 RCS0 on local bus RCS0 on PCI MAPSEL n=1 e=0 Map "B" / CHRP Map "A" / PReP PMCTYPE n=1 e=0 MOT MPPMC VITA PrPMC AGENT n=1 e=0 Free agent Wait for host PROGSEL n=1 e=0 RCS0 selects local flash (boot) RCS1 selects local flash (prog.) ROMSEL n=1 e=0 Main ROM selected Backup ROM selected M66EN n=1 e=0 66 MHz PCI allowed 33 MHz PCI only SYSRST n=1 e=0 COP resets only MPPMC COP resets system 123 45678 ON 12 345678 ON 3 2 1 e e n e e e e n n e e e n e e n e e e e n n e n n n e 107PLL 0 PCI BUS 33 33 e 20 40 e 33 66 e n 33 100 n 66 120 n 30 120 n 33 83 n 66 66 e bypass 0 1 2 n e e n n n n e n e n n n e n n e e n n e n e n e e n e e n n e e e e n n n n Revised: 2000 Jun 13 CPUPLL 3 Mult. 3X e 3.5X e 4X e n 4.5X n 5X n 5.5X n 6X e 6.5X 7X e n 7.5X 8X e n byp. n off 33 100 116 133 150 166 183 200 216 233 250 266 33 0 66 200 233 266 300 330 363 400 433 466 500 528 66 0 83 250 292 333 372 415 456 500 540 580 622 664 83 0 100 300 350 400 450 500 550 600 650 700 750 800 100 0 DESCRIPTION Talos* PPMC603 PPMC740 PPMC745 PRELIMINARY RELEASE This schematic is provided for reference purposes only. All information is subject to change without notice. No warranty, expressed or applied, is made as to the accuracy of the information contained herein. Contact Motorola Sale/FAEs to obtain the latest information on this product. Motorola Confidential Proprietary *Digital DNA from Motorola Schematic Notes 1. 2. Integrated circuits have default connections to power and ground unless explicitly shown otherwise. Global power connections are: GND VCC_3.3 VCC_2.5 VCC_5 VCORE 3. Part numbers used are for reference only; compatible parts may be used; refer to the bill of materials. 4. Motorola and the Motorola logo are registered trademarks of Motorola. PowerPC is a trademark of IBM. Other trademarks are the respective property of their respective copyright holders. No one can explain what the Matrix is, you have to see it for yourself. All rights reserved. No warranty is made, express or implied. 5. The sheet-to-sheet cross reference format is: Sheet "-" VertZoneLetter HorizZoneNumber Components surrounded by a dashed/crossed-out box are not to be installed by default; they are for test or manufacturing purposes only. 6. 7. Page Unless otherwise specified: All resistors are SMD0805, in ohms, 0.08W, +/-5% All capacitors are SMD0603, in microfarads (uF), +/-20%. All inductances are in microhenries (uH). All ferrites are Z=50 ohms at 100 MHz. All fuses are self-resetting polyswitch (PTC) devices. Board impedance is 50-60 ohms. Team Altimus Talos* Cindy Black Ivan Erickson Gary Milliorn Tony Saucedo Joey Tsai Gary Wojcik Cover Page 02 03 General Information Block Diagram 04 05 Routing and Layout Information Power Supply 06 07 MPC60X/MPC7XX Processor System Configuration MPC107: System Logic 08 09 All buses follow big-endian bit numbering order (bit 0 is the most-significant bit), except where industry standards apply (i.e. PCI). Little-endian numbering is noted at the source component. Contents 01 MPC107: Processor Interface 10 11 MPC107: PCI Interface MPC107: Memory Interface 12 13 SDRAM SODIMM Socket Local Boot ROM 14 15 Configuration Logic / LEDs PMC Connectors. 16 Stand-alone Support PCB CAD Program Mgr. Designer Components Documentation Manager Motorola Confidential Proprietary CHANGES REV DATE X1 99AUG02 Initial version Power Supply Processor Motorola MPC60X/MPC740 350-450 MHz 5V to 1.9..2.5V Switcher Programmable <05> <06-08> 64/72-bit 50-83 MHz Local Bus Boot ROM Northbridge 1Mbyte Memory SDRAM SODIMM Motorola MPC107 <16> <11-14> 32-bit 33/66 MHz PCI Bus PMC Connector 32 bit PPMC Extensions <18> Motorola Confidential Proprietary <15> Layout/Routing Instructions 05 Use split power plane to connect VCORE from power supply to CPU core. Place 820 uF low-ESR capacitors near CPU. Place VID pulldown resistors in order shown. Use split power plane or very heavy traces for power path: +5V => MOSFET Qx => Inductor Lx => Low-Ohm Res. Rx => VCORE Plane Keep trace from 680 uF low-ESR capacitors within 2 cm of high-side MOSFET (Q2). Keep MOSFET gate drive lines < 2 cm. Keep VCCA/VCCP attachment within 2 cm of input filter location. Keep VCORE power flowing point-to-point through MOSFETs, inductor, resistor and output filter capacitors. Use short traces throughout. Use DPAK pads that meet or exceed thermal relief recommendations. Place MPC107 power supply beneath MPC107 if possible. 06 Avoid routing traces, especially noisy ones, across CPUPLL bus. Keep AVDD filter near MPC60X. Use heavy, short traces from filter to pins. 07 Place switches as shown on diagram. COP header does not need to be near anything. It should be placed in a relatively accessible area. Do not swap pins on the switches; position is important. 11 Place series termination resistors very near source (MPC107), < 2cm. Route SDRAM clocks to equal lengths, including SDRAM_SYNCOUT to SDRAM_SYNCIN path. 12 No special routes. 13 Keep data bus load for ROMs short. 14 15 Place LEDs away from COP overhang (for visibility). Maximum trace length for PCI signals to MPC107 is 1.5" per the PCI specification. COP SWITCH SWITCH LEDs MPC60X or MPC74x Motorola Confidential Proprietary MPC107 LT1118 POWER RC5051 P2 PCI clock input must be 2.5" (per specification). Keep AVDD/AVDD2/LAVDD filters near MPC107. Use heavy, short traces from filter to pins. Place beneath the part if possible, in the center cavity area. Surround MPC107 with bypass caps to provide additional ground-return paths. Use two ground-attach vias. P1 No special routes. 10 FLASH Am29LV800 09 FLASH Am29LV800 Avoid routing traces, especially noisy ones, across MPC107 PLL bus. Do not swap order of MPC107 PLL switch connections. SODIMM Socket 08 i i VCC_2.5 OUTPUT Low-power regulator supplies +2.5V to the MPC107 core logic. Add 2-3 cm^2 to the ground plane area on the top of the PCB for additional thermal dissipation. i VCORE OUTPUT i VOLTAGE SEQUENCING Programmable CPU core voltage; may be programmed from 1.8V to 3.6V. VCORE OUTPUT 4 O O O O O O O O O O O O O O O O I I I I I I I I I I I I I I I I VID 3 2 O O O O O O O O O I O I O I O I I O I O I O I O I I I I I I I I O O O O O O O O O I O I O I O I I O I O I O I O I I I I I I I I 1 O O I I O O I I O O I I O O I I O O I I O O I I O O I I O O I I 0 O I O I O I O I O I O I O I O I O I O I O I O I O I O I O I O I VCORE 2.05V 2.00V 1.95V 1.90V 1.85V 1.80V 1.75V 1.70V 1.65V 1.60V 1.55V 1.50V 1.45V 1.40V 1.35V 1.30V 3.5V 3.4V 3.3V 3.2V 3.1V 3.0V 2.9V 2.8V 2.7V 2.6V 2.5V 2.4V 2.3V 2.2V 2.1V 0.00V i i KELVIN CONNECTION Route IFB and VFB traces paired BULK CAPACITANCE Distribute around the board. MPC750A MPC60X Motorola Confidential Proprietary Restricts power supplies to specification limits. Not needed if ramp < 500 uS. Motorola Confidential Proprietary i CP0 CP1 CP2 CP3 CPU PLL SETTINGS (MPC740) i BUS CLOCK 66 83 100 200 250 300 233 292 -266 --- CP2 CP3 BUS MULT ---- ON -ON ON --- ON ON ON 3X 3.5X 4X 33 --133 ON ----ON -ON ON -ON ON --ON ON --- ----ON ON 4.5X 5X 5.5X 6X 6.5X 7X 150 166 183 200 216 233 300 ------ ------- ------- ON -ON -- ON -ON -- ON ON --- -ON --- 7.5X 8X bypass off 250 266 33 0 --66 0 --83 0 --100 0 C3P0 CP1 XP0 XP1 XP2 XP3 i i MPC107 PLL SETTINGS PCI CLOCK 33 20 33 MULT. 1X 2X 2X GP0 ON ON ON GP1 ON ON -- GP2 ON -ON GP3 -ON -- -----ON ON ON ON --ON ON ON -ON ON -- ON -ON ON --- 33 66 30 33 66 33-66 3X 1.5X 4 2.5X 1X 1X 100 100 120 83 66 33-66 -- -- -- -- -- OFF -- ROM LOCATION RL ROM LOCATION ON -- ROM on PCI Bus ROM on Local Bus ADDRESS MAP SELECT AM ON -- RL AM ADDRESS MAP MAP "B": CHRP MAP "A": PREP PPMC TYPE D32 PT ON -- AG PM RS DATA BUS SIZE Motorola PPMC VITA PPMC AGENT MODE P66 AM ON -- US AGENT MODE Wait for initialization (Peripheral Mode) Free Agent Mode PROGRAM MODE PM PROGRAM MODE ON -- Enable local ROM alias. Normal mode. ROM SELECT RS ON -- ROM SELECT Auxillary ROM (swap RCS0/RCS1) Normal ROM. PCI 66 MHz ENABLE P66 ON -- PCI 66 MHz Enable 66 MHz operation 33 MHz only. SYSTEM RESET SR ON -- i DEFINITION COP can reset target system. COPonly resets local CPU/MPC107. COP Connector Processor debug access port. NOTE: Connector should be routed to look as appears below. Motorola Confidential Proprietary BUS CLOCK 33 40 66 CPU Power and Bypass Capacitors Keep near CPU i CLOCK FEEDBACK Add 1 ns delay (6 inches) to compensate for trace delay added to SDRAM clock feedback path. Motorola Confidential Proprietary Motorola Confidential Proprietary i PCI Clamp Voltage 3.3V or 5V depending upon VIO selection (see page 15). i PLL Filters Use 15 mil traces and keep them short. i VITA PPMC Spec Compliance If not compliant with forthcoming VITA PPMC, install both resistors. i Motorola Confidential Proprietary PCI Clock Trace Must equal exactly 2.5" from connector pin to MPC107 pin, per specifications. i SERIES TERMINATION Keep within 2 cm of MPC107. i CLOCK FEEDBACK Set trace length equal to that of other clocks and SDRAM control traces plus 1 ns (6 inches). Clock delay is added only to this feedback path. Motorola Confidential Proprietary Motorola Confidential Proprietary i SECTOR PROTECT/UNPROTECT Apply 12V to activate or override the boot sector protection. Resistor need not be removed. Motorola Confidential Proprietary i i Diagnostic PLD Optional instalation for LED monitoring and in-system programming support. Motorola Confidential Proprietary MPC107 Configuration Logic Refer to Book IV, table 144 for details. i V(I/O) SELECTION Select 3.3V or 5V V(I/O) option. ONE ONLY! Motorola Confidential Proprietary i i STAND ALONE CLOCK Install oscillator or socket for standalone operation. STAND ALONE RESET Install jumper to enable on-board reset switch. Talos PowerPMC Errata Page 1 /3 Talos PowerPMC Errata c Board Revision Level X1 Errata Revision Level A Copyright 1999 by Motorola Incorporated. All rights reserved. Motorola Inc. Unrestricted Distribution Permitted 00 Mar 24 Talos PowerPMC Errata Page 2 /3 Revision History Version A Date 1999 Oct 21 Changes Initial errata. Motorola Inc. Unrestricted Distribution Permitted 00 Mar 24 Talos Errata Page 3 /3 Table 1: Summary of Talos Errata # 1 Type Design Problem Impact Work-Around Affects Sector Protection circuitry is incorrect; attempts to apply +12V (sector protect enable) would impress +12V on the system reset logic. Second ROM cannot be sector protected because damage to the board may occur. Cut trace fromU5 pin 12. Connect U5 pin 12 to TP "SECPROT". A Rev Motorola Inc. Unrestricted Distribution Permitted 00 Mar 24 SP3 TALOS Unity UNITY ALTIM VALIS Unity X4 (MPPMC824X) Configuration Guide ON 1234 5678 ON 1234567 8 DESCRIPTION NAME DEF ROMLOC e=1 n=0 RCS0 on PMC RCS0 on PCI MAPSEL e=1 n=0 Map "B"/ CHRP Map "A"/ PReP PrMCTYPE e=1 n=0 MOTSPS PrPMC VITA PrPMC AGENT e=1 n=0 Free agent Wait for host PROGSEL e=1 n=0 RCS0 selects local flash (boot) RCS1 selects local flash (prog.) ROMSEL e=1 n=0 Main ROM selected Backup ROM selected M66EN e=1 n=0 66 MHz PCI allowed 33 MHz PCI only SYSRST e=1 n=0 COP resets only PrMC COP resets system Revised: 2000 Oct 04 CPU PLL Settings CPUPLL PCI Memory CPU 0 1 2 3 4 Clock Clock Clock nnnnn 33 100 250 nne nn 25 50 100 ne nnn 33 33 100 nee nn 33 66 166 nee e n 33 66 200 e nnnn 33 100 200 e nne n 66 100 200 e ne nn 33 66 233 e ne e n 33 66 266 e e nnn 33 83 250 e e ne n 66 66 266 e e enn 50 75 225 e e ene 66 100 250 n n e e X bypass n n n n X off PCI 5 6 Hold n n 0.5 - 0.9 ns n e 1.3 - 1.7 ns e n 2.1 - 2.5 ns e e 2.9 - 3.3 ns 7 e n PCI Drive 25 ohms 50 ohms 4 * Unity X PPMC8240 PPMC824X PRELIMINARY VERSION This schematic is provided for reference purposes only. All information is subject to change without notice. No warranty, expressed or applied, is made as to the accuracy of the information contained herein. Contact Motorola Sale/FAEs to obtain the latest information on this product. You're not really paying attention, are you, I could write anything here and you'd never notice. *Digital DNA from Motorola GARY MILLIORN Schematic Notes 1. Page Contents Unless otherwise specified: All resistors are SMD0603, in ohms, 0.08W, +/-5% All capacitors are SMD0603, in microfarads (uF), +/-20%. All inductances are in microhenries (uH). All ferrites are Z=50 ohms at 100 MHz. All fuses are self-resetting polyswitch (PTC) devices. Board impedance is 50-60 ohms. 01 Cover Page 02 03 General Information Block Diagram 2. Integrated circuits have default connections to power and ground unless explicitly shown otherwise. Global power connections are: VCC_2.5V GND VCORE VCC_3.3V VCC_5V 04 05 Routing and Layout Information Power Supply 3. Part numbers used are for reference only; compatible parts may be used; refer to the bill of materials. 4. Motorola and the Motorola logo are registered trademarks of Motorola. PowerPC is a trademark of IBM. Other trademarks are the respective property of their respective copyright holders. I've got good news! That gum you like is going to come back in style. All rights reserved. 06 07 System Configuration MPC8240 System Interface; I2C 5. The sheet-to-sheet cross reference format is: Sheet "-" VertZoneLetter HorizZoneNumber Components surrounded by a dashed/crossed-out box are not to be installed by default; they are for test or manufacturing purposes only: 08 09 MPC8240 Memory; SODIMM Socket MPC8240 PCI Interface; Power 10 11 Dual Flash ROMs UART; Standalone Support 12 13 Miscellany; LEDs; Mode Mux PMC Connectors P1, P2 6. 7. All buses follow big-endian bit numbering order (bit 0 is the most-significant bit), except where industry standards apply (i.e. PCI). Little-endian numbering is noted at the source component. 4 * Unity X REV DATE CHANGES X1 X2 98APR22 98OCT04 Original X3 X4 99OCT20 00FEB22 MPC8240 II Support; VITA PPMC changes; More Flash; I2C; Delete debug headers Chip pinout changes; COP tweak. PCB Changes only. UART <11> Power Supply 5V->2.5V Switcher <05> 64-bit 100 MHz Local Bus Configuration PLL Modes Board Modes <06> Boot Flash ROM Auxillary ROM Processor SDRAM Motorola MPC8240 200-266 MHz <10> SODIMM 16-64 MByte <07-09> Monitors and Modes LEDs Mot/VITA PMC Mode <12> 32-bit 33/66 MHz PCI Bus Standalone Support Clock: 33 MHz Reset PMC Connector <11> 32 bit PPMC Extensions <13> <08> GARY MILLIORN Layout/Routing Instructions 05 Use split power plane to connect VCC_2.5 from power supply to CPU core. Place 820 uF low-ESR capacitors near CPU. Place VID pulldown resistors in order shown. Use split power plane or very heavy traces for power path: +5V => MOSFET Qx => Inductor Lx => Low-Ohm Res. Rx => VCC_2.5 Plane Keep trace from 68 uF low-ESR capacitors within 2 cm of high-side MOSFET (Q2). Keep MOSFET gate drive lines < 2 cm. Keep VCCA/VCCP attachment within 2 cm of input filter location. Keep VCC_2.5 power flowing point-to-point through MOSFETs, inductor, resistor and output filter capacitors. Use short traces throughout. 07 No special restrictions 08 Place series termination resistors very near source, < 1.5 cm. Route terminated traces using equal trace lengths towards SDRAM array. Route SDRAM_SYNC_OUT => SDRAM_SYNC_IN path to equal longest clock trace. Route all control, address and data traces to equal lengths. 09 Place PLL filters on bottom of PCB beneath MPC8240 Use short heavy traces on PLL filter power. Surround MPC8240 with bypass caps shown to provide additional ground-return paths; use two ground-attach vias. Place bulk capacitance near BGA IVDD and +3.3V ground planes. 10 Place SODIMM socket within 3.5cm of MPC6xx (center-to-center). 11 No special instructions. 12 Place LEDs so they are visible on the top and legends are nearby. 13 Maximum trace length for PCI signals to MPC8240 is 1.5" per the PCI specification. Reset Serial Port SODIMM Socket FLASH Am29DL323 VDD OVDD LEDs STAT PCI ROM RAM iSP COP P2 Place slide switches in vertical orientation and do not swap PLL config pins. P1 06 i i VCC_2.5 OUTPUT 4 O O O O O O O O O O O O O O O O I I I I I I I I I I I I I I I I VID 3 2 O O O O O O O O O I O I O I O I I O I O I O I O I I I I I I I I O O O O O O O O O I O I O I O I I O I O I O I O I I I I I I I I 1 O O I I O O I I O O I I O O I I O O I I O O I I O O I I O O I I 0 O I O I O I O I O I O I O I O I O I O I O I O I O I O I O I O I VCORE 2.05V 2.00V 1.95V 1.90V 1.85V 1.80V 1.75V 1.70V 1.65V 1.60V 1.55V 1.50V 1.45V 1.40V 1.35V 1.30V 3.5V 3.4V 3.3V 3.2V 3.1V 3.0V 2.9V 2.8V 2.7V 2.6V 2.5V 2.4V 2.3V 2.2V 2.1V 0.00V i MPC824X BULK CAPACITANCE Distribute around the board. i VOLTAGE SEQUENCING Restricts power supplies to specification limits. Not needed if ramp < 500 uS. VCC_2.5 OUTPUT Nominal voltage; actual output may be programmed from 1.8V to 3.6V. i P0 P1 P2 P3 P4 SYSTEM SPEED SETTINGS P0 P1 P2 P3 P4 PCI Clock Memory Clock Processor C C C C C C C - C C - C C C C - C C C C C 33 MHz 25 MHz 33 MHz 33 MHz 33 MHz 100 MHz 50 MHz 33 MHz 66 MHz 66 MHz 250 MHz 100 MHz 100 MHz 166 MHz 200 MHz - C C C C - C C C C C C C C C C C 33 MHz 66 MHz 33 MHz 33 MHz 33 MHz 100 MHz 100 MHz 66 MHz 66 MHz 83 MHz 200 MHz 200 MHz 233 MHz 266 MHz 250 MHz C - C - C - C C - C C X X 66 MHz 50 MHz 66 MHz Bypass Off 66 MHz 75 MHz 100 MHz Bypass 0 266 MHz 225 MHz 250 MHz Bypass 0 DEBUG ENABLE i BUS WIDTH Install to enable debug mode. PCI HOLD TIME PH0 PH1 PH0 PH1 PD 0 0 1 1 0 1 0 1 PCI Hold 0.5 - 0.9 ns 1.3 - 1.7 ns 2.1 - 2.5 ns 2.9 - 3.3 ns PCI DRIVE STRENGTH D2 i D1 PD PCI Bus 0 50 ohm 1 25 ohm MEMORY DRIVE STRENGTH D2 D1 0 0 1 1 i 0 1 0 1 Memory 40 ohm 20 ohm 13 ohm 8 ohm ROM LOCATION RL ON ROM LOCATION ROM on PCI Bus -- ROM on Local Bus ADDRESS MAP SELECT AM ON -- ADDRESS MAP MAP "A": PREP MAP "B": CHRP PPMC TYPE RL PT ON -- AM PT AG DATA BUS SIZE Motorola PPMC VITA PPMC AGENT MODE PM AM AGENT MODE RS ON -- Wait for initialization (Peripheral Mode) Free Agent Mode P66 PROGRAM MODE SR PM ON -- PROGRAM MODE Enable local ROM alias. Normal mode. ROM SELECT RS ON -- ROM SELECT Select alternate ROM Select normal ROM PCI 66 MHz ENABLE P66 ON -- PCI 66 MHz Enable 66 MHz operation 33 MHz only. SYSTEM RESET SR ON -- i DEFINITION COP can reset target system. COPonly resets local CPU/MPC107. COP Connector Processor debug access port. NOTE: Connector should be routed to look as appears below. Install for 32-bit bus mode. i BOARD ID i CLOCK TRACE ROUTING Route all clock traces from MPC8240 to series resistors in equal trace lengths. Route from series resistors to destination in equal lengths plus any additional trace length needed to compensate for high speeds or high loads. Refer to AN1722/D for details. i i PCI Clock Trace Must equal exactly 2.5" from connector pin to MPC824X pin, per specifications. PCI Clamp Voltage 3.3V or 5V depending upon VIO selection (see page 15). i SECTOR PROTECT/UNPROTECT Apply 12V to activate or override the boot sector protection. Resistor need not be removed. i i STAND ALONE CLOCK Install oscillator or socket for standalone operation. STAND ALONE RESET Install jumper to enable on-board reset switch. i V(I/O) SELECTION Select 3.3V or 5V V(I/O) option. ONE ONLY! Unity Errata Page 1 /3 Unity PowerPMC Errata c Board Revision Level X4 Errata Revision Level B Copyright 1999 by Motorola Incorporated. All rights reserved. Motorola Inc. Unrestricted Distribution Permitted 00 Mar 24 Unity Errata Page 2 /3 Revision History Version A Date 2000 Mar 24 Changes Initial errata. Motorola Inc. Unrestricted Distribution Permitted 00 Mar 24 Unity Errata Page 3 /3 Table 1: Summary of Unity Errata # Type Problem Impact Work-Around Affects Rev 1 Design MA11 is not a ROM address pin on the MPC8240 Cannot access all of Am29DL323 flash devices. Replace with Am29LB800 (1MByte) X4 A 2 Design R28 is not properly placed to allow sector protection of second flash. Cannot use sector protection on second flash (U4). Lift U4 pin 12 and connect to TP "SPR". X4 A 3 Design If debug mode is enabled (R29 installed), REQ4 will remain low, causing the arbiter to grant bus. Eventually this will be detected as a broken master and the arbiter will disable it. May reduce performance during startup for first 100 clock cycles or so. Don't enable debug mode if performance is important. X4 A Motorola Inc. Unrestricted Distribution Permitted 00 Mar 24 SP3 TALOS Altimus UNITY ALTIM VALIS Altimus X3 (MPPMC75x/MPPMC74x0) Configuration Guide ON 1234 5678 BOARD OPTIONS NAME SET n=0 e =1 SYSRST n=0 M66EN e =1 n=0 ROMSEL e =1 n=0 PROGSEL e =1 n=0 AGENT e =1 n=0 PMCTYPE e =1 n=0 MAPSEL e =1 n=0 ROMLOC e =1 ON 1234 5678 MPC75x/74xx PLL 3 2 1 0 Mult. e e n n byp. n n n e 3X n e e e 3.5X n e n e 4X n 4.5X e e e 5X e e n e n n 5.5X e e 6X e n e e n e n e 6.5X n e n n 7X e n n n 7.5X n n e e 8X n n n n 9X Revised: 2000 Oct 26 33 33 100 116 133 150 166 183 200 216 233 250 266 300 66 66 200 233 266 300 330 363 400 433 466 500 528 600 83 83 250 292 333 372 415 456 500 540 580 622 664 750 100 100 300 350 400 450 500 550 600 650 700 750 800 900 PCI COP resets MPPMC & system COP resets MPPMC only 33 MHz PCI only 66 MHz PCI allowed Alternate Flash selected Standard Flash selected Local flash is programmable Local flash is bootable Free agent Wait for host MOTSPS MPPMC (arbiter) VITA PrPMC (no arbiter) Map "A"/ PReP Map "B"/ CHRP RCS0 on PCI RCS0 on local bus MPC107 PLL 3 2 1 0 PCI BUS n n n n 33 33 n e n n 20 40 33 66 e n e n n n n e 33 100 66 120 e n n e n e n e 30 120 n n e e 33 83 n 66 66 e e e n n bypass e e Altimus Errata Page 1 /3 Altimus MPPMC75x/MPPMC74xx Errata c Board Revision Level X3 Errata Revision Level A Copyright 2000 by Motorola Incorporated. All rights reserved. Motorola Inc. Unrestricted Distribution Permitted 00 Nov 28 Altimus Errata Page 2 /3 Revision History Version A Date 2000 Oct 23 Changes Initial errata. Motorola Inc. Unrestricted Distribution Permitted 00 Nov 28 Altimus Errata Page 3 /3 Table 1: Summary of Altimus Errata # 1 Type Design Problem No pullup on CHKSTP_IN. Processor immediately checkstops. Impact CPU halts. Work-Around Affects Add pullup between COP header J7 pin 8 and R79 pin 1 (side not connected to J7). X3 Rev X4: Add 10K pullup to COP CHKSTP_IN* port. 2 CAD OVDD power traces are weak Possible problems w/2.5V I/O. None X3 X4: Enhance power traces from Micrel power supply into planes. 3 Design No pulldown option on SDMA1 to select DLL_EXTEND. May not operate at bus speeds below 50 MHz. Add pulldown to SDMA1 trace. X3 X4: Add pulldown config. option. Motorola Inc. Unrestricted Distribution Permitted 00 Nov 28 Altimus* PPMC750 PPMC755 PPMC7400 PPMC7410 X3 RELEASE This schematic is provided for reference purposes only. All information is subject to change without notice. No warranty, expressed or applied, is made as to the accuracy of the information contained herein. Contact Motorola Sale/FAEs to obtain the latest information on this product. *Digital DNA from Motorola Schematic Notes 1. 2. Integrated circuits have default connections to power and ground unless explicitly shown otherwise. Global power connections are: OVDD VDD_MEM GND VCC_3.3 VCC_2.5 VCC_PCI_C VCC_5 VCORE 3. Part numbers used are for reference only; compatible parts may be used; refer to the bill of materials. 4. Motorola and the Motorola logo are registered trademarks of Motorola. PowerPC is a trademark of IBM. Other trademarks are the respective property of their respective copyright holders. Drop by your local Monongahela metal foundry for some shiny steel ingots today! All rights reserved. No warranty is made, express or implied. 5. The sheet-to-sheet cross reference format is: Sheet "-" VertZoneLetter HorizZoneNumber Components labelled with "No_Stuff" are not to be installed by default; they are for test or manufacturing purposes only. 6. 7. Page Unless otherwise specified: All resistors are SMD0603, in ohms, 0.08W, +/-5% All capacitors are SMD0603, in microfarads (uF), +/-20%. All inductances are in microhenries (uH). All ferrites are Z=50 ohms at 100 MHz. All fuses are self-resetting polyswitch (PTC) devices. Board impedance is 55 +/- 5 ohms. All buses follow big-endian bit numbering order (bit 0 is the most-significant bit), except where industry standards apply (i.e. PCI). Little-endian numbering is noted at the source component. Team Altimus Altimus* Layout Cindy Black Ivan Erickson Program Mgr. Designer Gary Milliorn Tony Saucedo Components Documentation Joey Tsai Margarito TrevinoTechnician Gary Wojcik Ref. Plat. Mgr Contents 01 Cover Page 02 03 General Information Block Diagram 04 05 Routing and Layout Information Power Supplies and Power Options 06 07 MPC75x/MPC74x0 System Logic MPC75x/MPC74x0 Cache Interface 08 09 10 11 MPC75x/MPC74x0 Power/Options L2 Cache SRAM Reserved MPC107: System Logic 12 13 MPC107: Processor Interface MPC107: PCI Interface 14 15 MPC107: Memory Interface SDRAM: 64MB SMT + Parity/ECC 16 17 Boot and Secondary Flash Configuration Logic / LEDs 18 19 PMC Connectors. Analyzer Headers REV DATE CHANGES X1 98DEC01 Initial version X2 99JUN15 Add pullups; correct cap sizes; PAL logic; I2C; VITA changes. X3 00MAR22 MPC7410 2.5V IO support. SDRAM ECC support. Processor Motorola MCM69P/R737 1M/2M 100-400 MHz Motorola MPC74x0/MPC75x 300-600 MHz 06-08 Backside L2 Cache 09 5V to 1.5..2.6V Switcher Programmable 8A 05 Core Power Supply 32-bit 33/66 MHz PCI Bus PMC Connector 32 bit PPMC Extensions Memory Discrete SDRAM ECC/Parity 15 Motorola MPC107 11-14 Northbridge 05 1Mbyte 18 Boot ROM MPC107 Power 3.3V to 2.5V Linear 800 mA 64/72-bit 100+ MHz Local Bus 16 3.3V to 2.5V Linear 1.5A 05 2.5V OVDD Power Layout/Routing Instructions MICTOR SIG SIG L L2A(0:17), L2CE, L2WE, L2ZZ, L2CLKOUTA, L2CLKOUTB are routed as a split 'Y': B1 SIG FLASH Am29LV800 Avoid routing traces, especially noisy ones, across CPUPLL bus. Do not swap order of CPUPLL switch connections. Surround CPU with bypass caps to provide additional ground-return paths. Use two ground-attach vias. 09 See '07' for routing details. Place adjacent to CPU with 5mm clearance for clip-on CPU heatsink. Place VREF supply local to SRAM. 11 Place series termination resistors within 1 cm of corresponding clock pin. Route CPU_CLK(0:2) clocks to equal trace lengths SL (including path to series termination resistor). Then add same delay add additional delay as added to SDRAM_SYNC_OUT path (SDFEED). Place CK7 testpoint on top of PCB (accessibility). 13 Keep AVDD/LAVDD filters near CPU. Use shortest possible traces. Place Lt1118 power supply and bypass caps beneath MPC107 in center cavity. Use isolated/split power plane for MPC107 VDD power (VCC_2.5). Connect VCC_PCI_C (PCI Clamp) using heavy trace. 14 Place series termination resistors within 1 cm of corresponding clock/signal pin. Route SDCLK(1:4)/SDRAM_SYNC_OUT clocks to equal trace lengths SL (including path to series termination resistor). Then add 1.0ns (~15cm) to all clocks traces for output hold time adjust. See also CPU_CLK extra delay. 15 Keep trace lengths short (<3 cm) and equalized for all traces. Place two bypass caps per device. 16 Place ROMs so as to minimize length of D(0:7), preferably underneath SDRAM device on D(0:15). Place SPR testpoint on top of board. 17 Place LEDs together on edge of board with visible labels. 18 Place VCC_PCI_C option resistors adjacent. MIC2179 PAL MCM69(P/R)737 SRAM MPC107 MPC7400 or MPC75x MCM69(P/R)737 SRAM .062 LAYER 1 LAYER 2 LAYER 3 LAYER 4 LAYER 5 LAYER 6 LAYER 7 LAYER 8 LAYER 9 LAYER 10 LAYER 11 LAYER 12 VERT HOR VERT HOR VERT HOR VERT HOR SIGNAL1 POWER: GROUND SIGNAL2 SIGNAL3 POWER: VCC_3.3, VCORE SIGNAL4 SIGNAL5 POWER: VCC_MEM, OVDD, VCC_2.5, VCACHE, VCC_5 SIGNAL6 SIGNAL7 POWER: GROUND SIGNAL8 LT1118 RC5051 P2 SWITCH LEDs FLASH Am29LV800 ISP COP 08 MICTOR Fan SIG A B2 SIG Trace lengths must be equal, such that A+B1 = A + B2 = L for all cache signals. Trace length for L2SYNC_OUT to L2SYNC_IN feedback path (including the resistor) must equal other clocks (L). MICTOR P1 Keep AVDD/L2AVDD filters near CPU. Use shortest possible traces. All L2 cache signals should have the shortest path possible. Trace lengths should be equalized. CDATA(0:71) are routed point-to-point: MICTOR SWITCH 07 MICTOR SDRAM SDRAM Avoid routing traces, especially noisy ones, across CPUPLL bus. Keep CKO testpoint on top of board for accessibility. SDRAM 06 SDRAM Use split power plane or very heavy traces for power path: +5V => MOSFET Qx => Inductor Lx => Low-Ohm Res. Rx => VCORE Plane Use split power plane to connect VCORE from power supply to CPU core. Place 820 uF low-ESR capacitors near CPU. Keep trace from 680 uF low-ESR capacitors within 2 cm of high-side MOSFET (Q2). Keep MOSFET gate drive lines < 2 cm. Keep VCCA/VCCP attachment within 2 cm of input filter location. SDRAM 06 i Fansink Power Connector. i VCORE OUTPUT 4 O O O O O O O O O O O O O O O O I I I I I I I I I I I I I I I I VID 3 2 O O O O O O O O O I O I O I O I I O I O I O I O I I I I I I I I O O O O O O O O O I O I O I O I I O I O I O I O I I I I I I I I 1 O O I I O O I I O O I I O O I I O O I I O O I I O O I I O O I I 0 O I O I O I O I O I O I O I O I O I O I O I O I O I O I O I O I VCORE 2.05V 2.00V 1.95V 1.90V 1.85V 1.80V 1.75V 1.70V 1.65V 1.60V 1.55V 1.50V 1.45V 1.40V 1.35V 1.30V 3.5V 3.4V 3.3V 3.2V 3.1V 3.0V 2.9V 2.8V 2.7V 2.6V 2.5V 2.4V 2.3V 2.2V 2.1V 0.00V i KELVIN CONNECTION i MPC107 CORE POWER i VCORE OUTPUT i CACHE POWER i CACHE I/O POWER i OVDD POWER Route IFB and VFB traces paired Low-power regulator supplies +2.5V to the MPC107 core logic, or can connect to OVDD. Add 2-3 cm^2 to the ground plane area on the top of the PCB for additional thermal dissipation. Programmable CPU core voltage; may be programmed from 1.8V to 3.6V. Set to 2.5V (nominal) or 3.3V. MPC755 MPC750R MPC7400 i MPC750A Set to 2.5V (nominal) or 3.3V BULK CAPACITANCE Distribute around the board. Trimmable, nominally 2.5V, or connect to 3.3V power. i OVDD L2OVDD SELECTION BVSEL GND HRESET* OVDD OVDD 1.8V 2.5V 3.3V L2VSEL L2OVDD GND 1.8V HRESET* 2.5V OVDD 3.3V i PLL/L2 DLL Filters Place <1 cm from pin i L2 Clocks 1. Route L2 clocks to equal lengths. 2. Route CLKOUTA/B as a differential pair. i CP0 CP1 CP2 i CPU PLL SETTINGS i MPC107 PLL SETTINGS i BOARD OPTIONS SETTINGS i COP CONNECTOR See Configuration Guide CP3 XP0 XP1 XP2 See Configuration Guide XP3 RL AM PT AG PM See Configuration Guide TS P66 SR Processor debug access port. NOTE: Connector should be routed to look as appears below. CPU Power and Bypass Capacitors Keep near CPU i 69P737 SE3 Install for 69P737 to control SE3 properly. Motorola Confidential Proprietary i CPU Clock Delay 1. Route CPU clocks to equal lengths. 2. ADD same extra trace length as for SDFEED. i Board ID I2C ID=57 i SDRAM CONFIG I2C ID=50 i PCI Clamp Voltage 3.3V or 5V depending upon VIO selection (see page 15). i PLL Filters Use 15 mil traces and keep them short. i PCI Clock Trace Must equal exactly 2.5" from connector pin to MPC8240 pin, per specifications. Route aux-clock to connector pin. i SDRAM CLOCK ROUTING 1. Keep MPC107 STERM trace length < 2cm. 2. Route SDCLK1:4 plus SDFEED to equal lengths. 3. Add 15cm (~1ns) ADDITIONAL delay to SDFEED. i i SECTOR PROTECT/UNPROTECT Apply 12V to activate or override the boot sector protection. Resistor need not be removed. NOTE: The flash is little endian, so the bit numbering is reversed from normal PowerPC standards. i MPC107 Configuration Logic Refer to Book IV, table 144 for details. i V(I/O) SELECTION Select 3.3V or 5V V(I/O) option. ONE ONLY! SP3 TALOS Valis UNITY ALTIM VALIS Valis X1 (MPPMC7450) Configuration Guide BOARD OPTIONS NAME SET n=1 SYSRST e =0 n=1 M66EN e =0 n=1 ROMSEL e =0 n=1 PROGSEL e =0 n=1 AGENT e =0 n=1 PMCTYPE e =0 n=1 MAPSEL e =0 n=1 ROMLOC e =0 PCI COP resets MPPMC only COP resets system 66 MHz PCI allowed 33 MHz PCI only Standard Flash selected Alternate Flash selected Local flash is bootable Local flash is programmable Wait for host Free agent VITA PrPMC (no arbiter) MOT MPPMC (arbiter) Map "B"/ CHRP Map "A"/ PReP RCS0 on local bus RCS0 on PCI 1234567 8 ON 1234567 8 ON 1 2345678 DEFAULT= ON 1234 5678 DEFAULT= Revised: 2001 Feb 08 MPC7450 PLL 1 2 3 4 Mult. 2X e n e e e n n e 2.5X n e e e 3X n n n e 3.5X n e n e 4X e n n n 4.5X n e n n 5X n e e n 5.5X n n e n 6X e n e n 6.5X 7X e e n e e e e n 7.5X n n e e 8X ON MPC107 PLL 0 1 2 3 PCI BUS n n n n 33 33 n n e n 20 40 n e n e 33 66 33 100 e n n n 66 120 e n n e 30 120 e n e n 33 83 e e n n 66 66 e e n e n n e e bypass 66 83 100 200 233 266 300 333 366 400 433 466 500 533 208 250 292 333 375 416 458 500 542 584 625 666 250 300 350 400 450 500 550 600 650 700 750 800 133 266 333 400 466 532 600 666 733 800 866 933 1000 1066 Valis Errata Page 1 /12 Valis MPPMC7450 Board Errata c Board Revision Level X1 Errata Revision Level A Copyright 2000 by Motorola Incorporated. All rights reserved. Motorola Inc. Unrestricted Distribution Permitted 01 Feb 02 Valis Errata Page 2 /12 Revision History Version A Date 2000 Aug 28 2001 Feb 02 Changes Initial errata. Added #25-34. Motorola Inc. Unrestricted Distribution Permitted 01 Feb 02 Valis Errata Page 3 /12 Table 1: Summary of Valis Errata # 1 2 3 4 Type Layout ? Layout Layout Problem Impact Work-Around C9 should attach directly to plane, instead uses a trace. Poor transient response; may increase possibility of failure. None. BA/Package(?) added useless `1'to LED legends. Confusing, hard to read, wastes precious space. None. SW1/SW2 geometry is backwards. Pin 1 should be in the upper left hand corner, same as all ICs. Instead, pin 1 is upper right. Configuration switches work backwards. None. Q3 geometry or silkscreen is backwards. Power supply inoperative. Install Q3 opposite of silkscreen image. Affects Rev X1 X2: Move cap or plane so direct attachment is possible. X1 X2: Either find way to eliminate or go back to using explicit legends. X1 X2: Fix geometry. X1 X2: Fix geometry. 5 Design Power supply not configured for V'ger. V'ger is targeted for 1.8V core. CPU will not run. Code for 1.8V is "00101". Move R45 to R19. Add 0 ohm resistor (or wire) to R20. X1 X2: Update no_stuff options. Add p/s code table to schematics. 6 Design R57 should not be installed. OVDD shorted. Remove R57. X1 X2: Add no_stuff option to R57. 7 8 Design Design BVSEL options incorrect; 2.5V I/O for CPU (OVDD) not selected. L3 will not work. L3VSEL options incorrect; 1.8V I/O for L3 (L3OVDD) not selected. L3 will not work. Install 0-ohm resistor (or wire) at R16. X1 X2: Add 10K pullup to BVSEL. Remove "no_stuff" attribute from R16. Install 0-ohm resistor (or wire) at R17. X1 X2: Add 10K pullup to L3VSEL. Remove "no_stuff" attribute from R17. Motorola Inc. Unrestricted Distribution Permitted 01 Feb 02 Valis Errata Page 4 /12 Table 1: Summary of Valis Errata # 9 Type Design 10 Design Problem Impact L3 IO and core power connections wrong. L3 will not work. Pins 1, 2 & 3 of U16 should be grounded. U16 has the same address as U15, so neither are useable. I2C information cannot be read. Work-Around Rewire as shown on detail page. Affects Rev X1 X2: Swap VCACHE and VCACHEIO connections. 1. Lift U16 pins 1, 2, and 3. X1 2. Connect lifted pins 1, 2, and 3 to U16 pin 4. X2: Ground pins 1, 2, and 3. 11 Layout CKO and CK1 pins not on top of board. Hard to debug. None. X1 X2: Move to top layer. 12 13 14 15 Mech Design Design Design C67 too tall for heatsink. Interferes with mechanical placement. Mill out area on heatsink. Pullups should be added for BVSEL, L2VSEL, since V'ger does not have internal pullups. None, currently only 2.5V I/O supported. None. COP_HRST* is connected directly to CPU, violating I/O levels and eliminating reset path. Can't reset board; I/O damage with COP. Rewire as shown on detail page. Inductor is current limited; power supply cannot start up quickly, or at all. Power supply inoperative. Remove SMD inductor. Attach toroid inductor by bending leads to attach to SMT pads. X1 X2: Move to bottom layer or change component. X1 X2: Add pullups. X1 X2: COP_HRST* goes to LVT16244 for isolation, CPU_HRST* drives CPU HRST*. X1 X2: Use through-hold toroid instead of SMD. Motorola Inc. Unrestricted Distribution Permitted 01 Feb 02 Valis Errata Page 5 /12 Table 1: Summary of Valis Errata # Type 16 Layout Problem MOSFET Q2 ground lead attachment too puny. Impact Power supply problems. Work-Around Affects 1. Refer to Errata #34 which removes C25 X1 Rev 2. Connect minimum 20 gauge insulated wire from C25 ground hole (round pad) to Q2 pin S (nearest pin). X2: More vias! More vias! 17 Design No pullup on CHKSTP_IN. Processor immediately checkstops. CPU halts. Add pullup between COP header J7 pin 8 and R79 pin 1 (side not connected to J7). X1 X2: Add 10K pullup to COP CHKSTP_IN* port. 18 19 Debug Design/ Package No pullups on some signals such as TBST* annoys some logic analyzer disassemblers. Debugging somewhat confusing. Sense resistor should be 0.0028, not 0.028 CPU core voltage wrong. None. X1 X2: Add 10K pullups to GBL*, CI*, WT*, TS*, TBST*, TSIZ. Change R55 to correct component or use 3 inches of 20 gauge solid wire. X1 X2: Change component value. 20 21 Improve Improve Add bypass caps to V'ger routing channels. None. Add fan sink header. None None. X1 X2: Add or relocate bypass caps to directly under V'ger. None. X1 X2: Add fan sink power connector (3pin Berg). 22 Improve PLL_TEST is actually a PLL configuration bit. Hard to configure for higher (>=9X) PLL multipliers. None. X1 X2: Change M66EN to non-pop resistor and use for PLL_CFG(4) (aka PLL_TEST). Motorola Inc. Unrestricted Distribution Permitted 01 Feb 02 Valis Errata Page 6 /12 Table 1: Summary of Valis Errata # Type 23 Design Problem The DQM bits are scrambled; memory cannot work in byte-writable mode. Impact Cannot use memory. Work-Around Affects Either: A. Configure memory to operate in read -modify-write (RMW) mode, so that all DQM signals are always used; X1 Rev or: B. Rewire the DQM signals as shown on the detail page. X2: Correct order of DQM signals. 24 25 Improve Design Add option to select BIST using CHKS*. None. None. No pullup on AP[0]. Address parity may not work. X1 X2: Reallocate switch to BIST or use resistor. None. X1 X2: Pullup AP[0]. 26 Design No pullup on CHKS*. Might enter checker mode and fail to run. 1. Connect 4.7K resistor to CHK1 pad. X1 2. Connect wire from resistor to RN3/RN4 center pins. X2: Provide ability to pullup CHKS*, assert with HRESET*, or pulldown. 27 Design No pullups on SHD0/SHD1 pins. Might cause snoop failures. 1. Connect two 4.7K resistors to SH1 and SH2 pads. X1 2. Connect wires from resistor to RN3/ RN4 center pins. X2: Provide pullups on SHD0* and SHD1*. 28 Design GBL* requires strong pullup. Unknown, but strongly recommended. 1. TBD X1 X2: Provide 1K discrete pullup on GBL*. Motorola Inc. Unrestricted Distribution Permitted 01 Feb 02 Valis Errata Page 7 /12 Table 1: Summary of Valis Errata # Type 29 Layout Problem Q4 trace needs to be thicker. Impact Unknown. Work-Around 1. None. Affects Rev X1 X2: Enhance trace thickness on gate (G), use multiple power vias (minimum 3 to 5) on drain (D) and source (S). 30 Layout Gate drive for Q2 needs to be shorter. Slower, less performance/heat. 1. None. X1 X2: Route gate drive to left through pins instead of to right. 31 32 Design Design Default drive strength for MPC107 incorrect. May fail? A[0:3] should be pulled down. Unknown. 1. Populate R4 and R6 (470 ohm). X1 X2: Remove "No_Stuff" on R4 and R6. 1. None X1 X2: Add pulldown to A[0:3]. 33 Design PMON_IN should be pulled down. Performance monitor cannot run. 1. None X1 X2: Add pulldown to A[0:3]. 34 Layout C21/C25/C29 placement. C25 interferes with heatsink attachment. Cannot/hard to install heatsink. Capacitors less effective for noise filtering. 1. Remove C25. Change BOM to `nostuff'. X1 X2: Relocate. Revisit capacitor placement to put C21, C29, C25 near CPU+SRAM. Motorola Inc. Unrestricted Distribution Permitted 01 Feb 02 Valis Errata Page 8 /12 Errata 9: L3 Cache Power Connections OVERVIEW The L3Cache power and IO powers are swapped. WORKAROUND The work-around is to rewire the power using heavy (22 ga.) wire. 1. Connect a wire to the top of R59 (between the caps on the bottom of the board) to Q4 pin 3 (left gull-wing pin). This connects VCACHEIO to VCC_1.8. 2. Connect a wire to the left of R56 (above the CPU) to R59 pin 2. This connects VCACHE to VCC_2.5. Avoid running wire over the CPU -- there will be a heatsink there.. R59 Q4 R56 Motorola Inc. Unrestricted Distribution Permitted 01 Feb 02 Valis Errata Page 9 /12 Errata 14: Reset Connections OVERVIEW The system reset connections are miswired. WORKAROUND 1. On the front of the board, cut the indicated trace RN18 U10 U13 U17 R26 R25 2. On the back of the board, connect a trace between U17 pin 20 and the indicated via. 20 C50 DQM1 DQM0 DQM6 DQM1 DQM0 RN7 DQM7 Motorola Inc. Unrestricted Distribution Permitted 01 Feb 02 Valis Errata Page 10 /12 Errata 23: SDRAM DQM Connections OVERVIEW The SDRAM DQM connections are scrambled. WORKAROUND A. Use RMW mode, in which case DQM ordering is irrelevant. B. Rewire the DQM signals, as follows: 1. Cut traces DQM(1:0) exiting RN13 pins 1 and 2 on the top of the PCB. 2. Connect RN13 pin 2 to U12 pin 15. 3. Connect RN13 pin 1 to via between traces connected to RN11 pins 5 and 6. . U11 U9 U12 15 15 DQM7 DQM1 DQM1 DQM7 DQM6 RN15 RN11 RN13 DQM6 DQM6 UTDQM6 UTDQM7 UTDQM2 UTDQM3 4. Cut traces DQM(7:6) exiting RN12 pins 3 and 4 on the bottom of the PCB. 5. Connect RN12 pin 3 to via under end of old DQM7 trace. 6. Connect RN12 pin 2 to via at bottom end of U10 as shown. Motorola Inc. Unrestricted Distribution Permitted 01 Feb 02 Page 11 /12 U10 R26 R25 Valis Errata U13 1 R23 R24 U3 C50 1 DQM1 DQM0 DQM0 DQM6 DQM7 UTDQM5 UTDQM0 UTDQM4 UTDQM1 RN12 Motorola Inc. Unrestricted Distribution Permitted 01 Feb 02 Valis Errata Page 12 /12 Errata 28: GBL* Pullup OVERVIEW The GBL* signal requires a strong pullup. WORKAROUND 1. Connect 470 ohm resistor to RN3 pin 10 on bottom of board beneath MPC107 (U14). 2. Connect wire from resistor to via shown . C83 CK1 . TO1 RN3 Motorola Inc. Unrestricted Distribution Permitted 01 Feb 02 V a l i s* MPC7450 (V'ger) This schematic is provided for reference purposes only. All information is subject to change without notice. No warranty, expressed or applied, is made as to the accuracy of the information contained herein. Contact Motorola Sale/FAEs to obtain the latest information on this product. *Digital DNA from Motorola Schematic Notes Page Contents Unless otherwise specified: All resistors are SMD0603, in ohms, 0.08W, +/-5% All capacitors are SMD0603, in microfarads (uF), +/-20%. All inductances are in microhenries (uH). All ferrites are Z=50 ohms at 100 MHz. All fuses are self-resetting polyswitch (PTC) devices. Board impedance is 55 +/- 5 ohms. 01 Cover Page 02 03 General Information Block Diagram 2. Integrated circuits have default connections to power and ground unless explicitly shown otherwise. Global power connections are: VCACHE VCACHE_IO GND VCC_3.3 VCC_2.5 OVDD VCC_5 VCORE VCC_12 04 05 Routing and Layout Information Power Supply 3. Part numbers used are for reference only; compatible parts may be used; refer to the bill of materials. 4. Motorola and the Motorola logo are registered trademarks of Motorola. PowerPC is a trademark of IBM. Other trademarks are the respective property of their respective copyright holders. There is no spoon. All rights reserved. No warranty is made, express or implied. 06 07 MPC7450 System Logic MPC7450 Cache Interface 5. The sheet-to-sheet cross reference format is: Sheet "-" VertZoneLetter HorizZoneNumber Components with the visible property "NO STUFF" are not to be installed by default; they are for test or manufacturing purposes only. 08 09 10 11 MPC7450 Power/Options L2 Cache SRAM Reserved MPC107: System Logic 12 13 MPC107: Processor Interface MPC107: PCI Interface 14 15 MPC107: Memory Interface SDRAM SODIMM Socket 16 17 Local Boot ROM Configuration Logic / LEDs 18 19 PMC Connectors. PMC Connector 20 Analyzer Headers 1. 6. 7. All buses follow big-endian bit numbering order (bit 0 is the most-significant bit), except where industry standards apply (i.e. PCI). Little-endian numbering is noted at the source component. Team Altimus Vali s* Layout Cindy Black Ivan Erickson Program Mgr. Designer Gary Milliorn Tony Saucedo Components Joey Tsai Documentation Margarito TrevinoTechnician Gary Wojcik Ref. Plat. Mgr REV DATE CHANGES X1 00MAY01 Initial version Power Supplies Backside L2 Cache Processor Motorola MPC7450 500-800 MHz Motorola MCM64E836 1M 100-300 MHz Programmable VDD Multiple outputs <09> <05> <06-08> 64/72-bit 133 MHz Local Bus Boot ROM Northbridge (2) 1MByte Flash Motorola MPC107 <16> Memory SDRAM Components ECC/Parity <11-14> 32-bit 33/66 MHz PCI Bus Logic Analyzer PMC Connector 32 bit PPMC Extensions Mictor Headers <20> <18-19> <15> Layout/Routing Instructions 05 06 Place components approximately as shown on this page. Keep relative distances short and use heavy traces for everything. All power connections are to be made to a plane. Avoid routing traces, especially noisy ones, across CPUPLL bus. 07 Keep AVDD filter near CPU. Route all groups to equal lengths. L3RU L3RL L3X 08 Avoid routing traces, especially noisy ones, across CPUPLL bus. Do not swap order of PLL switch connections. Surround MPC7450 with bypass caps to provide additional ground-return paths. Use two ground-attach vias. Place bulk capacitance near BGA IVDD and +3.3V ground planes. Place COP connector in I/O area. Proximity to CPU is not a high priority. Insure that COP pin numbering matches view as shown on schematic (i.e. pin 1 and pin 16 are on opposite corners). 09 Place cache SRAMs within 3.5cm of MPC750 (center-to-center). Route all control, address and data traces to equal lengths. Surround each component with bypass capacitors. Use thick trace (>=12mil) for VREF, 24mil for VCACHE. 11 Avoid routing traces, especially noisy ones, across MPC107 PLL bus. Do not swap order of MPC107 PLL switch connections. PCI clock input must be 2.5" (per specification). MICTOR MICTOR MICTOR MICTOR MICTOR LEDs AUX POWER 10 I2C SWITCH Keep data bus length for ROM short. LVT 16 SWITCH SDRAM (5x) 17 18 Maximum trace length for PCI signals to MPC107 is 1.5" per the PCI specification. PNP FET 19 MCM64E836 SRAM MPC7450 V'ger MCM64E836 SRAM MPC107 FET LT1118 FET P3 CS51313 358 20 P2 15 I2C P1 Place series termination resistors very near source (MPC107), < 2cm. Route SDRAM clocks to equal lengths, including SDRAM_SYNCOUT to SDRAM_SYNCIN path. PAL QS3384 14 FLASH (2x) Am29LV800 Keep AVDD/LAVDD filters near MPC107. Use heavy, short traces from filter to pins. Surround MPC107 with bypass caps to provide additional ground-return paths. Use two ground-attach vias. Connect VCC_PCI_C (PCI Clamp) using heavy trace. COP 13 ISP 12 i VCORE OUTPUT 18A MAX i 3A MAX i 1A MAX V'ger i CPU PLL Filters Place <1 cm from pin i CP0 CP1 CP2 CP3 XP0 i MPC7450/MPC107 PLL SETTINGS See Configuration Guide XP1 XP2 XP3 RL AM PT AG PM TS P66 SR i ROM LOCATION BOARD OPTIONS CPU Power and Bypass Capacitors Keep near CPU i CPU Clock Delay 1. Route CPU clocks to equal lengths. 2. ADD same extra trace length as for SDFEED. i Board ID I2C ID=57 i SDRAM Configuration ID I2C ID=50 i PCI Clamp Voltage 3.3V or 5V depending upon VIO selection (see page 15). i PLL Filters Use 15 mil traces and keep them short. i PCI Clock Trace Must equal exactly 2.5" from connector pin to MPC8240 pin, per specifications. Route aux-clock to connector pin. i SDRAM CLOCK ROUTING 1. Keep MPC107 STERM trace length < 2cm. 2. Route SDCLK1:4 plus SDFEED to equal lengths. 3. Add 15cm (~1ns) ADDITIONAL delay to SDFEED. i SECTOR PROTECT/UNPROTECT Apply 12V to activate or override the boot sector protection. i MPC107 Configuration Logic Refer to Book IV, table 144 for details. i V(I/O) SELECTION Select 3.3V or 5V V(I/O) option. ONE ONLY! i 64-bit PMC Header Used for additional power and ground only.