Sandpoint III
Sandpoint
System
Documentation
Covering Sandpoint and Associated
MPPMC Processor Mezzanine Cards
Rev 1
2001 Feb 16
Contents
Sandpoint III User’s Manual
Schematics
Errata List
Talos (603/740/745) Configuration Guide
Schematics
Errata List
Unity (8240/8245) Configuration Guide
Schematics
Errata List
Altimus (75x/7400/7410) Configuration Guide
Schematics
Errata List
Valis (7450) Configuration Guide
Schematics
Errata List
TALOS UNITY ALTIM VALIS
SP3
Sandpoint
III
TALOS UNITY ALTIM VALIS
SP3
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Order Number: SP3UM/A
Rev. 0.2, 2/2001
Semiconductor Products Sector
This document contains information on a new product under development by Motorola. Motorola
reserves the right to change or discontinue this product without notice.
© Motorola, Inc., 2001. All rights reserved.
Sandpoint III
User’s Manual
Welcome to Sandpoint, Motorola’s PowerPC development platform. Using Sandpoint you can evaluate
current and future PowerPC devices using MPPMC (Motorola Processor PCI Mezzanine Cards). These
cards are interchangable and one Sandpoint platform can support numerous processor-specific PPMC cards
(but just one at a time).
This User’s Manual covers the following issues:
Topic Page
Section1, “Introduction”page2
Section2, “Setup”page4
Section3, “Configuration”page6
Section4, “Programmers Model”page15
Section5, “Development Issues”page21
Section6, “Troubleshooting”page24
Section7, “FAQ”page27
To locate any published errata or updates for this document, refer to the website at http://www.mot.com/
SPS/PowerPC/.
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1 Introduction
The Sandpoint III motherboard, or “SP3” for short, is an evaluation baseboard which accepts one Motorola
Processor PMC ( MPPMC) or PrPMC card, as well as up to four PCI cards, and supplies typical PC-I/O
peripherals. Sandpoint provides a flexible base for the evaluation of new PowerPC devices, and for early
software design for customer project using P owerPC processors. Figure1-1 shows a block diagram of the
Sandpoint III system.
Figure1-1. Sandpoint III Block Diagram
1.1 Features
SP3 has the following features:
•One MPPMC slot for a processor board (PrPMC compatible with PCI arbitration extensions).
Motorola
MPPMC
Board
PCI Slots
Winbond
IDE
IDE
SuperIO
KBD
MSE
SPF100
COM1
COM2
PAR
FLP
ROM1
ROM2
NVRM
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•Two 32-bit PCI slots (5V)
•Two 32/64-bit PCI slots (5V)
•PMC and PCI slots auto-sense/auto-select 33 or 66 MHz operation.
•Two standard 16650-compatible ESD-protected serial ports.
•IEEE 1284 parallel port.
•Floppy disk port.
•Two ATA33 bus-master IDE ports.
•PS/2 mouse and keyboard connectors.
•BBVRAM; 1K bytes
•Real-Time Clock.
•Switch-selectable operating modes.
•Advanced Power Controller (“soft on/off”).
•LED monitors for critical functions.
The I/O subsystem is identical to that of the Sandpoint 2 and the “EC” version of the older Yellowknife
development platform. When properly configured, software written for these platforms should operate
identically when executed on a Sandpoint 3.
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2 Setup
Sandpoint 3 is shipped ready to run the DINK debugger software. If you will be running other operating
systems, refer to the respective installation and setup instructions. Many OSes will communicate using the
same serial port DINK does, so the following setup may apply as well.
To setup your system, you will need the following material:
•Sandpoint 3 system
•Mac, PC or workstation running a terminal program.
•Null-modem cable.
Figure2-1. Sandpoint III Setup Diagram
STEP 1
Connect the Sandpoint to a 120 VAC source using the supplied AC power code. For international operation
at 240 VAC, replace the connector with an appropriately-keyed power cable.
STEP 2
Turn the power supply on using the switch at the back of the Sandpoint chassis near the power cord. The
system will not turn on at this time.
STEP 3
Attach a null-modem cable between the Sandpoint COM1 port (top-most as shown in Figure2-1) to the PC
(or workstation) serial port (usually COM1).
STEP 4
Startup a terminal emulator program. Common terminal emulators include “Hyperterminal”, available for
free with most Windows PCs, and many commercial programs such as Hayes “SmartComm”. Setup the PCs
terminal program to use the following settings:
•9600 Baud
•8 Bits
•No Parity
1
COM1 COM2
1
COM1 COM2
DINK32>> go 900
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•1 Stop Bit
•No Handshaking
•Terminal Emulation: any
STEP 5
Turn on the Sandpoint by pushing the power switch on the front of the chassis. DINK will start and print a
banner:
###### ### # # # # ##### #####
# # # ## # # # # # # #
# # # # # # # # # #
# # # # # # ## ##### #####
# # # # # # # # # #
# # # # ## # # # # #
###### ### # # # # ##### #######
( ( ( ( (AltiVec) ) ) ) )
Version : 12.2, Metaware Build
Released : Jan 31, 2001
Written by : Motorola's RISC Applications Group, Austin, TX
System : Sandpoint with Altimus/Talos (MPPMC60x/7xx/74xx)
Processor : MPC7400 V2.8 @ 500 MHz, Memory @ 100 MHz
Memory : Map B (CHRP), 00000000...03FFFFFF
Copyright Motorola Inc. 1993-2001
Refer to `history.c' for release info, changes, errata and fixes.
DINK32_MAX >>
At this point, DINK is ready to accept user commands such as downloading and starting code or assembling
user programs. Refer to the DINK User’s Manual for more details on using DINK. If you are using another
ROM, such as for an OS, follow the instructions for the ROM.
2.1 Null Modem Cable
Since both Sandpoint 3 and the PC or workstation it communicates with are computers and therefore are
DTEs (Data Terminal Equipments), a special serial cable known as a null-modem cable is required. These
cables are readily available from computer supply stores. In addition, it is simple to make, as shown in
Figure2-2.
Figure2-2. Null Modem Diagram
Once the cable is available or constructed, attach one end to the Sandpoint COM1 port and the other to the
PC/Workstation. Either end will work with either computer.
DB9 Female
Back View
1
59
6
2
3
48
7
DB9 Female
Back View
1
59
6
2
3
48
7
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3 Configuration
Sandpoint 3 is shipped ready to run the DINK firmware b y default. The following configuration options are
preset:
•MPPMC is the PCI arbiter.
•MPPMC is the interrupt controller using Serial-EPIC.
Occasionally, however, software will require other configurations, which Sandpoint supports to a limited
extent. This is often done to make a Sandpoint more closely resemble the target development platform.
Configurable features include:
•Using an external PCI arbiter instead of the PMC-resident arbiter.
•Using the 8259 PIC in the Winbond instead of the PMC interrupt controller.
•PnP (Plug-and-Play) PC I/O devices can remain uninitialized and ‘virtually’ disappear.
Another reason to change the configuration is to use the legacy modes for Sandpoint 2 compatibility. Refer
to AppendixA for details on legacy configurations. All options on Sandpoint 3 are set via two ‘DIP’
switches, as shown in Figure3-1.
Figure3-1: Sandpoint 3 in an ATX Chassis
The switches have the same orientation; with the system standing vertically, the switches operate as shown
POWER
SUPPLY
WINBOND
WINBOND SW2
SW1
POWER
SWITCH
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in Figure3-2
Figure3-2: Sandpoint 3 SW1/SW2 Configuration Switches
All configuration switches should be changed with the power off; changes only take effect on a system
power-on reset. The system pushbutton reset is not necessarily sufficient.
3.1 SW1 Options
SW1 is located near the bottom of the Sandpoint 3 board, near the end of the fourth PCI slot. It controls the
features shown in Table3-1:
Table3-1. Sandpoint 3 SW1 Options
Switch Name Definition Default
1ROMSEL ROM Selection
2ROM1WP ROM1 Write Protect
3reserved reserved
4FRCPCI33 Force PCI to 33MHz
5EXTCLK Use external clock
6SSCLK Spread-Spectrum Clock
12345678
ON
RIGHT = ON
LEFT = OFF
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3.1.1 ROMSEL
The “ROMSEL” switch may be used to select between the primary and secondary flash device (if any) on
the Sandpoint 3.
NOTE: Not all Sandpoint 3’s have a secondary flash.
NOTE: The RMODE switch (see Section3.2.4) overrides this switch.
3.1.2 ROM1WP
The “ROM1WP” switch may be used to write-protect the secondary (backup) PCI-hosted boot ROM, if any.
This primary ROM normally contains the DINK debugger, but with the backup ROM protected, users may
overwrite the boot ROMs with development code and still return to DINK as a backup measure.
NOTE: Not all Sandpoint 3’s have a secondary flash.
3.1.3 Reserved
Switch SW2-3 is reserved and has no function.
3.1.4 FRCPCI33
The “FRCPCI33” switch may be used to cause the PCI bus to operate at 33 MHz regardless of the status of
the M66EN signal, which normally allows the PCI bus to automatically select 66 MHz PCI. This switch is
normally enabled, forcing only 33 MHz operation since the Winbond component does not support 66 MHz
7SSRNG Spread-Spectrum Range
8PSON Force Power Supply ON
Table3-2. Sandpoint 3 ROMSEL Option
ROMSEL Definition Notes
SW1-1
On (right) Primary ROM (29F040) is used for PCI boot option. Normal mode.
Off (left) Secondary ROM (28F800) is used for PCI boot
option.
Table3-3. Sandpoint 3 ROM1WP Switch
ROM1WPDefinition Notes
SW1-2
On (right) ROM1 may be read to or written from. Use to store OS code.
Off (left) ROM1 is write-protected.
Table3-1. Sandpoint 3 SW1 Options
Switch Name Definition Default
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operation.
It may be possible to operate the PCI bus at 66 MHz if software does not use the Winbond or the ISA bus.
3.1.5 EXTCLK
The “EXTCLK” switch allows the user to switch from the standard, on-board 33/66 MHz PCI bus clock
generator, from which all other clocks are derived, to an externally-supplied clock signal. This allows
testing the system at different frequencies other than the standard 33 MHz or 66 MHz frequencies supported.
The clock source must be attached to the coaxial SMA connector on the board, and the clock signal supplied
must meet the requirements listed in Table3-6.
NOTE: Care must be used that the devices receiving the clock are capable of and are configured to operate
at the new clock speed. In particular, PowerPC devices have internal PLLs which require a minimum clock
input to operate properly.
NOTE: The external clock source must be on before power is applied to the Sandpoint.
3.1.6 SSCLK
The spread-spectrum enable (“SSCLK”) switch allows the user to enable and evaluate the spread-spectrum
clock generator (SSCG) option. If enabled, the SSCG modulates the PCI base clock frequency by a
selectable amount (see Section3.1.7).
NOTE: The Sandpoint system is not guaranteed to operate if the SSCLK switch is set; this is for testing
purposes only.
Table3-4. Sandpoint 3 FRCPCI33 Switch
Force PCI33 Definition Notes
SW1-4
On (right) Force 33 MHz PCI only. Normal mode.
Off (left) Allow automatic 33/66 MHz PCI. Experimental purposes only.
Table3-5. Sandpoint 3 EXTCLK Switch
EXTCLK Definition Notes
SW1-5
On (right) Normal clock mode Normal mode.
Off (left) Accept clock from SMA connector. Use for testing.
Table3-6. Sandpoint 3 External Clock Requirements
Parameter Value
ZIN 50 Ω
VIN 3V
Table3-7. Sandpoint 3 SSCLK Switch
SSCLK Definition Notes
SW1-6
On (right) PCI clocks are modulated by -1.25% or -3.75%. Use for testing.
Off (left) Normal PCI clocks. Normal mode.
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3.1.7 SSRNG
The spread-spectrum range (“SSRNG”) switch allows the user to change the amount of modulation applied
to the PCI clock signals if the SSCG is enabled (see Section3.1.6).
3.1.8 PSON
The “PSON” switch allows the user to force the system to power up whenever AC power is applied to the
system power supply. Normally, the system power is controlled with the APC in the SuperIO chip, and
power is controlled through the chassis switch, motherboard pushbutton, or APC under software control. If
PSON is selected, the system remains on until external power is removed.
3.2 SW2 Options
SW2 is located near the top of the Sandpoint 3 board, near the socketed flash ROM socket, between the
PMC and the floppy connector. This switch controls the features shown in Table3-10:
Table3-8. Sandpoint 3 SSRNG Switch
SSRNG Definition Notes
SW1-7
On (right) -3.75% modulation:
66 MHz PCI: 63.5 ... 66.0 MHz
33 MHz PCI: 31.8 ... 33.0 MHz
Normal mode.
Off (left) -1.25% modulation:
66 MHz PCI: 65.2 ... 66.0 MHz
33 MHz PCI: 32.6 ... 33.0 MHz
Table3-9. Sandpoint 3 PSON Switch
PSON Definition Notes
SW1-8
On (right) Force power on always. Normal mode.
Off (left) Normal power control mode
Table3-10. Sandpoint 3 SW2 Options
Switch Name Definition Default
1 & 2 AMODE PCI Arbiter Architecture
3ILEGACY Interrupt Legacy Modes
4 & 5 IMODE Interrupt Architecture
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3.2.1 AMODE
The AMODE switches are used to configure the PCI arbitration connections.
3.2.1.1 AMODE FULL
When AMODE is set such that the FULL option is selected, the MPPMC and the SPF100 work in tandem
to provide arbitration handling for all possible PCI devices. Requests are assigned as follows:
PMC_REQ(0) = WB_REQ(0) or SLOT_REQ(1)
PMC_REQ(1) = WB_REQ(1)
PMC_REQ(2) = SLOT_REQ(2) or SLOT_REQ(3)
PMC_REQ(3) = SLOT_REQ(4)
And grants are handled correspondingly.
3.2.1.2 AMODE PARTIAL
When AMODE is set such that the PARTIAL option is selected, the MPPMC provides arbitration handling
for four PCI devices (the maximum permitted by the MPPMC/PrPMC spec). Requests are assigned as
follows:
PMC_REQ(0) = WB_REQ(0)
PMC_REQ(1) = WB_REQ(1)
PMC_REQ(2) = SLOT_REQ(3)
PMC_REQ(3) = SLOT_REQ(4)
And grants are handled correspondingly.
3.2.1.3 AMODE WINBOND
When AMODE is set such that the Winbond is selected as the system arbiter, the arbiter on the MPPMC is
disabled and the Winbond is enabled. Thereafter, requests are assigned as follows:
WB_REQ(0) = PMC_REQ(0)
WB_REQ(1) = SLOT_REQ(1)
6RMODE ROM Mode
7&8 USER User Options
Table3-11. Sandpoint 3 AMode Switches
AMODE[0:1] Definition Notes
SW2-1SW2-2
On (right) On (right) Full Default PCI arbitration mode.
On (right) Off (left) Partial
Off (left) On (right) Winbond
Off (left) Off (left) reserved
Table3-10. Sandpoint 3 SW2 Options
Switch Name Definition Default
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WB_REQ(2) = SLOT_REQ(2)
WB_REQ(3) = SLOT_REQ(3)
WB_REQ(4) = SLOT_REQ(4)
And grants are handled correspondingly.
3.2.2 ILEGACY
The ILEGACY switch is used to select between standard SP3 interrupt connections and support for legacy
interrupt connections.
3.2.3 IMODE
The IMODE switches are connected to the SPF FPGA to configure the PCI interrupt connections.
3.2.3.1 IMODE Serial
When AMODE is set such that Serial is selected, the SPF100 enables an internal serial multiplexer that
works with the serial demultiplexer in the EPIC portion of the MPC107 or MPC824X on MPPMC cards.
This allows many interrupts to be conveyed to the MPPMC than would normally be possible with the four
allocated pins. shows the serial ‘slot’ corresponding to each external interrupt
Table3-12. Sandpoint 3 ILEGACY Switches
ILEGACY Definition Notes
SW2-3
On (right) Standard SP3 Interrupt Modes Default
Off (left) Legacy Sandpoint 1/2 Interrupt Modes See AppendixB
Table3-13. Sandpoint 3 IMode Switches
IMODE[0:1] Definition Notes
SW2-4 SW2-5
On (right) On (right) Serial Default.
On (right) Off (left) Wire-OR
Off (left) On (right) reserved
Off (left) Off (left) reserved
Table3-14. Sandpoint 3 Serial Interrupt Slot Assignment
Slot Interrupt Source Note
0SIOINT Inverted, so active low
1SLOT #1 See technical summary for details on
PCI cards with multiple interrupt
outputs.
2SLOT #2
3SLOT #3
4SLOT #4
5WinBond INTA#
6WinBond INTB#
7WinBond INTC# IDE Interrupt
8WinBond INTD# IDE Interrupt
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3.2.3.2 IMODE WireOR
When IMODE is set such that the WireOR option is selected, the MPPMC will merge all interrupt inputs
into one, and the SPF100 work in tandem to provide arbitration handling for all possible PCI devices.
Requests are assigned as follows:
PMC_INT(0) = SLOT_INT(1) OR
SLOT_INT(2) OR
SLOT_INT(3) OR
SLOT_INT(4) OR
SIOINT (inverted).
The other MPPMC interrupt pins (1 to 3) are not asserted. Software must generally poll known devices to
clear the interrupt status, so Wire-OR is a very weak architecture but it is effective in checking that interrupt
signalling is setup properly, and suitable for embedded systems with minimal interrupt requirements.
3.2.4 RMODE
The RMODE switch is used to select an alternate method of addressing the dual flash devices.
NOTE: This switch overrides the ROMSEL switch (see Section3.1.1).
NOTE: Not all Sandpoint 3’s have a secondary flash.
3.2.5 USER
The USER switches are connected to the SuperIO GPIO port #1, bits 2 and 3, respectively. Sandpoint 3
9
reserved
10
11
12
13
14
15
Table3-15. Sandpoint 3 RMode Switches
RMODE Definition Notes
SW2-6
On (right) ROMSEL governs ROM/Flash access Default
Off (left) Primary ROM: 0xFFF0_0000 ... 0xFFFF_FFFF
Secondary ROM: 0xFF80_0000 ... 0xFFFF_FFFF
Table3-14. Sandpoint 3 Serial Interrupt Slot Assignment
Slot Interrupt Source Note
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makes no use of these switch settings, they are provided for user-defined functions.
See Section4 for details on reading the GPIO port.
Table3-16. Sandpoint 3 USER Switches
USER[0:1] Definition Notes
SW2-7SW2-8
On (right) On (right) GPIO1 = ”XXXX00XX”Default
On (right) Off (left) GPIO1 = ”XXXX01XX”
Off (left) On (right) GPIO1 = ”XXXX10XX”
Off (left) Off (left) GPIO1 = ”XXXX11XX”
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4 Programmers Model
This section describes support information which may be useful to hardware or software designers who are
using Sandpoint 3.
4.1 Address Map
Table4-1shows the general address map of the Sandpoint 3, and Table4-2 shows the specific location of
ISA/PCI I/O addresses. Both tables assume Map “B” (CHRP), which is the default and officially
encouraged standard.
NOTES:
1. Requires memory control registers to be properly programmed (MCCR[1:4], MS[E]AR[1:2], ME[E]AR[1:2], MBEN).
2. MPC107 or MPC8245 only.
3. Only software-enabled PCI devices appear in this space.
4. Only software-enabled PCI/ISA I/O devices appear in this space.
The detailed address map in Table4-2 assumes that the PnP devices have not been changed from the default
locations.
Table4-1. Global Address Map
START END Definition Notes
0000_0000 3FFF_FFFF SDRAM 1
4000_0000 77FF_FFFF reserved
7800_0000 7BFF_FFFF RCS3 ROM space 2
7C00_0000 7FFF_FFFF RCS2 ROM space 2
8000_0000 FCFF_FFFF PCI memory 3
FD00_0000 FDFF_FFFF PCI/ISA memory
FE00_0000 FEBF_FFFF PCI/ISA I/O space 4
FEC0_0000 FEDF_FFFF PCI configuration address
register
FEE0_0000 FEEF_FFFF PCI configuration data
register
FEF0_0000 FEFF_FFFF Interrupt Acknowledge
FF00_0000 FF7F_FFFF RCS1 ROM space
FF80_0000 FFFF_FFFF RCS0 ROM space (Boot
ROM)
Table4-2: Detailed ISA I/O Address Map
Start End Mode Device Register Notes
FE00_0000 --- R/W WB DMA Channel 0 Base/Current Address
FE00_0001 --- R/W WB DMA Channel 0 Base/Current Word
FE00_0002 --- R/W WB DMA Channel 1 Base/Current Address
FE00_0003 --- R/W WB DMA Channel 1 Base/Current Word
FE00_0004 --- R/W WB DMA Channel 2 Base/Current Address
FE00_0005 --- R/W WB DMA Channel 2 Base/Current Word
FE00_0006 --- R/W WB DMA Channel 3 Base/Current Address
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FE00_0007 --- R/W WB DMA Channel 3 Base/Current Word
FE00_0008 --- RWB DMA Controller 1 Status
WDMA Controller 1 Command
FE00_0009 --- WWB DMA Controller 1 Request
FE00_000A --- WWB DMA Controller 1 Mask
FE00_000B --- WWB DMA Controller 1 Mode
FE00_000C --- WWB DMA Controller 1 Clear Byte Pointer
FE00_000D --- WWB DMA Controller 1 Master Clear
FE00_000E --- WWB DMA Controller 1 Clear Mask
FE00_000F --- WWB DMA Controller 1 Write All Mask
FE00_0010 FE00_001F unassigned
FE00_0020 --- R/W WB PIC 1 Command
FE00_0021 --- R/W WB PIC 1 Command
FE00_0022 FE00_003F unassigned
FE00_0040 --- R/W WB Counter 0
FE00_0041 --- R/W WB Counter 1
FE00_0042 --- R/W WB Counter 2
FE00_0043 --- WWB Timer/Counter Control
FE00_0044 FE00_005F unassigned
FE00_0060 --- R/W SIO Keyboard Controller Data 1
FE00_0061 --- R/W WB NMI Status/Control
FE00_0062 FE00_0063 unassigned
FE00_0064 --- R/W SIO Keyboard Controller Command 1
FE00_0065 FE00_006F unassigned
FE00_0070 --- R/W SIO RTC/APC Index 1
"--- WWB RTC Index (shadow)
FE00_0071 FE00_0077 unassigned
FE00_0078 FF80_0079 R/W WB BIOS Timer
FE00_007A FF80_007B R/W WB BIOS Timer Reserved
FE00_007C FE00_007F unassigned
FE00_0080 --- -WB DMA Reserved Page
FE00_0081 --- R/W WB DMA Memory Page 2
FE00_0082 --- R/W WB DMA Memory Page 3
FE00_0083 --- R/W WB DMA Memory Page 1
FE00_0084 FF80_0086 -WB DMA Reserved Page
FE00_0087 --- R/W WB DMA Memory Page 0
FE00_0088 --- -WB DMA Reserved Page
FE00_0089 --- R/W WB DMA Memory Page 6
FE00_008A --- R/W WB DMA Memory Page 7
FE00_008B --- R/W WB DMA Memory Page 5
FE00_008C FF80_008E -WB DMA Reserved Page
Table4-2: Detailed ISA I/O Address Map
Start End Mode Device Register Notes
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FE00_008F FE00_0091 unassigned
FE00_0092 --- R/W WB Port 92: System Reset
FE00_0093 FE00_009F unassigned
FE00_00A0 --- R/W WB PIC 2 Command
FE00_00A1 --- R/W WB PIC 2 Command
FE00_00A2 FE00_00BF unassigned
FE00_00C0 --- R/W WB DMA Channel 4 Base/Current Address
FE00_00C1 --- R/W WB DMA Channel 4 Base/Current Word
FE00_00C2 FE00_00C3 unassigned
FE00_00C4 --- R/W WB DMA Channel 5 Base/Current Address
FE00_00C5 unassigned
FE00_00C6 --- R/W WB DMA Channel 5 Base/Current Word
FE00_00C7 unassigned
FE00_00C8 --- R/W WB DMA Channel 6 Base/Current Address
FE00_00C9 unassigned
FE00_00CA --- R/W WB DMA Channel 6 Base/Current Word
FE00_00CB unassigned
FE00_00CC --- R/W WB DMA Channel 7 Base/Current Address
FE00_00CD unassigned
FE00_00CE --- R/W WB DMA Channel 7 Base/Current Word
FE00_00CF unassigned
FE00_00D0 RWB DMA Controller 2 Status
"W WB DMA Controller 2 Command
FE00_00D3 unassigned
FE00_00D2 --- WWB DMA Controller 2 Request
FE00_00D3 unassigned
FE00_00D4 --- WWB DMA Controller 2 Mask
FE00_00D5 unassigned
FE00_00D6 --- WWB DMA Controller 2 Mode W
FE00_00D7 unassigned
FE00_00D8 --- WWB DMA Controller 2 Clear Byte Pointer
FE00_00D9 unassigned
FE00_00DA --- WWB DMA Controller 2 Master Clear
FE00_00DB unassigned
FE00_00DC --- WWB DMA Controller 2 Clear Mask
FE00_00DD unassigned
FE00_00DE --- WWB DMA Controller 2 Write All Mask
FE00_00DF FE00_00EF unassigned
FE00_00F0 --- WWB Coprocessor Error
FE00_00F1 FE00_015B unassigned
FE00_015C --- R/W SIO PnP Index Register
Table4-2: Detailed ISA I/O Address Map
Start End Mode Device Register Notes
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FE00_015D --- R/W SIO PnP Data Register
FE00_015E FE00_016F unassigned
FE00_0170 FE00_0177 R/W WB IDE Channel 2 Primary
FE00_0178 FE00_01EF unassigned
FE00_01F0 FE00_01F7 R/W WB IDE Channel 1 Primary
FE00_01F8 FE00_0277 unassigned
FE00_0278 FE00_027F R/W SIO Parallel Port Registers 1
FE00_0280 FE00_02F7 unassigned
FE00_02F8 FE00_02FF R/W SIO COM2 UART Registers 1
FE00_0300 FE00_0375 unassigned
FE00_0376 --- R/W WB IDE Channel 2 Secondary
FE00_0377 FE00_03F1 unassigned
FE00_03F2 FE00_03F3 R/W SIO FDC Floppy Registers 1
FE00_03F4 FE00_03F5 unassigned
FE00_03F6 --- R/W WB IDE Channel 1 Secondary
FE00_03F7 unassigned
FE00_03F8 FE00_03FF R/W SIO COM1 UART Registers 1
FE00_0400 FE00_0409 unassigned
FE00_040A --- RWB DMA Scatter/Gather Interrupt Status
FE00_040B --- WWB DMA Controller 1 Extended Mode
FE00_040C FE00_0414 unassigned
FE00_0415 --- WWB DMA Scatter/Gather Channel 5 Command
FE00_0416 --- WWB DMA Scatter/Gather Channel 6 Command
FE00_0417 --- WWB DMA Scatter/Gather Channel 7 Command
FE00_0418 FE00_041C unassigned
FE00_041D --- RWB DMA Scatter/Gather Channel 5 Status
FE00_041E --- RWB DMA Scatter/Gather Channel 6 Status
FE00_041F --- RWB DMA Scatter/Gather Channel 7 Status
FE00_0420 FE00_0433 unassigned
FE00_0434 FE00_0437 R/W WB DMA Scatter/Gather Channel 5 Table Pointer
FE00_0438 FE00_043B R/W WB DMA Scatter/Gather Channel 6 Table Pointer
FE00_043C FE00_043F R/W WB DMA Scatter/Gather Channel 7 Table Pointer
FE00_0440 FE00_0480 unassigned
FE00_0481 --- R/W WB DMA Page Register 2
FE00_0482 --- R/W WB DMA Page Register 3
FE00_0483 --- R/W WB DMA Page Register 1
FE00_0484 FE00_0486 unassigned
FE00_0487 --- R/W WB DMA Page Register 0
FE00_0488 unassigned
FE00_0489 --- R/W WB DMA Page Register 6
FE00_048A --- R/W WB DMA Page Register 7
Table4-2: Detailed ISA I/O Address Map
Start End Mode Device Register Notes
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NOTES:
1. Requires that the indicated device in the SIO has been enabled through the PnP (Plug-and-Play) enumeration port (PnP
Index/Data registers).
2. This register is programmable; shown is the DINK debugger default value.
4.2 Initializing Sandpoint
A typical start-up sequence includes the following:
1. Initialize CPU (all CPUs recognized)
2. Initialize BATs
3. Initialize Cache
4. Initialize Bridge Chip (MPC107 or 842X)
5. Setup stack pointer
6. Initialize Winbond PCI/ISA bridge
7. Initialize SuperIO
8. Initialize Serial IO
9. Bus speed detection
10. Size memory
11. Setup decrementer and timers
12. Initialize EPIC and enable exceptions
13. Begin User Code
(perhaps more, perhaps less). These functions are too detailed to go into in this document, so instead refer
to the DINK source code.
FE00_048B --- R/W WB DMA Page Register 5
FE00_048C FE00_04CF unassigned
FE00_04D0 --- R/W WB PIC 1 Interrupt Control
FE00_04D1 --- R/W WB PIC 2 Interrupt Control
FE00_04D2 FE00_06FF unassigned
FE00_0700 --- R/W SIO GPIO Port #0: Data 2
FE00_0701 --- R/W SIO GPIO Port #0: Direction 2
FE00_0702 FE00_080F unassigned
FE00_0810 --- WWB RTC CMOS RAM Protect 1
FE00_0812 --- WWB RTC CMOS RAM Protect 2
FE00_0813 FEBF_FFFF unassigned
Table4-3. Dink Functions
Step Functions Source file Notes
1CPU setup except2.s starting at “system_reset:”
2BAT setup except2.s starting at “mmu_setup:”
3Cache setup except2.s
cache.s starting at “init_L2backside_cache”
all of “cache.s”
4MPC107/MPC8240 setup mpc107.s or kahlua.s All or both
Table4-2: Detailed ISA I/O Address Map
Start End Mode Device Register Notes
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Starting with DINK release 12.3 and later, a demonstration Sandpoint initialization file “spinit.s” will be
available.
5Stack setup except2.s init_global_cont:
6Winbond setup yk.c winbond_initialize()
7Super IO yk.c ns308_defaults()
8Serial Init yk.c CommInit()
9Bus speed detection pmc.c GetBusPeriod()
IDProcessor()
10 Size memory meminfo.c meminfo(), memcheck()
11 Decrementer except2.s EH500S
12 Initialize EPIC and exceptions drivers/epic/epic1.c all
Table4-3. Dink Functions
Step Functions Source file Notes
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5 Development Issues
The following sections cover a few issues related to developing software on the Sandpoint platform.
5.1 Code Development
Software can generally be developed on a Unix workstation or PC and downloaded to the Sandpoint using
assemblers or compilers from a variety of third-party resources. Refer to:
http://www.mot.com/SPS/PowerPC/3rdparty/index.html
for further details. Issues regarding code development on Sandpoint were covered in Section4. Once the
code has been developed, it is generally transferred to the Sandpoint by one method or another for testing.
There are several ways of doing this, depending on the
5.2 Speeding Up Code Downloading
DINK currently only supports loading program images through the S-record download command (“dl”). To
speed up the process, the baud rate should generally be set to 38,400 baud.
DINK32_MAX >> sb -k 38400
DINK32_MAX >> dl -k -o 90000
12000 lines transferred.
DINK32_MAX >>
In addition, DINK supports a binary download feature which is about 150% faster again. To use this facility,
the ‘srec2bin’ utility in the DINK source code must be compiled, and the resulting program is used to
translate your program’s S-Record file to binary. Then, the DINK command:
DINK32_MAX >> dl -k -b -o 90000
436 bytes transferred.
DINK32_MAX >>
will initiate a binary download. After issuing the “dl” command, use your terminal emulation program to
send the file as-is (no translation, padding or flow control). DINK stops accepting characters from the
terminal program after 5 seconds of inactivity.
NOTE: The basic “Hyperterminal” program on a PC inserts NULLs every 32K or so, so it is not generally
usable with this facility. The facility for transferring binary files must be completely ‘transparent’ and not
alter any characters sent or received. This is sometimes referred to as ‘8-bit clean’.
5.3 Instant Code Downloading
An alternate way of debugging boot code is to use a ROM emulator, such as the PromJET from Emulation
Technologies (http://www.emutec.com/pjetmain.html). The Sandpoint has a 32-pin, 5V socketed flash
device which can be removed and replaced with an in-circuit emulator. Though limited to 512K, this can be
a very fast method of code checkout. Equivalent solutions are available for the TSOP48-packaged flash on
the MPPMC boards, but this requires desoldering and replacing the flash with a special cable.
5.4 Running Code Under DINK
Once the program has been downloaded into memory, it can be execute by entering ‘go 90000’ (or other
starting address). DINK will preset all the registers (integer, floating and special-purpose) to the default
values, and then execute the program. The code can return to DINK by ending with a ‘blr’ instruction, or by
setting a breakpoint.
Changing the SPR registers using DINK can help with measuring program operation under varying
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conditions; for example, if a program has been downloaded to address 0x90000, the following sequence:
DINK32_MPC755 >> rm -e l2cr
L2CR = 0x00000000
New Value ? 0x00000000
DINK32_MPC755 >> go 90000
(measure performance)
User code returned to DINK.
DINK32_MPC755 >> rm l2cr
L2CR = 0x00000000
New Value ? 0x3D014000
DINK32_MPC755 >> go 90000
(measure performance)
User code returned to DINK.
DINK32_MPC755 >>
By enabling or disabling the L2, the user code effectively emulates running on an MPC755 (w/L2 cache) or
an MPC745 (w/no L2 cache).
5.5 Saving User Code in Flash
DINK has the capability of saving user code to the ROM on the Sandpoint motherboard (but this overwrites
DINK itself) or to one of the two flashes on most MPPMC cards. The “fupdate” command can be used for
this purpose:
1. Download the code to memory
dl -k -o 100000
and download your program as usual.
2. Make sure the PROGMODE switch on the MPPMC card is on (see the configuration guides for the
corresponding MPPMC card for switch location).
3. Issue the command:
fu -l 100000 ff000000 100000
(you can reduce the last argument to the actual size of your program).
4. Decide if you want to boot directly into your code (your code initializes the entire platform):
Turn the PROGMODE switch OFF
Set the ROMLOC switch to “RSC0 on local bus”
Press the reset button -- DINK will boot directly into your code.
or if you want DINK to do the init.
Leave the PROGMODE switch ON
To run your code, use the command “go ff000000” (assuming your code started at the offset
0; otherwise use a different offset).
To automatically run your code upon reset, enter the command:
“ENV BOOT=0xFF000000”
5.6 Compatibility Issues
With the use of the MPPMC standard for evaluation processor modules, it is relatively easy to swap out the
processor card in a Sandpoint with another CPU. This allows evaluating code for a variety of PowerPC
devices, and each PMC card has the ability to change the operating speed to further adjust Sandpoint to
resemble the target platform.
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SP3 supports, and is shipped with, one of the following MPPMC cards.
Note: Due to the evolution between the Motorola’s MPPMC specification and the changes made to it by
VITA as part of their standardization process for the PrPMC standard, Motorola cannot guarantee that
MPPMC cards will necessarily work outside the SP3 environment, nor that PrPMC cards will work in
VITA-PrPMC systems. An option switch on some MPPMC cards attempts to mitigate this, but for this
reason and others MPPMC cards are not sold except with an attached MPPMC card.
For information on changing the operating speeds of an individual MPPMC cards, refer to the
“configuration guide” included in the bound documentation, or on the Sandpoint website (see AppendixC).
5.7 Upgrading DINK
Occasionally, DINK is upgraded with new facilities and bug fixes. DINK 12.1 or later has the ability to
update itself using the “fupdate” command. To update DINK with a new version, follow this sequence:
1. Consider making a safety copy of the current DINK first by saving it to the flash on the MPPMC:
Set the PROGMODE switch and enter
fu -l fff00000 ff000000 7ff00
2. Obtain the DINK S-record file for Yellowknife/Sandpoint. The latest version is at:
http://www.mot.com/SPS/PowerPC/teksupport/tools/DINK32/dinkindex.htm
3. Download the S-record file to the Sandpoint platform using the command:
dl -k -o 100000
with the terminal program, in the usual manner. You can also convert it to binary for faster
download, as described in Section5.2).
4. Issue the command:
fu -h 100000 fff00000 7ff00
Restart, and the new version of DINK should activate. If an error occurs, DINK will not work and the flash
will need to be externally re-programmed on a PROM programmer. If the safety copy was made in step 1
above, just set the ROMLOC switch to boot from the local flash instead of PCI.
Table5-1. Supported MPPMC Cards
MPPMC Board Processor Bridge SDRAM Notes
MPPMC603 Talos
X1
MPC603r
MCP107 64MB
SODIMM
SODIMM memory (no parity/ECC)
(2) 1MB flash
MPPMC740 MPC740
MPPMC745 MPC745
MPPMC750
Altimus
X3
MPC750
MCP107 64MB
discrete
ECC/Parity support
(2) 1MB flash
MPPMC755 MPC755
MPPMC7400 MPC7400
MPPMC7410 MPC7410
MPPMC7450 Valis
X1 MPC750 MCP107 64MB
discrete ECC/Parity support
(2) 1MB flash
MPPMC8240 Unity
X4 MPC8240 -64MB
SODIMM SODIMM memory (no parity/ECC)
(2) 1MB flash
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6 Troubleshooting
If you are having trouble with
6.1 DINK Does Not Start Up
•Make sure the switch under the power cord is on. If there is AC power switched on at the power
supply, the green LED labelled “STANDBY POWER” will be on (you must open the cover to see
it).
•If STANDBY POWER is on, but the board will no power up
•
Table6-1. Troubleshooting SP3
Problem What to Check Verify
DINK will not start Make sure power cord is plugged in.
Make sure power supply switch is ON (switch is under the
power cord at the back)
If AC power is active, the green
“STANDBY POWER” LED on the SP3
motherboard will be on (open the chassis to
verify).
If the standby power is now active, press the
POWER switch on the front of the chassis.
If STANDBY POWER is on but the front panel power
switch does not start DINK,. Open the chassis and press the red POWER
switch at the bottom right corner (second
from the bottom).
If power is now available (MAIN POWER
is on), the chassis power switch may be
disconnected. Make sure the cabled
connecter labelled “POWER SW” or
equivalent is connected to the chassis
header (J29) on the pins labelled “PWR
SW” (pins 24 and 26).
If STANDBY POWER is on but neither the front panel
power switch nor the internal red button will start DINK,
set the PSON switch (see Section3.1.8).
If power is now available (MAIN POWER
is on), the APC unit is not functioning.
Make sure that the battery is installed and is
not discharged (replace if necessary).
Sandpoint will work without the APC but
power must be turned on and off with the
power supply switch.
If STANDBY POWER and MAIN POWER are both on,
press the red reset button inside (bottom right corner). If DINK starts, the front-panel reset switch
may be disconnected. Insure that the cable
labelled “RESET” or equivalent is
connected to the chassis header J26 pins 2/
4/6/8.
If power is on and the reset button does not start DINK,
check the activity of the MPPMC LEDs and the SP3
LEDs.
If all MPPMC LEDs do not activate while
the Reset button is pressed and held, the
MPPMC card is not installed or not
functioning. Insure card is firmly seated and
re-try.
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If power is on and LEDs are active while reset pressed,
release reset and monitor PCI bus activity. If the PCI LED on the SP3 motherboard is
not active (flickering), DINK is not running
from the ROM. This can be caused by:
1. Improper configuration of the MPPMC
card (review configuration guide)
2. Improper configuration of the SP3 board
(refer to this document).
3. Socketed SDRAM loose (reseat).
Reseat socketed devices, and/or restore the
system to factory defaults (shaded settings
on MPPMC configuration guides and as
stated in this document).
If power is on, LEDs are active, system is in default
configuration. If the PCI LED flickers momentarily and
then stops, the cause could be the PCI boot
ROM:
1. A mis-programmed flash (user code)
2. Broken ROM socket (common with
mishandled PromJETs).
Restore or replace the DINK ROM and
retry. Also consider trying the ROM in a
second Sandpoint or verifying it on an
external programming system.
If power is on, LEDs are active, system is in default
configuration, and the PCI LED is active continuously: DINK is running. Check the serial port
connections.
1. Make sure you are using a null-modem
cable. A standard cable will not work.
2. Make sure the cable is in COM1 on the
Sandpoint system (nearest the power cord).
3. Make sure you’re using the COM port
your terminal expects (try the other one).
If power is on, LEDs are active, system is in default
configuration, and the PCI LED is active continuously, and
the connections are correct.
DINK is running. Check the terminal setup:
1. Check that the terminal is setup for no-
handshaking:
Remove the cable from the Sandpoint and
connect a wire or piece of metal between
pins 2 and 3. There are no dangerous
voltages present. If you can type on the
terminal, the handshaking is correct.
If power is on, LEDs are active, system is in default
configuration, and the PCI LED is active continuously, and
the connections and handshaking are correct.
Contact Motorola technical support.
DINK writes
characters to the
screen, but they’re
illegible.
Make sure the terminal program is set to 9600 baud, 8N1,
no handshaking. Check settings.
Make sure the DINK baud rate has not been changed with
the ENV command. Press the backspace key and hold it down
while pressing RESET. If DINK comes up,
enter the command “ENV -c”
Table6-1. Troubleshooting SP3
Problem What to Check Verify
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DINK prints “DUART
Initialized...” then
hangs.
Make sure DINK is not trying to setup an invalid L2/L3
setting (if appropriate) or other configuration. Press the backspace key and hold it down
while pressing RESET. If DINK comes up,
enter the command “ENV -c”
DINK runs fine for a
while, then hangs until
it cools down.
Open the chassis and make sure the heat sink, especially
those with a fan, is firmly attached and that the fan is
connected to a power source and is turning.
Reseat the heatsink if necessary and turn it
gently to tighten.
Check fan power connections.
Table6-1. Troubleshooting SP3
Problem What to Check Verify
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7 FAQ
These questions are frequently asked.
1. What mode should I use if my software was running fine on Sandpoint 2?
Use AMODE=00, ILEGACY=1 and IMODE=00 or 01 (this are equivalent to modes 0 and 1 on
SP2).
2. What mode should I use if I am developing new software for Sandpoint 2?
Use the defaults: AMODE=00, ILEGACY=0 and IMODE=00 -- these give better performance and
enable all features of the system.
3. How can I write to the serial port? It doesn’t seem to be at the address shown.
Like any plug-and-play device, ISA IO devices need to be plugged and played. DINK includes
setup for the serial port in the file “yk.c” for both the SuperIO and the COM ports.
4. How do I access/configure the PCI devices.
This depends to some extent on the MPPMC card present. If it supports Map “B” (CHRP), then the
configuration cycles are performed by writing the configuration address (0x8000_0000 with the
appropriate bit set for the device number) to the PCI configuration address register (0xFEC0_0000)
and reading/writing from the PCI configuration data register (0xFEE0_0000). See the file
“pciLib.c” in the DINK source code for examples.
5. How can I control the STAT and FAIL LEDs?
To do this the GPIO port in the SuperIO needs to be enabled. Use the code in “yk.c:ns308defaults()”
as a starting point. This file sets the GPIO programmable address decoder to an ISA address of
0x0700, making the IO registers available at 0xFE00_0700. Elsewhere in “yk.c” the IO port
direction is set to output for bits 1 and 0. Thereafter, writing a ‘0’ to that port activates the LED, and
writing a ‘1’ deactivates it.
7.1 Detecting Sandpoint 3
The Sandpoint 3 motherboard has a loopback connection between GPIO pins 7 and 6. If software needs to
know which platform it is operating on, the following sequence will work:
1. Enable the GPIO port on the SuperIO.
2. Program GPIO pin 7 to output.
3. Program GPIO pin 6 to input.
4. Write 1 to GPIO pin 7; read GPIO pin 6.
5. Write 0 to GPIO pin 7; read GPIO pin 6.
6. If read values are “[1, 0]”, then the motherboard is 3; else it is 2.
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AppendixA:Sandpoint 3 Changes
There are several differences between Sandpoint 2 and Sandpoint 3. Table7-1 lists them, as well as any
likely effect on software.
Table7-1. Sandpoint 3 Changes
Change Effect on Software
IDSEL disconnected for MPPMC slot. None, but software no longer has to avoid sending
configuration cycles to device #12 (IDSEL addr = AD12).
Secondary, larger, PCI-hosted ROM. None as long as standard addresses are used (0xFFF0_0000
to 0xFFF7_FFFF).
On-board spread-spectrum clock generator. None, spread-spectrum is disabled by default.
IDE interface corrected. None, 2 was rewired.
IDE PCI interrupts connected properly. Software may use PCI interrupts instead of 8259 interrupts.
On-board reset controller for more reliable resetting, particularly
from COP. None.
Cabled battery replaced with standard socketed coin. None.
All PCI bus devices (PMC and PCI slots plus the Winbond) can
be configured for 5V or 3V operation (as a build option). None.
PCI slots are correctly numbered in order. None. Might affect any installation instructions, though if so,
they could only get clearer and less confusing.
Test clock input enable works. None.
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AppendixB: Legacy Interrupt Support
Sandpoint 2 had an “interesting” interrupt architecture, mostly an attempt to funnel seven interrupts into the
four available MPPMC interrupts with little logic support. SP3 solves this by using the “SPF100” logic in
conjunction with the serial interrupt EPIC device avaiable on Motorola MPPMC cards.
However, for backward compatibility purposes, SP3 supports the SP 1/2 interrupt scheme. For more details
on the interconnections, refer to the SPX2TS (Sandpoint 2 Technical Summary), available on the Motorola
Website.
To enable Legacy-mode interrupt connections, set the ILEGACY switch OFF (SW2-3 to the left). Then
select one of the interrupt connections according to Table7-2.
Note: This SP3 supports legacy mode in the manner SP2 should have; namely, supporting IDE interrupt
from the Winbond on INTC#/INTD# (SP3) instead of INTA#/INTB# (SP2); there’s not much point
emulating SP2 bugs.
Using the standard modes is highly encouraged, as nothing like this will be supported on future Sandpoint
platform or any other platform.
Table7-2. Legacy Interrupt Connections
SW2-5 SW2-5 Sandpoint 2
Modes Interrupt Connections Notes
On (right) On (right)
0
inverted interrupt
share SLOT2
PMC_INT0 = Winbond INTC# Winbond IDE can output to
INTC#/INTD#
SIOINT is inverted
PMC_INT1 = Winbond INTD# or
SIOINT
PMC_INT2 = SLOT3 INTA#
PMC_INT3 = SLOT4 INTA#
On (right) Off (left)
0
normal interrupt
share SLOT2
PMC_INT0 = Winbond INTC# Winbond IDE can output to
INTC#/INTD#
SIOINT is not inverted
PMC_INT1 = Winbond INTD# or
SIOINT
PMC_INT2 = SLOT3 INTA#
PMC_INT3 = SLOT4 INTA#
Off (left) On (right)
0
inverted interrupt
share SLOT3
PMC_INT0 = Winbond INTC# Winbond IDE can output to
INTC#/INTD#
PMC_INT1 = Winbond INTD#
PMC_INT2 = SLOT3 INTA# or
SIOINT
SIOINT is inverted
PMC_INT3 = SLOT4 INTA#
Off (left) Off (left)
0
normal interrupt
share SLOT3
PMC_INT0 = Winbond INTC# Winbond IDE can output to
INTC#/INTD#
PMC_INT1 = Winbond INTD#
PMC_INT2 = SLOT3 INTA# or
SIOINT
SIOINT is not inverted
PMC_INT3 = SLOT4 INTA#
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AppendixC: Reference Documentation
Table7-3 describes reference documentation which may be useful for understanding the operation of the
Sandpoint or an attached MPPMC card:
AppendixD: Glossary
Table7-4 explains some terminology used in this document:
Table7-3. Reference Documentation
Document Number/Reference
Sandpoint 3 Technical Summary
Schematics
Errata
http://www.mot.com/SPS/PowerPC/teksupport/
refdesigns/sandpoint.html
MPPMC Schematics
Documentation
Errata
http://www.mot.com/SPS/PowerPC/teksupport/
refdesigns/sandpoint.html
MPC8240 User’s Manual http://e-www.motorola.com/brdata/PDFDB/
MICROPROCESSORS/32_BIT/POWERPC/
MPC82XX/MPC8240UM.pdf
MPC107 User’s Manual http://e-www.motorola.com/brdata/PDFDB/
MICROPROCESSORS/32_BIT/POWERPC/
MPC1XX/MPC107UM.pdf
DINK User’s Manual
and code updates http://www.mot.com/SPS/PowerPC/teksupport/
tools/DINK32/dinkindex.htm
Draft Standard Physical and Environmental Layers for Processor PCI
Mezzanine Cards: PrPMC http://www.vita.com/vso/
PCI 2.1 Specification http://www.pcisig.com
Draft Standard Physical and Environmental Layers for PCI Mezzanine
Cards: PMC IEEE P1386.1/Draft 2.0 04-APR-1995
Draft Standard for a Common Mezzanine Card Family: CMC IEEE P1386/Draft 2.0 04-APR-1995
Winbond W83C553 Datasheet http://www.winbond.com.tw/sheet/w83c553f.pdf
or
http:///www.winbond.com.tw/
National Semi. PC87307/97307 Datasheet http://www.national.com/pf/PC/PC97307.html
or
http:///www.national.com/design/
Table7-4. Terminology
Term Definition
ATA AT (PC format) Attach - protocol for communicating over IDE bus.
ATX Form factor for chassis.
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BBRAM Battery-Backed Random Access Memory
IDE Integrated Device Electronics -- common disk interface signalling.
MPPMC Motorola Processor PCI Mezzanine Card -- an superset of the VITA PrPMC specification
proposal which adds PCI arbitration.
PCI Peripheral Connect Interface
PMC PCI Mezzanine Card -- a small form-factor PCI-2.0 compliant daughtercard standard.
PPMC Processor PCI Mezzanine Card -- an early name for PrPMC; no longer used.
PrPMC Processor PCI Mezzanine Card -- an extension to the IEEE1386 PMC standard adding host-
related functions and PCI-2.1 compatibility (was formerly called PPMC).
RAM Are you kidding?
RTCReal Time Clock
SIO System I/O (or SuperIO) - National Semi. PC-I/O device.
WBWinBond, manufacturer of the ISA/IDE interface.
Table7-4. Terminology
Term Definition
*
**
**
accuracy of the information contained herein. Contact
Sandpoint
Digital DNA
MPPMC750 - Altimus
MPPMC755 - Altimus
MPPMC7400 - Altimus
MPPMC7410 - Altimus
MPPMC7450 - Valis
MPPMC8260 - Cygnus
...tbd...
This schematic is provided for reference purposes only.
No warranty, expressed or applied, is made as to the
All information is subject to change without notice.
*
**
*
*
**
*
*
Motorola Sale/FAEs to obtain the latest information on
this product.
*** **
from Motorola
*
Supporting
MPPMC603 - Talos
MPPMC740 - Talos
MPPMC745 - Talos
MPPMC8240 - Unity
MPPMC8245 - Unity
16
Cover Page
19
01
Part numbers used are for reference only; compatible
parts may be used; refer to the bill of materials.
Motorola and the Motorola logo are registered
trademarks of Motorola. PowerPC is a trademark of
ContentsSchematic Notes
Configuration Switches; Monitor LEDs
All inductances are in microhenries (uH).
07 64-bit PCI PMC Connector
05
98DEC11
Connector orientation; crosspoint tweaks.
18
the most-significant bit), except where industry standards
apply (i.e. PCI). Little-endian numbering is noted at the
Cindy Black
Designer
Sheet "-" VertZoneLetter HorizZoneNumber
Processor PMC Socket
04
SPF100 - Arbiter/Interrupt Controller
VCC_5V
Imperial Poobah
4.
5.
source component.
Board impedance is 50-60 ohms.
General Information
and ground unless explicitly shown otherwise. Global power Routing and Layout Information
02 Block Diagram
respective copyright holders. Diane, I am holding in my
Joey Tsai
13 Floppy, PC I/O Connectors12
17 PCI Boot ROMs, NVRAM
11
All buses follow big-endian bit numbering order (bit 0 is
Components
03
Power Supply
Pullups
Super I/O Controller
Gary Milliorn
Gary Wojcik
All fuses are self-resetting polyswitch (PTC) devices.
All ferrites are Z=50 ohms at 100 MHz.
Page
7.
REV DATE
All capacitors are SMD0603, in microfarads (uF), +/-20%.
X1 98MAR23
Original
X2
Serial Ports
Tony Saucedo
Unless otherwise specified:
All resistors are SMD0603, in ohms, 0.1W, +/-5%
06 Clock Generation
10
Integrated circuits have default connections to power
IBM. Other trademarks are the respective property of their
Team Sandpoint
Ivan Erickson
PCI Slots #3, #415 PCI Slots #1, #214
Documentation
Program Mgr.
PCB CAD
3.
IDE Connectors
08
hand a box of small, chocolate bunnies. All rights reserved.
6.
1.
2.
GND
Sandpoint
09
CHANGES
VCC_3.3V
GARY MILLIORN
PCI/ISA Bridge
by default; they are for test or manufacturing purposes only.
Components with the property "no_stuff" are not to be installed
*
X3 00JUL26
Many changes
connections are:
The sheet-to-sheet cross reference format is:
Non-Volatile RAM
<10>
(2) 33/66-MHz ATAPI
Interrupt Routing
Arbitration Routing
<05>
<09>
Reset Logic
PMC Connector
1) 512KB
ATX Chassis Header
PCI: 33 or 66 MHz
PC Clocks.
<06>
System Clocks
National 87307
PCI Slots
<14,15>
Super I/O Controller
<12,13>
<17>
Winbond W53C55x
ISA Bus
32-bit/64-bit 33/66 MHz PCI Bus
PPMC Extensions
PC I/O Ports
(2) 32-bit 5V PCI slots
(2) 64-bit 5V PCI slots
IDE Connectors
<16> <11>
66 MHz Extensions
32/64 bit
<17>
Southbridge
PS/2 Keyboard & Mouse
Parallel Port & Floppy
Serial Ports
APC/RTC Power Supply
8K bytes
<07-08>
Boot Flash Rom
<16>
Power Supply
Chassis Headers
<05>
2) 8MB
Use 12 mil traces for +12V and -12V.
Place IDSEL resistor near IDSEL pin.
Place series termination resistors near socket.
11
Recommended placement for status LEDs is under the disk tray area.
18
Use 12 mil traces for VBAT and VSTDBY.
Use equal-length traces on nets DAK(2:0) from WinBond to ’F138.
GARY MILLIORN
Place header in lower-left hand corner of the board (I/O connectors would
DISK
No special restrictions.
be in the upper right.
06
21
Distribute capacitors as shown, unless otherwise specified.
12
Allow clearance around header to allow for silkscreen legends.
Allow no other traces to enter or cross the crystal oscillator area.
10
PWR LED
Place LEDs in order and label with indicated text.
07
Use 12 mil traces between battery connector and diodes (before and after).
Keep series termination resistors near the output pins.
14
Place series resistors for parallel port near DB25 connector.
20
"
Surround MPC972 with 4-6 0.1uF caps to provide good ground-return paths.
15 Place IDSEL resistor near IDSEL pin.
Keep traces as short as possible. Pin swapping within and without of a package is
19
16
05
Layout/Routing Instructions
Place PMC at top side of ATX board.
SW
RESET STDBY
Use very short traces from 32kHz crystal to SuperI/O and to connected components.
Use heavy traces for power path through filter:
LED
Use split power planes for 5V and 3.3V power.
Route all PCI clock lengths to equal the WBCLK trace less 2.5"
08
IR Port
No special restrictions.
Keep traces very short between RS232 drivers (U1, U2) and DB9 connectors.
encouraged in order to minimize trace length.
+3.3V => VCCO pins & Rxxx/Rxxx Combo => VCCI Pin.
PWR
SWITCH
SPKR
Label pin groups as shown.
LED
09
Place EMI filtering caps and ferrite beads very close to DIN6 and DB25 connectors.
ON
Keep XTAL1 pin and jumper insanely close.
CHASSIS
17
Follow ATX chassis specs for ATX mounting hole sizes and plated area allowance.
13
i
i
i
i
i
ATX Chassis Mounting Holes
NVRAM SOURCING
Select VSTDBY or battery
as available.
of board for cable connection.
ATX Chassis Cable Header
Place in lower-left hand corner
Local Reset Switch
Local Power Switch
ii
CLOCK EQUALIZATION
PCI and PMC specifications.
Select CLKOFF to select external
TEST CLOCK INPUT
WBCLK less 2.5 inches per
Route indicated clocks to match
50ohm clock source.
i
Default: 5V
Select 3.3V or 5V VIO option.
PCI VIO SELECT
i
i
PRIMARY IDE
SECONDARY IDE
i
Keep all traces extremely short.
32kHz Oscillator
Route no traces through that area.
i
i
i
i
Floppy connector
Parallel Port
Right-angle PCB mount
PS/2 Keyboard
PS/2 Mouse
i
i
Serial Port #2
Serial Port #1
i
i
Next-closest to PMC.
PCI Slot #2
IDSEL AD14
PCI Slot #1
IDSEL AD13
Closest to PMC.
i
i
PCI Slot #4
IDSEL AD16
Furthest from PMC.
PCI Slot #3
IDSEL AD15
Third from PMC.
i
Place in visible area.
Diagnostic LEDs
Sandpoint Errata Page 1 /5
Motorola Inc.
Unrestricted Distribution Permitted 01 Feb 16
Sandpoint
Reference Platform Errata
Board Revision Level X3
Errata Revision Level A
Copyright 2001 by Motorola Incorporated. All rights reserved.
c
Sandpoint Errata Page 2 /5
Motorola Inc.
Unrestricted Distribution Permitted 01 Feb 16
Revision History
Version Date Changes
A2001 Jan 31 Initial errata.
2001 Feb 16 Changed method for errata #7.
Sandpoint Errata Page 3 /5
Motorola Inc.
Unrestricted Distribution Permitted 01 Feb 16
Table 1: Summary of Sandpoint Errata
#Type Problem Cause Work-Around Affects Rev
1Design Clocks not working. W185 enables are tied low; should be tied
high.
EN1 and EN2 should be connected to
+3.3V. Only EN1 is required.
1. Cut trace between U1 pin 18 and ground
via.
2. Connect U1 pin 18 to U1 pin 16 (+3.3V).
For X4: Connect pin 18 of U1 to +3.3V.
X3 A
2Design Soft-power inoperative. VBAT needs to be ~3.0V.
Coin cells are 3V, cabled batteries are 4.5V.
R44 values must be selected based upon
battery used.
If CR2032 Coin Battery used:
1. Remove 0 ohm resistor on half of dual-
resistor component R44 nearest ATX
power header.
If Rayovac Cabled Battery used:
1. Install 100K ohm resistor on portion of
R44 nearest National SuperIO.
2. Install 27K ohm resistor on portion of
R44 nearest ATX header.
For X4: Use two discrete resistors; stan-
dardize on coin cell.
X3A
3Design Soft power not working. No pullup allowed on PS_ON.1. Cut trace between RN72 pin 5 and via
connecting to VCC3.3.
For X4: Delete pullup.
X3 A
4Design PCI arbiter not working. No pullups on SLOT_REQ(1:4) Connect (4) 4.7K ohm resistors between
SLOT1/SLOT2/SLOT3/SLOT4 pins
B18 and B19 on the bottom of the board.
For X4: SLOT_INT(1:4) on page 19 should
be for SLOT_REQ(1:4).
X3A
5Design None. SLOT_INT(1:4) pulled up twice. None.
For X4: Remove redundant pullups.
X3A
Sandpoint Errata Page 4 /5
Motorola Inc.
Unrestricted Distribution Permitted 01 Feb 16
6Design None. WB_GNT(0:4) pulled up twice. None.
For X4: Remove redundant pullups.
X3A
7Design Slot 3 interrupt not respond-
ing. Slot 3 INTA/INTB pins connected incor-
rectly. 1. Remove all solder on SLOT3 pin A6.
2. Cover pin with Teflon or equiv. insulat-
ing sleeve.
3. Connect SLOT3 pin A6 to SLOT3 pin
B7.
For X4: Connect INTA# to SLOT_INT(3),
INTB# to SLOT_INT(4).
X3A
Table 1: Summary of Sandpoint Errata
#Type Problem Cause Work-Around Affects Rev
Sandpoint Errata Page 5 /5
Motorola Inc.
Unrestricted Distribution Permitted 01 Feb 16
Errata 7: SLOT3 Interrupt Connection
OVERVIEW
The SLOT #3 INTA# and INTB# interrupts are wired incorrectly.
WORKAROUND
The work-around corrects INTA# only. A multi-interrupt card should not be used in SLOT
3.
1. Remove all solder on SLOT3 pin A6. Place Teflon sleeve over pin.
2. Connect SLOT3 pin A6 to SLOT3 pin B7
SLOT 3
R21
SLOT 2
A1
SLOT 4
B7 A6
Talos
TALOS UNITY ALTIM VALIS
SP3
Talos X1 (PrPMC60x/PrPMC7x5) Configuration Guide
Revised: 2000 Jun 13
SYSRST COP resets only MPPMC
COP resets system
ñ
=1
ê
=0
M66EN 66 MHz PCI allowed
33 MHz PCI only
ñ
=1
ê
=0
ROMSEL Main ROM selected
Backup ROM selected
ñ
=1
ê
=0
PROGSEL RCS0 selects local flash (boot)
RCS1 selects local flash (prog.)
ñ
=1
ê
=0
AGENT Free agent
Wait for host
ñ
=1
ê
=0
PMCTYPE MOT MPPMC
VITA PrPMC
ñ
=1
ê
=0
MAPSEL Map “B” / CHRP
Map “A” / PReP
ñ
=1
ê
=0
ROMLOC RCS0 on local bus
RCS0 on PCI
ñ
=1
ê
=0
NAME DEF DESCRIPTION
1
ON
2345678
1
ON
2345678
107PLL
3 2 1 0 PCI BUS
ê
ê ê ê
33 33
ê
ñ
ê ê
20 40
ñ
ê
ñ
ê
33 66
ê ê ê
ñ33 100
ñ
ê ê
ñ66 120
ê
ñ
ê
ñ30 120
ê ê
ñ ñ 33 83
ñ
ê
ñ ñ 66 66
ñ ñ
ê ê
bypass
CPUPLL
0 1 2 3 Mult. 33 66 83 100
ñ
êêê
3X 100 200 250 300
ñ ñ ñ
ê
3.5X 116 233 292 350
ñ
ê
ñ
ê
4X 133 266 333 400
ê
ñ ñ ñ 4.5X 150 300 372 450
ñ
ê
ñ ñ 5X 166 330 415 500
ñ
ê ê
ñ5.5X 183 363 456 550
ñ ñ
ê
ñ6X 200 400 500 600
ñ
ê
ñ
ê
6.5X 216 433 540 650
ê ê
ñ
ê
7X 233 466 580 700
ê ê ê
ñ7.5X 250 500 622 750
ñ ñ
ê ê
8X 266 528 664 800
ê ê
ñ ñ byp. 33 66 83 100
ñ ñ ñ ñ off 0 0 0 0
Digital DNA
PPMC603
*
Motorola Confidential Proprietary
from Motorola
*
this product.
PPMC740
PPMC745
PRELIMINARY RELEASE
This schematic is provided for reference purposes only.
All information is subject to change without notice.
No warranty, expressed or applied, is made as to the
accuracy of the information contained herein. Contact
Motorola Sale/FAEs to obtain the latest information on
Talos
Local Boot ROM
10
reserved. No warranty is made, express or implied.
Matrix is, you have to see it for yourself. All rights
15
Contents
5.
Cindy Black
VCC_3.3
Program Mgr.
03
the most-significant bit), except where industry standards
Tony Saucedo
Talos
*
2.
respective copyright holders. No one can explain what the
Components surrounded by a dashed/crossed-out box are
6.
All buses follow big-endian bit numbering order (bit 0 is
3.
4.
Gary Wojcik
Motorola Confidential Proprietary
Cover Page
14
Unless otherwise specified:
IBM. Other trademarks are the respective property of their
Part numbers used are for reference only; compatible
VCC_5
The sheet-to-sheet cross reference format is:
and ground unless explicitly shown otherwise. Global power
09
Integrated circuits have default connections to power
MPC107: System Logic
06
Sheet "-" VertZoneLetter HorizZoneNumber
Components
02
connections are:
DATE
X1 99AUG02
13
05
Gary Milliorn
Manager
source component.
Routing and Layout Information
VCC_2.5
All fuses are self-resetting polyswitch (PTC) devices.
08
Block Diagram
System Configuration
7.
General Information
Power Supply
purposes only. MPC107: PCI Interface
Designer
GND
PMC Connectors.
Page
not to be installed by default; they are for test or manufacturing
All resistors are SMD0805, in ohms, 0.08W, +/-5%
PCB CAD
Configuration Logic / LEDs
11
Documentation
Stand-alone Support16
Ivan Erickson
apply (i.e. PCI). Little-endian numbering is noted at the
MPC107: Memory Interface
All capacitors are SMD0603, in microfarads (uF), +/-20%.
All inductances are in microhenries (uH).
SDRAM SODIMM Socket
CHANGES
Board impedance is 50-60 ohms.
12
MPC107: Processor Interface
01
Team Altimus
VCORE
Schematic Notes
1.
Motorola and the Motorola logo are registered
trademarks of Motorola. PowerPC is a trademark of
All ferrites are Z=50 ohms at 100 MHz.
Joey Tsai
Initial version
REV
parts may be used; refer to the bill of materials. MPC60X/MPC7XX Processor
07
04
32-bit 33/66 MHz PCI Bus
SDRAM SODIMM
Northbridge
Programmable
Power Supply
Motorola MPC60X/MPC740
Motorola MPC107
<05>
<11-14>
Motorola Confidential Proprietary
32 bit
64/72-bit 50-83 MHz Local Bus
5V to 1.9..2.5V Switcher
Boot ROM
<06-08>
PMC Connector
350-450 MHz
1Mbyte
Processor
<18>
<15><16>
Memory
PPMC Extensions
Low-Ohm Res. Rx => VCORE Plane
14
Do not swap order of MPC107 PLL switch connections.
Keep data bus load for ROMs short.
Am29LV800
Use split power plane or very heavy traces for power path:
Keep AVDD/AVDD2/LAVDD filters near MPC107. Use heavy, short traces from filter
Surround MPC107 with bypass caps to provide additional ground-return paths.
Use DPAK pads that meet or exceed thermal relief recommendations.
Socket
COP
MPC107
Use two ground-attach vias.
P2
POWER
P1
or
Place VID pulldown resistors in order shown.
07
SDRAM_SYNCIN path.
15
MPC60X
Keep VCCA/VCCP attachment within 2 cm of input filter location.
Use split power plane to connect VCORE from power supply to CPU core.
Place 820 uF low-ESR capacitors near CPU.
FLASH
Keep VCORE power flowing point-to-point through MOSFETs, inductor, resistor and
Route SDRAM clocks to equal lengths, including SDRAM_SYNCOUT to
12
Layout/Routing Instructions
Place LEDs away from COP overhang (for visibility).
Motorola Confidential Proprietary
Am29LV800
FLASH
SWITCH
Place MPC107 power supply beneath MPC107 if possible.
COP header does not need to be near anything. It should be placed in a relatively
Place switches as shown on diagram.
accessible area.
Do not swap pins on the switches; position is important.
09 No special routes.
Use short traces throughout.
06
LEDs
to pins. Place beneath the part if possible, in the center cavity area.
RC5051
+5V => MOSFET Qx => Inductor Lx =>
Avoid routing traces, especially noisy ones, across CPUPLL bus.
Maximum trace length for PCI signals to MPC107 is 1.5"
Avoid routing traces, especially noisy ones, across MPC107 PLL bus.
LT1118
SWITCH
Keep trace from 680 uF low-ESR capacitors within 2 cm of high-side MOSFET (Q2).
11
MPC74x
output filter capacitors.
10 PCI clock input must be 2.5" (per specification).
13
No special routes.
SODIMM
Place series termination resistors very near source (MPC107), < 2cm.
08
per the PCI specification.
Keep AVDD filter near MPC60X. Use heavy, short traces from filter to pins.
Keep MOSFET gate drive lines < 2 cm.
05
i
i
ii
i
i
O
I
I
II
O
O
I
O
I
O
O
1.45V
OI
O
I
O
2.8V
I
I
1.55V
MPC60X
2.7V
I
O 1.85V
I
I
1.60V
I
IO
O
I
O
O
I
O
IIO
OI
O
I
I
1.70V
O
O
I
I
O
1.90V
IOO
O
2.9V
O
I
VCORE
O
O
IO
O
VCORE OUTPUT
MPC750A
OO
O
1.95V
VID
I
O
II
O
O
O
O
VCORE OUTPUT
1.80V
O
I
OO
OO
I
may be programmed from 1.8V to 3.6V.
O
I
2.3V
I
I
2.5V
O
O
I
I
3.1V
I0.00V
Programmable CPU core voltage;
O 2.00V
I
dissipation.
OO
O
I
1.50V
O
O
O
IO
OO
II
1.30V
3.5V
O
O
I
I
I
O 1.40V
I
I
O
2.1V
O
I
O
3.2V
O
I
O
I
O
O
O
I
I
4
I
I
2
I
I
I
OO
the top of the PCB for additional thermal
3.4V
VOLTAGE SEQUENCING
Restricts power supplies to specification
limits. Not needed if ramp < 500 uS.
3.3V
O
O
3
O
O
II
I
I 1.75V
I
I
2.4VI
I
IO
3.0V
1
II
Motorola Confidential Proprietary
KELVIN CONNECTION
O
O
I
2.2V
I
VCC_2.5 OUTPUT
Low-power regulator supplies +2.5V
to the MPC107 core logic.
O
I
Route IFB and VFB traces paired
I
II
I
1.65V
O 2.05V
I
BULK CAPACITANCE
O
0
I
Distribute around the board.
Add 2-3 cm^2 to the ground plane area on
I
I
1.35V
O 2.6V
O
Motorola Confidential Proprietary
ii
i
i
i
-- bypass 33 66
PCI 66 MHz ENABLE
83 100
US
ON
XP0
XP1
--
Normal mode.
CP1
CP2
Normal ROM.
ROM SELECT
P66
ON ON -- 5.5X -- --
100
33 MHz only.
--
--
--
PCI CLOCKGP3
PCI 66 MHz
ON Enable 66 MHz operation
2.5X33 83
-- ON
ON ON 20
RS
P66
300 -- --
-- ON
7X
NOTE: Connector should be routed to
CP3
ADDRESS MAPAM
233
-- 1X
GP2
ON-- 3X
BUS CLOCK
XP3
MPC107 PLL SETTINGS
GP0
40
33 66
D32
AG
OFF
33
Auxillary ROM (swap RCS0/RCS1)
ON
-- --
ON ON --
--
-- -- off 0 0 0
--
RL ROM LOCATION
66 66
ON --
XP2
1X33 33
GP1
RL
AM
----
ON
120
Enable local ROM alias.
--
3.5X -- 233 292 --
ON
ON ON ON
-- ON
ADDRESS MAP SELECT
83
AGENT MODE
ON Wait for initialization (Peripheral Mode)
--
-- 100
ON ON
ON -- ON
SYSTEM RESET
PM
CPU PLL SETTINGS (MPC740)
ON
MAP "B": CHRP
150
CP0
-- 7.5X 250 --
--
--
--
ON
ON ROM on PCI Bus
-- ROM on Local Bus
ON
ON 1X33-66 33-66
-- --
-- ON
--
ON
CP3
ON
-- -- 5X 166 --
--
4X 133
--
-- --
266 --
33
AGENT MODE
SR DEFINITION
ON COP can reset target system.
COPonly resets local CPU/MPC107.
Processor debug access port.
-- 4.5X
---- -- ON ON 8X 266
CP1C3P0
look as appears below.
250 300
--
--
--
CPU Power and Bypass Capacitors
ROM SELECT
66
--
--
--
--
--
183 --
BUS CLOCK
--
MAP "A": PREP
ON -- 6X 200 -- --
216 --
COP Connector
Motorola Confidential Proprietary
-- --
ON
ON
-- ON
Keep near CPU
--
ON
Free Agent Mode
--
ROM LOCATION
--
-- --
-- 4
PM
--
--
BUS MULT
ON
PROGRAM MODE
RS
-- -- ON
PT DATA BUS SIZE
ON Motorola PPMC
-- VITA PPMC
PPMC TYPE
ON
-- ON --ON
200
MULT.
ON --
30
ON
0
--
3X
CP2
-- ON 6.5X
PROGRAM MODE
AM
ON
ON 2X
--
2X
1.5X66 100
i
CLOCK FEEDBACK
Add 1 ns delay (6 inches) to compensate for trace
delay added to SDRAM clock feedback path.
Motorola Confidential Proprietary
Motorola Confidential Proprietary
i
i
i
i
PCI Clamp Voltage
3.3V or 5V depending upon VIO
Motorola Confidential Proprietary
selection (see page 15).
them short.
VITA PPMC Spec Compliance
If not compliant with forthcoming VITA PPMC, install
both resistors.
Must equal exactly 2.5" from connector pin
to MPC107 pin, per specifications.
PCI Clock Trace
PLL Filters
Use 15 mil traces and keep
i
i
Set trace length equal to that of other clocks
CLOCK FEEDBACK
Motorola Confidential Proprietary
and SDRAM control traces plus 1 ns (6 inches).
Clock delay is added only to this feedback path.
SERIES TERMINATION
Keep within 2 cm of MPC107.
Motorola Confidential Proprietary
i
SECTOR PROTECT/UNPROTECT
sector protection. Resistor need not be
Motorola Confidential Proprietary
Apply 12V to activate or override the boot
removed.
i
i
Motorola Confidential Proprietary
in-system programming support.
MPC107 Configuration Logic
Diagnostic PLD
Optional instalation for LED monitoring and
Refer to Book IV, table 144 for details.
i
V(I/O) SELECTION
Select 3.3V or 5V V(I/O) option.
ONE ONLY!
Motorola Confidential Proprietary
i
i
Install oscillator or socket for stand-
STAND ALONE CLOCK
alone operation.
Install jumper to enable on-board
STAND ALONE RESET
reset switch.
Talos PowerPMC Errata Page 1 /3
Motorola Inc.
Unrestricted Distribution Permitted 00 Mar 24
Talos
PowerPMC Errata
Board Revision Level X1
Errata Revision Level A
Copyright 1999 by Motorola Incorporated. All rights reserved.
c
Talos PowerPMC Errata Page 2 /3
Motorola Inc.
Unrestricted Distribution Permitted 00 Mar 24
Revision History
Version Date Changes
A1999 Oct 21 Initial errata.
Talos Errata Page 3 /3
Motorola Inc.
Unrestricted Distribution Permitted 00 Mar 24
Table 1: Summary of Talos Errata
#Type Problem Impact Work-Around Affects Rev
1Design Sector Protection circuitry is incorrect;
attempts to apply +12V (sector protect
enable) would impress +12V on the sys-
tem reset logic.
Second ROM cannot be sector pro-
tected because damage to the board
may occur.
Cut trace fromU5 pin 12. Connect U5 pin
12 to TP “SECPROT”.A
Unity
TALOS UNITY ALTIM VALIS
SP3
Unity X4 (MPPMC824X) Configuration Guide
Revised: 2000 Oct 04
CPU PLL Settings
0 1 2 3 4 Clock Clock Clock
CPUPLL PCI Memory CPU
ñ ñ ñ ñ ñ 33 100 250
ñ ñ
ê
ñ ñ 25 50 100
ñ
ê
ñ ñ ñ 33 33 100
ñ
ê
ê
ñ ñ 33 66 166
ñ
ê
ê
ê
ñ 33 66 200
ê
ñ ñ ñ ñ 33 100 200
ê
ñ ñ
ê
ñ 66 100 200
ê
ñ
ê
ñ ñ 33 66 233
ê
ñ
ê
ê
ñ 33 66 266
ê
ê
ñ ñ ñ 33 83 250
ê
ê
ñ
ê
ñ 66 66 266
ê
ê
ê
ñ ñ 50 75 225
ê
ê
ê
ñ
ê
66 100 250
ñ ñ
ê
ê
X bypass
ñ ñ ñ ñ X off
1
ON
2345678
1
ON
2345678
Hold
PCI
ñ ñ 0.5 - 0.9 ns
ñ
ê
1.3 - 1.7 ns
ê
ñ 2.1 - 2.5 ns
ê
ê
2.9 - 3.3 ns
5 6 Drive
PCI
ê
25 ohms
7
ñ 50 ohms
SYSRST COP resets only PrMC
COP resets system
ê
=1
ñ
=0
M66EN 66 MHz PCI allowed
33 MHz PCI only
ê
=1
ñ
=0
ROMSEL Main ROM selected
Backup ROM selected
ê
=1
ñ
=0
PROGSEL RCS0 selects local flash (boot)
RCS1 selects local flash (prog.)
ê
=1
ñ
=0
AGENT Free agent
Wait for host
ê
=1
ñ
=0
PrMCTYPE MOTSPS PrPMC
VITA PrPMC
ê
=1
ñ
=0
MAPSEL Map “B” / CHRP
Map “A” / PReP
ê
=1
ñ
=0
ROMLOC RCS0 on PMC
RCS0 on PCI
ê
=1
ñ
=0
NAME DEF DESCRIPTION
this product. You’re not really paying attention, are
PRELIMINARY VERSION
Unity
PPMC824X
No warranty, expressed or applied, is made as to the
Motorola Sale/FAEs to obtain the latest information on
PPMC8240
All information is subject to change without notice.
X
*
This schematic is provided for reference purposes only.
4
Digital DNA
*
you, I could write anything here and you’d never notice.
accuracy of the information contained herein. Contact
from Motorola
REV
MPC8240 System Interface; I2C
12 PMC Connectors P1, P2
11 Miscellany; LEDs; Mode Mux
10 UART; Standalone Support
09 Dual Flash ROMs
08 MPC8240 PCI Interface; Power
2.
GND
3.
4.
7.
source component.
All capacitors are SMD0603, in microfarads (uF), +/-20%.
All inductances are in microhenries (uH).
Sheet "-" VertZoneLetter HorizZoneNumber
respective copyright holders. I’ve got good news! That
the most-significant bit), except where industry standards
Motorola and the Motorola logo are registered
System Configuration
Unity
*
X2 98OCT04
apply (i.e. PCI). Little-endian numbering is noted at the
Board impedance is 50-60 ohms.
VCC_2.5V
VCORE
04 Power Supply
trademarks of Motorola. PowerPC is a trademark of
03 Routing and Layout Information
02 Block Diagram
GARY MILLIORN
01 General Information
Part numbers used are for reference only; compatible
Integrated circuits have default connections to power
Cover Page
06
All buses follow big-endian bit numbering order (bit 0 is
MPC8240 Memory; SODIMM Socket
Page
All fuses are self-resetting polyswitch (PTC) devices.
Contents
07
VCC_5V
5.
6.
X4
X1
and ground unless explicitly shown otherwise. Global power
IBM. Other trademarks are the respective property of their
parts may be used; refer to the bill of materials.
purposes only:
13
05
X3 99OCT20
MPC8240 II Support; VITA PPMC changes; More
Flash; I2C; Delete debug headers
X4 00FEB22
PCB Changes only.
Components surrounded by a dashed/crossed-out box are
not to be installed by default; they are for test or manufacturing
DATE CHANGES
connections are:
The sheet-to-sheet cross reference format is:
Unless otherwise specified:
Chip pinout changes; COP tweak.
98APR22
gum you like is going to come back in style. All rights reserved.
All ferrites are Z=50 ohms at 100 MHz.
Original
All resistors are SMD0603, in ohms, 0.08W, +/-5%
Schematic Notes
1.
VCC_3.3V
Configuration
LEDs
200-266 MHz
Motorola MPC8240
<13>
Processor
32-bit 33/66 MHz PCI Bus
32 bit
Boot Flash ROM
<08>
SODIMM
Auxillary ROM
PLL Modes
<05>
Power Supply
Standalone Support
<11>
Clock: 33 MHz
Reset
5V->2.5V Switcher
64-bit 100 MHz Local Bus
<10>
SDRAM
Monitors and Modes
<12>
16-64 MByte
UART
<11>
Board Modes
<07-09>
PMC Connector
PPMC Extensions
<06>
Mot/VITA PMC Mode
P2
Place slide switches in vertical orientation and do not swap PLL config pins.
Place LEDs so they are visible on the top and legends are nearby.
Am29DL323
paths; use two ground-attach vias.
Socket
Place SODIMM socket within 3.5cm of MPC6xx (center-to-center).
Route all control, address and data traces to equal lengths.
Place 820 uF low-ESR capacitors near CPU.
Use split power plane to connect VCC_2.5 from power supply to CPU core.05
SODIMM
12
RAM
ROM
Place VID pulldown resistors in order shown.
Place series termination resistors very near source, < 1.5 cm.
Route terminated traces using equal trace lengths towards SDRAM array.
OVDD
Use short traces throughout.
Serial
13
Keep VCC_2.5 power flowing point-to-point through MOSFETs, inductor, resistor and
output filter capacitors.
Keep MOSFET gate drive lines < 2 cm.
P1
Keep trace from 68 uF low-ESR capacitors within 2 cm of high-side MOSFET (Q2).
Keep VCCA/VCCP attachment within 2 cm of input filter location.
Use split power plane or very heavy traces for power path:
+5V => MOSFET Qx => Inductor Lx =>
Low-Ohm Res. Rx => VCC_2.5 Plane
Surround MPC8240 with bypass caps shown to provide additional ground-return
per the PCI specification.
07 No special restrictions
Reset
LEDs
Route SDRAM_SYNC_OUT => SDRAM_SYNC_IN path to equal longest clock trace.
10
11 No special instructions.
Maximum trace length for PCI signals to MPC8240 is 1.5"
COP
FLASH
Port
iSP
Place PLL filters on bottom of PCB beneath MPC8240
Layout/Routing Instructions
Place bulk capacitance near BGA IVDD and +3.3V ground planes.
Use short heavy traces on PLL filter power.
PCI
STAT
VDD
GARY MILLIORN
06
08
09
i
i
i i
1.95V
O
I
I
I
1.45V
I
III
2.8V
II
O 1.40V
O
I 2.9V
OIO
1.75V
OO I
OI
IO
OO
II
3.2V
O
O
IO
II II
IO
2.4V
O
VID
I
1.50V
O
O O 2.00V
O
O I 3.3V
I
3
O
OI
I
VCC_2.5 OUTPUT
O
I
O
I O
OO
IO
3.5V
I
II
OI
I I 1.70V
O
BULK CAPACITANCE
Distribute around the board.
O
I
IO
I
I
3.4V
O
O
I
3.1V
I
O
O 2.2V
I
3.0V
1
O
O
OI
2.1V
I
OOO
0.00V
Restricts power supplies to specification
limits. Not needed if ramp < 500 uS.
O
2.7V
I
1.90V
I
O
may be programmed from 1.8V to 3.6V.
I
I
I
O
1.30V
2.5V
O
I
O
I
OOO
I
I
VOLTAGE SEQUENCING
O
OI
I
I
2.3V
I
I
O
4
I
0
I
I
O
I
I
O
O
O
O
I
O
O
2
I
IO
VCORE
1.35V
O O 2.6V
II
O
O
I
O
I
1.80V
O
Nominal voltage; actual output
I
I
1.85V
I
OO
1.65V
O
OI
O
VCC_2.5 OUTPUT
I
I
O
O
1.60V
OI
1.55V
O
2.05V
I
MPC824X
O
O
O
I
i
i
i
i
i
0
PM
ON
P66
-
--
NOTE: Connector should be routed to
ON Enable local ROM alias.
RS
C
-
PH0
0.5 - 0.9 ns
1.3 - 1.7 ns
PM PROGRAM MODE
C
SYSTEM RESET
1
--
P3
P4
0
PCI 66 MHz ENABLE
RL ROM LOCATION
ON
PROGRAM MODE
ROM SELECT
0 13 ohm
ON COP can reset target system.
Enable 66 MHz operation
33 MHz only.
33 MHz
-
VITA PPMC
COPonly resets local CPU/MPC107.
ON
P1
P2
-
PCI 66 MHz
ON
Wait for initialization (Peripheral Mode)
66 MHz
83 MHz
8 ohm
look as appears below.
AM
PT
C
C
-
-
- 266 MHz
C
COP Connector
PH1
1
--
--
--
P0
-
DATA BUS SIZE
ROM on PCI Bus
--
PCI Hold
PH1
MAP "A": PREP
ADDRESS MAP SELECT
ON
SR
AG
100 MHz 250 MHz
C
0
RS ROM SELECT
Select alternate ROM
Select normal ROM
P4
C
C
25 MHz
C
Free Agent Mode
AGENT MODE
MAP "B": CHRP
DEFINITION
2.1 - 2.5 ns
2.9 - 3.3 ns
MEMORY DRIVE STRENGTH
D2
-
0
Memory
40 ohm
Normal mode.
D1
PPMC TYPE
AM AGENT MODE
ON
1
- 66 MHz
66 MHz
P0
-- Motorola PPMC
P66
ADDRESS MAP
200 MHz
233 MHz
250 MHz
1
C
P1
ROM on Local Bus
Processor debug access port.
--
C
-
C
C
P2
-
-
PH0
C
PD
RL
AM
PT
P3
C
-
0
-
C
C50 MHz 100 MHzC
-C
1
SR
0
PCI Clock
33 MHz
33 MHz
33 MHz
50 MHz
66 MHz
33 MHz
33 MHz
20 ohm
Memory Clock
1
0
1
1
100 MHz
PCI Bus
100 MHz
Processor
SYSTEM SPEED SETTINGS
166 MHz
200 MHz
200 MHz
PCI HOLD TIME
PCI DRIVE STRENGTH
PD
Bypass
0
C
-
ROM LOCATION
C
CC
Bypass
-
C
--X
C
0
C
-
-
C
33 MHz
C
C- C
-
C
1
C
DEBUG ENABLE
-CC
33 MHz
75 MHz
33 MHz
66 MHz
50 ohm
Bypass
D2 D1
C
250 MHz
100 MHz
Install to enable debug mode.
BUS WIDTH
Install for 32-bit bus mode.
Off
--X
-
66 MHz 66 MHz 266 MHz
-
0
C
C
C
C-
C
25 ohm
66 MHz
100 MHz
-- 225 MHz
-
i
BOARD ID
i
in equal trace lengths. Route from series resistors to
needed to compensate for high speeds or high loads. Refer
destination in equal lengths plus any additional trace length
Route all clock traces from MPC8240 to series resistors
CLOCK TRACE ROUTING
to AN1722/D for details.
i
i
PCI Clock Trace
Must equal exactly 2.5" from connector pin
to MPC824X pin, per specifications.
PCI Clamp Voltage
3.3V or 5V depending upon VIO
selection (see page 15).
i
SECTOR PROTECT/UNPROTECT
Apply 12V to activate or override the boot
removed.
sector protection. Resistor need not be
i
i
Install oscillator or socket for stand-
Install jumper to enable on-board
reset switch.
STAND ALONE RESET
STAND ALONE CLOCK
alone operation.
i
V(I/O) SELECTION
ONE ONLY!
Select 3.3V or 5V V(I/O) option.
Unity Errata Page 1 /3
Motorola Inc.
Unrestricted Distribution Permitted 00 Mar 24
Unity
PowerPMC Errata
Board Revision Level X4
Errata Revision Level B
Copyright 1999 by Motorola Incorporated. All rights reserved.
c
Unity Errata Page 2 /3
Motorola Inc.
Unrestricted Distribution Permitted 00 Mar 24
Revision History
Version Date Changes
A2000 Mar 24 Initial errata.
Unity Errata Page 3 /3
Motorola Inc.
Unrestricted Distribution Permitted 00 Mar 24
Table 1: Summary of Unity Errata
#Type Problem Impact Work-Around Affects Rev
1Design MA11 is not a ROM address pin on the
MPC8240 Cannot access all of Am29DL323
flash devices. Replace with Am29LB800 (1MByte) X4 A
2Design R28 is not properly placed to allow sec-
tor protection of second flash. Cannot use sector protection on
second flash (U4). Lift U4 pin 12 and connect to TP “SPR”. X4 A
3Design If debug mode is enabled (R29
installed), REQ4 will remain low, caus-
ing the arbiter to grant bus. Eventually
this will be detected as a broken master
and the arbiter will disable it.
May reduce performance during
startup for first 100 clock cycles or
so.
Don’t enable debug mode if performance
is important. X4 A
Altimus
TALOS UNITY ALTIM VALIS
SP3
Altimus X3 (MPPMC75x/MPPMC74x0) Configuration Guide
Revised: 2000 Oct 26
1
ON
2345678
1
ON
2345678
MPC75x/74xx PLL
3 2 1 0 Mult. 33 66 83 100
ê ê
ñ ñ byp. 33 66 83 100
ñññ
ê
3X 100 200 250 300
ñ
êêê
3.5X 116 233 292 350
ñ
ê
ñ
ê
4X 133 266 333 400
êêê
ñ4.5X 150 300 372 450
ê ê
ñ
ê
5X 166 330 415 500
ê
ñ ñ
ê
5.5X 183 363 456 550
ê
ñ
ê ê
6X 200 400 500 600
ñ
ê
ñ
ê
6.5X 216 433 540 650
ñ
ê
ñ ñ 7X 233 466 580 700
ê
ñ ñ ñ 7.5X 250 500 622 750
ñ ñ
ê ê
8X 266 528 664 800
ñ ñ ñ ñ 9X 300 600 750 900
MPC107 PLL
3 2 1 0 PCI BUS
ñ ñ ñ ñ 33 33
ñ
ê
ñ ñ 20 40
ê
ñ
ê
ñ33 66
ñ ñ ñ
ê
33 100
ê
ñ ñ
ê
66 120
ñ
ê
ñ
ê
30 120
ñ ñ
ê ê
33 83
ê
ñ
ê ê
66 66
ê ê
ñ ñ bypass
BOARD OPTIONS
NAME SET PCI
SYSRST ñ=0 COP resets MPPMC & system
ê=1 COP resets MPPMC only
M66EN ñ=0 33 MHz PCI only
ê=1 66 MHz PCI allowed
ROMSEL ñ=0 Alternate Flash selected
ê=1 Standard Flash selected
PROGSEL ñ=0 Local flash is programmable
ê=1 Local flash is bootable
AGENT ñ=0 Free agent
ê=1 Wait for host
PMCTYPE ñ=0 MOTSPS MPPMC (arbiter)
ê=1 VITA PrPMC (no arbiter)
MAPSEL ñ=0 Map “A” / PReP
ê=1 Map “B” / CHRP
ROMLOC ñ=0 RCS0 on PCI
ê=1 RCS0 on local bus
Altimus Errata Page 1 /3
Motorola Inc.
Unrestricted Distribution Permitted 00 Nov 28
Altimus
MPPMC75x/MPPMC74xx Errata
Board Revision Level X3
Errata Revision Level A
Copyright 2000 by Motorola Incorporated. All rights reserved.
c
Altimus Errata Page 2 /3
Motorola Inc.
Unrestricted Distribution Permitted 00 Nov 28
Revision History
Version Date Changes
A2000 Oct 23 Initial errata.
Altimus Errata Page 3 /3
Motorola Inc.
Unrestricted Distribution Permitted 00 Nov 28
Table 1: Summary of Altimus Errata
#Type Problem Impact Work-Around Affects Rev
1Design No pullup on CHKSTP_IN. Processor
immediately checkstops. CPU halts. Add pullup between COP header J7 pin 8
and R79 pin 1 (side not connected to J7).
X4: Add 10K pullup to COP
CHKSTP_IN* port.
X3
2CAD OVDD power traces are weak Possible problems w/2.5V I/O. None
X4: Enhance power traces from Micrel
power supply into planes.
X3
3Design No pulldown option on SDMA1 to select
DLL_EXTEND. May not operate at bus speeds
below 50 MHz. Add pulldown to SDMA1 trace.
X4: Add pulldown config. option.
X3
PPMC7410
X3 RELEASE
This schematic is provided for reference purposes only.
All information is subject to change without notice.
No warranty, expressed or applied, is made as to the
accuracy of the information contained herein. Contact
Motorola Sale/FAEs to obtain the latest information on
Altimus
Digital DNA
PPMC750
PPMC755
PPMC7400
this product.
*
from Motorola
*
OVDD VDD_MEM
VCC_PCI_C
trademarks of Motorola. PowerPC is a trademark of
All ferrites are Z=50 ohms at 100 MHz.
Joey Tsai
Board impedance is 55 +/- 5 ohms.
Program Mgr.
PAL logic; I2C; VITA changes.
MPC107: PCI Interface
REV
parts may be used; refer to the bill of materials.
DATE CHANGES
VCORE
Gary Wojcik Ref. Plat. Mgr
Motorola and the Motorola logo are registered 07
5.
1.
MPC75x/MPC74x0 Cache Interface
04
the most-significant bit), except where industry standards
01
7.
by default; they are for test or manufacturing purposes only.
Contents
05
Schematic Notes
PMC Connectors.
Cover Page
L2 Cache SRAM
Technician
source component.
MPC75x/MPC74x0 Power/Options
X2
Components labelled with "No_Stuff" are not to be installed Reserved
Layout
14
6.
All buses follow big-endian bit numbering order (bit 0 is
All resistors are SMD0603, in ohms, 0.08W, +/-5%
All capacitors are SMD0603, in microfarads (uF), +/-20%.
15
11
Altimus
*
All fuses are self-resetting polyswitch (PTC) devices.
Integrated circuits have default connections to power
Configuration Logic / LEDs
Team Altimus
Margarito Trevino
02
connections are:
MPC107: Processor Interface
Part numbers used are for reference only; compatible
17
VCC_5
X3 00MAR22 MPC7410 2.5V IO support.
Analyzer Headers19
4.
3.
Power Supplies and Power Options
03 Routing and Layout Information
VCC_2.5
Cindy Black
18
Designer
The sheet-to-sheet cross reference format is:
06
Tony Saucedo
MPC75x/MPC74x0 System Logic
2.
GND
Initial version
Unless otherwise specified:
Ivan Erickson
Page
12
Sheet "-" VertZoneLetter HorizZoneNumber
Components
09
metal foundry for some shiny steel ingots today! All rights
reserved. No warranty is made, express or implied.
SDRAM ECC support.
Block Diagram
General Information
VCC_3.3
16
and ground unless explicitly shown otherwise. Global power
X1 98DEC01
Gary Milliorn
Documentation
apply (i.e. PCI). Little-endian numbering is noted at the MPC107: Memory Interface
MPC107: System Logic
08
99JUN15 Add pullups; correct cap sizes;
IBM. Other trademarks are the respective property of their
respective copyright holders. Drop by your local Monongahela
All inductances are in microhenries (uH).
SDRAM: 64MB SMT + Parity/ECC
Boot and Secondary Flash
13
10
Backside L2 Cache
5V to 1.5..2.6V Switcher 300-600 MHz
Northbridge
3.3V to 2.5V Linear
1.5A
ECC/Parity
Core Power Supply
Discrete SDRAM
PPMC Extensions
Motorola MCM69P/R737
Memory
Motorola MPC74x0/MPC75x
PMC Connector
32 bit
64/72-bit 100+ MHz Local Bus
1M/2M 100-400 MHz
Programmable
Motorola MPC107
Boot ROM
06-08
15
11-14
16
18
05 05 05
8A
09
MPC107 Power
2.5V OVDD Power
32-bit 33/66 MHz PCI Bus
3.3V to 2.5V Linear
Processor
800 mA
1Mbyte
Use two ground-attach vias.
Keep VCCA/VCCP attachment within 2 cm of input filter location.
or
SRAM
Do not swap order of CPUPLL switch connections.
LAYER 1 SIGNAL1
LAYER 2 POWER: GROUND
MPC107
RC5051
POWER: VCC_3.3, VCORE
LAYER 9
14
Place series termination resistors within 1 cm of corresponding clock/signal pin.
Route SDCLK(1:4)/SDRAM_SYNC_OUT clocks to equal trace lengths SL (including
termination resistor). Then add same delay add additional delay as added to
POWER: VCC_MEM, OVDD, VCC_2.5, VCACHE, VCC_5
HOR
VERT
LAYER 10
16
Place ROMs so as to minimize length of D(0:7), preferably underneath
SDRAM device on D(0:15).
Place SPR testpoint on top of board.
L2A(0:17), L2CE, L2WE, L2ZZ, L2CLKOUTA, L2CLKOUTB are routed as a split ’Y’:
P1
SRAM
Fan
06
HOR
HOR
HOR
Avoid routing traces, especially noisy ones, across CPUPLL bus.
LEDs
06
Am29LV800
SWITCH
ISP
PAL
Use split power plane to connect VCORE from power supply to CPU core.
SWITCH
path to series termination resistor). Then add 1.0ns (~15cm) to all clocks traces for
SDRAM_SYNC_OUT path (SDFEED).
Place CK7 testpoint on top of PCB (accessibility).
SDRAM
FLASH
+5V => MOSFET Qx => Inductor Lx =>
Place 820 uF low-ESR capacitors near CPU.
CDATA(0:71) are routed point-to-point:
Surround CPU with bypass caps to provide additional ground-return paths.
MCM69(P/R)737
Avoid routing traces, especially noisy ones, across CPUPLL bus.
MPC7400
LT1118
SIGNAL5
LAYER 8
Keep trace lengths short (<3 cm) and equalized for all traces.
Place two bypass caps per device.
08
See ’07’ for routing details.
Place adjacent to CPU with 5mm clearance for clip-on CPU heatsink.
09
Place VREF supply local to SRAM.
Route CPU_CLK(0:2) clocks to equal trace lengths SL (including path to series
Place series termination resistors within 1 cm of corresponding clock pin.
11
MICTOR MICTOR
MICTOR MICTOR
17
Place LEDs together on edge of board with visible labels.
18
Place VCC_PCI_C option resistors adjacent.
LSIG
Trace length for L2SYNC_OUT to L2SYNC_IN feedback path (including the resistor)
must equal other clocks (L).
Keep MOSFET gate drive lines < 2 cm.
Keep AVDD/L2AVDD filters near CPU. Use shortest possible traces.
Use split power plane or very heavy traces for power path:
P2
MICTOR
MPC75x
Keep trace from 680 uF low-ESR capacitors within 2 cm of high-side MOSFET (Q2).
POWER: GROUND
VERT
LAYER 11
.062
SIG
B2
B1
output hold time adjust. See also CPU_CLK extra delay.
ASIG
MIC2179
Keep CKO testpoint on top of board for accessibility.
07
Trace lengths must be equal, such that A+B1 = A + B2 = L for all cache signals.
All L2 cache signals should have the shortest path possible. Trace lengths should
13
Keep AVDD/LAVDD filters near CPU. Use shortest possible traces.
Place Lt1118 power supply and bypass caps beneath MPC107 in center cavity.
Use isolated/split power plane for MPC107 VDD power (VCC_2.5).
Layout/Routing Instructions
Connect VCC_PCI_C (PCI Clamp) using heavy trace.
be equalized.
SIG
SIG
15
Am29LV800
FLASH
SDRAM
SDRAM
SDRAM
SDRAM
MCM69(P/R)737
COP
LAYER 3 SIGNAL2
LAYER 4 SIGNAL3
LAYER 5
LAYER 6 SIGNAL4
LAYER 7
Low-Ohm Res. Rx => VCORE Plane
SIGNAL6
LAYER 12
SIGNAL7
VERT
VERT
SIGNAL8
i
i
i
ii
i
i
i
i
IOOI 3.2VI
IIII
2.4VIO
OOOI 1.30V
OII 2.6V
O1.70VIIIO
OI
II
OO IO
Fansink Power Connector.
OI 3.0VOIIOO
O
OOO 2.00VOO
O1.45V
I2.7V
VID VCORE12034
III 2.5V
the top of the PCB for additional thermal
I
Distribute around the board.
MPC107 CORE POWER
dissipation.
1.65VOOOI
MPC7400
MPC750R
MPC750A
VCORE OUTPUT
may be programmed from 1.8V to 3.6V.
O1.75V
OI
OII 2.2VOII
IO
O
BULK CAPACITANCE
OO 1.95VIO
O1.90VIOI
MPC755IO
OI
OOOII 2.8VI
0.00V
2.9VI
3.1V Trimmable, nominally 2.5V, or connect to
3.3V power.
CACHE I/O POWER
Set to 2.5V (nominal) or 3.3V
CACHE POWER
Set to 2.5V (nominal) or 3.3V.
OVDD POWER
Low-power regulator supplies +2.5V to the
O
III
Programmable CPU core voltage;
VCORE OUTPUT
II
3.3VIOOOI 3.4V
II 2.3VO
I3.5V
1.35V
O1.85VOIOO
2.05VOOOOO
OIO 1.60V
OIO 1.50VIOI
IIOI
O
I
IO 1.55VI
OOIIO
I
Add 2-3 cm^2 to the ground plane area on
MPC107 core logic, or can connect to OVDD.
IIOIO 1.40VOIII
II
Route IFB and VFB traces paired
OOO 1.80VOII
OOIO
IO
O
I2.1V
KELVIN CONNECTION
I
i
3.3V
L2VSEL
GND
HRESET*
OVDD
L2OVDD
1.8V
2.5V
3.3V
2.5V
OVDD L2OVDD SELECTION
BVSEL
GND
HRESET*
OVDD
OVDD
1.8V
i
i
L2 Clocks
1. Route L2 clocks to equal lengths.
2. Route CLKOUTA/B as a differential pair.
Place <1 cm from pin
PLL/L2 DLL Filters
i
i
i
i
i
CPU PLL SETTINGS
PT
AM
CPU Power and Bypass Capacitors
look as appears below.
NOTE: Connector should be routed to
Keep near CPU
COP CONNECTOR
XP0
XP1
XP2
RL
XP3
CP0
See Configuration Guide
MPC107 PLL SETTINGS
See Configuration Guide
BOARD OPTIONS SETTINGS
See Configuration Guide
Processor debug access port.
CP1
CP2
CP3
TS
PM
SR
P66
AG
i
69P737 SE3
Install for 69P737 to control
SE3 properly.
Motorola Confidential Proprietary
i i
i
ID=50
CPU Clock Delay
1. Route CPU clocks to equal lengths.
2. ADD same extra trace length as for SDFEED.
Board ID I2C SDRAM CONFIG I2C
ID=57
i
i
i
Route aux-clock to connector pin.
PCI Clamp Voltage
3.3V or 5V depending upon VIO
PCI Clock Trace
PLL Filters
Use 15 mil traces and keep
them short.
selection (see page 15).
to MPC8240 pin, per specifications.
Must equal exactly 2.5" from connector pin
i
SDRAM CLOCK ROUTING
1. Keep MPC107 STERM trace length < 2cm.
2. Route SDCLK1:4 plus SDFEED to equal lengths.
3. Add 15cm (~1ns) ADDITIONAL delay to SDFEED.
i
i
sector protection. Resistor need not be
SECTOR PROTECT/UNPROTECT
removed.
NOTE:
The flash is little endian, so the bit numbering
is reversed from normal PowerPC standards.
Apply 12V to activate or override the boot
i
MPC107 Configuration Logic
Refer to Book IV, table 144 for details.
i
V(I/O) SELECTION
Select 3.3V or 5V V(I/O) option.
ONE ONLY!
Valis
TALOS UNITY ALTIM VALIS
SP3
Valis X1 (MPPMC7450) Configuration Guide
Revised: 2001 Feb 08
1
ON
2345678
1
ON
2345678
MPC7450 PLL
1 2 3 4 Mult. 66 83 100 133
ê
ñ
ê ê
2X 266
ê
ñ ñ
ê
2.5X 208 250 333
ñ
êêê
3X 200 250 300 400
ñññ
ê
3.5X 233 292 350 466
ñ
ê
ñ
ê
4X 266 333 400 532
ê
ñ ñ ñ 4.5X 300 375 450 600
ñ
ê
ñ ñ 5X 333 416 500 666
ñ
ê ê
ñ5.5X 366 458 550 733
ñ ñ
ê
ñ6X 400 500 600 800
ê
ñ
ê
ñ6.5X 433 542 650 866
ê ê
ñ
ê
7X 466 584 700 933
êêê
ñ7.5X 500 625 750 1000
ñ ñ
ê ê
8X 533 666 800 1066
BOARD OPTIONS
NAME SET PCI
SYSRST ñ=1 COP resets MPPMC only
ê=0 COP resets system
M66EN ñ=1 66 MHz PCI allowed
ê=0 33 MHz PCI only
ROMSEL ñ=1 Standard Flash selected
ê=0 Alternate Flash selected
PROGSEL ñ=1 Local flash is bootable
ê=0 Local flash is programmable
AGENT ñ=1 Wait for host
ê=0 Free agent
PMCTYPE ñ=1 VITA PrPMC (no arbiter)
ê=0 MOT MPPMC (arbiter)
MAPSEL ñ=1 Map “B” / CHRP
ê=0 Map “A” / PReP
ROMLOC ñ=1 RCS0 on local bus
ê=0 RCS0 on PCI
MPC107 PLL
0 1 2 3 PCI BUS
ññññ 33 33
ñ ñ
ê
ñ20 40
ñ
ê
ñ
ê
33 66
ê
ñññ 33 100
ê
ñ ñ
ê
66 120
ê
ñ
ê
ñ30 120
ê ê
ñ ñ 33 83
ê ê
ñ
ê
66 66
ñ ñ
ê ê
bypass
1
ON
2345678
DEFAULT=
1
ON
2345678
DEFAULT=
Valis Errata Page 1 /12
Motorola Inc.
Unrestricted Distribution Permitted 01 Feb 02
Valis
MPPMC7450 Board Errata
Board Revision Level X1
Errata Revision Level A
Copyright 2000 by Motorola Incorporated. All rights reserved.
c
Valis Errata Page 2 /12
Motorola Inc.
Unrestricted Distribution Permitted 01 Feb 02
Revision History
Version Date Changes
A2000 Aug 28 Initial errata.
2001 Feb 02 Added #25-34.
Valis Errata Page 3 /12
Motorola Inc.
Unrestricted Distribution Permitted 01 Feb 02
Table 1: Summary of Valis Errata
#Type Problem Impact Work-Around Affects Rev
1Layout C9 should attach directly to plane,
instead uses a trace. Poor transient response; may
increase possibility of failure. None.
X2: Move cap or plane so direct attach-
ment is possible.
X1
2?BA/Package(?) added useless ‘1’ to LED
legends. Confusing, hard to read, wastes
precious space. None.
X2: Either find way to eliminate or go
back to using explicit legends.
X1
3Layout SW1/SW2 geometry is backwards. Pin 1
should be in the upper left hand corner,
same as all ICs. Instead, pin 1 is upper
right.
Configuration switches work back-
wards. None.
X2: Fix geometry.
X1
4Layout Q3 geometry or silkscreen is backwards. Power supply inoperative. Install Q3 opposite of silkscreen image.
X2: Fix geometry.
X1
5Design Power supply not configured for V’ger.
V’ger is targeted for 1.8V core. CPU will not run. Code for 1.8V is “00101”. Move R45 to
R19. Add 0 ohm resistor (or wire) to
R20.
X2: Update no_stuff options.
Add p/s code table to schematics.
X1
6Design R57 should not be installed. OVDD shorted. Remove R57.
X2: Add no_stuff option to R57.
X1
7Design BVSEL options incorrect; 2.5V I/O for
CPU (OVDD) not selected. L3 will not work. Install 0-ohm resistor (or wire) at R16.
X2: Add 10K pullup to BVSEL. Remove
“no_stuff” attribute from R16.
X1
8Design L3VSEL options incorrect; 1.8V I/O for
L3 (L3OVDD) not selected. L3 will not work. Install 0-ohm resistor (or wire) at R17.
X2: Add 10K pullup to L3VSEL. Remove
“no_stuff” attribute from R17.
X1
Valis Errata Page 4 /12
Motorola Inc.
Unrestricted Distribution Permitted 01 Feb 02
9Design L3 IO and core power connections
wrong. L3 will not work. Rewire as shown on detail page.
X2: Swap VCACHE and VCACHEIO
connections.
X1
10 Design Pins 1, 2 & 3 of U16 should be
grounded. U16 has the same address as
U15, so neither are useable.
I2C information cannot be read. 1. Lift U16 pins 1, 2, and 3.
2. Connect lifted pins 1, 2, and 3 to U16
pin 4.
X2: Ground pins 1, 2, and 3.
X1
11 Layout CKO and CK1 pins not on top of board. Hard to debug. None.
X2: Move to top layer.
X1
12 Mech C67 too tall for heatsink. Interferes with mechanical place-
ment. Mill out area on heatsink.
X2: Move to bottom layer or change com-
ponent.
X1
13 Design Pullups should be added for BVSEL,
L2VSEL, since V’ger does not have
internal pullups.
None, currently only 2.5V I/O sup-
ported. None.
X2: Add pullups.
X1
14 Design COP_HRST* is connected directly to
CPU, violating I/O levels and eliminat-
ing reset path.
Can’t reset board; I/O damage with
COP. Rewire as shown on detail page.
X2: COP_HRST* goes to LVT16244 for
isolation, CPU_HRST* drives CPU
HRST*.
X1
15 Design Inductor is current limited; power supply
cannot start up quickly, or at all. Power supply inoperative. Remove SMD inductor. Attach toroid
inductor by bending leads to attach to
SMT pads.
X2: Use through-hold toroid instead of
SMD.
X1
Table 1: Summary of Valis Errata
#Type Problem Impact Work-Around Affects Rev
Valis Errata Page 5 /12
Motorola Inc.
Unrestricted Distribution Permitted 01 Feb 02
16 Layout MOSFET Q2 ground lead attachment
too puny. Power supply problems. 1. Refer to Errata #34 which removes C25
2. Connect minimum 20 gauge insulated
wire from C25 ground hole (round pad)
to Q2 pin S (nearest pin).
X2: More vias! More vias!
X1
17 Design No pullup on CHKSTP_IN. Processor
immediately checkstops. CPU halts. Add pullup between COP header J7 pin 8
and R79 pin 1 (side not connected to J7).
X2: Add 10K pullup to COP
CHKSTP_IN* port.
X1
18 Debug No pullups on some signals such as
TBST* annoys some logic analyzer dis-
assemblers.
Debugging somewhat confusing. None.
X2: Add 10K pullups to GBL*, CI*, WT*,
TS*, TBST*, TSIZ.
X1
19 Design/
Package Sense resistor should be 0.0028, not
0.028 CPU core voltage wrong. Change R55 to correct component or use 3
inches of 20 gauge solid wire.
X2: Change component value.
X1
20 Improve Add bypass caps to V’ger routing chan-
nels. None. None.
X2: Add or relocate bypass caps to
directly under V’ger.
X1
21 Improve Add fan sink header. None None.
X2: Add fan sink power connector (3pin
Berg).
X1
22 Improve PLL_TEST is actually a PLL configura-
tion bit. Hard to configure for higher
(>=9X) PLL multipliers. None.
X2: Change M66EN to non-pop resistor
and use for PLL_CFG(4) (aka
PLL_TEST).
X1
Table 1: Summary of Valis Errata
#Type Problem Impact Work-Around Affects Rev
Valis Errata Page 6 /12
Motorola Inc.
Unrestricted Distribution Permitted 01 Feb 02
23 Design The DQM bits are scrambled; memory
cannot work in byte-writable mode. Cannot use memory. Either:
A. Configure memory to operate in read
-modify-write (RMW) mode, so that all
DQM signals are always used;
or:B. Rewire the DQM signals as shown
on the detail page.
X2: Correct order of DQM signals.
X1
24 Improve Add option to select BIST using
CHKS*. None. None.
X2: Reallocate switch to BIST or use
resistor.
X1
25 Design No pullup on AP[0]. Address parity may not work. None.
X2: Pullup AP[0].
X1
26 Design No pullup on CHKS*. Might enter checker mode and fail
to run. 1. Connect 4.7K resistor to CHK1 pad.
2. Connect wire from resistor to RN3/RN4
center pins.
X2: Provide ability to pullup CHKS*,
assert with HRESET*, or pulldown.
X1
27 Design No pullups on SHD0/SHD1 pins. Might cause snoop failures. 1. Connect two 4.7K resistors to SH1 and
SH2 pads.
2. Connect wires from resistor to RN3/
RN4 center pins.
X2: Provide pullups on SHD0* and
SHD1*.
X1
28 Design GBL* requires strong pullup. Unknown, but strongly recom-
mended. 1. TBD
X2: Provide 1K discrete pullup on GBL*.
X1
Table 1: Summary of Valis Errata
#Type Problem Impact Work-Around Affects Rev
Valis Errata Page 7 /12
Motorola Inc.
Unrestricted Distribution Permitted 01 Feb 02
29 Layout Q4 trace needs to be thicker. Unknown. 1. None.
X2: Enhance trace thickness on gate (G),
use multiple power vias (minimum 3 to
5) on drain (D) and source (S).
X1
30 Layout Gate drive for Q2 needs to be shorter. Slower, less performance/heat. 1. None.
X2: Route gate drive to left through pins
instead of to right.
X1
31 Design Default drive strength for MPC107
incorrect. May fail? 1. Populate R4 and R6 (470 ohm).
X2: Remove “No_Stuff” on R4 and R6.
X1
32 Design A[0:3] should be pulled down. Unknown. 1. None
X2: Add pulldown to A[0:3].
X1
33 Design PMON_IN should be pulled down. Performance monitor cannot run. 1. None
X2: Add pulldown to A[0:3].
X1
34 Layout C21/C25/C29 placement. C25 interferes
with heatsink attachment. Cannot/hard to install heatsink.
Capacitors less effective for noise
filtering.
1. Remove C25. Change BOM to ‘no-
stuff’.
X2: Relocate. Revisit capacitor placement
to put C21, C29, C25 near CPU+SRAM.
X1
Table 1: Summary of Valis Errata
#Type Problem Impact Work-Around Affects Rev
Valis Errata Page 8 /12
Motorola Inc.
Unrestricted Distribution Permitted 01 Feb 02
Errata 9: L3 Cache Power Connections
OVERVIEW
The L3Cache power and IO powers are swapped.
WORKAROUND
The work-around is to rewire the power using heavy (22 ga.) wire.
1. Connect a w ire to the top of R59 (between the caps on the bottom of the board) to Q4
pin 3 (left gull-wing pin). This connects VCACHEIO to VCC_1.8.
2. Connect a w ire to the left of R56 (above the CPU) to R59 pin 2. This connects
VCACHE to VCC_2.5. Avoid running wire over the CPU -- there will be a heatsink
there..
R59
Q4
R56
Valis Errata Page 9 /12
Motorola Inc.
Unrestricted Distribution Permitted 01 Feb 02
Errata 14: Reset Connections
OVERVIEW
The system reset connections are miswired.
WORKAROUND
1. On the front of the board, cut the indicated trace
2. On the back of the board, connect a trace between U17 pin 20 and the indicated via.
RN18
U13U10
RN7
R26
R25
DQM7
DQM6
DQM1
C50
DQM0
DQM1
DQM0
U17
20
Valis Errata Page 10 /12
Motorola Inc.
Unrestricted Distribution Permitted 01 Feb 02
Errata 23: SDRAM DQM Connections
OVERVIEW
The SDRAM DQM connections are scrambled.
WORKAROUND
A. Use RMW mode, in which case DQM ordering is irrelevant.
B. Rewire the DQM signals, as follows:
1.Cut traces DQM(1:0) exiting RN13 pins 1 and 2 on the top of the PCB.
2. Connect RN13 pin 2 to U12 pin 15.
3. Connect RN13 pin 1 to via between traces connected to RN11 pins 5 and 6.
.
4. Cut traces DQM(7:6) exiting RN12 pins 3 and 4 on the bottom of the PCB.
5. Connect RN12 pin 3 to via under end of old DQM7 trace.
6. Connect RN12 pin 2 to via at bottom end of U10 as shown.
U12
U9U11
DQM1
DQM1
DQM6
DQM7
15
DQM7
15
RN13
RN11
DQM6
UTDQM6
DQM6
UTDQM7
UTDQM2
UTDQM3
RN15
Valis Errata Page 11 /12
Motorola Inc.
Unrestricted Distribution Permitted 01 Feb 02
U13U10
R26
R25
DQM7
DQM6
UTDQM1
U3
R23
R24
DQM0
C50
DQM0
DQM0
DQM1
UTDQM0
RN12
1
1
UTDQM5
UTDQM4
Valis Errata Page 12 /12
Motorola Inc.
Unrestricted Distribution Permitted 01 Feb 02
Errata 28: GBL* Pullup
OVERVIEW
The GBL* signal requires a strong pullup.
WORKAROUND
1.Connect 470 ohm resistor to RN3 pin 10 on bottom of board beneath MPC107
(U14).
2. Connect wire from resistor to via shown .
.
C83
CK1
RN3
TO1
*
from Motorola
*
this product.
This schematic is provided for reference purposes only.
All information is subject to change without notice.
No warranty, expressed or applied, is made as to the
accuracy of the information contained herein. Contact
Motorola Sale/FAEs to obtain the latest information on
V a l i s
Digital DNA
MPC7450 (V’ger)
V a l i s
*
All fuses are self-resetting polyswitch (PTC) devices.
Integrated circuits have default connections to power
The sheet-to-sheet cross reference format is:
Configuration Logic / LEDs
Team Altimus
Margarito Trevino
2.
GND
07
02
connections are:
MPC107: Processor Interface12
Sheet "-" VertZoneLetter HorizZoneNumber
PMC Connector
Contents
05
Schematic Notes
PMC Connectors.
Cover Page
4.
All resistors are SMD0603, in ohms, 0.08W, +/-5%
MPC7450 Power/Options
Gary Milliorn
All buses follow big-endian bit numbering order (bit 0 is
Components with the visible property "NO STUFF" are
Analyzer Headers
Layout
14 MPC107: Memory Interface
Power Supply
VCACHE_IO
03 Routing and Layout Information
Cindy Black
reserved. No warranty is made, express or implied.
11
Joey Tsai
Board impedance is 55 +/- 5 ohms.
Program Mgr.
purposes only.
04
respective copyright holders. There is no spoon. All rights
All inductances are in microhenries (uH).
18
Designer
SDRAM SODIMM Socket
Local Boot ROM
VCORE MPC7450 System Logic
13
Page
MPC107: PCI Interface
REV
parts may be used; refer to the bill of materials.
19
01
7.
not to be installed by default; they are for test or manufacturing
VCC_3.3
16
and ground unless explicitly shown otherwise. Global power
DATE CHANGES
Gary Wojcik Ref. Plat. Mgr
Motorola and the Motorola logo are registered
5.
1.
MPC7450 Cache Interface
Block Diagram
General Information
X1 00MAY01
L2 Cache SRAM
Technician
source component.
Documentation
apply (i.e. PCI). Little-endian numbering is noted at the
Reserved
MPC107: System Logic
08
trademarks of Motorola. PowerPC is a trademark of
All ferrites are Z=50 ohms at 100 MHz.
IBM. Other trademarks are the respective property of their
Part numbers used are for reference only; compatible
17
VCC_5 06
Tony Saucedo
Initial version
Unless otherwise specified:
Ivan Erickson
Components
09
the most-significant bit), except where industry standards
10
VCC_2.5
3.
All capacitors are SMD0603, in microfarads (uF), +/-20%.
15
20
VCACHE
6.
OVDD
VCC_12
Memory
(2) 1MByte Flash Motorola MPC107
Power Supplies
Motorola MCM64E836
<15>
<09>
<16>
Logic Analyzer
Boot ROM
<06-08>
<20>
Mictor Headers 32 bit
64/72-bit 133 MHz Local Bus
Northbridge
PMC Connector
Motorola MPC7450
SDRAM Components
<18-19>
Processor
<05>
1M 100-300 MHz
Multiple outputs
ECC/Parity
PPMC Extensions
Backside L2 Cache
Programmable VDD 500-800 MHz
32-bit 33/66 MHz PCI Bus
<11-14>
Do not swap order of MPC107 PLL switch connections.
L3RU
MICTOR MICTOR
SWITCH
ISP
Surround MPC107 with bypass caps to provide additional ground-return paths.
MPC7450
V’ger
Place cache SRAMs within 3.5cm of MPC750 (center-to-center).
12
Place components approximately as shown on this page.
SRAM
Route all control, address and data traces to equal lengths.
SDRAM_SYNCIN path.
MICTOR MICTOR
Keep relative distances short and use heavy traces for everything.
10
MICTOR
SDRAM (5x)
Use two ground-attach vias.
15
14
Do not swap order of PLL switch connections.
Surround each component with bypass capacitors.
P3
Avoid routing traces, especially noisy ones, across CPUPLL bus.
05
Use two ground-attach vias.
Route SDRAM clocks to equal lengths, including SDRAM_SYNCOUT to
06
Am29LV800
CS51313
PNP
LVT
SRAM
Keep AVDD/LAVDD filters near MPC107. Use heavy, short traces from filter
LT1118
Avoid routing traces, especially noisy ones, across CPUPLL bus.
08
per the PCI specification.
18
L3RL
L3X
pin 16 are on opposite corners).
07
MCM64E836
to pins.
Place bulk capacitance near BGA IVDD and +3.3V ground planes.
PCI clock input must be 2.5" (per specification).
13
Layout/Routing Instructions
16
Insure that COP pin numbering matches view as shown on schematic (i.e. pin 1 and
Route all groups to equal lengths.
Place series termination resistors very near source (MPC107), < 2cm.
FLASH (2x)
09
Keep data bus length for ROM short.
11
MPC107
17
Connect VCC_PCI_C (PCI Clamp) using heavy trace.
Keep AVDD filter near CPU.
PAL
AUX POWER
FET
FET
358
LEDs
Surround MPC7450 with bypass caps to provide additional ground-return paths.
I2C
I2C
QS3384
SWITCH
MCM64E836
Avoid routing traces, especially noisy ones, across MPC107 PLL bus.
COP
19
20
Maximum trace length for PCI signals to MPC107 is 1.5"
P1
Use thick trace (>=12mil) for VREF, 24mil for VCACHE.
FET
All power connections are to be made to a plane.
P2
Place COP connector in I/O area. Proximity to CPU is not a high priority.
i
i
i
VCORE OUTPUT
3A MAX
18A MAX
1A MAX
V’ger
i
Place <1 cm from pin
CPU PLL Filters
i
i
i
CP2
SR
AG
XP2
PM
P66
BOARD OPTIONS
XP3
MPC7450/MPC107 PLL SETTINGS
CP1
TS
Keep near CPU
See Configuration Guide
PT
CP0
XP0
XP1
CP3
ROM LOCATION
RL
CPU Power and Bypass Capacitors
AM
i
i i
2. ADD same extra trace length as for SDFEED.
Board ID I2C
ID=57 SDRAM Configuration ID I2C
ID=50
CPU Clock Delay
1. Route CPU clocks to equal lengths.
i
i
i
Must equal exactly 2.5" from connector pin
to MPC8240 pin, per specifications.
Route aux-clock to connector pin.
PCI Clamp Voltage
3.3V or 5V depending upon VIO
PCI Clock Trace
PLL Filters
Use 15 mil traces and keep
them short.
selection (see page 15).
i
3. Add 15cm (~1ns) ADDITIONAL delay to SDFEED.
SDRAM CLOCK ROUTING
1. Keep MPC107 STERM trace length < 2cm.
2. Route SDCLK1:4 plus SDFEED to equal lengths.
i
SECTOR PROTECT/UNPROTECT
Apply 12V to activate or override the boot
sector protection.
i
MPC107 Configuration Logic
Refer to Book IV, table 144 for details.
i
Select 3.3V or 5V V(I/O) option.
ONE ONLY!
V(I/O) SELECTION
i
64-bit PMC Header
Used for additional power and ground only.
