AN32180A-VB - PANASONIC ELECTRONIC COMPONENTS

AN32180A

Page 1 of 49

Product Standards

FEATURES DESCRIPTION

4 x 4 Dots Matrix LED Driver LSI

AN32180A is a 16 Dots Matrix LED Driver.

It can drive up to 4 channels of RGB LEDs.

4 4 LED Matrix Driver (Total LED that can be driven = 16)

LED Selectable Maximum Current

LED Music Synchronizing Function

I2C interface (Standard Mode, Fast Mode and Fast Mode

Plus) (4 Slave address selectable)

16 pin Plastic Quad Flat Non-leaded Package (QFN Type)

APPLICATIONS

VCC

Battery

GND1

GND2

SDA

NRST

39 k 

SCL

SLAVSEL

IREF

CLKIO

LDO

1.0 F

CPU I/F

VDD

Mobile Phone

Smart Phone

PCs

Game Consoles

Home Appliances etc.

TYPICAL APPLICATION

Note)

This application circuit is an example. The operation of the mass production set is not guaranteed. Customers shall perform

enough evaluation and verification on the design of mass production set. Customers shall be fully responsible for the

incorporation of the above application circuit and information in the design of the equipment.

http://www.semicon.panasonic.co.jp/en/

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Revision.

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Revised

2013-03-22

AN32180A

Page 2 of 49

Product Standards

CONTENTS

FEATURES ………………………………………………………………………………… 1

DESCRIPTION ……..……………………………………………………………………… 1

APPLICATIONS …………………………………………………………………………… 1

TYPICAL APPLICATION ………………………………………………………………… 1

ABSOLUTE MAXIMUM RATINGS ……………………………………………………… 3

POWER DISSIPATION RATING ………………………………………………………… 3

RECOMMENDED OPERATING CONDITIONS ……………………………………….. 4

ELECTRICAL CHARACTERISTICS .…………………………………………………… 5

PIN CONFIGURATION ……………………………………………………………………11

PIN FUNCTIONS ..………………………………………………………………………… 11

FUNCTIONAL BLOCK DIAGRAM ………………………………………………………12

OPERATION ….…………………………………………………………………………… 13

PACKAGE INFORMATION ………………………………………………………………48

IMPORTANT NOTICE .…………………………………………………………………… 49

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Product Standards

ABSOLUTE MAXIMUM RATINGS

*2C– 30 to + 85Topr

Operating ambience temperature

*2C– 30 to + 125Tj

Operating junction temperature

*2C–55to+125Tstg

Storage temperature

—V– 0.3 to 6.0

SLAVSEL, SCL, SDA,

CLKIO, NRST

Input Voltage Range

Output Voltage Range —V– 0.3 to 6.0

IREF, LDO, CLKIO,

Z1, Z2, Z3, Z4, Z5

—kV2.0HBMESD

*1V6.0VDDMAX

NoteUnitRatingSymbolParameter

*1V6.0VCCMAX

Supply voltage

POWER DISSIPATION RATING

Note) For the actual usage, please refer to the PD-Ta characteristics diagram in the package specification, follow the power

supply voltage, load and ambient temperature conditions to ensure that there is enough margin and the thermal design

does not exceed the allowable value.

Note) This product may sustain permanent damage if subjected to conditions higher than the above stated absolute maximum

rating. This rating is the maximum rating and device operating at this range is not guaranteeable as it is higher than our

stated recommended operating range. When subjected under the absolute maximum rating for a long time, the reliability

of the product may be affected.

*1: VCCMAX = VCC, VDDMAX = VDD.

The values under the condition not exceeding the above absolute maximum ratings and the power dissipation.

*2: Except for operating ambient temperature, operating junction temperature and storage temperature,

all ratings are for Ta = 25C.

0.212 W0.529 W189.2 C /W

16 pin Plastic Quad Flat Non-leaded package (QFN Type)

PD(Ta=85 C)PD(Ta=25 C)JA

PACKAGE

CAUTION

Although this LSI has built-in ESD protection circuit, it may still sustain permanent damage if not handled

properly. Therefore, proper ESD precautions are recommended to avoid electrostatic damage to the

MOS gates

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Product Standards

RECOMMENDED OPERATING CONDITIONS

*1VVDD + 0.3—–0.3

SLAVSEL, SCL, SDA,

CLKIO

Input Voltage Range

*1VVCC + 0.3—–0.3NRST

*1VVCC + 0.3—–0.3

IREF, LDO, CLKIO,

Z1, Z2, Z3, Z4, Z5

Output Voltage Range

—V

5.55.03.1VCC

5.0

Typ.

1.7

Min.

—V

5.5VDD

Supply voltage range

NoteUnitMax.SymbolParameter

Note) Voltage values, unless otherwise specified, are with respect to GND. GND is voltage for GND.

VCC is voltage for VCC. VDD is voltage for VDD.

Do not apply external currents or voltages to any pin not specifically mentioned.

*1 : (VCC + 0.3 ) V must not exceed 6 V. (VDD + 0.3) V must not exceed 6 V.

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Product Standards

V2.952.852.75ILDO = – 10 AVL1Output voltage (1)

Constant Voltage Source (LDO)

Internal Oscillator

—A500250—NRST = HighICC2

Circuit Current (2)

OFF Mode

SCAN Switch

—MHz2.882.401.92VCC = 3.6 VFDC1Oscillation Frequency

V2.952.852.75ILDO = –15mAVL2Output voltage (2)

—31.5—

VCC = 3.6 V

IZ1~Z4 = – 20 mA

RSCANSwitch On Resistance

—V

VDD

+ 0.3

—

0.7 

VDD

High Level Acknowledged

Voltage (At External CLK

Input Mode)

VIH1High Level Input Voltage Range

CLKIO

—V

VDD

+ 0.3

—

0.8 

VDD

ICLKIO = – 1 mA

(At Internal CLK Output

Mode)

VOH1High Level Output Voltage

—V

0.3 

VDD

—–0.3

Low Level Acknowledged

Voltage (At External CLK

Input Mode)

VIL1Low Level Input Voltage Range

—V

0.2 

VDD

—–0.3

ICLKIO = 1 mA

(At Internal CLK Output

Mode)

VOL1Low Level Output Voltage

—A10–1

VCC = 5.5 V

VCLKIO = 5.5 V

IIH1High Level input Current

—A10–1

VCC = 5.5 V

VCLKIO = 0 V

IIL1Low Level input Current

—A10—NRST = 0 VICC1

Circuit Current (1)

OFF Mode

Circuit Current

Limits

Typ Unit

Max Note

Min

Condition SymbolParameter

ELECTRICAL CHARACTERISTICS

VCC = 3.6 V, VDD = 1.85 V

Note) Operating Ambient Temperature, Ta= 25 C 2 C, unless specifically mentioned

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Product Standards

—%5—–5

LED Current Setting = 20.2 mA

IMAX = [011], BRTXX = [1010]

Difference of Z1 to 5 current from

the average current value

IMXCHChannel Difference

—A1—–1

VCC = 5.5 V, VDD = 5.5 V

OFF Mode

VZ1~Z5 = 0 V

IMXOFF2OFF Mode Leak Current2

*1 mA21.220.219.2

LED Current Setting = 20.2 mA

IMAX = [011], BRTXX = [1010]

VZ1~Z5 = 1 V

IMX1Output Current (1)

Constant Current Source (Matrix LED)

—A1—–1

VCC = 5.5 V, VDD = 5.5 V

OFF Mode

VZ1~Z5 = 5.5 V

IMXOFF1OFF Mode Leak Current1

—mA420

DAC Constant Current Mode

LED Current Setting = 20.2 mA

IMAX = [011], BRTXX = [1010]

VZ1~Z5 = 1 V, IDAC1 = IZ1~Z5

LED Current Setting = 22 mA

IMAX = [011], BRTXX = [1011]

VZ1~Z5 = 1 V, IDAC2 = IZ1~Z5

DACSTEP = IDAC2 – IDAC1

DACSTEPDAC Current Step

Voltage at which LED driver can keep constant current value

—V——0.4

LED Current Setting = 20.2 mA

IMAX = [011], BRTXX = [1010]

Voltage at which LED Current

change within 5 % compared

with LED Current of pin voltage =

0.5 V.

VLD2LED Driver Voltage

Limits

Typ Unit

Max Note

Min

Condition SymbolParameter

ELECTRICAL CHARACTERISTICS (continued)

VCC = 3.6 V, VDD = 1.85 V

Note) Operating Ambient Temperature, Ta= 25 C 2 C, unless specifically mentioned

Note) * 1: This is allowable value when recommended parts (ERJ2RHD393X) are used for the terminal IREF.

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Product Standards

—A10–1

VCC = 5.5 V

VSLAVSEL = 0 V

IIL2Low Level Input Current

—A10–1

VCC = 5.5 V

VSLAVSEL = 5.5 V

IIH2High Level Input Current

—V

0.3 

VDD

—–0.3Low Level Acknowledged VoltageVIL2

Low Level Input Voltage

Range

—V0.6—–0.3Low Level Acknowledged Voltage VIL3

Low Level Input Voltage

Range

—V

VCC

+ 0.3

—1.5High Level Acknowledged VoltageVIH3

High Level Input Voltage

Range

NRST

I2C bus (Internal I/O stage characteristics)

—A10–1

VCC = 5.5 V

VNRST = 0 V

IIL3Low Level Input Current

—A10–1

VCC = 5.5 V

VNRST = 5.5 V

IIH3High Level Input Current

—V0.4—0

VDD > 2 V

ISDA = 3 mA

VOL1

Low-level output voltage 1

*2V

VDDMAX

+ 0.5

—

0.7 

VDD

Voltage which recognized that SDA

and SCL are High-level

VIH

High-level input voltage

*2V

0.3 

VDD

—–0.5

Voltage which recognized that SDA

and SCL are Low-level

VIL

Low-level input voltage

—A100–10

VCC = 5.5 V, VDD = 5.5 V

VSCL, VSDA = 0.1 VDDMAX to 0.9

VDDMAX

Input current each I/O pin

—mA——20VSDA = 0.4 VIOL

Low-level output current

—V

0.2 

VDD

—0

VDD < 2 V

ISDA = 3 mA

VOL2

Low-level output voltage 2

—V

VDD

+ 0.3

—

0.7 

VDD

High Level Acknowledged VoltageVIH2

High Level Input Voltage

Range

SLAVSEL

—kHz1000—0—fSCL

SCL clock frequency

Limits

Typ Unit

Max Note

Min

Condition SymbolParameter

ELECTRICAL CHARACTERISTICS (continued)

VCC = 3.6 V, VDD = 1.85 V

Note) Operating Ambient Temperature, Ta= 25 C 2 C, unless specifically mentioned

Note) VDDmax refers to the maximum operating supply voltage of VDD.

*2 : The input threshold voltage of I2C bus (Vth) is linked to VDD (I2C bus I/O stage supply voltage).

In case the pull-up voltage is not VDD, the threshold voltage (Vth) is fixed to ((VDD / 2) (Schmitt width) / 2 )

and High-level, Low-level of input voltage are not specified.

In this case, pay attention to Low-level (max.) value (VILMAX).

It is recommended that the pull-up voltage of I2C bus is set to the I2C bus I/O stage supply voltage (VDD).

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Product Standards

MaxTyp NoteUnit

Limits

Condition SymbolParameter Min

—

0.1 

VDD

0.05 

VDD

—

ns50—tSP

Pulse width of spikes which

must be suppressed by the input

filter

ns120

Bus capacitance

: 10 pF to 550 pF

IP20 mA (VOLmax = 0.4 V)

IP: Max. sink current

tof

Output fall time from VIHmin to

VILmax

V—

VDD < 2 V,

Hysteresis of SDA, SCL

Vhys2

Hysteresis of Schmitt trigger

input 2

pF10—Ci

Capacitance for each I/O pin

C—150—

Temperature which Constant

current circuit, and Matrix SW

turn off.

TdetDetection temperature

Constant Voltage Source (LDO)

*4dB—–50

VCC = 3.6 V + 0.3 V [p-p]

f = 1 kHz

ILDO = – 15 mA

PSL11 = 20 log (acVLDO / 0.3)

PSL11Ripple rejection ratio (1)

*4dB—–40

VCC = 3.6 V + 0.3 V[p-p]

f = 10 kHz

ILDO = – 15 mA

PSL12 = 20 log (acVLDO / 0.3)

PSL12Ripple rejection ratio (2)

TSD (Thermal shutdown protection circuit)

I2C bus (Internal I/O stage characteristics) (Continued)

*4mA—40VLDO = 0 VIPT1Short-circuit protection current

V—

VDD > 2 V,

Hysteresis of SDA, SCL

Vhys1

Hysteresis of Schmitt trigger

input 1

Note) *3 : Constant current circuit, and Matrix SW turn off and IC reset when TSD operates.

*4 : Typical Design Value

*5 : The timing of Fast-mode Plus devices in I2C-bus is specified in Page.10. All values referred to VIHMIN and VILMAX level.

*6 : These are values checked by design but not production tested.

ELECTRICAL CHARACTERISTICS (continued)

VCC = 3.6 V, VDD = 1.85 V

Note) Operating Ambient Temperature, Ta= 25 C 2 C, unless specifically mentioned

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Product Standards

MaxTyp NoteUnit

Limits

Condition SymbolParameter Min

—

s—0.26—tSU:STA

Set-up time for a repeat START

condition

s—0.26—tHIGH

High period of the SCL clock

s—0.5—tLOW

Low period of the SCL clock

ns120——tr

Rise time of both SDA and SCL

signals

ns50—tSU:DAT

Data set-up time

s—0—tHD:DAT

Data hold time

s—0.5—tBUF

Bus free time between STOP

and START condition

s—0.26—tSU:STO

Set-up time of STOP condition

ns120——tf

Fall time of both SDA and SCL

signals

s0.45——tVD:ACK

Data valid acknowledge

s0.45——tVD:DAT

Data valid time

pF550——Cb

Capacitive load for each bus line

I2C bus (Bus line specifications) (Continue)

V—

0.1 

VDD

—VnL

Noise margin at the Low-level

for each connected device

s—0.26

The first clock pulse is

generated after tHD:STA.

tHD:STA

Hold time

(repeated) START condition

V—

0.2 

VDD

—VnH

Noise margin at the High-level

for each connected device

Note) *5 : The timing of Fast-mode Plus devices in I2C-bus is specified in Page.10. All values referred to VIHMIN and VILMAX level.

*6 : These are values checked by design but not production tested.

ELECTRICAL CHARACTERISTICS (continued)

VCC = 3.6 V, VDD = 1.85 V

Note) Operating Ambient Temperature, Ta= 25 C 2 C, unless specifically mentioned

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Product Standards

S : START condition

Sr : Repeat START condition

P : STOP condition

tftr

70 %

30 %

SDA

SCL

tHD;STA

70 %

30 %

70 %

30 %

S1 / fSCL

1st clock cycle

tHD;DAT

tSU;DAT

70 %

30 %

70 %

30 %

tLOW

70 %

30 %

tHIGH

tVD;DAT

●●●

cont.

9th clock

●●●

cont.

tHD;STA

tSP

70 %

30 %

tSU;STO

VILMAX = 0.3 VDD

VIHMIN = 0.7 VDD

tSU;STA

9th clock

tVD;ACK

tBUF

P S

ELECTRICAL CHARACTERISTICS (continued)

VCC = 3.6 V, VDD = 1.85 V

Note) Operating Ambient Temperature, Ta= 25 C 2 C, unless specifically mentioned

SDA

SCL

●●●

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Product Standards

PIN CONFIGURATION

PIN FUNCTIONS

(Required pin)Power supply pin for I2C interfacePower supplyVDD1

(Required pin)Resistor connection pin for constant current setupOutputIREF2

(Required pin)Ground pinGround

GND1

GND2

Open

Constant current circuit, PWM control output pin,

Control switch pin for matrix driver

OutputZ14

Open

Constant current circuit, PWM control output pin,

Control switch pin for matrix driver

OutputZ25

Battery or External

power supply

Power supply pin for matrix driver and Internal

reference circuit

Power supplyVCC6

(Required pin)LDO output pin OutputLDO7

Open

Constant current circuit, PWM control output pin,

Control switch pin for matrix driver

OutputZ38

Open

Constant current circuit, PWM control output pin,

Control switch pin for matrix driver

OutputZ49

Open

Constant current circuit, PWM control output pin,

Control switch pin for matrix driver

OutputZ511

OpenReference clock input output / Music Input pinInput/OutputCLKIO12

(Required pin)Reset input pinInputNRST13

(Required pin)Data input / output pin for I2C interfaceInput/OutputSDA14

(Required pin)

Clock input pin for I2C interface

InputSCL 15

(Required pin)Slave address selection pin for I2C interfaceInputSLAVSEL16

Pin processing

at unused

DescriptionTypePin namePin No.

Top View

NRST

SDA

SCL

SLAVSEL

LDO

VCC

CLKIO

GND2

VDD

IREF

GND1

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Product Standards

FUNCTIONAL BLOCK DIAGRAM

VDD

LDO

SLAVSEL

Periodical

Scanning

Selectors

LED

drivers

I2C

serial

interface

frame

and brightness

controller

Moving pattern

generator

Logic

Reference

Generator

Music

Synchronize

Function

Clock Output

PWM Step control

Voltage

regulators

(7)

VCC

(6)

(5)

(8)

Z1 (4)

(3)

(2)

(1)

GND1

IREF

(10) GND2

(9) Z4

(12)

(11)

CLKIO

NRST (13)

SDA

SCL

(14)

(15)

(16)

Notes: This block diagram is for explaining functions. Part of the block diagram may be omitted, or it may be simplified.

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Product Standards

OPERATION

1. Power Supply Sequence

Serial Input is possible

NRST

>1 ms

VCC

VDD

>3 ms

Note) For the Startup Timing of VCC and VDD, it is possible to be changed.

Note) For the Shut down Timing of VCC and VDD, it is possible to be changed.

NRST

Serial Input is possible

VDD

VCC

1 ms or more

Power ON

Power OFF

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Product Standards

OPERATION ( continued )

IMAX

Reserved

----

IMAX[2:0]

Y1MSKY3MSK Y2MSKY4MSK

Y1Y2Y3Y4R/W00hYCONST0Eh

GRP4_0GRP4_1GRP4_2GRP4_3GRP8_0GRP8_1

GRP_ALL

--R/W00h

MDLMODE2

0Ah

SLOPEEXTH[1:0]SLOPEEXTL[1:0]FADTIMSCANSET[1:0]--R/W00hSLPTIME0Fh

X1X2X3X4X5------R/W00hXCONST0Dh

MLDCOM[2:0]----------R/W03hMLDCOM0Bh

MLDC1MLDC2MLDC3MLDC4MLDD1MLDD2MLDD3MLDD4R/W00hMDLEN209h

MLDA1MLDA2MLDA3MLDA4MLDB1MLDB2MLDB3MLDB4R/W00hMDLEN108h

THOLD[7:0]R/W00hTHOLD0Ch

PWMA1PWMA2PWMA3PWMA4PWMB1PWMB2PWMB3PWMB4R/W00hPWMEN106h

PWMC1PWMC2PWMC3PWMC4PWMD1PWMD2PWMD3PWMD4R/W00hPWMEN207h

EXTCLKCLKOUT

SRSTRAMRST------------R/W00hRST01h

MTXON--

MLDACT

ZPDEN----

----------

1Eh

00h

Default

R/W

--MTXON05h

--OPTION04h

--reserved03h

OSCEN------------

POWERCNT

02h

D0D1D2D3D4D5D6D7

Name

ADDR

DATA

Note) "Reserved" registers and data bits indicated by "--" cannot be accessed. "Reserved" registers are not used.

For data bits indicated by "--" in other registers except for "reversed" registers, will return "zero" value if these bits are read.

Writing to these bits will be ignored. IMAX Reserved will give default value [1].

2. Register Map

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Product Standards

SDTD4[2:0]

SDTD3[2:0]

SDTD2[2:0]

SDTD1[2:0]

SDTC4[2:0]

SDTC3[2:0]

SDTC2[2:0]

SDTC1[2:0]

SDTB4[2:0]

SDTB3[2:0]

SDTB2[2:0]

SDTB1[2:0]

SDTA4[2:0]

SDTA3[2:0]

SDTA2[2:0]

SDTA1[2:0]

BRTD3[3:0]R/W00hD32Eh

DTC1[7:0]R/W00hDTC118h

DTB3[7:0]R/W00hDTB316h

DTB4[7:0]R/W00hDTB417h

DTC2[7:0]R/W00hDTC219h

DTC3[7:0]R/W00hDTC31Ah

DTC4[7:0]R/W00hDTC41Bh

DTD1[7:0]R/W00hDTD11Ch

DTD2[7:0]R/W00hDTD21Dh

DTD3[7:0]R/W00hDTD31Eh

DTD4[7:0]R/W00hDTD41Fh

BRTA1[3:0]R/W00hA120h

BRTA2[3:0]R/W00hA221h

BRTA3[3:0]R/W00hA322h

BRTA4[3:0]R/W00hA423h

BRTB1[3:0]R/W00hB124h

BRTB2[3:0]R/W00hB225h

BRTB3[3:0]R/W00hB326h

BRTB4[3:0]R/W00hB427h

BRTC1[3:0]R/W00hC128h

BRTC2[3:0]R/W00hC229h

BRTC3[3:0]R/W00hC32Ah

BRTC4[3:0]R/W00hC42Bh

BRTD1[3:0]R/W00hD12Ch

BRTD2[3:0]R/W00hD22Dh

BRTD3[3:0]R/W00hD42Fh

00h

Default

R/W

DTB2[7:0]DTB215h

DTB1[7:0]DTB114h

DTA4[7:0]DTA413h

DTA3[7:0]DTA312h

DTA2[7:0]DTA211h

DTA1[7:0]DTA110h

D0D1D2D3D4D5D6D7

Name

ADDR DATA

Note) Data bits indicated by "--" cannot be accessed. It will return "zero" value if these bits are read.

Writing to these bits will be ignored.

OPERATION ( continued )

2. Register Map (continued)

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Product Standards

OPERATION ( continued )

Default

01h

Address

SRSTRAMRST------------R/W

0000000000h

D0D1D2D3D4D5D6D7R/W

RSTRegister Name

Default

02h

Address

OSCEN--------------R/W

0000000000h

D0D1D2D3D4D5D6D7R/W

POWERCNTRegister Name

D1 : RAMRST RAM reset

[0] : RAM can be overwritten (default)

[1] : Clear all PWM duty setting and intensity setting

D0 : SRST Soft reset control

[0] : Reset release state (default)

[1] : Reset reset

D0 : OSCEN Internal oscillator ON/OFF bit

[0] : Internal oscillator OFF (default)

[1] : Internal oscillator ON

• This register will auto-return to zero when written with "High" logic value.

• Oscillator will auto turn ON if any of the LED drivers are enabled (MTXON = 1) even if this bit is [0].

3. Register map Detailed Explanation

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Product Standards

Default

04h

Address

EXTCLKCLKOUTMLDACTZPDEN------R/W

0000000000h

D0D1D2D3D4D5D6D7R/W

OPTIONRegister Name

IMAX

Reserved IMAX[2:0]

Default

05h

Address

MTXON----R/W

011110001Eh

D0D1D2D3D4D5D6D7R/W

MTXONRegister Name

D3 : ZPDEN Ghost Image Prevention Enable

[0] : Turn off ghost image prevention (default)

[1] : Turn on ghost image prevention

D2 : MLDACT External Melody Input Selection

[0] : Turn off melody mode (default)

[1] : Turn on melody mode

D1 : CLKOUT Internal clock output enable

[0] : Internal clock is not output from CLKOUT (default)

[1] : Internal clock is output from CLKOUT

D0 : EXTCLK Internal/external synchronous clock selection

[0] : Internal clock operation (default)

[1] : External clock operation

D3-1 : IMAX Maximum current setup selection

[000] : 7.5 mA [100] : 37.5 mA

[001] : 15 mA [101] : 45 mA

[010] : 22.5 mA [110] : 52.5 mA

[011] : 30 mA [111] : 60 mA (default)

D0 : MTXON LED Matrix Set up ON/OFF control

[0] : OFF (default)

[1] : ON

• Ghost Image Prevention may not remove the ghost image perfectly. It depends on the LED color combination

and LED connection method. Please refer to Page.46 for details.

Please refer to Page.47 for details especially when this LSI is used for RGB driver.

• For D2, D1 and D0 cannot be set to High at the same time. In such case, the priority of operation will be

EXTCLK then CLKOUT and then Melody Mode will have the least priority.

• For better accuracy, it is advisable to set IMAX at 30 mA (IMAX = 011). The brightness can be adjusted

lower by using brightness register (BRT*[3:0] (register #20h to #2Fh)) or PWM register (DT*[7:0]

(register #10h to #1Fh)).

OPERATION ( continued )

3. Register map Detailed Explanation (continued)

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Product Standards

Default

06h

Address

PWMA1PWMA2PWMA3PWMA4PWMB1PWMB2PWMB3PWMB4

R/W

0000000000h

D0D1D2D3D4D5D6D7R/W

PWMEN1Register Name

D7 : PWMB4 B4 PWM mode enable

[0] : Not PWM mode (default)

[1] : PWM mode

D6 : PWMB3 B3 PWM mode enable

[0] : Not PWM mode (default)

[1] : PWM mode

D5 : PWMB2 B2 PWM mode enable

[0] : Not PWM mode (default)

[1] : PWM mode

D4 : PWMB1 B1 PWM mode enable

[0] : Not PWM mode (default)

[1] : PWM mode

D3 : PWMA4 A4 PWM mode enable

[0] : Not PWM mode (default)

[1] : PWM mode

D2 : PWMA3 A3 PWM mode enable

[0] : Not PWM mode (default)

[1] : PWM mode

D1 : PWMA2 A2 PWM mode enable

[0] : Not PWM mode (default)

[1] : PWM mode

D0 : PWMA1 A1 PWM mode enable

[0] : Not PWM mode (default)

[1] : PWM mode

OPERATION ( continued )

3. Register map Detailed Explanation (continued)

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Product Standards

Default

07h

Address

PWMC1PWMC2PWMC3PWMC4PWMD1PWMD2PWMD3PWMD4

R/W

0000000000h

D0D1D2D3D4D5D6D7R/W

PWMEN2Register Name

D7 : PWMD4 D4 PWM mode enable

[0] : Not PWM mode (default)

[1] : PWM mode

D6 : PWMD3 D3 PWM mode enable

[0] : Not PWM mode (default)

[1] : PWM mode

D5 : PWMD2 D2 PWM mode enable

[0] : Not PWM mode (default)

[1] : PWM mode

D4 : PWMD1 D1 PWM mode enable

[0] : Not PWM mode (default)

[1] : PWM mode

D3 : PWMC4 C4 PWM mode enable

[0] : Not PWM mode (default)

[1] : PWM mode

D2 : PWMC3 C3 PWM mode enable

[0] : Not PWM mode (default)

[1] : PWM mode

D1 : PWMC2 C2 PWM mode enable

[0] : Not PWM mode (default)

[1] : PWM mode

D0 : PWMC1 C1 PWM mode enable

[0] : Not PWM mode (default)

[1] : PWM mode

OPERATION ( continued )

3. Register map Detailed Explanation (continued)

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Product Standards

Default

08h

Address

MLDA1MLDA2MLDA3MLDA4MLDB1MLDB2MLDB3MLDB4R/W

0000000000h

D0D1D2D3D4D5D6D7R/W

MDLEN1Register Name

D7 : MLDB4 B4 Melody mode enable

[0] : Not Melody mode (default)

[1] : Melody mode

D6 : MLDB3 B3 Melody mode enable

[0] : Not Melody mode (default)

[1] : Melody mode

D5 : MLDB2 B2 Melody mode enable

[0] : Not Melody mode (default)

[1] : Melody mode

D4 : MLDB1 B1 Melody mode enable

[0] : Not Melody mode (default)

[1] : Melody mode

D3 : MLDA4 A4 Melody mode enable

[0] : Not Melody mode (default)

[1] : Melody mode

D2 : MLDA3 A3 Melody mode enable

[0] : Not Melody mode (default)

[1] : Melody mode

D1 : MLDA2 A2 Melody mode enable

[0] : Not PWM mode (default)

[1] : Melody mode

D0 : MLDA1 A1 Melody mode enable

[0] : Not Melody mode (default)

[1] : Melody mode

OPERATION ( continued )

3. Register map Detailed Explanation (continued)

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D7 : MLDD4 D4 Melody mode enable

[0] : Not Melody mode (default)

[1] : Melody mode

D6 : MLDD3 D3 Melody mode enable

[0] : Not Melody mode (default)

[1] : Melody mode

D5 : MLDD2 D2 Melody mode enable

[0] : Not Melody mode (default)

[1] : Melody mode

D4 : MLDD1 D1 Melody mode enable

[0] : Not Melody mode (default)

[1] : Melody mode

D3 : MLDC4 C4 Melody mode enable

[0] : Not Melody mode (default)

[1] : Melody mode

D2 : MLDC3 C3 Melody mode enable

[0] : Not Melody mode (default)

[1] : Melody mode

D1 : MLDC2 C2 Melody mode enable

[0] : Not PWM mode (default)

[1] : Melody mode

D0 : MLDC1 C1 Melody mode enable

[0] : Not Melody mode (default)

[1] : Melody mode

Default

09h

Address

MLDC1MLDC2MLDC3MLDC4MLDD1MLDD2MLDD3MLDD4R/W

0000000000h

D0D1D2D3D4D5D6D7R/W

MDLEN2Register Name

OPERATION ( continued )

3. Register map Detailed Explanation (continued)

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Product Standards

D6 : GRP_ALL All LED blink with external input as a group

[0] : Normal (default)

[1] : Bar meter mode

(D1C1B1A1D2C2B2A2D3C3B3A3D4C4B4A4)

D5 : GRP8_1 Column 3 and Column 4 blink with external input as a group

[0] : Normal (default)

[1] : Bar meter mode (D3C3B3A3D4C4B4A4)

D4 : GRP8_0 Column 1 and Column 2 blink with external input as a group

[0] : Normal (default)

[1] : Bar meter mode (D1C1B1A1D2C2B2A2)

D3 : GRP4_3 Column 4 blink with external input as a group

[0] : Normal (default)

[1] : Bar meter mode (D4C4B4A4)

D2 : GRP4_2 Column 3 blink with external input as a group

[0] : Normal (default)

[1] : Bar meter mode (D3C3B3A3)

D1 : GRP4_1 Column 2 blink with external input as a group

[0] : Normal (default)

[1] : Bar meter mode (D2C2B2A2)

D0 : GRP4_0 Column 1 blink with external input as a group

[0] : Normal (default)

[1] : Bar meter mode (D1C1B1A1)

Default

0Ah

Address

GRP4_0GRP4_1GRP4_2GRP4_3GRP8_0GRP8_1GRP_ALL

--R/W

0000000000h

D0D1D2D3D4D5D6D7R/W

MDLMODE2Register Name

Melody mode of A11000

Bar meter mode of Column 1 x100

Bar meter mode of Column 1 and Column 2xx10

Bar meter mode of all LEDxxx1

Normal mode0000

Melody ModesMLDA1GRP4_0GRP8_0GRP_ALL

D4D3D2D1

C4C3C2C1

B4B3B2B1

A4A3A2A1

• During Bar Meter Mode, auto threshold detection should be used. This LSI does not support Bar Meter

Mode with fixed threshold setting.

OPERATION ( continued )

3. Register map Detailed Explanation (continued)

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Product Standards

Default

0Bh

Address

MLDCOM[2:0]----------R/W

1100000003h

D0D1D2D3D4D5D6D7R/W

MLDCOMRegister Name

D2-0 : MLDCOM LED Turn on time compensation in melody mode

[000] : 0 s

[001] : 0.86 µs

[010] : 1.72 µs

[011] : 2.58 µs (default)

[100] : 3.44 µs

[101] : 4.30 µs

[110] : 5.17 µs

[111] : 6.03 µs

OPERATION ( continued )

3. Register map Detailed Explanation (continued)

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Product Standards

Default

0Ch

Address

THOLD[7:0]R/W

0000000000h

D0D1D2D3D4D5D6D7R/W

THOLDRegister Name

D7 : THOLD[7] Threshold 8 is used as voltage detection.

[0] : Others (default)

[1] : Threshold 8 is used. (Threshold 8 is about 1.93 V)

D6 : THOLD[6] Threshold 7 is used as voltage detection.

[0] : Others (default)

[1] : Threshold 7 is used. (Threshold 7 is about 1.80 V)

D5 : THOLD[5] Threshold 6 is used as voltage detection.

[0] : Others (default)

[1] : Threshold 6 is used. (Threshold 6 is about 1.67 V)

D4 : THOLD[4] Threshold 5 is used as voltage detection.

[0] : Others (default)

[1] : Threshold 5 is used. (Threshold 5 is about 1.55 V)

D3 : THOLD[3] Threshold 4 is used as voltage detection.

[0] : Others (default)

[1] : Threshold 4 is used. (Threshold 4 is about 1.42 V)

D2 : THOLD[2] Threshold 3 is used as voltage detection.

[0] : Others (default)

[1] : Threshold 3 is used. (Threshold 3 is about 1.30 V)

D1 : THOLD[1] Threshold 2 is used as voltage detection.

[0] : Others (default)

[1] : Threshold 2 is used. (Threshold 2 is about 1.17 V)

D0 : THOLD[0] Threshold 1 is used as voltage detection.

[0] : Others (default)

[1] : Threshold 1 is used. (Threshold 1 is about 1.04 V)

• When all bits are set zero, threshold is in auto-detection mode (default)

• Do not set more than 1 register bit to logic "High" value at the same time.

• If 2 bits are set to "High" at the same time, system will only recognize the first "High" bit threshold that is set.

OPERATION ( continued )

3. Register map Detailed Explanation (continued)

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Product Standards

D4 : X5 Z5 is fixed as constant current mode.

[0] : Normal matrix operation (default)

[1] : Z5 is fixed as constant current mode. The LED D1’s current setting is used.

D3 : X4 Z4 is fixed as constant current mode.

[0] : Normal matrix operation (default)

[1] : Z4 is fixed as constant current mode. The LED A4’s current setting is used.

D2 : X3 Z3 is fixed as constant current mode.

[0] : Normal matrix operation (default)

[1] : Z3 is fixed as constant current mode. The LED A3’s current setting is used.

D1 : X2 Z2 is fixed as constant current mode.

[0] : Normal matrix operation (default)

[1] : Z2 is fixed as constant current mode. The LED A2’s current setting is used.

D0 : X1 Z1 is fixed as constant current mode.

[0] : Normal matrix operation (default)

[1] : Z1 is fixed as constant current mode. The LED A1’s current setting is used.

Default

0Dh

Address

X1X2X3X4X5------R/W

0000000000h

D0D1D2D3D4D5D6D7R/W

XCONSTRegister Name

OPERATION ( continued )

3. Register map Detailed Explanation (continued)

• Please refer to Page.30 for details.

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Product Standards

Default

0Eh

Address

Y1MSKY2MSKY3MSKY4MSKY1Y2Y3Y4R/W

0000000000h

D0D1D2D3D4D5D6D7R/W

YCONSTRegister Name

D7 : Y4 Z4 output is fixed to High (VCC level).

[0] : Normal matrix operation (default)

[1] : Switch between VCC and Z4 turns on (VCC level).

D6 : Y3 Z3 output is fixed to High (VCC level).

[0] : Normal matrix operation (default)

[1] : Switch between VCC and Z3 turns on (VCC level).

D5 : Y2 Z2 output is fixed High (VCC level).

[0] : Normal matrix operation (default)

[1] : Switch between VCC and Z2 turns on (VCC level).

D4 : Y1 Y1CNT is fixed to High (VCC level).

[0] : Normal matrix operation (default)

[1] : Switch between VCC and Z1 turns on (VCC level).

D3 : Y4MSK Z4 output is fixed to OFF.

[0] : Normal matrix operation (default)

[1] : Switch between VCC and Z4 turns off.

D2 : Y3MSK Z3 output is fixed to OFF.

[0] : Normal matrix operation (default)

[1] : Switch between VCC and Z3 turns off.

D1 : Y2MSK Z2 output is fixed to OFF.

[0] : Normal matrix operation (default)

[1] : Switch between VCC and Z2 turns off.

D0 : Y1MSK Z1 output is fixed to OFF.

[0] : Normal matrix operation (default)

[1] : Switch between VCC and Z1 turns off.

OPERATION ( continued )

3. Register map Detailed Explanation (continued)

• Please refer to Page.30 for details.

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Product Standards

D6-5 : SCANSET Scan number control.

[00] : Only scan the first column.

[01] : Only scan the first 2 column.

[10] : Only scan the first 3 column.

[11] : Scan all column (default)

D4 : FADTIM Fade out time control.

[0] : T3 = T1 (default)

[1] : T3 = T1 2

D3-2 : SLOPEEXTL T4 time extent control.

[00] : T4 = T1 (default)

[01] : T4 = T1 0.25

[10] : T4 = T1 0.5

[11] : T4 = T1 2

D1-0 : SLOPEEXTH T2 time extent control.

[00] : T2 = T1 (default)

[01] : T2 = T1 0.25

[10] : T2 = T1 0.5

[11] : T2 = T1 2

Default

0Fh

Address

SLOPEEXTH[1:0]SLOPEEXTL[1:0]FADTIMSCANSET[1:0]--R/W

0000011060h

D0D1D2D3D4D5D6D7R/W

SLPTIMERegister Name

T1 T3T2 T4

• This bit also affect in PWM fade out mode. Fade out time becomes 2 times of fade in time when FADTIM = 1.

• T1 time is controlled by the register #20h to #2Fh.

OPERATION ( continued )

3. Register map Detailed Explanation (continued)

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Product Standards

D7-0 : DTA1 A1 PWM duty control.

[0000_0000] : 0%. (default)

[0000_0001] : 0.39%. (1/256)

[0000_0010] : 0.78%. (2/256)

[0000_0011] : 1.17%. (3/256)

…

[1111_1100] : 98.8%. (253/256)

[1111_1110] : 99.2%. (254/256)

[1111_1111] : 99.6%. (255/256)

Default

10h

Address

DTA1[7:0]R/W

0000000000h

D0D1D2D3D4D5D6D7R/W

DTA1Register Name

• This duty setting is only effective when PWMA1 is High.

• The definition for register addresses #11h to #1Fh is the same as address #10h.

OPERATION ( continued )

3. Register map Detailed Explanation (continued)

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Product Standards

SDTA1[2:0]

Default

20h

Address

--BRTA1[3:0]R/W

0000000000h

D0D1D2D3D4D5D6D7R/W

A1Register Name

D7-4 : BRTA1 Luminance set up of LED A1 (in case of IMAX [2:0] == [011])

[0000] : 0 mA (default)

[0001] : 2 mA

[0010] : 4 mA

[0011] : 6 mA

[0100] : 8 mA

[0101] : 10 mA

[0110] : 12 mA

[0111] : 14 mA

[1000] : 16 mA

[1001] : 18 mA

[1010] : 20 mA

[1011] : 22 mA

[1100] : 24 mA

[1101] : 26 mA

[1110] : 28 mA

[1111] : 30 mA

D2-0 : SDTA1 (SCANSET == [11], default setting)

(1) Firefly Operation (PWMA1 == 0)

[000] : Constant current mode (default)

[001] : 0.22 s

[010] : 0.44 s

[011] : 0.88 s

[100] : 1.32 s

[101] : 1.76 s

[110] : 2.2 s

[111] : 2.64 s

(2) PWM Fade-in/out Operation (PWMA1 == 1)

[000] : Instant change mode (default)

[001] : 1.72 ms

[010] : 3.44 ms

[011] : 6.89 ms

[100] : 10.34 ms

[101] : 13.79 ms

[110] : 17.3 ms

[111] : 20.7 ms

T1 T3T2 T4

• In case of PWM duty change from 0 to 255, the longest time is 255 20.7 ms = 5.2785 s.

• T1 time is also controlled by SCANSET in register #0Fh. The calculation method is as follow:

SCANSET == 00 : T1 = 0.25 T_default

SCANSET == 01 : T1 = 0.5 T_default

SCANSET == 10 : T1 = 0.75 T_default

• The definition for register addresses #21h to #2Fh is the same as address #20h.

OPERATION ( continued )

3. Register map Detailed Explanation (continued)

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Product Standards

OPERATION ( continued )

Firefly mode!=000001

PWM modex10001

Y*MSK

Constant current mode0001

Switch between VCC and Z4 turns on

(VCC level).

xx01

Switch between VCC and Z* turns off

xx01

Z* constant current modexx11

OFFxxx0

Operation ModeSDT*PWM*X*MTXON

4. Operation Mode priority

• * for X*, PWM*, SDT* == 1 ~ 5, * for Y*MSK, Y* == 1 ~ 4.

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OPERATION ( continued )

START condition

SDA

SCL

STOP condition

START or

repetitive START

condition

STOP or

repetitive START

condition

SCL

SDA

MSB

ACK ACK

12 789 123 –89

ACK signal from slave ACK signal from receiver

Completion of Byte Transfer &

Slave interruption.

5.1 Basic Rules

5.2 START and STOP conditions

When SDA signal changes from "High" to "Low" while SCL is "High" will trigger START condition. Whereas,

STOP condition will be triggered when SDA signal changes from "Low" to "High" while SCL is "High".

START condition and STOP condition are always formed by the master. After the START condition occurs, the

bus becomes busy state. After STOP condition occurs, the bus becomes free again.

5.3 Data Transfer

Length of each byte output to SDA line is always 8 bits. There is no limitation in the number of bytes that can be

transmitted at 1 time. Many bytes can be sent. The acknowledge bit is necessary for each byte.

Data is sequentially transmitted from most significant bit (MSB).

5. I2C Bus Interface

• This LSI, I2C-bus, is designed to correspond to the Standard-mode (100 kbps), Fast-mode(400 kbps) and

Fast-mode plus (1 000 kbps) devices in the version 2.1 of NXP's specification. However, it does not correspond

to the HS-mode (to 3.4 Mbps).

• This LSI will operate as a slave device in the I2C-bus system. This LSI will not operate as a master device.

• The program operation check of this LSI has not been conducted on the multi-master bus system and the

mix-speed bus system, yet. The connected confirmation of this LSI to the CBUS receiver also has not been

checked. Please confirm with our company if it will be used in these mode systems.

• The I2C is the brand of NXP.

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OPERATION ( continued )

S Slave address Sub address

Stop condition

ACK : 0

Start condition Write mode : 0

W A A Data byte A P

7-bit 8-bit 8-bit

ACK : 0 ACK : 0

Sub address

X data

Sub address

X+1 data

S Slave address Sub address

ACK : 0

Start condition Write mode : 0

W A A Data byte A

7-bit 8-bit 8-bit

ACK : 0 ACK : 0

Data byte

8-bit

Sub address

X+m-1 data

Sub address

X+m data

Data byte A

8-bit

ACK : 0

Data byte

8-bit

ACK : 0

：Data transmission from Master

：Data transmission from Slave

1010 010XSCL

1010 001XHigh

SDI

Low

SLAVSEL

1010 000X

1010 011X

Slave address

Data byte can be written in Sub address by transmitting data byte continuously.

Sub address is incremented automatically.

Sub address is not incremented automatically.

The next data byte is written in the same Sub address by transmitting data byte continuously.

5.4 I2C Interface - Data Format

In this LSI, 4 different Slave address can be changed by selecting SLAVSEL ( "Low" or "High" or "SCL" or

"SDI").

The slave addresses of this LSI are as follow:

5. I2C Bus Interface (continued)

Write mode

Write mode (Auto increment mode)

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OPERATION ( continued )

S Slave address Sub address

ACK : 0

Start condition Write mode : 0

W A Sr Slave address A

7-bit 8-bit 7-bit

ACK : 0

Data byte

8-bit

NACK : 1

A PR

Stop conditionRepeated start condition Read mode : 1

ACK : 0

Sub address

X+m–1 data

Sub address

X+m data

Data byte A

8-bit

ACK : 0

Data byte

8-bit

NACK : 1

S Slave address Sub address

ACK : 0

Start condition

W A Sr Slave address A

7-bit 8-bit 7-bit

ACK : 0

Data byte

8-bit

ACK : 0

A R

Repeated start condition Read mode : 1

ACK : 0

Sub address

X data

Stop condition

Write mode : 0

S Slave address Data byte

Stop condition

ACK : 0

Start condition Read mode : 1

RA A P

7-bit 8-bit

NACK : 1

5. I2C Bus Interface (continued)

Sub address is not incremented automatically.

The next data byte reads the same Sub address by transmitting data byte continuously.

When Sub address 8 bit is not specified and data is read, this LSI allows to read the value of adjacent Sub

address specified in the last Write mode.

The next data byte reads the same Sub address by transmitting data byte continuously.

It is possible to read data byte in continuous Sub address by transmitting data byte continuously.

Sub address is incremented automatically.

5.4 I2C Interface - Data Format (continued)

Read mode (in case Sub address is not specified)

Read mode (in case Sub address is specified)

Read mode (Auto increment mode)

：Data transmission from Master

：Data transmission from Slave

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OPERATION ( continued )

VCC

VLDO

VDD

GND1

GND2

LOGIC SCAN

SW I2C

BGR LED

Driver

Music

Sync

TSD

6.2 Distribution diagram of control / clock system

Oscillator 2.4 MHz

(PAD) CLKIO

(Register) EXTCLK

Logic block

(Matrix)

*Matrix operation, PWM control

(Register) CLKOUT

6. Signal distribution diagram

6.1 Distribution diagram of power supply

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OPERATION ( continued )

Connected

pin name

4321

LED matrix driver circuit individually drives LED of 4 4 matrix. In total, the LSI can drive and light up 16 LED.

In this specification, LED's number controlled by each pin corresponds as follows.

The internal logic circuit is operated by using an internal clock or the external clock input to the terminal CLKIO.

7. Block Configuration of Matrix LED

7.1 Matrix LED descriptions, Matrix LED’s numbers

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OPERATION ( continued )

7. Block Configuration of Matrix LED (continued)

7.2 Driver Configuration

VCC / External DCDC

PWM

Y3CNT

Y4CNT

Y2CNT

Y1CNT

PWM

X2CNT

X4CNT

X3CNT

X5CNT

Matrix SCAN Switches

Current Sink with

Slope control timing

Control

Logic

X1CNT

1234

• Actual driver configuration is shown in the following figure.

• The anodes and cathode of each LED are connected to different Z pin as shown in figure below.

• Z5 pin consists of only Current Sink and Slope control timing driver. Thus, LED anode are not to be connected

to Z5 pin.

• Please do not remove any of the LED inside the matrix if it is not used. If LED are to be removed, it is advised

to remove the entire row (e.g: all LED in row A) instead of removing only 1 LED. If only one LED in the row is

removed instead of the whole row, user needs to avoid using LED whose reverse breakdown voltage is lower

than the operating VCC level.

• Internal control logic according to user register settings is used to control Y1 to Y4CNT(PMOS ON/Off Scan

Switches) as well as X1 to X5CNT (Current sink value as well as PWM/Slope timing for lighting effects)

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OPERATION ( continued )

• The figure below shows a timing chart when in operation.

• Timing can be controlled according to the external clock frequency input to CLKIO pin.

• In default condition, it is controlled by internal 2.4 MHz clock.

• Y1 to Y4CNT are scan timing which is turned on one at a time. The ON period of each pin is constant 255 clks

(106.08 µs) and includes the interval of 4 clks (1.664 µs).

• 16 LED (4 4 matrix) are controlled by X1 to X5CNT according to below figure.

• When Yx = Xx = Low, the actual waveform of Zx is set to Hi-Z.

Scan period : 1036 clks (approx 2.32 kHz @ 2.4 MHz Clock)

Y1CNT

Y2CNT

Y3CNT

Y4CNT

X1~X5

CNT

4 clks

Y2CNT

Y3CNT

X*CNT

Max Duty : 255 clks (106.08 µs) Min Duty : 1 clk (0.416 µs)

255 clks

• Duty can be set using register DT*[7:0] from registers #10h to #1Fh. Additional brightness control is provided

through register BRT*[3:0] (registers #20h to #2Fh).

7. Block Configuration of Matrix LED (continued)

7.3 Timing Chart when in operation

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OPERATION ( continued )

IMAX Setting : 7.5 mA to 60 mA (max)

DAC Current Step (Brightness) : 0.5 mA to 4 mA (max) step

Constant current mode1

IMAX Setting : 7.5 mA to 60 mA (max)

DAC Current Step (Brightness) : 0.5 mA to 4 mA (max) step

Group LED can synchronize with Music Input from CLKIO pin

Bar Meter Mode has more priority than Melody mode.

Bar Meter Mode5

IMAX Setting : 7.5 mA to 60 mA (max)

DAC Current Step (Brightness) : 0.5 mA to 4 mA (max) step

Each LED can synchronize with Music Input from CLKIO pin

Melody mode4

No.

Fixed Current at 100% Duty IMAX Setting : 7.5 mA to 60 mA (max)

DAC Current Step (Brightness) : 0.5 mA to 4 mA (max) step

Adjustable detention Time for each step : (0.22 s to 2.64 s / step)

Firefly mode

IMAX Setting : 7.5 mA to 60 mA (max)

DAC Current Step (Brightness) : 0.5 mA to 4 mA (max) step

Adjustable detention Time for each step : (1.72 ms to 20.7 ms / step)

PWM mode and Fade-in/out

mode

Setting RangeFeatures

8. LED Driver Block Function

Maximum current setting value can be set up as 60 mA using register IMAX[2:0] (register 05h). Brightness can

be set through the register BRT*[3:0] (register #20h to #2Fh) for individual LED.

Example)

E.g. If user sets register IMAX[2:0] (#05h) = 011 and BRT*[3:0] = 1111, the current will be 30 mA.

E.g. If user sets register IMAX[2:0] (#05h) = 111 and BRT*[3:0] = 1111, the current will be 60 mA.

E.g. If user sets register IMAX[2:0] (#05h) = 111 and BRT*[3:0] = 0111, the current will be 28 mA.

8.1 Constant Current Mode

60 mA (max)

Current value

Functions Table for LED Driver

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OPERATION ( continued )

8. LED Driver Block Function (continued)

8.2 PWM Mode and Fade-in/out Mode

This operation is characterized by PWM signal having variable duty depending on register DT*[7:0]

(registers #10h to #1Fh). However, any changes in duty is not instantaneous, but rather it will step to the

new duty at time determined by register SDT*[2:0].

Example)

Case 1 : LED*DT(new) > LED*DT(old) (PWM Mode without Fade in/out control)

Case 2 : LED*DT(new) > LED*DT(old) (PWM Mode with Fade in control)

In Case 1, PWM duty has been changed from low to high duty. But the register SDT*[2:0] setting is [000]

indicating that there is no Fade in/out control. Therefore, PWM duty changes instantaneously. Users can

see that LED becomes brighter instantaneously once PWM duty has been changed.

In Case 2, PWM duty has also been changed from low to high duty. Unlike in case 1, the register SDT*[2:0]

setting is not [000] in case 2. Therefore, PWM duty has changed according to the register SDT*[2:0] setting.

This is called PWM mode with Fade in control. Users can see that LED becomes brighter slowly according to

the timing set in register SDT*[2:0].

SDT*[2:0] = [000]

LED*DT(new)

LED*DT(old)

Duty

SDT*[2:0] (not [000])

LED*DT(new)

LED*DT(old)

Duty

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OPERATION ( continued )

8. LED Driver Block Function (continued)

8.2 PWM Mode and Fade-in/out Mode (continued)

DT*[7:0] is set through register #10h to #1Fh. FADTIM is set through register #0Fh. SDT*[2:0] is set through

Example) (continued)

Case 3 : LED*DT(new) < LED*DT(old), FADTIM = 0 (PWM Mode with Fade out control)

SDT*[2:0] (not [000])

LED*DT(old)

LED*DT(new)

Duty

In Case 3, PWM duty has been changed from high to low duty. Unlike in case 1, the register SDT*[2:0] setting

is not [000] in case 3. Therefore, PWM duty has changed according to the register SDT*[2:0] setting. This is

called PWM mode with Fade out control. Users can see that LED becomes dimmer slowly according to the

timing set in register SDT*[2:0].

Case 4 : LED*DT(new) < LED*DT(old), FADTIM = 1 (PWM Mode with Fade out control)

SDT*[2:0] 2 (not [000])

LED*DT(old)

LED*DT(new)

Duty

In Case 4, PWM duty has also been changed from high to low duty. Unlike in case 3, the register FADTIM is

not [0]. Again, the register SDT*[2:0] setting is also not [000] in case 4. PWM duty has changed according to

the register SDT*[2:0] setting. Users can see that LED becomes dimmer slowly. It is slower than Case3 as

FADTIM register is high (2 times slower than Case 3 Fade out control).

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OPERATION ( continued )

8. LED Driver Block Function (continued)

8.3 Firefly Control

This operation is characterized by PWM signal cycling from minimum to maximum duty and vice versa with

auto repeat function at time step determined by register SDT*[2:0]. Unlike PWM Fade in/out mode, firefly is

auto repeat and thus creating LED blinking function effect.

256/256

Duty

0/256

STATE = 0 STATE = 1 STATE = 2 STATE = 3

SDT

256 steps

SDTH

64 steps

128 steps

256 steps

512 steps

FADTIM

256 steps

SDTL

64 steps

128 steps

256 steps

512 steps

Example)

Example 1 : SDTH = 00 (SDT 1), SDTL = 00 (SDT 1), FADTIM = 0

Example 2 : SDTH = 00 (SDT 1), SDTL = 00 (SDT 1), FADTIM = 1 (SDT 2)

Example 3 : SDTH = 01 (SDT 0.25), SDTL = 11 (SDT 2), FADTIM = 0

The SDTH is controlled by SLOPEEXTH[1:0] register, SDTL is controlled by SLOPEEXTL[1:0] register.

All these registers, SLOPEEXTH[1:0], SLOPEEXTL[1:0] and FADTIM can be set through register #0Fh.

SDT*[2:0] registers are set individually through register #20h to #2Fh. All other combinations of SDTH,

SDTL and FADTIM is possible.

Duty

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OPERATION ( continued )

8. LED Driver Block Function (continued)

8.4 Melody Mode Explanation

Case 1 : CLKIO as output pin

CLKIO output internal frequency by using

CLKOUT register

Case 2 : CLKIO as input for external clock

CLKIO uses as external input by using

EXTCLK register

Case 3 : CLKIO as input for music signal during melody mode

CLKIO uses as music input when melody mode

is enabled by register MLDACT from register

04h.

Melody mode is to synchronize LED to external music signal. Melody mode can be set through register

MLDACT from register 04h. Each of the 16 LED matrix can be individually enabled for external music

synchronization through register data (address #08h to #09h when register address 04h is set as data 04h).

External Music Signal can be injected from CLKIO pin. CLKIO pin serve as both input and output. CLKIO pin

can output internal oscillator frequency by using CLKOUT register (register 04h).

CLKIO pin can be used as input for external signal by using EXTCLK register (register 04h). External clock

frequency is typically 2.4 MHz. It is advisable to use external clock frequency from 1.2 MHz to 4.8 MHz.

Please do not set MLDACT, EXTCLK and CLKOUT register to "High" at the same time. In such case, the

priority of operation will be EXTCLK then CLKOUT and then Melody Mode will have the least priority.

CLKIO

2.4 MHz

External

Signal

1.2 to 4.8MHz

CLKIO

AC music

signal

CLKIO

Note : If input CLKIO voltage is higher than VDD, there will be back flow current to VDD. It can be calculated as below :

(VCLKIO –0.7 V –VDD)

IBackFlow =

393 k

Cin

Note : Cin can be calculated as below : In case of that the applicable music frequency is 20 Hz.

Cin >= = 45.5 nF

( 20 Hz ) 2 3.14 175 k

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OPERATION ( continued )

8. LED Driver Block Function (continued)

8.4 Melody Mode Explanation (continued)

AC music signal input from CLKIO pin will be compared with internal threshold setting. Based on the

comparison of music signal and threshold voltage, PWM driver control will change and control the LED

ON/OFF. Therefore, LED light on/off control will synchronize with music tempo while LED brightness will

synchronize with music loudness. There are two threshold mode, one is “auto threshold” and the other is

“fixed threshold mode”.

There are 8 threshold voltage levels in this LSI as defined in the register 0Ch (THOLD[7:0]). Auto threshold

mode means that the 8 threshold voltages will be scanned automatically from the lowest to highest

threshold voltages at a fixed frequency higher than audio frequency. Input music signal will be compared

with these scanning threshold voltages to control PWM Driver in order to have music synchronization

effects. This mode allows user to easily use music synchronize function without having the trouble of

manually setting the detection threshold. When melody mode is enabled, auto threshold mode will be the

default mode.

Fixed threshold mode means that the threshold voltage is fixed at one threshold level. It can be set using

user. During fixed threshold mode, do not set more than 1 register bit to logic "High" value at the same time.

If user set more register bits to logic "High" after setting 1 register bit to "High", system will only recognise

the first "High" bit threshold that is set. In this mode, user can have the flexibility to configure different

threshold voltage levels to achieve the desired LED music synchronizing visual effect according to the

system music input level.

It is also advised that AC music signal peak to peak voltage to be at least 0.35 V and not more than 2.8 V.

Additional brightness compensation in melody mode can be achieved by increasing or decreasing the turning

on period of LED. Using brightness compensation register #0Bh, LED turning on period can be controlled

and LED can become brighter or dimmer.

This additional brightness compensation will be effective only in auto threshold mode. If fixed threshold mode

is used, this register will not be able to control LED brightness.

Example of Fixed threshold mode

PWM Driver

Constant current

AC music signal

& fixed

Threshold voltage

•Brightness Compensation in Melody Mode

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OPERATION ( continued )

8. LED Driver Block Function (continued)

8.5 Bar Meter Mode Explanation

In the above diagram (A), column 1 = group4_0, column 2 = group4_1, column 3 = group4_2 and

column 4 = group4_3.

Each group can be enabled through register GRP4_0, 4_1, 4_2, 4_3 (address #0Ah). The LED in the all

groups will be synchronized to threshold signals as follow:

Bar Meter Mode operation is another method of external melody mode wherein a group of LEDs are used

instead of individual LED. Bar Meter Mode has higher priority than individual LED melody mode.

GRP4_0

GRP4_1

GRP4_2

GRP4_3

GRP8_1

1111

3333

5555

7777

GRP8_0

5151

6262

7373

8484

1234

Threshold 1 to 8

(A) (B)

Threshold 1 to 8

7531

8642

GRP_ALL

1234

(C)

In the above diagram (B), another pattern of grouping is shown. Column 1 & 2 = group8_0 and

Column 3 & 4 = group8_1.

Each group can be enable through register GRP8_0 & GRP8_1 (address #0Ah). The LED in the all groups

will be synchronized to threshold signals as follow:

Row's A, B, C, D

Threshold 7

Row's B, C, D

Threshold 5

Row's C, D

Threshold 3

Row's D

Threshold 1

Bar Meter Mode Group LED ONThreshold Signal

LED B2, B4, C2, C4, D2, D4, A1, A3, B1, B3, C1, C3, D1, D3

Threshold 7

LED C1, C3, D1, D3

Threshold 2

LED B1, B3 , C1, C3, D1, D3

Threshold 3

LED A1, A3, B1, B3, C1, C3, D1, D3

Threshold 4

LED A2, A4, B2, B4, C2, C4, D2, D4, A1, A3, B1, B3, C1, C3, D1, D3

Threshold 8

LED C2, C4, D2, D4, A1, A3, B1, B3, C1, C3, D1, D3

Threshold 6

LED D2, D4, A1, A3, B1, B3, C1, C3, D1, D3

Threshold 5

LED D1, D3

Threshold 1

Bar Meter Mode Group LED ONThreshold Signal

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OPERATION ( continued )

In the above diagram (C), another pattern of grouping is shown. The whole 4 4 matrix is grouped. It can be

enable through register GRP_ALL (address #0Ah). The LED in the all groups will be synchronized to threshold

signals as follow:

8. LED Driver Block Function (continued)

8.5 Bar Meter Mode Explanation (continued)

Note : During Bar Meter mode, auto threshold detection should be used. This LSI does not support Bar Meter Mode with

fixed threshold setting. It is also recommended not to use other modes together with Bar Meter Mode.

LED C4, D4, A3, B3, C3, D3, A2, B2, C2, D2, A1, B1, C1, D1

Threshold 7

LED A1, B1, C1, D1

Threshold 2

LED C2, D2, A1, B1, C1, D1

Threshold 3

LED A2, B2, C2, D2, A1, B1, C1, D1

Threshold 4

LED A4, B4, C4, D4, A3, B3, C3, D3, A2, B2, C2, D2, A1, B1, C1, D1

Threshold 8

LED A3, B3, C3, D3, A2, B2, C2, D2, A1, B1, C1, D1

Threshold 6

LED C3, D3, A2, B2, C2, D2, A1, B1, C1, D1

Threshold 5

LED C1, D1

Threshold 1

Bar Meter Mode Group LED ONThreshold Signal

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Product Standards

OPERATION ( continued )

9. Ghost Image Prevention Function

Ghost images sometimes appear during LED matrix mode operation. Very dim light can appear in some LED

even during OFF condition. This is called Ghost Image. In this LSI, Ghost Image Prevention Function is

included to prevent Ghost Image. Ghost Image Prevention Function can be enabled through register ZPDEN

(register 04h).

• Ghost Image Prevention may not remove the ghost image perfectly. It depends on the LED color

combination and LED connection method.

Y1CNT

Y2CNT

Y3CNT

Y4CNT

Ghost

Discharge

Signals

4 clks

Y3CNT

Y4CNT

2 clks

Ghost

Discharge

Signals

Ghost Discharge Disabled Ghost Discharge Enabled

Ghost discharge signal turns on for 2 clks

during dead time between Y*CNT.

During normal operation, ghost discharge signal will be always low. When ghost image prevention function is

enabled through register 04h, ghost discharge signal will turn on for 2 clks cycle during 4 clks dead time

between each YCNT. During on period of 2 clks cycle, output Z pin will be forced to half of VCC.

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OPERATION ( continued )

9. Ghost Image Prevention Function (continued)

Example of RGB LED connection

To minimize ghost image, it is recommended to use LED with same forward voltage drop in LED panel. If user

wants to use LED with different forward voltage drop in LED panel (e.g. RGB LED in LED panel), it is

recommended that all the cathodes of LED connected to the same pin must have same forward voltage drop.

(i.e. same colour LED sharing the same cathode). A recommended RGB LED connection to minimize ghost

image is shown in diagram below.

LED1-B

Connected

pin name

LED1-G LED1-R

LED2-RLED2-GLED2-B

LED3-B LED3-RLED3-G

LED4-RLED4-B LED4-G

1 2 3 4

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Product Standards

PACKAGE INFORMATION ( Reference Data )

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Product Standards

IMPORTANT NOTICE

1. When using the LSI for new models, verify the safety including the long-term reliability for each product.

2. When the application system is designed by using this LSI, please confirm the notes in this book.

Please read the notes to descriptions and the usage notes in the book.

3. This LSI is intended to be used for general electronic equipment.

Consult our sales staff in advance for information on the following applications: Special applications in which exceptional

quality and reliability are required, or if the failure or malfunction of this LSI may directly jeopardize life or harm the human

body.

Any applications other than the standard applications intended.

(1) Space appliance (such as artificial satellite, and rocket)

(2) Traffic control equipment (such as for automobile, airplane, train, and ship)

(3) Medical equipment for life support

(4) Submarine transponder

(5) Control equipment for power plant

(6) Disaster prevention and security device

(7) Weapon

(8) Others : Applications of which reliability equivalent to (1) to (7) is required

Our company shall not be held responsible for any damage incurred as a result of or in connection with the LSI being used for

any special application, unless our company agrees to the use of such special application.

4. This LSI is neither designed nor intended for use in automotive applications or environments unless the specific product is

designated by our company as compliant with the ISO/TS 16949 requirements.

Our company shall not be held responsible for any damage incurred by customers or any third party as a result of or in

connection with the LSI being used in automotive application, unless our company agrees to such application in this book.

5. Please use this product in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled

substances, including without limitation, the EU RoHS Directive. Our company shall not be held responsible for any damage

incurred as a result of our LSI being used by our customers, not complying with the applicable laws and regulations.

6. Pay attention to the direction of LSI. When mounting it in the wrong direction onto the PCB (printed-circuit-board), it might emit

smoke or ignite.

7. Pay attention in the PCB (printed-circuit-board) pattern layout in order to prevent damage due to short circuit between pins. In

addition, refer to the Pin Description for the pin configuration.

8. Perform visual inspection on the PCB before applying power, otherwise damage might happen due to problems such as

solder-bridge between the pins of the semiconductor device. Also, perform full technical verification on the assembly quality,

because the same damage possibly can happen due to conductive substances, such as solder ball, that adhere to the LSI

during transportation.

9. Take notice in the use of this product that it might be damaged or occasionally emit smoke when an abnormal state occurs

such as output pin-VCC short (Power supply fault), output pin-GND short (Ground fault), or output-to-output-pin short (load

short). Safety measures such as installation of fuses are recommended because the extent of the above-mentioned damage

and smoke emission will depend on the current capability of the power supply..

10. The protection circuit is for maintaining safety against abnormal operation. Therefore, the protection circuit should not work

during normal operation.

Especially for the thermal protection circuit, if the area of safe operation or the absolute maximum rating is momentarily

exceeded due to output pin to VCC short (Power supply fault), or output pin to GND short (Ground fault), the LSI might be

damaged before the thermal protection circuit could operate.

11. Unless specified in the product specifications, make sure that negative voltage or excessive voltage are not applied to the

pins because the device might be damaged, which could happen due to negative voltage or excessive voltage generated

during the ON and OFF timing when the inductive load of a motor coil or actuator coils of optical pick-up is being driven.

12. Verify the risks which might be caused by the malfunctions of external components.

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Request for your special attention and precautions in using the technical information and

semiconductors described in this book

(1) If any of the products or technical information described in this book is to be exported or provided to non-residents, the laws and

regulations of the exporting country, especially, those with regard to security export control, must be observed.

(2) The technical information described in this book is intended only to show the main characteristics and application circuit examples

of the products. No license is granted in and to any intellectual property right or other right owned by Panasonic Corporation or any

other company. Therefore, no responsibility is assumed by our company as to the infringement upon any such right owned by any

other company which may arise as a result of the use of technical information described in this book.

(3) The products described in this book are intended to be used for general applications (such as office equipment, communications

equipment, measuring instruments and household appliances), or for specific applications as expressly stated in this book.

Consult our sales staff in advance for information on the following applications:

– Special applications (such as for airplanes, aerospace, automotive equipment, traffic signaling equipment, combustion equipment,

life support systems and safety devices) in which exceptional quality and reliability are required, or if the failure or malfunction of

the products may directly jeopardize life or harm the human body.

It is to be understood that our company shall not be held responsible for any damage incurred as a result of or in connection with

your using the products described in this book for any special application, unless our company agrees to your using the products in

this book for any special application.

(4) The products and product specifications described in this book are subject to change without notice for modification and/or im-

provement. At the final stage of your design, purchasing, or use of the products, therefore, ask for the most up-to-date Product

Standards in advance to make sure that the latest specifications satisfy your requirements.

(5) When designing your equipment, comply with the range of absolute maximum rating and the guaranteed operating conditions

(operating power supply voltage and operating environment etc.). Especially, please be careful not to exceed the range of absolute

maximum rating on the transient state, such as power-on, power-off and mode-switching. Otherwise, we will not be liable for any

defect which may arise later in your equipment.

Even when the products are used within the guaranteed values, take into the consideration of incidence of break down and failure

mode, possible to occur to semiconductor products. Measures on the systems such as redundant design, arresting the spread of fire

or preventing glitch are recommended in order to prevent physical injury, fire, social damages, for example, by using the products.

(6) Comply with the instructions for use in order to prevent breakdown and characteristics change due to external factors (ESD, EOS,

thermal stress and mechanical stress) at the time of handling, mounting or at customer's process. When using products for which

damp-proof packing is required, satisfy the conditions, such as shelf life and the elapsed time since first opening the packages.

(7) This book may be not reprinted or reproduced whether wholly or partially, without the prior written permission of our company.

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