SN55107A, SN55107B, SN55108A, SN55108B
SN75107A, SN75107B, SN75108A, SN75108B
DUAL LINE RECEIVERS
SLLS069B – JANUARY 1977 – REVISED MAY 1995
Copyright 1995, Texas Instruments Incorporated
2–1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
•High Speed
•Standard Supply Voltage
•Dual Channels
•High Common-Mode Rejection Ratio
•High Input Impedance
•High Input Sensitivity
•Differential Common-Mode Input Voltage
Range of ±3 V
•Strobe Inputs for Receiver Selection
•Gate Inputs for Logic Versatility
•TTL Drive Capability
•High dc Noise Margin
•’107A and ’107B Have Totem-Pole Outputs
•’108A and ’108B Have Open-Collector
Outputs
•B Versions Have Diode-Protected Input for
Power-Off Condition
description
These circuits are TTL-compatible, high-speed
line receivers. Each is a monolithic dual circuit
featuring two independent channels. They are
designed for general use as well as such specific
applications as data comparators and balanced,
unbalanced, and party-line transmission systems.
These devices are unilaterally interchangeable
with and are replacements for the SN55107,
SN55108, SN75107, and SN75108, but offer
diode-clamped strobe inputs to simplify circuit
design.
The essential difference between the A and B versions can be seen in the schematics. Input-protection diodes
are in series with the collectors of the differential-input transistors of the B versions. These diodes are useful
in certain party-line systems that may have multiple VCC+ power supplies and may be operated with some of
the VCC+ supplies turned off. In such a system, if a supply is turned off and allowed to go to ground, the equivalent
input circuit connected to that supply would be as follows:
Input
A Version
Input
B Version
This would be a problem in specific systems that might possibly have the transmission lines biased to some
potential greater than 1.4 V.
The SN55107A, SN55107B, SN55108A, and SN55108B are characterized for operation over the full military
temperature range of –55°C to 125°C. The SN75107A, SN75107B, SN75108A, and SN75108B are
characterized for operation from 0°C to 70°C.
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1A
1B
NC
1Y
1G
S
GND
VCC+
VCC–
2A
2B
NC
2Y
2G
SN55107A, SN55107B, SN55108A,
SN55108B ... J OR W PACKAGE
SN75107A, SN75107B, SN75108A,
SN75108B . . . D, J, OR N PACKAGE
(TOP VIEW)
3 2 1 20 19
910111213
4
5
6
7
8
18
17
16
15
14
2A
NC
2B
NC
NC
NC
NC
1Y
NC
1G
SN55107A, SN55107B, SN55108A,
SN55108B . . . FK PACKAGE
(TOP VIEW)
1B
1A
NC
2Y
S
GND
NC
NC – No internal connection
CC +
V
2G CC –
V
THE SN75108B IS NOT
RECOMMENDED FOR NEW DESIGN
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
SN55107A, SN55107B, SN55108A, SN55108B
SN75107A, SN75107B, SN75108A, SN75108B
DUAL LINE RECEIVERS
SLLS069B – JANUAR Y 1977 – REVISED MAY 1995
2–2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic symbols†
2G
2B
2A
1G
1B
1A
S
8
11
12
5
2
1
6
2Y
1Y
9
4
&
EN
SN55107
SN75107
2G
2B
2A
1G
1B
1A
S
8
11
12
5
2
6
2Y
1Y
9
4
&
EN
SN55108
SN75108
1
†These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, J, N, and W packages.
logic diagram (positive logic)
2B
2A
2G
1G
1B
1A
S
11
12
8
5
2
1
6
2Y
1Y
9
4
FUNCTION TABLE
DIFFERENTIAL INPUTS STROBES OUTPUT
A – B G S Y
VID ≥ 25 mV X X H
X L H
–25 mV < VID < 25 mV L X H
H H Indeterminate
X L H
VID ≤ –25 mV L X H
H H L
H = high level, L = low level, X = irrelevant
SN55107A, SN55107B, SN55108A, SN55108B
SN75107A, SN75107B, SN75108A, SN75108B
DUAL LINE RECEIVERS
SLLS069B – JANUAR Y 1977 – REVISED MAY 1995
2–3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
schematic (each receiver)
To Other Receiver
Output Y
GND
Strobe G
Strobe S
4, 9
7
5, 8
6
800 Ω
Common
to Both
Receivers
1 kΩ1 kΩ400 Ω4 kΩ1.6 kΩ120 Ω
4.8 kΩ
760 ΩR†
4.25 kΩ
3 kΩ3 kΩ
13
2, 11
1, 12
14
VCC +
A
B
Inputs
VCC –
Pin numbers shown are for D, J, N, and W packages.
†R = 1 kΩ for ’107A and ’107B, 750 Ω for ’108A and ’108B.
NOTES: 1. Resistor values shown are nominal.
2. Components shown with dashed lines in the output circuitry are applicable to the ’107A and ’107B only. Diodes in series with the
collectors of the differential input transistors are short circuited on ’107A and ’108A.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡
Supply voltage, VCC+ (see Note 3) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply voltage, VCC– –7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Differential input voltage, V ID (see Note 4) ±6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Common-mode input voltage, VIC (see Note 5) ±5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Strobe input voltage 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, TA: SN55’ –55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN75’ 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Case temperature for 60 seconds, Tc: FK package 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J package 300°C. . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D, N, or W package 260°C. . . . . . . . . . . . .
‡Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTES: 3. All voltage values, except differential voltages, are with respect to network ground terminal.
4. Differential voltage values are at the noninverting (A) terminal with respect to the inverting (B) terminal.
5. Common-mode input voltage is the average of the voltages at the A and B inputs.
SN55107A, SN55107B, SN55108A, SN55108B
SN75107A, SN75107B, SN75108A, SN75108B
DUAL LINE RECEIVERS
SLLS069B – JANUAR Y 1977 – REVISED MAY 1995
2–4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DISSIPATION RATING TABLE
PACKAGE TA ≤ 25°C
POWER RATING DERATING F ACTOR
ABOVE TA = 25°CTA = 70°C
POWER RATING TA = 125°C
POWER RATING
D950 mW 7.6 mW/°C 608 mW —
FK 1375 mW 11.0 mW/°C 880 mW 275 mW
J (SN5510_A,B) 1375 mW 11.0 mW/°C 880 mW 275 mW
J (SN7510_A,B) 1025 mW 8.2 mW/°C 656 mW —
N 1150 mW 9.2 mW/°C 736 mW —
W1000 mW 8.0 mW/°C 640 mW 200 mW
recommended operating conditions (see Note 6)
SN55107A, SN55107B SN75107A, SN75107B
,
SN55108A, SN55108B
,
SN75108A, SN75108B UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, VCC+ 4.5 5 5.5 4.75 5 5.25 V
Supply voltage, VCC– –4.5 –5 –5.5 –4.75 –5 –5.25 V
High-level input voltage between differential inputs, VIDH (see Note 7) 0.025 5 0.025 5 V
Low-level input voltage between differential inputs, VIDL (see Note 7) –5†–0.025 –5†–0.025 V
Common-mode input voltage, VIC (see Notes 7 and 8) –3†3 –3†3 V
Input voltage, any differential input to GND (see Note 8) –5†3 –5†3 V
High-level input voltage at strobe inputs, VIH(S) 25.5 2 5.5 V
Low-level input voltage at strobe inputs, VIL(S) 00.8 0 0.8 V
Low-level output current, IOL –16 –16 mA
Operating free-air temperature, TA–55 125 0 70 °C
†The algebraic convention, in which the less positive (more negative) limit is designated as minimum, is used in this data sheet for input voltage
levels only.
NOTES: 6. When using only one channel of the line receiver, the strobe G of the unused channel should be grounded and at least one of the
differential inputs of the unused receiver should be terminated at some voltage between –3 V and 3 V.
7. The recommended combinations of input voltages fall within the shaded area in Figure 1.
8. The common-mode voltage may be as low as –4 V provided that the more positive of the two inputs is not more negative than
–3 V.
SN55107A, SN55107B, SN55108A, SN55108B
SN75107A, SN75107B, SN75108A, SN75108B
DUAL LINE RECEIVERS
SLLS069B – JANUAR Y 1977 – REVISED MAY 1995
2–5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
–1
–3
–4
–5
–5 –4 –3 –2 –1 0
Input A to GND Voltage – V
1
2
Input B to GND Voltage – V
RECOMMENDED COMBINATIONS
OF INPUT VOLTAGES
3
123
0
–2
Figure 1. Recommended Combinations of Input Voltages
SN55107A, SN55107B, SN55108A, SN55108B
SN75107A, SN75107B, SN75108A, SN75108B
DUAL LINE RECEIVERS
SLLS069B – JANUAR Y 1977 – REVISED MAY 1995
2–6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS†
’107A, ’107B ’108A, ’108B
UNIT
PARAMETER
TEST
CONDITIONS†
MIN TYP‡MAX MIN TYP‡MAX
UNIT
VOH
High level out
p
ut voltage
VCC± = MIN, VIL(S) = 0.8 V,
VIDH 25 mV IOH 400 µA
24
V
V
OH
High
-
le
v
el
o
u
tp
u
t
v
oltage
V
IDH =
25
m
V
,
I
OH = –
400
µ
A
,
VIC = –3 V to 3 V
2
.
4
V
VOL
Low level out
p
ut voltage
VCC± = MIN, VIH(S) = 2 V,
VIDL 25 mV IOL 16 mA
04
04
V
V
OL
Lo
w-
le
v
el
o
u
tp
u
t
v
oltage
V
IDL = –
25
m
V
,
I
OL =
16
m
A
,
VIC = –3 V to 3 V
0
.
4
0
.
4
V
IIH
High-level A
VCC±= MAX
VID = 5 V 30 75 30 75
µA
I
IH
input current B
V
CC± =
MAX
VID = –5 V 30 75 30 75 µ
A
IIL
Low-level A
VCC±= MAX
VID = –5 V –10 –10
µA
I
IL input current B
V
CC± =
MAX
VID = 5 V –10 –10 µ
A
IIH
High-level input current VCC± = MAX, VIH(G) = 2.4 V 40 40 µA
I
IH
g
into 1G or 2G VCC± = MAX, VIH(G) = MAX VCC+ 1 1 mA
IIL
Low-level input current
VCC±= MAX VIL(G) =04V
16
16
mA
I
IL into 1G or 2G
V
CC± =
MAX
,
V
IL(G) =
0
.
4
V
–
1
.
6
–
1
.
6
mA
IIH
High-level input VCC± = MAX, VIH(S) = 2.4 V 80 80 µA
I
IH
g
current into S VCC± = MAX, VIH(S) = MAX VCC+ 2 2 mA
IIL
Low-level input
VCC±= MAX VIL(S)=04V
32
32
mA
I
IL current into S
V
CC± =
MAX
,
V
IL(S)=
0
.
4
V
–
3
.
2
–
3
.
2
mA
IOH
High-level
VCC±= MIN VOH = MAX VCC
250
µA
I
OH
g
output current
V
CC± =
MIN
,
V
OH =
MAX
V
CC+
250
µ
A
IOS
Short-circuit
VCC±= MAX
18
70
mA
I
OS output current§
V
CC± =
MAX
–
18
–
70
mA
ICCH
Supply current from
VCC±= MAX TA=25
°
C
18
30
18
30
mA
I
CCH+
y
VCC+, outputs high
V
CC± =
MAX
,
T
A =
25°C
18
30
18
30
mA
ICCH– Supply current from
VCC–, outputs high VCC± = MAX, TA = 25°C –8.4 –15 –8.4 –15 mA
†For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
‡All typical values are at VCC+ = 5 V, VCC– = –5 V, T A = 25°C.
§Not more than one output should be shorted at a time.
switching characteristics, VCC± = ±5 V, TA = 25°C, RL = 390 Ω (see Figure 2)
PARAMETER
TEST ’107A, ’107B ’108A, 108B
UNIT
PARAMETER
CONDITIONS MIN TYP MAX MIN TYP MAX
UNIT
tPLH(D)
Propagation delay time, low- to high-level output, CL = 50 pF 17 25
ns
t
PLH(D)
gy,g ,
from differential inputs A and B CL = 15 pF 19 25
ns
tPHL(D)
Propagation delay time, high- to low-level output, CL = 50 pF 17 25
ns
t
PHL(D)
gy,g ,
from differential inputs A and B CL = 15 pF 19 25
ns
tPLH(S)
Propagation delay time, low- to high-level output, CL = 50 pF 10 15
ns
t
PLH(S)
gy,g ,
from strobe input G or S CL = 15 pF 13 20
ns
tPHL(S)
Propagation delay time, high- to low-level output, CL = 50 pF 8 15
ns
t
PHL(S)
gyg
from strobe input G or S CL = 15 pF 13 20
ns
SN55107A, SN55107B, SN55108A, SN55108B
SN75107A, SN75107B, SN75108A, SN75108B
DUAL LINE RECEIVERS
SLLS069B – JANUAR Y 1977 – REVISED MAY 1995
2–7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
1.5 V
Pulse
Generator
(see Note A)
Differential
Input VCC–
1G S2G
V
CC+
50 Ω
390 Ω
390 Ω
Output
‘107A, ‘107B
(see Note D)
(see Note C)
50 pF
50 Ω
Vref
100 mV
1A
1B
2A
2B
1Y
2Y
15 pF
Output
‘108A, ‘108B
CL
Strobe
Input
(see Note B)
TEST CIRCUIT
VOLTAGE WAVEFORMS
1.5 V 1.5 V
1.5 V
100 mV 100 mV 200 mV
0 V
3 V
VOH
VOL
1.5 V 1.5 V
tPLH(S) tPHL(S)
tPLH(D) tPHL(D)
Output Y
Input A
Strobe Input
G or S
CL
Pulse
Generator
(see Note A)
(see Note C)
tp2
tp1
NOTES: A. The pulse generators have the following characteristics: ZO = 50 Ω, tr = 10 ± 5 ns, tf = 10 ± 5 ns, tpd1 = 500 ns, PRR ≤ 1 MHz,
tpd2 = 1 µs, PRR ≤ 500 kHz.
B. Strobe input pulse is applied to Strobe 1G when inputs 1A-1B are being tested, to Strobe S when inputs 1A-1B or 2A-2B are being
tested, and to Strobe 2G when inputs 2A-2B are being tested.
C. CL includes probe and jig capacitance.
D. All diodes are 1N916.
Figure 2. Test Circuit and Voltage Waveforms
SN55107A, SN55107B, SN55108A, SN55108B
SN75107A, SN75107B, SN75108A, SN75108B
DUAL LINE RECEIVERS
SLLS069B – JANUAR Y 1977 – REVISED MAY 1995
2–8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS†
–75
TA – Free-Air Temperature – °C
100
125
0–25 0 25 50 75 100
20
40
60
80
VCC± = ±5 V
–40
VID – Differential Input Voltage – mV
6
40
0–30 –20 –10 0 10 20 30
1
2
3
4
5
VCC± = ±5 V
RL = 400 Ω
TA = 25°C
’108A, ’108B
Inverting
Inputs Inputs
Noninverting
’107A, ’107B
VO – Output Voltage – V
OUTPUT VOLTAGE
vs
DIFFERENTIAL INPUT VOLTAGE
IIH – High-Level Input Current –
HIGH-LEVEL INPUT CURRENT (1A OR 2A)
vs
FREE-AIR TEMPERATURE
–50
ÁÁ
ÁÁ
VO
IIH Aµ
Figure 3 Figure 4
40
0
5
10
15
20
25
30
35
–75
TA – Free-Air Temperature – °C
125–50 –25 0 25 50 75 100
tPLH(D)
tPHL(D)
30
0
5
10
15
20
25
1007550250–25–50 125
TA – Free-Air Temperature – °C
–75
VCC± = ±5 V
ICC+
ICC–
– Supply Current – mA
SUPPPLY CURRENT (OUTPUTS HIGH)
vs
FREE-AIR TEMPERATURE
Propagation Delay Time – ns
PROPAGATION DELAY TIME
(DIFFERENTIAL INPUTS)
vs
FREE-AIR TEMPERATURE
CL = 50 pF
RL = 390 Ω
VCC± = ±5 V
| ICCH |
tpd –
Figure 5 Figure 6
†Values below 0°C and above 70°C apply to SN55’ only.
SN55107A, SN55107B, SN55108A, SN55108B
SN75107A, SN75107B, SN75108A, SN75108B
DUAL LINE RECEIVERS
SLLS069B – JANUAR Y 1977 – REVISED MAY 1995
2–9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS†
RL = 390 Ω
RL = 1950 Ω
–75
TA – Free-Air Temperature – °C
40
125
0–50 –25 0 25 50 75 100
5
10
15
20
25
30
35
–75
TA – Free-Air Temperature – °C
120
125
0–50 –25 0 25 50 75 100
20
40
80
100
60
RL = 1950 Ω
RL = 390 Ω
tPLH(D) – Propagation Delay Time – ns
PROPAGATION DELAY TIME (LOW-TO-HIGH LEVEL)
(DIFFERENTIAL INPUTS)
vs
FREE-AIR TEMPERATURE
PROPAGATION DELAY TIME (LOW-TO-HIGH LEVEL)
(DIFFERENTIAL INPUTS)
vs
FREE-AIR TEMPERATURE
CL = 15 pF
VCC± = ±5 V
PLH(D)
t
tPLH(D) – Propagation Delay Time – ns
PLH(D)
t
RL = 3900 Ω
VCC ± = ±5 V
CL = 15 pF
RL = 3900 Ω
Figure 7 Figure 8
1007550250–25–50 125
TA – Free-Air Temperature – °C
–75
35
30
25
20
15
10
5
0
40
1007550250–25–50 125
TA – Free-Air Temperature – °C
–75
35
30
25
20
15
10
5
0
40
– Propagation Delay Time – ns
’108A, ’108B
PROPAGATION DELAY TIME (STROBE INPUTS)
vs
FREE-AIR TEMPERATURE
’108A, ’108B
PROPAGATION DELAY TIME (STROBE INPUTS)
vs
FREE-AIR TEMPERATURE
tPLH(S)
tPHL(S)
tPLH(S)
tPHL(S)
tpd
– Propagation Delay Time – ns
tpd
VCC± = ±5 V
RL = 390 Ω
CL = 50 pF
VCC± = ±5 V
RL = 390 Ω
CL = 15 pF
Figure 9 Figure 10
†Values below 0°C and above 70°C apply to SN55’ only.
SN55107A, SN55107B, SN55108A, SN55108B
SN75107A, SN75107B, SN75108A, SN75108B
DUAL LINE RECEIVERS
SLLS069B – JANUAR Y 1977 – REVISED MAY 1995
2–10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
basic balanced-line transmission system
The ’107A, ’107B, ’108A, and ’108B dual line circuits are designed specifically for use in high-speed data
transmission systems that utilize balanced terminated transmission lines such as twisted-pair lines. The system
operates in the balanced mode, so noise induced on one line is also induced on the other. The noise appears
common mode at the receiver input terminals where it is rejected. The ground connection between the line driver
and receiver is not part of the signal circuit so that system performance is not affected by circulating ground
currents.
The unique driver-output circuit allows terminated transmission lines to be driven at normal line impedances.
High-speed system operation is ensured since line reflections are virtually eliminated when terminated lines are
used. Crosstalk is minimized by low signal amplitudes and low line impedances.
The typical data delay in a system is approximately 30 + 1.3 L ns, where L is the distance in feet separating the
driver and receiver. This delay includes one gate delay in both the driver and receiver.
Data is impressed on the balanced-line system by unbalancing the line voltages with the driver output current.
The driven line is selected by appropriate driver-input logic levels. The voltage difference is approximately:
VDIFF ≈ 1/2IO(on) • RT
High series line resistance will cause degradation of the signal. The receivers, however, will detect signals as
low as 25 mV (or less). For normal line resistances, data may be recovered from lines of several thousand feet
in length.
Line-termination resistors (RT) are required only at the extreme ends of the line. For short lines, termination
resistors at the receiver only may prove adequate. The signal amplitude will then be approximately:
VDIFF ≈ IO(on) • RT
Transmission Line Having
Characteristic Impedance ZO
RT = ZO/2
L
RT
RT
A
B
C
DStrobes
RT
RT
Y
Receiver
‘107A, ‘107B, ‘108A,
‘108B
Driver
SN55109A, SN551 10A,
SN75109A, SN751 10A,
SN75112
Data Input
Inhibit
Figure 11. Typical Differential Data Line
data-bus or party-line system
The strobe feature of the receivers and the inhibit feature of the drivers allow these dual line circuits to be used
in data-bus or party-line systems. In these applications, several drivers and receivers may share a common
transmission line. An enabled driver transmits data to all enabled receivers on the line while other drivers and
receivers are disabled. Data is thus time multiplexed on the transmission line. The device specifications allow
widely varying thermal and electrical environments at the various driver and receiver locations. The data-bus
system offers maximum performance at minimum cost.
SN55107A, SN55107B, SN55108A, SN55108B
SN75107A, SN75107B, SN75108A, SN75108B
DUAL LINE RECEIVERS
SLLS069B – JANUAR Y 1977 – REVISED MAY 1995
2–11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
C
RT
RT
RT
RT
Drivers
SN55109A, SN55110A,
SN75109A, SN751 10A,
SN75112 Receiver 1 Receiver 2 Receiver 4
Driver 1 Driver 3 Driver 4
Location 1 Location 3 Location 4
Strobes
Receivers
‘107A, ‘107B,
‘108A, ‘108B
Location 2
Data
Input
Inhibit
A
B
C
D
A
BB
A
C
DD
YY Y
Strobes Strobes
Figure 12. Typical Differential Party Line
unbalanced or single-line systems
These dual-line circuits may also be used in unbalanced or single-line systems. Although these systems do not
offer the same performance as balanced systems for long lines, they are adequate for very short lines where
environmental noise is not severe.
The receiver threshold level is established by applying a dc reference voltage to one receiver input terminal.
The signal from the transmission line is applied to the remaining input. The reference voltage should be
optimized so that signal swing is symmetrical about it for maximum noise margin. The reference voltage should
be in the range of –3 V to 3 V. It can be provided by a voltage supply or by a voltage divider from an available
supply voltage.
A single-ended output from a driver may be used in single-line systems. Coaxial or shielded line is preferred
for minimum noise and crosstalk problems. For large signal swings, the high output current (typically 27 mA)
of the SN75112 is recommended. Drivers may be paralleled for higher current. When using only one channel
of the line drivers, the other channel should be inhibited and/or have its outputs grounded.
Input
Vref
Input
Inhibit
SN55109A, SN55110A,
SN75109A, SN751 10A,
SN75112
A
B
C
D
Output
VO = –IO • R
R‘107A, ‘107B,
‘108A, ‘108B
Strobes
Output
Figure 13. Single-Ended Operation
Output
‘108A, ‘108B
‘108A, ‘108B
SN5401/SN7401 or
Equivalent Dot-AND
Connection
Figure 14. Dot-AND Connection
Table 2. Typical Propagation Delays for Receiver
With Attenuator Test Circuit Shown in Figure 14
DEVICE TYPICAL
(ns)
’107A,’107B
INPUT
ATTENUATOR
20
32
42
22
31
33
36
47
57
29
38
41
PARAMETERS
1
2
3
1
2
3
1
2
3
1
2
3
tPLH
tPHL
tPLH
tPHL
’108A,’108B
SN55107A, SN55107B, SN55108A, SN55108B
SN75107A, SN75107B, SN75108A, SN75108B
DUAL LINE RECEIVERS
SLLS069B – JANUAR Y 1977 – REVISED MAY 1995
2–12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
’108A, ’108B dot-AND output connections
The ’108A, ’108B line receivers feature an
open-collector-output circuit that can be con-
nected in the dot-AND logic configuration with
other similar open-collector outputs. This allows a
level of logic to be implemented without additional
logic delay.
increasing common-mode input voltage range
of receiver
The common-mode voltage range (CMVR) is
defined as the range of voltage applied
simultaneously to both input terminals that if exceeded does not allow normal operation of the receiver.
The recommended operating CMVR is ±3 V, making it useful in all but the noisiest environments. In extremely
noisy environments, common-mode voltage can easily reach ±10 V to ±15 V if some precautions are not taken
to reduce ground and power supply noise, as well as crosstalk problems. When the receiver must operate in
such conditions, input attenuators should be used to decrease the system common-mode noise to a tolerable
level at the receiver inputs. Differential noise is also reduced by the same ratio. These attenuators have been
intentionally omitted from the receiver input terminals so the designer may select resistors that will be compatible
with his particular application or environment. Furthermore, the use of attenuators adversely affects the input
sensitivity, the propagation delay time, the power dissipation, and in some cases (depending on the selected
resistor values) the input impedance, therefore, reducing the versatility of the receiver.
The ability of the receiver to operate with approximately ±15 V common-mode voltage at the inputs has been
checked using the circuit shown in Figure 15. The resistors R1 and R2 provide a voltage divider network.
Dividers with three different values presenting a 5-to-1 attenuation were used so as to operate the dif ferential
inputs at approximately ±3 V common-mode voltage. Careful matching of the two attenuators is needed so as
to balance the overdrive at the input stage. The resistors used are shown in Table 1.
Table 2 shows some of the typical switching results obtained under such conditions.
Table 1
Attenuator 1: R1 = 2 kΩ,R2 = 0.5 kΩ
Attenuator 2: R1 = 6 kΩ, R2 = 1.5 kΩ
Attenuator 3: R1 = 12 kΩ,R2 = 3 kΩ
SN55107A, SN55107B, SN55108A, SN55108B
SN75107A, SN75107B, SN75108A, SN75108B
DUAL LINE RECEIVERS
SLLS069B – JANUAR Y 1977 – REVISED MAY 1995
2–13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
R1 R2
Receiver
One Attenuator
on Each Input
16 V
– 14 V
or
14 V
– 16 V
15 V or –15 V R1 R2
5 V
5 V
RL = 390 Ω
Figure 15. Common-Mode Circuit for Testing Input Attenuators With Results Shown In Table 2
Two methods of terminating a transmission line to reduce reflections are:
R2R3 R3R3
Method 1 R1
R2
R2
R3
R1
R3 = R1 + R2 = ZO/2
Method 2 R1
R2
R3
R1
R3
R1 + R2 > ZO
R3 = ZO/2
Figure 16. Termination Techniques
The first method uses the resistors as the attenuation network and line termination. The second method uses two
additional resistors for the line terminations.
SN55107A, SN55107B, SN55108A, SN55108B
SN75107A, SN75107B, SN75108A, SN75108B
DUAL LINE RECEIVERS
SLLS069B – JANUAR Y 1977 – REVISED MAY 1995
2–14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
For party-line operation, method 2 should be used as follows:
Attenuation Network
R3
+
ZO
2R3
+
ZO
2R3
+
ZO
2R3
+
ZO
2
Figure 17. Party-Line Termination Technique
To minimize the loading, the values of R1 and R2 should be fairly large. Examples of possible values are shown
in Table 1.
furnace control using the SN75108A
The furnace control circuit in Figure 18 is an example of the possible use of the SN55107A Series in areas other
than what would normally be considered electronic systems. Basically, a description of the operation of this
control follows. When the room temperature is below the desired level, the resistance of the room temperature
sensor is high and channel 1 noninverting input is below (less positive than) the reference level set on the input
differential amplifier . This situation causes a low output, operating the heat on relay and turning on the heat. The
channel 2 noninverting input is below the reference level when the bonnet temperature of the furnace reaches
the desired level. This causes a low output thus operating the blower relay. Normally the furnace is shut down
when the room temperature reaches the desired level and the channel 1 output goes high, turning the heat off.
The blower remains on as long as the bonnet temperature is high, even after the heat on relay is off. There is
also a safety switch in the bonnet that shuts the furnace down if the temperature there exceeds desired
limitations. The types of temperature-sensing devices and bias-resistor values used are determined by the
particular operating conditions encountered.
1 Y
+ T Room
Temp.
Sensor – T
Blower on Control
Room
Temp.
Setting
A
B
2A
2B
2 Y
To Heat on
Relay Return
To Blower
Relay Return
Bonnet Upper
Limit Switch
Channel 1
Channel 2
Bonnet
Temp.
Sensor
5 V
Figure 18. Furnace Control Using SN75108A
SN55107A, SN55107B, SN55108A, SN55108B
SN75107A, SN75107B, SN75108A, SN75108B
DUAL LINE RECEIVERS
SLLS069B – JANUAR Y 1977 – REVISED MAY 1995
2–15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
repeaters for long lines
In some cases, the driven line may be so long that the noise level on the line reaches the common-mode limits
or the attenuation becomes too large and results in poor reception. In such a case, a simple application of a
receiver and a driver as repeaters [shown in Figure 19(a)] restores the signal level and allows an adequate signal
level at the receiving end. If multichannel operation is desired, then proper gating for each channel must be sent
through the repeater station using another repeater set as in Figure 19(b).
Driver
Strobe
Ckt
P
Receiver
P
P P
P P
Data In
Clock In
Data Out
(a) SINGLE-CHANNEL LINE
(b) MULTICHANNEL LINE WIDTH WITH STROBE
Repeaters
Data In
Driver Receiver
Driver Receiver Driver Receiver
Receiver Driver Receiver
Data Out
Figure 19. Receiver-Driver Repeaters
receiver as dual differential comparator
There are many applications for differential comparators, such as voltage comparison, threshold detection,
controlled Schmitt triggering, and pulse-width control.
As a differential comparator, a ’107A or ’108A may be connected to compare the noninverting input terminal with
the inverting input as shown in Figure 20. Thus the output will be high or low resulting from the A input being
greater or less than the reference. The strobe inputs allow additional control over the circuit so that either output
or both may be inhibited.
Strobe 1, 2
Reference 1
Reference 2
Strobe 2
Strobe 1
Output 1
Output 2
1A
1B
2A
2B
Figure 20. SN55107A Series Receiver as a Dual Differential Comparator
SN55107A, SN55107B, SN55108A, SN55108B
SN75107A, SN75107B, SN75108A, SN75108B
DUAL LINE RECEIVERS
SLLS069B – JANUAR Y 1977 – REVISED MAY 1995
2–16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
window detector
The window detector circuit in Figure 21 has a large number of applications in test equipment and in determining
upper limits, lower limits, or both at the same time – such as detecting whether a voltage or signal has exceeded
its limits or window. Illumination of the upper-limit (lower-limit) indicator shows that the input voltage is above
(below) the selected upper (lower) limit. A mode selector is provided for selecting the desired test. For window
detecting, the upper and lower limits test position is used.
Mode
Selector
1
2
3
4
500 Ω
500 Ω
5 V –5 V
1 kΩ1 kΩ
Set
Upper
Limit
Set
Lower
Limit
5 kΩ
1 kΩ
Upper-Limit
Indicator
Lower-Limit
Indicator
MODE SELECTOR LEGEND
POSITION CONDITION
1Off
2 Test for Upper Limit
3 Test for Lower Limit
4 Test for Upper and Lower Limits
5 V
Input From
Test Point
4.7 kΩ
4.7 kΩ
4.7 kΩ
Figure 21. Window Detector Using SN75108A
SN55107A, SN55107B, SN55108A, SN55108B
SN75107A, SN75107B, SN75108A, SN75108B
DUAL LINE RECEIVERS
SLLS069B – JANUAR Y 1977 – REVISED MAY 1995
2–17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
temperature controller with zero-voltage switching
The circuit in Figure 22 switches an electric-resistive heater on or off by providing negative-going pulses to the
gate of a triac during the time interval when the line voltage is passing through zero. The pulse generator is the
2N5447 and four diodes. This portion of the circuit provides negative-going pulses during the short time
(approximately 100 µs) when the line voltage is near zero. These pulses are fed to the inverting input of one
channel of the ’108A. If the room temperature is below the desired level, the resistance of the thermistor is high
and the noninverting input of channel 2 is above the reference level determined by the thermostat setting. This
provides a high-level output from channel 2. This output is ANDed with the positive-going pulses from the output
of channel 1, which are reinverted in the 2N5449.
Heater
Load
2B
120 V to
220 V, 60 Hz
5-V
Zener
– T
Thermostat
Setting
GND
Channel 1
Channel 2
10-V
Zener
250 µF
2N5449
2N5447
250 µF‘108A
VCC +VCC –
1A
1B
2A
+
+
Figure 22. Zero-Voltage Switching Temperature Controller
2–18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICA TIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1999, Texas Instruments Incorporated