CY7C1312SV18-250BZC - Cypress Semiconductor

PRELIMINARY

18-Mb Burst of 2 Pipelined SRAM with QDR™ Architecture

CY7C1303V25

CY7C1306V25

Cypress Semiconductor Corporation • 3901 North First Street • San Jose,CA 95134 • 408-943-2600

Document #: 38-05100 Rev. *B Revised February 2, 2004

Features

• Separate independent Read and Write data ports

— Supports concurrent transactions

• 167-MHz Clock for high bandwidth

— 2.5 ns Clock-to-Valid access time

• 2-Word Burst on all accesses

• Double Data Rate (DDR) interfaces on both Read & Write

Ports (data transferred at 333 MHz) @167 MHz

• Two input clocks (K and K) for precise DDR timing

— SRAM uses rising edges only

• Two output clocks (C and C) account for clock skew

and flight time mismatching

• Single multiplexed address input bus latches address

inputs for both Read and Write ports

• Separate Port Selects for depth expansion

• Synchronous internally self-timed writes

• 2.5V core power supply with HSTL Inputs and Outputs

• 13 x 15 x 1.2 mm 1.0-mm pitch fBGA package, 165 ball

(11x15 matrix) Variable drive HSTL output buffers

• Expanded HSTL output voltage (1.4V–1.9V)

• JTAG Interface

• Variable Impedance HSTL

Configurations

CY7C1303V25 – 1M x 18

CY7C1306V25 – 512K x 36

Functional Description

The CY7C1303V25 and CY7C1306V25 are 2.5V

Synchronous Pipelined SRAMs equipped with QDR™ archi-

tecture. QDR architecture consists of two separate ports to

access the memory array. The Read port has dedicated Data

Outputs to support Read operations and the Write Port has

dedicated Data inputs to support Write operations. Access to

each port is accomplished through a common address bus.

The Read address is latched on the rising edge of the K clock

and the Write address is latched on the rising edge of K clock.

QDR has separate data inputs and data outputs to completely

eliminate the need to “turn-around” the data bus required with

common I/O devices. Accesses to the CY7C1303V25/

CY7C1306V25 Read and Write ports are completely

independent of one another. All accesses are initiated

synchronously on the rising edge of the positive input clock

(K). In order to maximize data throughput, both Read and

Write ports are equipped with Double Data Rate (DDR) inter-

faces. Therefore, data can be transferred into the device on

every rising edge of both input clocks (K and K) and out of the

device on every rising edge of the output clock (C and C, or K

and K when in single clock mode) thereby maximizing perfor-

mance while simplifying system design. Each address location

is associated with two 18-bit words (CY7C1303V25) or two

36-bit words (CY7C1306V25) that burst sequentially into or

out of the device.

Depth expansion is accomplished with a Port Select input for

each port. Each Port Selects allow each port to operate

independently.

All synchronous inputs pass through input registers controlled

by the K or K input clocks. All data outputs pass through output

registers controlled by the C or C input clocks. Writes are

conducted with on-chip synchronous self-timed write circuitry.

Logic Block Diagram (CY7C1303V25)

512Kx18

CLK

(18:0)

Gen.

Control

Logic

Address

D[17:0]

Read Add. Decode

Read Data Reg.

RPS

WPS

Q[17:0]

Control

Logic

Address

Reg.

Write

BWS0

Vref

Write Add. Decode

Data Reg

Write

Data Reg

Memory

Array

512Kx18

Memory

Array

A(18:0)

BWS1

PRELIMINARY

CY7C1303V25

CY7C1306V25

Document #: 38-05100 Rev. *B Page 2 of 21

Selection Guide

7C1303V25-167

7C1306V25-167

7C1303V25-133

7C1306V25-133

7C1303V25-100

7C1306V25-100 Unit

Maximum Operating Frequency 167 133 100 MHz

Maximum Operating Current 550 470 420 mA

Logic Block Diagram (CY7C1306V25)

256Kx36

CLK

(17:0)

Gen.K

Control

Logic

Address

D[35:0]

Read Add. Decode

Read Data Reg.

RPS

WPS

Q[35:0]

Control

Logic

Address

Reg.

Write

BWS0

Vref

Write Add. Decode

Data Reg

Write

Data Reg

Memory

Array

256Kx36

Memory

Array

A(17:0)

BWS1

BWS2

BWS3

PRELIMINARY

CY7C1303V25

CY7C1306V25

Document #: 38-05100 Rev. *B Page 3 of 21

Pin Configuration - CY7C1303V25 (TOP VIEW)

1234567891011

ANC

Gnd/

144M

NC/

36M WPS BWS1KNC RPS A

Gnd/

72M NC

BNC Q9 D9 A NC K BWS0ANCNCQ8

CNC NC D10 VSS A A A VSS NC Q7 D8

DNC D11 Q10 VSS VSS VSS VSS VSS NC NC D7

ENC NC Q11 VDDQ VSS VSS VSS VDDQ NC D6 Q6

FNC Q12 D12 VDDQ VDD VSS VDD VDDQ NC NC Q5

GNC D13 Q13 VDDQ VDD VSS VDD VDDQ NC NC D5

HNC VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ

JNC NC D14 VDDQ VDD VSS VDD VDDQ NC Q4 D4

KNC NC Q14 VDDQ VDD VSS VDD VDDQ NC D3 Q3

LNC Q15 D15 VDDQ VSS VSS VSS VDDQ NC NC Q2

MNC NC D16 VSS VSS VSS VSS VSS NC Q1 D2

NNC D17 Q16 VSS A A A VSS NC NC D1

PNC NC Q17 A A C A A NC D0 Q0

RTDOTCKAAACAAATMSTDI

Pin Configuration - CY7C1306V25 (TOP VIEW)

1234567891011

ANC

Gnd/

288M NC/ 72M WPS BWS2KBWS1RPS NC/36M

Gnd/

144M NC

BQ27 Q18 D18 A BWS3KBWS

0AD17Q17Q8

CD27 Q28 D19 VSS A A A VSS D16 Q7 D8

DD28 D20 Q19 VSS VSS VSS VSS VSS Q16 D15 D7

EQ29 D29 Q20 VDDQ VSS VSS VSS VDDQ Q15 D6 Q6

FQ30 Q21 D21 VDDQ VDD VSS VDD VDDQ D14 Q14 Q5

GD30 D22 Q22 VDDQ VDD VSS VDD VDDQ Q13 D13 D5

HNC VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ

JD31 Q31 D23 VDDQ VDD VSS VDD VDDQ D12 Q4 D4

KQ32 D32 Q23 VDDQ VDD VSS VDD VDDQ Q12 D3 Q3

LQ33 Q24 D24 VDDQ VSS VSS VSS VDDQ D11 Q11 Q2

MD33 Q34 D25 VSS VSS VSS VSS VSS D10 Q1 D2

ND34 D26 Q25 VSS A A A VSS Q10 D9 D1

PQ35 D35 Q26 A A C A A Q9 D0 Q0

RTDO TCK A A A C AAATMSTDI

PRELIMINARY

CY7C1303V25

CY7C1306V25

Document #: 38-05100 Rev. *B Page 4 of 21

Pin Definitions

Name I/O Description

D[x:0] Input-

Synchronous

Data input signals, sampled on the rising edge of K and K clocks during valid write

operations.

CY7C1303V25 – D[17:0]

CY7C1306V25 – D[35:0]

WPS Input-

Synchronous

Write Port Select, active LOW. Sampled on the rising edge of the K clock. When as-

serted active, a Write operation is initiated. Deasserting will deselect the Write port.

Deselecting the Write port will cause D[x:0] to be ignored.

BWS0, BWS1,

BWS2, BWS3

Input-

Synchronous

Byte Write Select 0, 1, 2 and 3 - active LOW. Sampled on the rising edge of the K and

K clocks during Write operations. Used to select which byte is written into the device

during the current portion of the Write operations.

CY7C1303V25 - BWS0 controls D[8:0] and BWS1 controls D[17:9].

CY7C1306V25 - BWS0 controls D[8:0], BWS1 controls D[17:9], BWS2 controls D[26:18] and

BWS3 controls D[35:27]

Bytes not written remain unaltered. Deselecting a Byte Write Select will cause the cor-

responding byte of data to be ignored and not written into the device.

AInput-

Synchronous

Address Inputs. Sampled on the rising edge of the K clock during active Read opera-

tions and on the rising edge of K for Write operations. These address inputs are multi-

plexed for both Read and Write operations. Internally, the device is organized as 1M x

18 (2 arrays each of 512K x 18) for CY7C1303V25 and 512K x 36 (2 arrays each of 256K

x 36) for CY7C1306V25. Therefore, only 19 address inputs are needed to access the

entire memory array of CY7C1303V25 and 18 address inputs for CY7C1306V25. These

inputs are ignored when the appropriate port is deselected.

Q[x:0] Outputs-

Synchronous

Data Output signals. These pins drive out the requested data during a Read operation.

Valid data is driven out on the rising edge of both the C and C clocks during Read

operations or K and K when in single clock mode. When the Read port is deselected,

Q[x:0] are automatically three-stated.

CY7C1303V25 - Q[17:0]

CY7C1306V25 - Q[35:0]

RPS Input-

Synchronous

Read Port Select, active LOW. Sampled on the rising edge of positive input clock (K).

When active, a Read operation is initiated. Deasserting will cause the Read port to be

deselected. When deselected, the pending access is allowed to complete and the output

drivers are automatically three-stated following the next rising edge of the K clock. Each

read access consists of a burst of two sequential 18-bit or 36-bit transfers.

CInput-Clock Positive Output Clock Input. C is used in conjunction with C to clock out the Read data

from the device. C and C can be used together to deskew the flight times of various

devices on the board back to the controller. See application example for further details.

CInput-Clock Negative Output Clock Input. C is used in conjunction with C to clock out the Read

data from the device. C and C can be used together to deskew the flight times of various

devices on the board back to the controller. See application example for further details.

KInput-Clock Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs

to the device and to drive out data through Q[x:0] when in single clock mode. All accesses

are initiated on the rising edge of K.

KInput-Clock Negative Input Clock Input. K is used to capture synchronous inputs to the device and

to drive out data through Q[x:0] when in single clock mode.

ZQ Input Output Impedance Matching Input. This input is used to tune the device outputs to the

system data bus impedance. Q[x:0] output impedance are set to 0.2 x RQ, where RQ is

a resistor connected between ZQ and ground. Alternately, this pin can be connected

directly to VDD, which enables the minimum impedance mode. This pin cannot be con-

nected directly to GND or left unconnected.

TDO Output TDO pin for JTAG.

TCK Input TCK pin for JTAG.

TDI Input TDI pin for JTAG.

TMS Input TMS pin for JTAG.

NC/36M N/A Address expansion for 36M. This pin is not connected to the die and so can be tied to

any voltage level on CY7C1303V25/CY7C1306V25.

PRELIMINARY

CY7C1303V25

CY7C1306V25

Document #: 38-05100 Rev. *B Page 5 of 21

Introduction

Functional Overview

The CY7C1303V25/CY7C1306V25 are synchronous

pipelined Burst SRAM equipped with both a Read port and a

Write port. The Read port is dedicated to Read operations and

the Write port is dedicated to Write operations. Data flows into

the SRAM through the Write port and out through the Read

port. These devices multiplex the address inputs in order to

minimize the number of address pins required. By having

separate Read and Write ports, this architecture completely

eliminates the need to “turn-around” the data bus and avoids

any possible data contention, thereby simplifying system

design. Each access consists of two 18-bit data transfers in

the case of CY7C1303V25, and two 36-bit data transfers in the

case of CY7C1306V25, in one clock cycle.

Accesses for both ports are initiated on the rising edge of the

Positive Input Clock (K). All synchronous input timing is refer-

enced from the rising edge of the input clocks (K and K) and

all output timings are referenced to rising edge of output clocks

(C and C or K and K when in single clock mode).

All synchronous data inputs (D[x:0]) pass through input

registers controlled by the rising edge of the input clocks (K

and K). All synchronous data outputs (Q[x:0]) pass through

output registers controlled by the rising edge of the output

clocks (C and C, or K and K when in single clock mode).

All synchronous control (RPS, WPS, BWS[x:0]) inputs pass

through input registers controlled by the rising edge of input

clocks (K and K).

The following descriptions take CY7C1303V25 as an

example. The same basic descriptions apply to

CY7C1306V25.

Read Operations

The CY7C1303V25 is organized internally as 2 arrays of 512K

x 18. Accesses are completed in a burst of two sequential

18-bit data words. Read operations are initiated by asserting

RPS active at the rising edge of the positive input clock (K).

The address is latched on the rising edge of the K clock.

Following the next K clock rise the corresponding lower order

18-bit word of data is driven onto the Q[17:0] using C as the

output timing reference. On the subsequent rising edge of C

the higher order data word is driven onto the Q[17:0]. The

requested data will be valid 2.5 ns from the rising edge of the

output clock (C and C, or K and K when in single clock mode,

167-MHz device).

Synchronous internal circuitry will automatically three-state

the outputs following the next rising edge of the positive output

clock (C). This will allow for a seamless transition between

devices without the insertion of wait states in a depth

expanded memory.

Write Operations

Write operations are initiated by asserting WPS active at the

rising edge of the positive input clock (K). On the same K clock

rise the data presented to D[17:0] is latched and stored into the

lower 18-bit Write Data register provided BWS[1:0] are both

asserted active. On the subsequent rising edge of the negative

input clock (K), the address is latched and the information

presented to D[17:0] is stored into the Write Data register

provided BWS[1:0] are both asserted active. The 36 bits of data

are then written into the memory array at the specified

location.

When deselected, the Write port will ignore all inputs after the

pending Write operations have been completed.

Byte Write Operations

Byte Write operations are supported by the CY7C1303V25. A

Write operation is initiated as described in the Write Operation

section above. The bytes that are written are determined by

BWS0 and BWS1 which are sampled with each set of 18-bit

data word. Asserting the appropriate Byte Write Select input

during the data portion of a write will allow the data being

presented to be latched and written into the device.

Deasserting the Byte Write Select input during the data portion

of a write will allow the data stored in the device for that byte

to remain unaltered. This feature can be used to simplify

Read/Modify/Write operations to a Byte Write operation.

Single Clock Mode

The CY7C1303V25 can be used with a single clock mode. In

this mode the device will recognize only the pair of input clocks

(K and K) that control both the input and output registers. This

operation is identical to the operation if the device had zero

skew between the K/K and C/C clocks. All timing parameters

remain the same in this mode. To use this mode of operation,

the user must tie C and C HIGH at power-up.This function is

a strap option and not alterable during device operation.

GND/72M Input Address expansion for 72M. This pin has to be tied to GND on CY7C1303V25.

NC/72M N/A Address expansion for 72M. This pin can be tied to any voltage level on CY7C1306V25.

GND/144M Input Address expansion for 144M. This pin has to be tied to GND on

CY7C1303V25/CY7C1306V25.

GND/288M Input Address expansion for 288M. This pin has to be tied to GND on CY7C1306V25.

NC N/A Not connected to the die. Can be tied to any voltage level.

VREF Input-

Reference

Reference Voltage Input. Static input used to set the reference level for HSTL inputs

and Outputs as well as AC measurement points.

VDD Power Supply Power supply inputs to the core of the device.

VSS Ground Ground for the device.

VDDQ Power Supply Power supply inputs for the outputs of the device.

Pin Definitions (continued)

Name I/O Description

PRELIMINARY

CY7C1303V25

CY7C1306V25

Document #: 38-05100 Rev. *B Page 6 of 21

Concurrent Transactions

The Read and Write ports on the CY7C1303V25 operate

completely independently of one another. Since each port

latches the address inputs on different clock edges, the user

can Read or Write to any location, regardless of the trans-

action on the other port. Also, reads and writes can be started

in the same clock cycle. If the ports access the same location

at the same time, the SRAM will deliver the most recent infor-

mation associated with the specified address location. This

includes forwarding data from a Write cycle that was initiated

on the previous K clock rise.

Depth Expansion

The CY7C1303V25 has a Port Select input for each port. This

allows for easy depth expansion. Both Port Selects are

sampled on the rising edge of the Positive Input Clock only (K).

Each port select input can deselect the specified port.

Deselecting a port will not affect the other port. All pending

transactions (Read and Write) will be completed prior to the

device being deselected.

Programmable Impedance

An external resistor, RQ, must be connected between the ZQ

pin on the SRAM and VSS to allow the SRAM to adjust its

output driver impedance. The value of RQ must be 5X the

value of the intended line impedance driven by the SRAM, The

allowable range of RQ to guarantee impedance matching with

a tolerance of ±15% is between 175Ω and 350Ω, with

VDDQ=1.5V. The output impedance is adjusted every 1024

cycles to account for drifts in supply voltage and temperature.

Application Example[1]

Truth Table[2, 3, 4, 5, 6, 7]

Operation K RPS WPS DQ DQ

Write Cycle:

Load address on the rising edge of K clock; input write

data on K and K rising edges.

L-H X L D(A+0) at

K(t) ↑

D(A+1) at

K(t) ↑

Read Cycle:

Load address on the rising edge of K clock; wait one

cycle; read data on 2 consecutive C and C rising edges.

L-H L X Q(A+0) at

C(t+1)↑Q(A+1) at

C(t+1) ↑

NOP: No Operation L-H H H D = X

Q = High-Z

D = X

Q = High-Z

Standby: Clock Stopped Stopped X X Previous

State

Notes:

1. The above application shows 4 QDR-I being used.

2. X = Don't Care, H = Logic HIGH, L = Logic LOW, ↑represents rising edge.

3. Device will power-up deselected and the outputs in a three-state condition.

4. “A” represents address location latched by the devices when transaction was initiated. A+0, A+1 represent the addresses sequence in the burst.

5. “t” represents the cycle at which a Read/Write operation is started. t+1 is the first clock cycle succeeding the “t” clock cycle.

6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.

7. It is recommended that K = K and C = C when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging

symmetrically

PRELIMINARY

CY7C1303V25

CY7C1306V25

Document #: 38-05100 Rev. *B Page 7 of 21

Write Descriptions (CY7C1303V25)[2, 8]

BWS0BWS1KK Comments

L L L-H - During the Data portion of a Write sequence, both bytes (D[17:0]) are written into the device.

L L - L-H During the Data portion of a Write sequence, both bytes (D[17:0]) are written into the device.

L H L-H - During the Data portion of a Write sequence, only the lower byte (D[8:0]) is written into the

device. D[17:9] remains unaltered.

L H - L-H During the Data portion of a Write sequence, only the lower byte (D[8:0]) is written into the

device. D[17:9] remains unaltered.

H L L-H - During the Data portion of a Write sequence, only the byte (D[17:9]) is written into the device.

D[8:0] remains unaltered.

H L - L-H During the Data portion of a Write sequence, only the byte (D[17:9]) is written into the device.

D[8:0] remains unaltered.

H H L-H - No data is written into the device during this portion of a write operation.

H H - L-H No data is written into the device during this portion of a write operation.

Write Descriptions (CY7C1306V25)[2, 8]

BWS0BWS1BWS2BWS3KK Comments

LLLLL-H- During the Data portion of a Write sequence, all four bytes (D

[35:0]) are

written into the device.

LLLL- L-HDuring the Data portion of a Write sequence, all four bytes (D

[35:0]) are

written into the device.

L H H H L-H - During the Data portion of a Write sequence, only the lower byte (D[8:0])

is written into the device. D[35:9] will remain unaltered.

L H H H - L-H During the Data portion of a Write sequence, only the lower byte (D[8:0])

is written into the device. D[35:9] will remain unaltered.

H L H H L-H - During the Data portion of a Write sequence, only the byte (D[17:9]) is

written into the device. D[8:0] and D[35:18] will remain unaltered.

H L H H - L-H During the Data portion of a Write sequence, only the byte (D[17:9]) is

written into the device. D[8:0] and D[35:18] will remain unaltered.

H H L H L-H - During the Data portion of a Write sequence, only the byte (D[26:18]) is

written into the device. D[17:0] and D[35:27] will remain unaltered.

H H L H - L-H During the Data portion of a Write sequence, only the byte (D[26:18]) is

written into the device. D[17:0] and D[35:27] will remain unaltered.

H H H L L-H - During the Data portion of a Write sequence, only the byte (D[35:27]) is

written into the device. D[26:0] will remain unaltered.

H H H L - L-H During the Data portion of a Write sequence, only the byte (D[35:27]) is

written into the device. D[26:0] will remain unaltered.

HHHHL-H- No data is written into the device during this portion of a Write operation.

HHHH- L-HNo data is written into the device during this portion of a Write operation.

Note:

8. Assumes a Write cycle was initiated per the Write Port Cycle Description Truth Table. BWS0, BWS1, in the case of CY7C1303V25 and also BWS2 and BWS3

in the case of CY7C1306V25 can be altered on different portions of a write cycle, as long as the set-up and hold requirements are achieved.

PRELIMINARY

CY7C1303V25

CY7C1306V25

Document #: 38-05100 Rev. *B Page 8 of 21

Maximum Ratings

(Above which the useful life may be impaired.)

Storage Temperature ................................. –65°C to +150°C

Ambient Temperature with

Power Applied.............................................–55°C to +125°C

Supply Voltage on VDD Relative to GND........ –0.5V to +3.6V

DC Applied to Outputs in High Z State –0.5V to VDDQ + 0.5V

DC Input Voltage[13] ............................ –0.5V to VDDQ + 0.5V

Current into Outputs (LOW)......................................... 20 mA

Static Discharge Voltage........................................... >2001V

(per MIL-STD-883, Method 3015)

Latch-Up Current.................................................... >200 mA

Operating Range

Range

Ambient

Temperature (TA) VDD[9] VDDQ[9]

Com’l 0°C to +70°C 2.5 ± 0.1V 1.4V to 1.9V

Electrical Characteristics Over the Operating Range[10]

DC Electrical Characteristics Over the Operating Range

Parameter Description Test Conditions Min. Typ. Max. Unit

VDD Power Supply Voltage 2.4 2.5 2.6 V

VDDQ I/O Supply Voltage 1.4 1.5 1.9 V

VOH Output HIGH Voltage Note 11 VDDQ/2 – 0.12 VDDQ/2 + 0.12 V

VOL Output LOW Voltage Note 12 VDDQ/2 – 0.12 VDDQ/2 + 0.12 V

VOH(LOW) Output HIGH Voltage IOH = –0.1 mA, Nominal Impedance VDDQ – 0.2 VDDQ V

VOL(LOW) Output LOW Voltage IOL = 0.1 mA, Nominal Impedance VSS 0.2 V

VIH Input HIGH Voltage[13] VREF + 0.1 VDDQ + 0.3 V

VIL Input LOW Voltage[13, 14] –0.3 VREF – 0.1 V

VIN Clock Input Voltage –0.3 VDDQ + 0.3 V

VREF Input Reference Voltage[15] Typical value = 0.75V 0.68 0.75 0.95 V

IXInput Load Current GND ≤ VI ≤ VDDQ –5 5µA

IOZ Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled –5 5µA

IDD VDD Operating Supply VDD = Max.,

IOUT = 0 mA,

f = fMAX = 1/tCYC

167 MHz 550 mA

133 MHz 470 mA

100 MHz 420 mA

ISB1 Automatic

Power-Down

Current

Max. VDD, Both Ports

Deselected, VIN ≥ VIH

or VIN ≤ VIL f = fMAX =

1/tCYC, Inputs Static

167 MHz 350 mA

133 MHz 330 mA

100 MHz 250 mA

AC Input Requirements Over the Operating Range

Parameter Description Test Conditions Min. Typ. Max. Unit

VIH Input High (Logic 1) Voltage VREF + 0.2 – – V

VIL Input Low (Logic 0) Voltage – – VREF – 0.2 V

Notes:

9. Power-up: Assumes a linear ramp from 0V to VDD(min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD.

10. All Voltage referenced to Ground.

11. Output are impedance controlled. IOH = –VDDQ/2)/(RQ/5) for values of 175Ω <= RQ <= 350Ω.

12. Output are impedance controlled. IOL = (VDDQ/2)/(RQ/5) for values of 175Ω <= RQ <= 350Ω.

13. Overshoot: VIH(AC) < VDDQ +0.85V (Pulse width less than tCYC/2), Undershoot: VIL(AC) > –1.5V (Pulse width less than tCYC/2).

14. This spec is for all inputs except C and C Clock. For C and C Clock, VIL(Max.) = VREF – 0.2V.

15. VREF (Min.) = 0.68V or 0.46VDDQ, whichever is larger, VREF (Max.) = 0.95V or 0.54VDDQ, whichever is smaller.

PRELIMINARY

CY7C1303V25

CY7C1306V25

Document #: 38-05100 Rev. *B Page 9 of 21

Thermal Resistance[16]

Parameter Description Test Conditions

165 FBGA

Package Unit

ΘJA Thermal Resistance

(Junction to Ambient)

Test conditions follow standard

test methods and procedures for

measuring thermal impedance,

per EIA/JESD51.

16.7 °C/W

ΘJC Thermal Resistance

(Junction to Case)

6.5 °C/W

Capacitance[20]

Parameter Description Test Conditions Max.

CIN Input Capacitance TA = 25°C, f = 1 MHz,

VDD = 2.5V.

VDDQ = 1.5V

CCLK Clock Input Capacitance 6

COOutput Capacitance 7

AC Test Loads and Waveforms

Note:

16. Tested initially and after any design or process change that may affect these parameters.

1.25V

0.25V

R = 50Ω

5pF

INCLUDING

JIG AND

SCOPE

ALL INPUT PULSES

Device RL= 50Ω

Z0= 50Ω

VREF = 0.75V

VDDQ/2

[15]

0.75V

Under

Test

VDDQ/2

Device

Under

Test

OUTPUT

VDDQ/2

VREF

OUTPUT

(a)

RQ =

250Ω

(b)

RQ =

250Ω

PRELIMINARY

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Document #: 38-05100 Rev. *B Page 10 of 21

Switching Characteristics Over the Operating Range[17]

Cypress

Parameter

Consortium

Parameter

-167 -133 -100

Description Min. Max. Min. Max. Min. Max. Unit

tPower[18] VCC (typical) to the First Access Read or Write 10 10 10 µs

Cycle Time

tCYC tKHKH K Clock and C Clock Cycle Time 6.0 7.5 10.0 ns

tKH tKHKL Input Clock (K/K and C/C) HIGH 2.4 3.2 3.5 ns

tKL tKLKH Input Clock (K/K and C/C) LOW 2.4 3.2 3.5 ns

tKHKHtKHKHK/K Clock Rise to K/K Clock Rise and C/C to C/C Rise

(rising edge to rising edge)

2.7 3.3 3.4 4.1 4.4 5.4 ns

tKHCH tKHCH K/K Clock Rise to C/C Clock Rise

(rising edge to rising edge)

0.0 2.0 0.0 2.5 0.0 3.0 ns

Set-up Times

tSA tSA Address Set-up to Clock (K and K) Rise 0.7 0.8 1.0 ns

tSC tSC Control Set-up to Clock (K and K) Rise (RPS, WPS,

BWS0, BWS1)

0.7 0.8 1.0 ns

tSD tSD D[x:0] Set-up to Clock (K and K) Rise 0.7 0.8 1.0 ns

Hold Times

tHA tHA Address Hold after Clock (K and K) Rise 0.7 0.8 1.0 ns

tHC tHC Control Signals Hold after Clock (K and K) Rise (RPS,

WPS, BWS0, BWS1)

0.7 0.8 1.0 ns

tHD tHD D[x:0] Hold after Clock (K and K) Rise 0.7 0.8 1.0 ns

Output Times

tCO tCHQV C/C Clock Rise (or K/K in single clock mode) to Data

Valid

2.5 3.0 3.0 ns

tDOH tCHQX Data Output Hold after Output C/C Clock Rise (Active to

Active)

1.2 1.2 1.2 ns

tCHZ tCHZ Clock (C and C) rise to High-Z (Active to High-Z)[19, 20] 2.5 3.0 3.0 ns

tCLZ tCLZ Clock (C and C) rise to Low-Z[19, 20] 1.2 1.2 1.2 ns

Notes:

17. Unless otherwise noted, test conditions assume signal transition time of 2V/ns, timing reference levels of 0.75V,Vref = 0.75V, RQ = 250Ω, VDDQ = 1.5V, input

pulse levels of 0.25V to 1.25V, and output loading of the specified IOL/IOH and load capacitance shown in (a) of AC test loads.

18. This part has a voltage regulator that steps down the voltage internally; tPower is the time power needs to be supplied above VDD minimum initially before a read

or write operation can be initiated.

19. tCHZ, tCLZ, are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 100 mV from steady-state voltage.

20. At any given voltage and temperature tCHZ is less than tCLZ and, tCHZ less than tCO.

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Document #: 38-05100 Rev. *B Page 11 of 21

Switching Waveforms[21, 22, 23]

Notes:

21. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, i.e., A0+1.

22. Outputs are disabled (High-Z) one clock cycle after a NOP.

23. In this example, if address A2 = A1 then data Q2 0= D10 and Q21 = D11. Write data is forwarded immediately as read results.This note applies to the whole

diagram.

READ READ WRITE WRITEWRITE NOPREAD WRITE NOP

12345 8 1

RPS

D10

tKH tKHKH

tKHCH tCO

tKL tCYC

tHC

tSA tHA

tHD

tKHCH

DON’T CARE UNDEFINE

tCLZ tCHZ

tSC

tKH tKL

A2 A3 A4 A5 A6

tHA

D11 D30 D31 D50 D51 D60 D61

tSD tHD

Q00 Q21Q01 Q20 Q40 Q41

tCO

tDOH tDOH

tKHKH tCYC

tSA

tSD

PRELIMINARY

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Document #: 38-05100 Rev. *B Page 12 of 21

IEEE 1149.1 Serial Boundary Scan (JTAG)

These SRAMs incorporate a serial boundary scan test access

port (TAP) in the FBGA package. This part is fully compliant

with IEEE Standard #1149.1-1900. The TAP operates using

JEDEC standard 2.5V I/O logic levels.

Disabling the JTAG Feature

It is possible to operate the SRAM without using the JTAG

feature. To disable the TAP controller, TCK must be tied LOW

(VSS) to prevent clocking of the device. TDI and TMS are inter-

nally pulled up and may be unconnected. They may alternately

be connected to VDD through a pull-up resistor. TDO should

be left unconnected. Upon power-up, the device will come up

in a reset state which will not interfere with the operation of the

device.

Test Access Port—Test Clock

The test clock is used only with the TAP controller. All inputs

are captured on the rising edge of TCK. All outputs are driven

from the falling edge of TCK.

Test Mode Select

The TMS input is used to give commands to the TAP controller

and is sampled on the rising edge of TCK. It is allowable to

leave this pin unconnected if the TAP is not used. The pin is

pulled up internally, resulting in a logic HIGH level.

Test Data-In (TDI)

The TDI pin is used to serially input information into the

registers and can be connected to the input of any of the

registers. The register between TDI and TDO is chosen by the

instruction that is loaded into the TAP instruction register. For

information on loading the instruction register, see the TAP

Controller State Diagram. TDI is internally pulled up and can

be unconnected if the TAP is unused in an application. TDI is

connected to the most significant bit (MSB) on any register.

Test Data-Out (TDO)

The TDO output pin is used to serially clock data-out from the

registers. The output is active depending upon the current

state of the TAP state machine (see Instruction codes). The

output changes on the falling edge of TCK. TDO is connected

to the least significant bit (LSB) of any register.

Performing a TAP Reset

A Reset is performed by forcing TMS HIGH (VDD) for five rising

edges of TCK. This RESET does not affect the operation of

the SRAM and may be performed while the SRAM is

operating. At power-up, the TAP is reset internally to ensure

that TDO comes up in a high-Z state.

TAP Registers

Registers are connected between the TDI and TDO pins and

allow data to be scanned into and out of the SRAM test

circuitry. Only one register can be selected at a time through

the instruction registers. Data is serially loaded into the TDI pin

on the rising edge of TCK. Data is output on the TDO pin on

the falling edge of TCK.

Instruction Register

Three-bit instructions can be serially loaded into the instruction

TDI and TDO pins as shown in TAP Controller Block Diagram.

Upon power-up, the instruction register is loaded with the

IDCODE instruction. It is also loaded with the IDCODE

instruction if the controller is placed in a reset state as

described in the previous section.

When the TAP controller is in the Capture IR state, the two

least significant bits are loaded with a binary “01” pattern to

allow for fault isolation of the board level serial test path.

Bypass Register

To save time when serially shifting data through registers, it is

sometimes advantageous to skip certain chips. The bypass

and TDO pins. This allows data to be shifted through the

SRAM with minimal delay. The bypass register is set LOW

(VSS) when the BYPASS instruction is executed.

Boundary Scan Register

The boundary scan register is connected to all of the input and

output pins on the SRAM. Several no connect (NC) pins are

also included in the scan register to reserve pins for higher

density devices.

The boundary scan register is loaded with the contents of the

RAM Input and Output ring when the TAP controller is in the

Capture-DR state and is then placed between the TDI and

TDO pins when the controller is moved to the Shift-DR state.

The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instruc-

tions can be used to capture the contents of the Input and

Output ring.

The Boundary Scan Order tables show the order in which the

bits are connected. Each bit corresponds to one of the bumps

on the SRAM package. The MSB of the register is connected

to TDI, and the LSB is connected to TDO.

Identification (ID) Register

The ID register is loaded with a vendor-specific, 32-bit code

during the Capture-DR state when the IDCODE command is

loaded in the instruction register. The IDCODE is hardwired

into the SRAM and can be shifted out when the TAP controller

is in the Shift-DR state. The ID register has a vendor code and

other information described in the Identification Register

Definitions table.

TAP Instruction Set

Eight different instructions are possible with the three-bit

instruction register. All combinations are listed in the

Instruction Code table. Three of these instructions are listed

as RESERVED and should not be used. The other five instruc-

tions are described in detail below.

Instructions are loaded into the TAP controller during the

Shift-IR state when the instruction register is placed between

TDI and TDO. During this state, instructions are shifted

through the instruction register through the TDI and TDO pins.

To execute the instruction once it is shifted in, the TAP

controller needs to be moved into the Update-IR state.

IDCODE

The IDCODE instruction causes a vendor-specific, 32-bit code

to be loaded into the instruction register. It also places the

instruction register between the TDI and TDO pins and allows

the IDCODE to be shifted out of the device when the TAP

controller enters the Shift-DR state. The IDCODE instruction

PRELIMINARY

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CY7C1306V25

Document #: 38-05100 Rev. *B Page 13 of 21

is loaded into the instruction register upon power-up or

whenever the TAP controller is given a test logic reset state.

SAMPLE Z

The SAMPLE Z instruction causes the boundary scan register

to be connected between the TDI and TDO pins when the TAP

controller is in a Shift-DR state. The SAMPLE Z command puts

the output bus into a High-Z state until the next command is

given during the “Update IR” state.

SAMPLE/PRELOAD

SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When

the SAMPLE/PRELOAD instructions are loaded into the

instruction register and the TAP controller is in the Capture-DR

state, a snapshot of data on the inputs and output pins is

captured in the boundary scan register.

The user must be aware that the TAP controller clock can only

operate at a frequency up to 10 MHz, while the SRAM clock

operates more than an order of magnitude faster. Because

there is a large difference in the clock frequencies, it is

possible that during the Capture-DR state, an input or output

will undergo a transition. The TAP may then try to capture a

signal while in transition (metastable state). This will not harm

the device, but there is no guarantee as to the value that will

be captured. Repeatable results may not be possible.

To guarantee that the boundary scan register will capture the

correct value of a signal, the SRAM signal must be stabilized

long enough to meet the TAP controller's capture set-up plus

hold times (tCS and tCH). The SRAM clock input might not be

captured correctly if there is no way in a design to stop (or

slow) the clock during a SAMPLE/PRELOAD instruction. If this

is an issue, it is still possible to capture all other signals and

simply ignore the value of the CK and CK captured in the

boundary scan register.

Once the data is captured, it is possible to shift out the data by

putting the TAP into the Shift-DR state. This places the

boundary scan register between the TDI and TDO pins.

PRELOAD allows an initial data pattern to be placed at the

latched parallel outputs of the boundary scan register cells

prior to the selection of another boundary scan test operation.

The shifting of data for the SAMPLE and PRELOAD phases

can occur concurrently when required—that is, while data

captured is shifted out, the preloaded data can be shifted in.

BYPASS

When the BYPASS instruction is loaded in the instruction

advantage of the BYPASS instruction is that it shortens the

boundary scan path when multiple devices are connected

together on a board.

EXTEST

The EXTEST instruction enables the preloaded data to be

driven out through the system output pins. This instruction also

selects the boundary scan register to be connected for serial

access between the TDI and TDO in the shift-DR controller

state.

EXTEST Output Bus Three-state

IEEE Standard 1149.1 mandates that the TAP controller be

able to put the output bus into a three-state mode.

The boundary scan register has a special bit located at bit #47.

When this scan cell, called the “extest output bus three-state”,

is latched into the preload register during the “Update-DR”

state in the TAP controller, it will directly control the state of the

output (Q-bus) pins, when the EXTEST is entered as the

current instruction. When HIGH, it will enable the output

buffers to drive the output bus. When LOW, this bit will place

the output bus into a High-Z condition.

This bit can be set by entering the SAMPLE/PRELOAD or

EXTEST command, and then shifting the desired bit into that

cell, during the “Shift-DR” state. During “Update-DR”, the value

loaded into that shift-register cell will latch into the preload

directly control the output Q-bus pins. Note that this bit is

pre-set HIGH to enable the output when the device is

powered-up, and also when the TAP controller is in the

“Test-Logic-Reset” state.

Reserved

These instructions are not implemented but are reserved for

future use. Do not use these instructions.

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TAP Controller State Diagram[24]

Note:

24. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.

TEST-LOGIC

RESET

TEST-LOGIC/

IDLE

SELECT

DR-SCAN

CAPTURE-DR

SHIFT-DR

EXIT1-DR

PAUSE-DR

EXIT2-DR

UPDATE-DR

SELECT

IR-SCAN

CAPTURE-DR

SHIFT-IR

EXIT1-IR

PAUSE-IR

EXIT2-IR

UPDATE-IR

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TAP Controller Block Diagram

TAP Electrical Characteristics Over the Operating Range [10, 13, 25]

Parameter Description Test Conditions Min. Max. Unit

VOH1 Output HIGH Voltage IOH = −2.0 mA 1.7 V

VOH2 Output HIGH Voltage IOH = −100 µA2.1 V

VOL1 Output LOW Voltage IOL = 2.0 mA 0.7 V

VOL2 Output LOW Voltage IOL = 100 µA0.2 V

VIH Input HIGH Voltage 1.7 VDD + 0.3 V

VIL Input LOW Voltage –0.3 0.7 V

IXInput and Output Load Current GND ≤ VI ≤ VDDQ −5 5 µA

Note:

25. These characteristic pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics Table

012..

3031

Boundary Scan Register

Identification Register

012..

.106

012

Instruction Register

Bypass Register

Selection

Circuitry Selection

Circuitry

TAP Controller

TDI TDO

TCK

TMS

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CY7C1306V25

Document #: 38-05100 Rev. *B Page 16 of 21

TAP AC Switching Characteristics Over the Operating Range[26, 27]

Parameter Description Min. Max. Unit

tTCYC TCK Clock Cycle Time 100 ns

tTF TCK Clock Frequency 10 MHz

tTH TCK Clock HIGH 40 ns

tTL TCK Clock LOW 40 ns

Set-up Times

tTMSS TMS Set-up to TCK Clock Rise 10 ns

tTDIS TDI Set-up to TCK clock Rise 10 ns

tCS Capture Set-up to TCK Rise 10 ns

Hold Times

tTMSH TMS Hold after TCK Clock Rise 10 ns

tTDIH TDI Hold after Clock Rise 10 ns

tCH Capture Hold after Clock Rise 10 ns

Output Times

tTDOV TCK Clock LOW to TDO Valid 20 ns

tTDOX TCK Clock LOW to TDO Invalid 0ns

TAP Timing and Test Conditions[27]

Notes:

26. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.

27. Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1 ns.

(a)

TDO

CL= 20 pF

Z0= 50Ω

GND

1.25V

Test Clock

Test Mode Select

TCK

TMS

Test Data-In

TDI

Test Data-Out

TDO

TCYC

TMSH

TMSS

TDIS

TDIH

TDOX

TDOV

50Ω

2.5V

ALL INPUT PULSES

1.25V

PRELIMINARY

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CY7C1306V25

Document #: 38-05100 Rev. *B Page 17 of 21

Identification Register Definitions

Instruction Field

Value

DescriptionCY7C1303V25 CY7C1306V25

Revision Number

(31:29)

000 000 Version number.

Cypress Device ID

(28:12)

01011010010010101 01011010010100101 Defines the type of SRAM.

Cypress JEDEC ID

(11:1)

00000110100 Allows unique identification of

SRAM vendor.

ID Register Presence

(0)

1Indicate the presence of an ID

Scan Register Sizes

Instruction 3

Bypass 1

ID 32

Boundary Scan 107

Instruction Codes

Instruction Code Description

EXTEST 000 Captures the Input/Output ring contents.

IDCODE 001 Loads the ID register with the vendor ID code and places the register

between TDI and TDO. This operation does not affect SRAM operation.

SAMPLE Z 010 Captures the Input/Output contents. Places the boundary scan register

between TDI and TDO. Forces all SRAM output drivers to a High-Z state.

RESERVED 011 Do Not Use: This instruction is reserved for future use.

SAMPLE/PRELOAD 100 Captures the Input/Output ring contents. Places the boundary scan regis-

ter between TDI and TDO. Does not affect the SRAM operation.

RESERVED 101 Do Not Use: This instruction is reserved for future use.

RESERVED 110 Do Not Use: This instruction is reserved for future use.

BYPASS 111 Places the bypass register between TDI and TDO. This operation does not

affect SRAM operation.

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Document #: 38-05100 Rev. *B Page 18 of 21

Boundary Scan Order

Bit # Bump ID

06R

16P

26N

37P

47N

57R

68R

78P

89R

911P

10 10P

11 10N

12 9P

13 10M

14 11N

15 9M

16 9N

17 11L

18 11M

19 9L

20 10L

21 11K

22 10K

23 9J

24 9K

25 10J

26 11J

27 11H

28 10G

29 9G

30 11F

31 11G

32 9F

33 10F

34 11E

35 10E

36 10D

37 9E

38 10C

39 11D

40 9C

41 9D

42 11B

43 11C

44 9B

45 10B

46 11A

47 Internal

48 9A

49 8B

50 7C

51 6C

52 8A

53 7A

54 7B

55 6B

56 6A

57 5B

58 5A

59 4A

60 5C

61 4B

62 3A

63 1H

64 1A

65 2B

66 3B

67 1C

68 1B

69 3D

70 3C

71 1D

72 2C

73 3E

74 2D

75 2E

76 1E

77 2F

78 3F

79 1G

80 1F

81 3G

82 2G

83 1J

84 2J

85 3K

86 3J

87 2K

Boundary Scan Order (continued)

Bit # Bump ID

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Document #: 38-05100 Rev. *B Page 19 of 21

88 1K

89 2L

90 3L

91 1M

92 1L

93 3N

94 3M

95 1N

96 2M

97 3P

98 2N

99 2P

100 1P

101 3R

102 4R

103 4P

104 5P

105 5N

106 5R

Boundary Scan Order (continued)

Bit # Bump ID

Ordering Information

Speed

(MHz) Ordering Code

Package

Name Package Type

Operating

Range

167 CY7C1303V25-167BZC BB165A 13 x 15 x 1.2 mm FBGA Commercial

CY7C1306V25-167BZC

133 CY7C1303V25-133BZC BB165A 13 x 15 x 1.2 mm FBGA

CY7C1306V25-133BZC

100 CY7C1303V25-100BZC BB165A 13 x 15 x 1.2 mm FBGA

CY7C1306V25-100BZC

PRELIMINARY

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CY7C1306V25

Document #: 38-05100 Rev. *B Page 20 of 21

of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize

its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

Quad Data Rate\TM SRAM and QDR\TM SRAM comprise a new family of products developed by Cypress, IDT, NEC and

Samsung. All products and company names mentioned in this document may be the trademarks of their respective holders.

Package Diagram

165-Ball FBGA (13 x 15 x 1.2 mm) BB165A

51-85122-*C

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Document History Page

Document Title:CY7C1303V25/CY7C1306V25 18-Mb Burst of 2 Pipelined SRAM with QDR™ Architecture

Document Number: 38-05100

REV. ECN NO. Issue Date Orig. of Change Description of Change

** 107655 07/10/01 SKX New Data Sheet

*A 122950 12/11/02 RCS Changed Status to Preliminary from Advanced Infor-

mation (All Pages)

Added Ex-Test feature to JTAG. This implementation

is backwards compatible with the previous

Non-Ex-Test feature set. (Page 19 and 24)

Changed Boundary Scan Order to 106 Cells from 69

(Page 24, 25 and 26)

Changed Cells 47 and 63 to an Internal Cells that

are Pre-Set to LOW in the Boundary Scan Order.

Note that these pins are 100% compatible with the

previous scan order because they had previously

been connected to VSS. (Page 25)

Specified minimum and maximum input voltages for

AC conditions. (Page 12)

Changed packaged height to 1.4 mm from 1.2 mm.

(Page 27)

Changed ball diameter to 0.5 mm from 0.45 mm.

(Page 27)

Added tPower specification and note 18. These de-

vices require 10 µs of VDD above VDD minimum

(2.4V) before operating. (page 13)

*B 203861 see ECN DIM Changed “Application Example” diagram.

Changed “Switching Waveforms” diagram.

Added “Thermal Resistance” table and values.

Added “Capacitance” table and values.

Changed package from BB165D to BB165A.

Added VOH(LOW) and VOL(LOW) specs to the

“Electrical Characteristics” table.

Revised the functional description of the device.

Added IDD and ISB1 values to the Electrical Charac-

teristics table.