1
Features
•Low-voltage and Standard-voltage Operation
– 2.7 (VCC = 2.7V to 5.5V)
– 1.8 (VCC = 1.8V to 5.5V)
•User Selectable Internal Organization
– 16K: 2048 x 8 or 1024 x 16
•Three-wire Serial Interface
•Sequential Read Operation
•Schmitt Trigger, Filtered Inputs for Noise Suppression
•2 MHz Clock Rate (5V) Compatibility
•Self-timed Write Cycle (10 ms max)
•High Reliability
– Endurance: 1 Million Write Cycles
– Data Retention: 100 Years
•Automotive Devices Available
•8-lead JEDEC PDIP, 8-lead JEDEC SOIC, 8-lead Ultra Thin Mini-MAP (MLP 2x3), and 8-
lead TSSOP Packages
•Die Sales: Wafer Form, Waffle Pack and Bumped Wafers
Description
The AT93C86A provides 16384 bits of serial electrically erasable programmable read
only memory (EEPROM), organized as 1024 words of 16 bits each when the ORG pin
is connected to VCC and 2048 words of eight bits each when it is tied to ground. The
device is optimized for use in many industrial and commercial applications where low-
power and low-voltage operations are essential. The AT93C86A is available in space
saving 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead Ultra Thin Mini-MAP (MLP 2x3), and 8-
lead TSSOP packages.
Table 1. Pin Configurations
Pin Name Function
CS Chip Select
SK Serial Data Clock
DI Serial Data Input
DO Serial Data Output
GND Ground
VCC Power Supply
ORG Internal Organization
NC No Connect
Three-wire
Serial
EEPROM
16K (2048 x 8 or 1024 x 16)
AT93C86A
Rev. 3408H–SEEPR–1/07
8-lead PDIP
1
2
3
4
8
7
6
5
CS
SK
DI
DO
VCC
NC
ORG
GND
8-lead TSSOP
1
2
3
4
8
7
6
5
CS
SK
DI
DO
VCC
NC
ORG
GND
8-lead
Ultra Thin Mini-MAP (MLP
2x3)
Bottom View
1
2
3
4
8
7
6
5
VCC
NC
O
RG
G
ND
C
S
S
K
D
I
D
O
8-lead SOIC
1
2
3
4
8
7
6
5
CS
SK
DI
DO
VCC
NC
ORG
GND
2AT93C86A
3408H–SEEPR–1/07
The AT93C86A is enabled through the Chip Select pin (CS), and accessed via a three-
wire serial interface consisting of Data Input (DI), Data Output (DO), and Shift Clock
(SK). Upon receiving a Read instruction at DI, the address is decoded and the data is
clocked out serially on the data output pin DO. The Write cycle is completely self-timed
and no separate Erase cycle is required before Write. The Write cycle is only enabled
when the part is in the Erase/Write Enable state. When CS is brought “high” following
the initiation of a Write cycle, the DO pin outputs the Ready/Busy status of the part. The
AT93C86A is available in a 2.7V to 5.5V version.
Figure 1. Block Diagram
Note: When the ORG pin is connected to Vcc, the x 16 organization is selected. When it is connected to ground, the x 8 organization
is selected. If the ORG pin is left unconnected and the application does not load the input beyond the capability of the internal 1
Meg ohm pullup, then the x 16 organization is selected.
Absolute Maximum Ratings*
Operating Temperature......................................−55°C to +125°C*NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability
Storage Temperature .........................................−65°C to +150°C
Voltage on any Pin
with Respect to Ground........................................ −1.0V to +7.0V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current........................................................ 5.0 mA
ADDRESS
DECODER
OUTPUT
BUFFER
DO
O
RG
DI
CS
SK
Vcc GND
CLOCK
GENERATOR
MODE
DECODE
LOGIC
DATA
REGISTER
MEMORY ARRAY
2048 x 8
OR
1024 x 16
3
AT93C86A
3408H–SEEPR–1/07
Note: 1. This parameter is characterized and is not 100% tested.
Note: 1. VIL min and VIH max are reference only and are not tested.
Table 2. Pin Capacitance(1)
Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted)
Symbol Test Conditions Max Units Conditions
COUT Output Capacitance (DO) 5 pF VOUT = 0V
CIN Input Capacitance (CS, SK, DI) 5 pF VIN = 0V
Table 3. DC Characteristics
Applicable over recommended operating range from: TAI = −40°C to +85°C, VCC = +1.8V to +5.5V,
TAE = −40°C to +125°C, VCC = +1.8V to +5.5V (unless otherwise noted)
Symbol Parameter Test Condition Min Typ Max Unit
VCC1 Supply Voltage 1.8 5.5 V
VCC2 Supply Voltage 2.7 5.5 V
VCC3 Supply Voltage 4.5 5.5 V
ICC Supply Current VCC = 5.0V READ at 1.0 MHz 0.5 2.0 mA
WRITE at 1.0 MHz 0.5 2.0 mA
ISB1 Standby Current VCC = 1.8V CS = 0V 0.4 1.0 µA
ISB2 Standby Current VCC = 2.7V CS = 0V 6.0 10.0 µA
ISB3 Standby Current VCC = 5.0V CS = 0V 10.0 15.0 µA
IIL Input Leakage VIN = 0V to VCC 0.1 3.0 µA
IOL Output Leakage VIN = 0V to VCC 0.1 3.0 µA
VIL1(1)
VIH1(1) Input Low Voltage
Input High Voltage 2.7V ≤ VCC ≤ 5.5V --−0.6
2.0
0.8
VCC + 1 V
VIL2(1)
VIH2(1) Input Low Voltage
Input High Voltage 1.8V ≤ VCC ≤ 2.7V −0.6
VCC x 0.7
VCC x 0.3
VCC + 1 V
VOL1
VOH1
Output Low Voltage
Output High Voltage 2.7V ≤ VCC ≤ 5.5V IOL = 2.1 mA 0.4 V
IOH = –0.4 mA 2.4 V
VOL2
VOH2
Output Low Voltage
Output High Voltage 1.8V ≤ VCC ≤ 2.7V IOL = 0.15 mA 0.2 V
IOH = –100 µAV
CC – 0.2 V
4AT93C86A
3408H–SEEPR–1/07
Note: 1. This parameter is ensured by characterization.
Table 4. AC Characteristics
Applicable over recommended operating range from TAI = −40°C to + 85°C, TAE = −40°C to +125°C, VCC = As Specified,
CL = 1 TTL Gate and 100 pF (unless otherwise noted)
Symbol Parameter Test Condition Min Typ Max Units
fSK
SK Clock
Frequency
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
0
0
0
2
1
0.25
MHz
tSKH SK High Time 2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
250
1000 ns
tSKL SK Low Time 2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
250
1000 ns
tCS
Minimum CS
Low Time
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
250
1000 ns
tCSS CS Setup Time Relative to SK 2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
50
200 ns
tDIS DI Setup Time Relative to SK 2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
100
400 ns
tCSH CS Hold Time Relative to SK 0 ns
tDIH DI Hold Time Relative to SK 2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
100
400 ns
tPD1 Output Delay to “1” AC Test 2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
250
1000 ns
tPD0 Output Delay to “0” AC Test 2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
250
1000 ns
tSV CS to Status Valid AC Test 2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
250
1000 ns
tDF
CS to DO in High
Impedance
AC Test
CS = VIL
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
150
400 ns
tWP Write Cycle Time 1.8V ≤ VCC ≤ 5.5V 0.1 3 10 ms
ms
Endurance(1) 5.0V, 25°C 1M Write Cycles
5
AT93C86A
3408H–SEEPR–1/07
Functional
Description
The AT93C86A is accessed via a simple and versatile three-wire serial communication
interface. Device operation is controlled by seven instructions issued by the host pro-
cessor. A valid instruction starts with a rising edge of CS and consists of a Start Bit
(logic “1”) followed by the appropriate Op Code and the desired memory address
location.
READ (READ): The Read (READ) instruction contains the address code for the mem-
ory location to be read. After the instruction and address are decoded, data from the
selected memory location is available at the serial output pin DO. Output data changes
are synchronized with the rising edges of serial clock SK. It should be noted that a
dummy bit (logic “0”) precedes the 8- or 16-bit data output string. The AT93C86A sup-
ports sequential read operations. The device will automatically increment the internal
address pointer and clock out the next memory location as long as CS is held high. In
this case, the dummy bit (logic “0”) will not be clocked out between memory locations,
thus allowing for a continuous stream of data to be read.
ERASE/WRITE (EWEN): To assure data integrity, the part automatically goes into the
Erase/Write Disable (EWDS) state when power is first applied. An Erase/Write Enable
(EWEN) instruction must be executed first before any programming instructions can be
carried out. Please note that once in the EWEN state, programming remains enabled
until an EWDS instruction is executed or VCC power is removed from the part.
ERASE (ERASE): The Erase (ERASE) instruction programs all bits in the specified
memory location to the logical “1” state. The self-timed erase cycle starts once the
ERASE instruction and address are decoded. The DO pin outputs the Ready/Busy sta-
tus of the part if CS is brought high after being kept low for a minimum of 250 ns (tCS). A
logic “1” at pin DO indicates that the selected memory location has been erased, and the
part is ready for another instruction.
WRITE (WRITE): The Write (WRITE) instruction contains the 8 or 16 bits of data to be
written into the specified memory location. The self-timed programming cycle tWP starts
after the last bit of data is received at serial data input pin DI. The DO pin outputs the
Ready/Busy status of the part if CS is brought high after being kept low for a minimum of
Table 5. Instruction Set for the AT93C86A
Instruction SB Op Code
Address Data
Commentsx 8 x 16 x 8 x 16
READ 1 10 A10 – A0A9 – A0Reads data stored in memory,
at specified address.
EWEN 1 00 11XXXXXXXXX 11XXXXXXXX Write enable must precede all
programming modes.
ERASE 1 11 A10 – A0A9 – A0Erases memory location An – A0.
WRITE 1 01 A10 – A0A9 – A0D7 – D0D15 – D0Writes memory location An – A0.
ERAL 1 00 10XXXXXXXXX 10XXXXXXXX Erases all memory locations.
Valid only at VCC = 4.5V to 5.5V.
WRAL 1 00 01XXXXXXXXX 01XXXXXXXX D7 – D0D15 – D0Writes all memory locations.
Valid when VCC = 4.5V to 5.5V and
Disable Register cleared.
EWDS 1 00 00XXXXXXXXX 00XXXXXXXX Disables all programming
instructions.
6AT93C86A
3408H–SEEPR–1/07
250 ns (tCS). A logic “0” at DO indicates that programming is still in progress. A logic “1”
indicates that the memory location at the specified address has been written with the
data pattern contained in the instruction and the part is ready for further instructions. A
Ready/Busy status cannot be obtained if the CS is brought high after the end of the self-
timed programming cycle tWP.
ERASE ALL (ERAL): The Erase All (ERAL) instruction programs every bit in the mem-
ory array to the logic “1” state and is primarily used for testing purposes. The DO pin
outputs the Ready/Busy status of the part if CS is brought high after being kept low for a
minimum of 250 ns (tCS). The ERAL instruction is valid only at VCC = 5.0V ± 10%.
WRITE ALL (WRAL): The Write All (WRAL) instruction programs all memory locations
with the data patterns specified in the instruction. The DO pin outputs the Ready/Busy
status of the part if CS is brought high after being kept low for a minimum of 250 ns (tCS).
The WRAL instruction is valid only at VCC = 5.0V ± 10%.
ERASE/WRITE DISABLE (EWDS): To protect against accidental data disturbance, the
Erase/Write Disable (EWDS) instruction disables all programming modes and should be
executed after all programming operations. The operation of the READ instruction is
independent of both the EWEN and EWDS instructions and can be executed at any
time.
7
AT93C86A
3408H–SEEPR–1/07
Timing Diagrams
Figure 2. Synchronous Data Timing
Note: 1. This is the minimum SK period.
Figure 3. READ Timing
Organization Key for Timing Diagrams
I/O
AT93C86A (16K)
x 8 x 16
ANA10 A9
DND7D15
8AT93C86A
3408H–SEEPR–1/07
Figure 4. EWEN Timing
Figure 5. EWDS Timing
Figure 6. WRITE Timing
C
S
11 ...
001
S
K
DI
tCS
C
StCS
S
K
DI 1 0 000 ...
SK
C
StCS
tWP
11
ANDN
0A0D0
... ...
DI
D
OHIGH IMPEDANCE BUSY READY
9
AT93C86A
3408H–SEEPR–1/07
Figure 7. WRAL Timing(1)
Note: 1. Valid only at VCC = 4.5V to 5.5V.
Figure 8. ERASE Timing
C
S
S
K
DI
D
OHIGH IMPEDANCE BUSY
READY
1 0 0 1 ... D
N
t
CS
t
WP
... D00
S
K
1 1 ...1
C
S
DI AN
t
CS
tSV tDF
tWP
AN-1 AN-2 A0
CHECK
STATUS
STANDBY
READY
BUSY
D
OHIGH IMPEDANCE HIGH IMPEDANC
E
10 AT93C86A
3408H–SEEPR–1/07
Figure 9. ERAL Timing(1)
Note: 1. Valid only at VCC = 4.5V to 5.5V.
11
AT93C86A
3408H–SEEPR–1/07
Notes: 1. For 2.7V devices used in a 4.5V to 5.5V range, please refer to performance values in the AC and DC characteristics tables.
2. “U” designates Green package + RoHS compliant.
3. “H” designates Green Package + RoHS compliant, with NiPdAu Lead Finish.
4. Available in Waffle pack and Wafer form; order as SL788 for inkless Wafer form. Bumped die available upon request. Please
contact Serial EEPROM marketing.
AT93C86A Ordering Information(1)
Ordering Code Package Operation Range
AT93C86A-10PU-2.7(2)
AT93C86A-10PU-1.8(2)
AT93C86A-10SU-2.7(2)
AT93C86A-10SU-1.8(2)
AT93C86A-10TU-2.7(2)
AT93C86A-10TU-1.8(2)
AT93C86AY1-10YU-1.8(2)(Not recommended for new
design)
AT93C86AY6-10YH-1.8(3)
8P3
8P3
8S1
8S1
8A2
8A2
8Y1
8Y6
Lead-Free/Halogen-Free/
Industrial Temperature
(−40°C to 85°C)
AT93C86A-W1.8-11(4) Die Sale Industrial Temperature
(−40°C to 85°C)
Package Type
8P3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
8A2 8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)
8Y1 8-lead, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP)
8Y6
8-lead, 2.00 mm x 3.00 mm Body, 0.50 mm Pitch, Ultra Thin Mini-MAP, Dual No Lead Package (DFN), (MLP 2x3
mm)
Options
−2.7 Low Voltage (2.7V to 5.5V)
−1.8 Low Voltage (1.8V to 5.5V)
12 AT93C86A
3408H–SEEPR–1/07
Packaging Information
8P3 – PDIP
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
8P3, 8-lead, 0.300" Wide Body, Plastic Dual
In-line Package (PDIP)
01/09/02
8P3 B
D
D1
E
E1
e
L
b2
b
A2 A
1
N
eA
c
b3
4 PLCS
Top View
Side View
End View
COMMON DIMENSIONS
(Unit of Measure = inches)
SYMBOL MIN NOM MAX NOTE
Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information.
2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.
3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.
4. E and eA measured with the leads constrained to be perpendicular to datum.
5. Pointed or rounded lead tips are preferred to ease insertion.
6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
A 0.210 2
A2 0.115 0.130 0.195
b 0.014 0.018 0.022 5
b2 0.045 0.060 0.070 6
b3 0.030 0.039 0.045 6
c 0.008 0.010 0.014
D 0.355 0.365 0.400 3
D1 0.005 3
E 0.300 0.310 0.325 4
E1 0.240 0.250 0.280 3
e 0.100 BSC
eA 0.300 BSC 4
L 0.115 0.130 0.150 2
13
AT93C86A
3408H–SEEPR–1/07
8Y6 - MLP 2x3 mm
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
8Y6, 8-lead 2.0 x 3.0 mm Body, 0.50 mm Pitch, Utlra Thin Mini-Map,
Dual No Lead Package (DFN) ,(MLP 2x3) C
8Y6
8/26/05
Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-229, for proper dimensions,
tolerances, datums, etc.
2. Dimension b applies to metallized terminal and is measured between 0.15 mm and 0.30 mm from the terminal tip. If the
terminal has the optional radius on the other end of the terminal, the dimension should not be measured in that radius area.
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
D 2.00 BSC
E 3.00 BSC
D2 1.40 1.50 1.60
E2 - - 1.40
A - - 0.60
A1 0.0 0.02 0.05
A2 - - 0.55
A3 0.20 REF
L 0.20 0.30 0.40
e 0.50 BSC
b 0.20 0.25 0.30 2
A2
b
(8X)
Pin 1 ID
Pin 1
Index
Area
A1
A3
D
E
A
L (8X)
e (6X)
1.50 REF.
D2
E2
14 AT93C86A
3408H–SEEPR–1/07
8S1 – JEDEC SOIC
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
TITLE DRAWING NO.
R
REV.
Note:
10/7/03
8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing
Small Outline (JEDEC SOIC) 8S1 B
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
A1 0.10 – 0.25
These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc.
A 1.35 – 1.75
B 0.31 – 0.51
C 0.17 – 0.25
D 4.80 – 5.00
E1 3.81 – 3.99
E 5.79 – 6.20
e 1.27 BSC
L 0.40 – 1.27
∅ 0° – 8°
∅
Top View
End View
Side View
eB
D
A
A1
N
E
1
C
E1
L
15
AT93C86A
3408H–SEEPR–1/07
8A2 – TSSOP
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
5/30/02
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
D 2.90 3.00 3.10 2, 5
E 6.40 BSC
E1 4.30 4.40 4.50 3, 5
A – – 1.20
A2 0.80 1.00 1.05
b 0.19 – 0.30 4
e 0.65 BSC
L 0.45 0.60 0.75
L1 1.00 REF
8A2, 8-lead, 4.4 mm Body, Plastic
Thin Shrink Small Outline Package (TSSOP)
Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances,
datums, etc.
2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed
0.15 mm (0.006 in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm
(0.010 in) per side.
4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the
b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between
protrusion and adjacent lead is 0.07 mm.
5. Dimension D and E1 to be determined at Datum Plane H.
8A2 B
Side View
End View
Top View
A2
A
L
L1
D
123
E1
N
b
Pin 1 indicator
this corner
E
e
16 AT93C86A
3408H–SEEPR–1/07
8Y1 - MAP
A – – 0.90
A1 0.00 – 0.05
D 4.70 4.90 5.10
E 2.80 3.00 3.20
D1 0.85 1.00 1.15
E1 0.85 1.00 1.15
b 0.25 0.30 0.35
e 0.65 TYP
L 0.50 0.60 0.70
PIN 1 INDEX AREA
D
E
A
A1 b
876
e
5
L
D1
E1
PIN 1 INDEX AREA
1234
A
Top View End View Bottom View
Side View
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
8Y1, 8-lead (4.90 x 3.00 mm Body) MSOP Array Package
(MAP) Y1 C
8Y1
2/28/03
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
MIN NOM MAX
NOTE
17
AT93C86A
3408H–SEEPR–1/07
Revision History
Doc. Rev. Date Comments
3408H 1/2007 Add “Bottom View” to pg 1 Ultra Thin MiniMap package drawing
pg 4 revise Note 1 added “ensured by characterization”
3408G 7/2006 Revision history implemented.
Deleted ‘Preliminary’ status from datasheet; Added ‘Ultra Thin’
description to MLP 2x3 package; Deleted ‘1.8V not available’ on
Figure 1 Note; Added 1.8V range on Table 4 under Write Cycle
Time.
Printed on recycled paper.
3408H–SEEPR–1/07
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ASIC/ASSP/Smart Cards
Zone Industrielle
13106 Rousset Cedex, France
Tel: (33) 4-42-53-60-00
Fax: (33) 4-42-53-60-01
1150 East Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906, USA
Tel: 1(719) 576-3300
Fax: 1(719) 540-1759
Scottish Enterprise Technology Park
Maxwell Building
East Kilbride G75 0QR, Scotland
Tel: (44) 1355-803-000
Fax: (44) 1355-242-743
RF/Automotive
Theresienstrasse 2
Postfach 3535
74025 Heilbronn, Germany
Tel: (49) 71-31-67-0
Fax: (49) 71-31-67-2340
1150 East Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906, USA
Tel: 1(719) 576-3300
Fax: 1(719) 540-1759
Biometrics/Imaging/Hi-Rel MPU/
High Speed Converters/RF Datacom
Avenue de Rochepleine
BP 123
38521 Saint-Egreve Cedex, France
Tel: (33) 4-76-58-30-00
Fax: (33) 4-76-58-34-80
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