4-11
MT8870D/MT8870D-1
Integrated DTMF Receiver
Features
Complete DTMF Receiver
Low power consumption
Internal gain setting amplifier
Adjustable guard time
Central office quality
Power-down mode
Inhibit mode
Backward compatible with
MT8870C/MT8870C-1
Applications
Receiver system for British Telecom (BT) or
CEPT Spec (MT8870D-1)
Paging systems
Repeater systems/mobile radio
Credit card systems
Remote control
Personal computers
Telephone answering machine
Description
The MT8870D/MT8870D-1 is a complete DTMF
receiver integrating both the bandsplit filter and
digital decoder functions. The filter section uses
switched capacitor techniques for high and low
group filters; the decoder uses digital counting
techniques to detect and decode all 16 DTMF tone-
pairs into a 4-bit code. External component count is
minimized by on chip provision of a differential input
amplifier, clock oscillator and latched three-state bus
interface.
Ordering Information
MT8870DE/DE-1 18 Pin Plastic DIP
MT8870DC/DC-1 18 Pin Ceramic DIP
MT8870DS/DS-1 18 Pin SOIC
MT8870DN/DN-1 20 Pin SSOP
-40 °C to +85 °C
Figure 1 - Functional Block Diagram
PWDN
IN +
IN -
GS
OSC1 OSC2 St/GT ESt STD TOE
Q1
Q2
Q3
Q4
VDD VSS VRef INH
Bias
Circuit
Dial
Tone
Filter
High Group
Filter
Low Group
Filter
Digital
Detection
Algorithm
Code
Converter
and Latch
St
GT Steering
Logic
Chip
Power Chip
Bias
VRef
Buffer
Zero Crossing
Detectors
to all
Chip
Clocks
ISSUE 4 August 1996
ISO2-CMOS
MT8870D/MT8870D-1 ISO2-CMOS
4-12
Figure 2 - Pin Connections
Pin Description
Pin #
Name Description
18 20
1 1 IN+ Non-Inverting Op-Amp (Input).
2 2 IN- Inverting Op-Amp (Input).
33 GS Gain Select. Gives access to output of front end differential amplifier for connection of
feedback resistor.
44 V
Ref Reference Voltage (Output). Nominally VDD/2 is used to bias inputs at mid-rail (see Fig. 6
and Fig. 10).
5 5 INH Inhibit (Input). Logic high inhibits the detection of tones representing characters A, B, C
and D. This pin input is internally pulled down.
6 6 PWDN Power Down (Input). Active high. Powers down the device and inhibits the oscillator. This
pin input is internally pulled down.
7 8 OSC1 Clock (Input).
8 9 OSC2 Clock (Output). A 3.579545 MHz crystal connected between pins OSC1 and OSC2
completes the internal oscillator circuit.
910 V
SS Ground (Input). 0V typical.
10 11 TOE Three State Output Enable (Input). Logic high enables the outputs Q1-Q4. This pin is
pulled up internally.
11-
14 12-
15 Q1-Q4 Three State Data (Output). When enabled by TOE, provide the code corresponding to the
last v alid tone-pair received (see Table 1). When TOE is logic low, the data outputs are high
impedance.
15 17 StD Delayed Steering (Output).Presents a logic high when a received tone-pair has been
registered and the output latch updated; returns to logic low when the voltage on St/GT falls
below VTSt.
16 18 ESt Early Steering (Output). Presents a logic high once the digital algorithm has detected a
valid tone pair (signal condition). Any momentary loss of signal condition will cause ESt to
return to a logic low.
17 19 St/GT Steering Input/Guard time (Output) Bidirectional. A v oltage greater than VTSt detected at
St causes the device to register the detected tone pair and update the output latch. A
voltage less than VTSt frees the device to accept a new tone pair. The GT output acts to
reset the external steering time-constant; its state is a function of ESt and the voltage on St.
18 20 VDD Positive power supply (Input). +5V typical.
7,
16 NC No Connection.
1
2
3
4
5
6
7
8
910
18
17
16
15
14
13
12
11
IN+
IN-
GS
VRef
INH
PWDN
OSC1
OSC2
VSS
VDD
St/GT
ESt
StD
Q4
Q3
Q2
Q1
TOE
18 PIN CERDIP/PLASTIC DIP/SOIC
1
2
3
4
5
6
7
8
9
10 11
12
20
19
18
17
16
15
14
13
IN+
IN-
GS
VRef
INH
PWDN
NC
OSC1
OSC2
VSS
20 PIN SSOP
VDD
St/GT
ESt
StD
Q4
Q3
Q2
Q1
TOE
NC
ISO2-CMOS MT8870D/MT8870D-1
4-13
Functional Description
The MT8870D/MT8870D-1 monolithic DTMF
receiver offers small size, low power consumption
and high performance. Its architecture consists of a
bandsplit filter section, which separates the high and
low group tones, followed by a digital counting
section which verifies the frequency and duration of
the received tones before passing the corresponding
code to the output bus.
Filter Section
Separation of the low-group and high group tones is
achieved by applying the DTMF signal to the inputs
of two sixth-order switched capacitor bandpass
filters, the bandwidths of which correspond to the lo w
and high group frequencies. The filter section also
incorporates notches at 350 and 440 Hz for
exceptional dial tone rejection (see Figure 3). Each
filter output is followed by a single order switched
capacitor filter section which smooths the signals
prior to limiting. Limiting is performed by high-gain
comparators which are provided with hysteresis to
prevent detection of unwanted low-level signals. The
outputs of the comparators provide full rail logic
swings at the frequencies of the incoming DTMF
signals.
Decoder Section
Following the filter section is a decoder employing
digital counting techniques to determine the
frequencies of the incoming tones and to verify that
they correspond to standard DTMF frequencies. A
complex averaging algorithm protects against tone
simulation b y extraneous signals such as voice while
Figure 4 - Basic Steering Circuit
providing tolerance to small frequency deviations
and variations. This averaging algorithm has been
developed to ensure an optimum combination of
immunity to talk-off and tolerance to the presence of
interfering frequencies (third tones) and noise. When
the detector recognizes the presence of two valid
tones (this is referred to as the “signal condition” in
some industry specifications) the “Early Steering”
(ESt) output will go to an active state. Any
subsequent loss of signal condition will cause ESt to
assume an inactive state (see “Steering Circuit”).
Steering Circuit
Before registration of a decoded tone pair, the
receiver checks for a v alid signal dur ation (referred to
as character recognition condition). This check is
perfor med by an external RC time constant dr iven by
ESt. A logic high on ESt causes vc (see Figure 4) to
rise as the capacitor discharges. Provided signal
VDD
C
vc
VDD
St/GT
ESt
StD
MT8870D/
MT8870D-1
R
tGTA=(RC)In(VDD/VTSt)
tGTP=(RC)In[VDD/(VDD-VTSt)]
Figure 3 - Filter Response
0
10
20
30
40
50
ATTENUATION
(dB)
XY ABCD
1kHz EF G H
PRECISE
DIAL TONES
X=350 Hz
Y=440 Hz
DTMF TONES
A=697 Hz
B=770 Hz
C=852 Hz
D=941 Hz
E=1209 Hz
F=1336 Hz
G=1477 Hz
H=1633 Hz
FREQUENCY (Hz)
MT8870D/MT8870D-1 ISO2-CMOS
4-14
condition is maintained (ESt remains high) for the
validation period (tGTP), vc reaches the threshold
(VTSt) of the steering logic to register the tone pair,
latching its corresponding 4-bit code (see Table 1)
into the output latch. At this point the GT output is
activated and drives vcto VDD. GT continues to dr ive
high as long as ESt remains high. Finally, after a
short delay to allow the output latch to settle, the
delayed steering output flag (StD) goes high,
signalling that a received tone pair has been
registered. The contents of the output latch are
made available on the 4-bit output bus by raising the
three state control input (TOE) to a logic high. The
steering circuit works in reverse to validate the
interdigit pause between signals. Thus, as well as
rejecting signals too short to be considered valid, the
receiver will tolerate signal interruptions (dropout)
too short to be considered a valid pause. This facility,
together with the capability of selecting the steering
time constants externally, allows the designer to
tailor performance to meet a wide variety of system
requirements.
Guard Time Adjustment
In many situations not requiring selection of tone
duration and interdigital pause, the simple steering
circuit shown in Figure 4 is applicable. Component
values are chosen according to the for mula:
t
REC
=t
DP
+t
GTP
t
ID
=t
DA
+t
GTA
The value of tDP is a device parameter (see Figure
11) and tREC is the minimum signal duration to be
recognized by the receiver. A value for C of 0.1 µF is
Figure 5 - Guard Time Adjustment
Table 1. Functional Decode Table
L=LOGIC LOW, H=LOGIC HIGH, Z=HIGH IMPEDANCE
X = DON‘T CARE
recommended for most applications, leaving R to be
selected by the designer.
Different steering arrangements may be used to
select independently the guard times for tone
present (tGTP) and tone absent (tGTA). This may be
necessary to meet system specifications which place
both accept and reject limits on both tone duration
and interdigital pause. Guard time adjustment also
allows the designer to tailor system parameters
such as talk off and noise immunity. Increasing tREC
improves talk-off performance since it reduces the
probability that tones simulated by speech will
maintain signal condition long enough to be
registered. Alternatively, a relatively short tREC with
a long tDO would be appropriate for extremely noisy
environments where fast acquisition time and
immunity to tone drop-outs are required. Design
information for guard time adjustment is shown in
Figure 5.
VDD
St/GT
ESt
C1
R1R2
a) decreasing tGTP; (tGTP<tGTA)
tGTP=(RPC1)In[VDD/(VDD-VTSt)]
tGTA=(R1C1)In(VDD/VTSt)
RP=(R1R2)/(R1+R2)
VDD
St/GT
ESt
C1
R1R2
tGTP=(R1C1)In[VDD/(VDD-VTSt)]
tGTA=(RPC1)In(VDD/VTSt)
RP=(R1R2)/(R1+R2)
b) decreasing tGTA; (tGTP>tGTA)
Digit TOE INH ESt Q4Q3Q2Q1
ANYLXHZZZZ
1HXH0001
2HXH0010
3HXH0011
4HXH0100
5HXH0101
6HXH0110
7HXH0111
8HXH1000
9HXH1001
0HXH1010
*HXH1011
#HXH1100
AHLH1101
BHLH1110
CHLH1111
DHLH0000
AHHL
undetected, the output code
will remain the same as the
previous detected code
BHHL
CHHL
DHHL
ISO2-CMOS MT8870D/MT8870D-1
4-15
Power-down and Inhibit Mode
A logic high applied to pin 6 (PWDN) will pow er down
the device to minimize the power consumption in a
standby mode. It stops the oscillator and the
functions of the filters.
Inhibit mode is enabled by a logic high input to the
pin 5 (INH). It inhibits the detection of tones
representing characters A, B, C, and D. The output
code will remain the same as the previous detected
code (see Table 1).
Differential Input Configuration
The input arrangement of the MT8870D/MT8870D-1
provides a differential-input operational amplifier as
well as a bias source (VRef) which is used to bias the
inputs at mid-rail. Pro vision is made for connection of
a feedback resistor to the op-amp output (GS) for
adjustment of gain. In a single-ended configuration,
the input pins are connected as shown in Figure 10
with the op-amp connected for unity gain and VRef
biasing the input at 1/2VDD. Figure 6 shows the
differential configuration, which permits the
adjustment of gain with the feedback resistor R5.
Crystal Oscillator
The internal clock circuit is completed with the
addition of an external 3.579545 MHz crystal and is
normally connected as shown in Figure 10 (Single-
Ended Input Configuration). Howev er, it is possible to
configure several MT8870D/MT8870D-1 devices
employing only a single oscillator crystal. The
oscillator output of the first device in the chain is
coupled through a 30 pF capacitor to the oscillator
input (OSC1) of the next device. Subsequent devices
are connected in a similar fashion. Refer to Figure 7
for details. The problems associated with
unbalanced loading are not a concern with the
arrangement shown, i.e., precision balancing
capacitors are not required.
Figure 6 - Differential Input Configuration
Figure 7 - Oscillator Connection
Table 2. Recommended Resonator Specifications
Note: Qm=quality factor of RLC model, i.e., 1/2ΠƒR1C1.
Parameter Unit Resonator
R1 Ohms 10.752
L1 mH .432
C1 pF 4.984
C0 pF 37.915
Qm - 896.37
f%±0.2%
C1R1
C2R4
R3
IN+
IN-
+
-
R5GS
R2VRef
MT8870D/
MT8870D-1
Differential Input Amplifier
C1=C2=10 nF
R1=R4=R5=100 k
R2=60k, R3=37.5 kAll resistors are ±1% tolerance.
All capacitors are ±5% tolerance.
R3=R2R5
R2+R5
VOLTAGE GAIN (Av diff)= R5
R1
INPUT IMPEDANCE
(ZINDIFF) = 2 R12+1
ωc
2
OSC1
OSC2
OSC2
OSC1
C
X-tal
C
To OSC1 of next
MT8870D/MT8870D-1
C=30 pF
X-tal=3.579545 MHz
MT8870D/MT8870D-1 ISO2-CMOS
4-16
Applications
RECEIVER SYSTEM FOR BRITISH TELECOM
SPEC POR 1151
The circuit shown in Fig. 9 illustrates the use of
MT8870D-1 device in a typical receiver system. BT
Spec defines the input signals less than -34 dBm as
the non-operate level. This condition can be attained
by choosing a suitable values of R1 and R2 to
provide 3 dB attenuation, such that -34 dBm input
signal will correspond to -37 dBm at the gain setting
pin GS of MT8870D-1. As shown in the diagram, the
component values of R3 and C2 are the guard time
requirements when the total component tolerance is
6%. For better performance, it is recommended to
use the non-symmetric guard time circuit in Fig. 8.
Figure 8 - Non-Symmetric Guard Time Circuit
tGTP=(RPC1)In[VDD/(VDD-VTSt)]
tGTA=(R1C1)In(VDD/VTSt)
RP=(R1R2)/(R1+R2)
VDD
St/GT
ESt
C1
R2
R1Notes:
R1=368K Ω ± 1%
R2=2.2M Ω ± 1%
C1=100nF ± 5%
Figure 9 - Single-Ended Input Configuration for BT or CEPT Spec
IN+
IN-
GS
VRef
INH
PWDN
OSC 1
OSC 2
VSS TOE
VDD
St/GT
ESt
StD
Q4
Q3
Q2
Q1
DTMF
Input
C1
R1
R2
X1
VDD
C2
R3
MT8870D-1
NOTES:
R1 = 102KΩ ± 1%
R2 = 71.5KΩ ± 1%
R3 = 390KΩ ±1 %
C1,C2 = 100 nF ± 5%
X1 = 3.579545 MHz ± 0.1%
VDD = 5.0V ± 5%
ISO2-CMOS MT8870D/MT8870D-1
4-17
Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Derate above 75 °C at 16 mW / °C. All leads soldered to board.
Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
Absolute Maximum Ratings
Parameter Symbol Min Max Units
1 DC Power Supply Voltage VDD 7V
2 Voltage on any pin VIVSS-0.3 VDD+0.3 V
3 Current at any pin (other than supply) II10 mA
4 Storage temperature TSTG -65 +150 °C
5 Package power dissipation PD500 mW
Recommended Operating Conditions -Voltages are with respect to ground (VSS) unless otherwise stated.
Parameter Sym Min TypMax Units Test Conditions
1 DC Power Supply Voltage VDD 4.75 5.0 5.25 V
2 Operating Temperature TO-40 +85 °C
3 Crystal/Clock Frequency fc 3.579545 MHz
4 Crystal/Clock Freq.Tolerance fc ±0.1 %
DC Electrical Characteristics -VDD=5.0V± 5%, VSS=0V, -40°C TO +85°C, unless otherwise stated.
Characteristics Sym Min TypMax Units Test Conditions
1S
U
P
P
L
Y
Standby supply current IDDQ 10 25 µA PWDN=VDD
2 Operating supply current IDD 3.0 9.0 mA
3 Power consumption PO15 mW fc=3.579545 MHz
4
I
N
P
U
T
S
High level input VIH 3.5 V VDD=5.0V
5 Low level input voltage VIL 1.5 V VDD=5.0V
6 Input leakage current IIH/IIL 0.1 µAV
IN=VSS or VDD
7 Pull up (source) current ISO 7.5 20 µA TOE (pin 10)=0,
VDD=5.0V
8 Pull down (sink) current ISI 15 45 µA INH=5.0V, PWDN=5.0V,
VDD=5.0V
9 Input impedance (IN+, IN-) RIN 10 M@ 1 kHz
10 Steering threshold voltage VTSt 2.2 2.4 2.5 V VDD = 5.0V
11
O
U
T
P
U
T
S
Low level output voltage VOL VSS+0.03 V No load
12 High level output voltage VOH VDD-0.03 V No load
13 Output low (sink) current IOL 1.0 2.5 mA VOUT=0.4 V
14 Output high (source) current IOH 0.4 0.8 mA VOUT=4.6 V
15 VRef output voltage VRef 2.3 2.5 2.7 V No load, VDD = 5.0V
16 VRef output resistance ROR 1k
MT8870D/MT8870D-1 ISO2-CMOS
4-18
Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing.
*NOTES
1. dBm= decibels above or below a reference power of 1 mW into a 600 ohm load.
2. Digit sequence consists of all DTMF tones.
3. Tone duration= 40 ms, tone pause= 40 ms.
4. Signal condition consists of nominal DTMF frequencies.
5. Both tones in composite signal have an equal amplitude.
6. Tone pair is deviated by ±1.5 %± 2 Hz.
7. Bandwidth limited (3 kHz ) Gaussian noise.
8. The precise dial tone frequencies are (350 Hz and 440 Hz) ± 2 %.
9. For an error rate of better than 1 in 10,000.
10. Referenced to lowest level frequency component in DTMF signal.
11. Referenced to the minimum valid accept level.
12. Guaranteed by design and characterization.
Operating Characteristics - VDD=5.0V±5%, VSS=0V, -40°C TO +85°C ,unless otherwise stated.
Gain Setting Amplifier
Characteristics Sym Min TypMax Units Test Conditions
1 Input leakage current IIN 100 nA VSS VIN VDD
2 Input resistance RIN 10 M
3 Input offset voltage VOS 25 mV
4 Power supply rejection PSRR 50 dB 1 kHz
5 Common mode rejection CMRR 40 dB 0.75 V VIN 4.25 V biased
at VRef =2.5 V
6 DC open loop voltage gain AVOL 32 dB
7 Unity gain bandwidth fC0.30 MHz
8 Output voltage swing VO4.0 Vpp Load 100 k to VSS @ GS
9 Maximum capacitive load (GS) CL100 pF
10 Resistive load (GS) RL50 k
11 Common mode range VCM 2.5 Vpp No Load
MT8870D AC Electrical Characteristics -V
DD=5.0V ±5%, VSS=0V, -40°C TO +85°C , using Test Circuit shown in
Figure 10.
Characteristics Sym Min TypMax Units Notes*
1V alid input signal le vels (each
tone of composite signal) -29 +1 dBm 1,2,3,5,6,9
27.5 869 mVRMS 1,2,3,5,6,9
2 Negative twist accept 8 dB 2,3,6,9,12
3 Positive twist accept 8 dB 2,3,6,9,12
4 Frequency deviation accept ±1.5% ± 2 Hz 2,3,5,9
5 Frequency deviation reject ±3.5% 2,3,5,9
6 Third tone tolerance -16 dB 2,3,4,5,9,10
7 Noise tolerance -12 dB 2,3,4,5,7,9,10
8 Dial tone tolerance +22 dB 2,3,4,5,8,9,11
ISO2-CMOS MT8870D/MT8870D-1
4-19
Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing.
*NOTES
1. dBm= decibels above or below a reference power of 1 mW into a 600 ohm load.
2. Digit sequence consists of all DTMF tones.
3. Tone duration= 40 ms, tone pause= 40 ms.
4. Signal condition consists of nominal DTMF frequencies.
5. Both tones in composite signal have an equal amplitude.
6. Tone pair is deviated by ±1.5 %± 2 Hz.
7. Bandwidth limited (3 kHz ) Gaussian noise.
8. The precise dial tone frequencies are (350 Hz and 440 Hz) ± 2 %.
9. For an error rate of better than 1 in 10,000.
10. Referenced to lowest level frequency component in DTMF signal.
11. Referenced to the minimum valid accept level.
12. Referenced to Fig. 10 input DTMF tone level at -25dBm (-28dBm at GS Pin) interference frequency range between 480-3400Hz.
13. Guaranteed by design and characterization.
MT8870D-1 AC Electrical Characteristics -V
DD=5.0V±5%, VSS=0V, -40°C TO +85°C , using Test Circuit shown
in Figure 10.
Characteristics Sym Min TypMax Units Notes*
1Valid input signal le vels (each
tone of composite signal) -31 +1 dBm T ested at VDD=5.0V
1,2,3,5,6,9
21.8 869 mVRMS
2 Input Signal Level Reject -37 dBm Tested at VDD=5.0V
1,2,3,5,6,9
10.9 mVRMS
3 Negative twist accept 8 dB 2,3,6,9,13
4 Positive twist accept 8 dB 2,3,6,9,13
5 Frequency deviation accept ±1.5%± 2 Hz 2,3,5,9
6 Frequency deviation reject ±3.5% 2,3,5,9
7 Third zone tolerance -18.5 dB 2,3,4,5,9,12
8 Noise tolerance -12 dB 2,3,4,5,7,9,10
9 Dial tone tolerance +22 dB 2,3,4,5,8,9,11
MT8870D/MT8870D-1 ISO2-CMOS
4-20
Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
*NOTES:
1. Used for guard-time calculation purposes only.
2. These, user adjustable parameters, are not device specifications. The adjustable settings of these minimums and maximums
are recommendations based upon network requirements.
3. With valid tone present at input, tPU equals time from PDWN going low until ESt going high.
Figure 10 - Single-Ended Input Configuration
AC Electrical Characteristics - VDD=5.0V±5%, VSS=0V, -40°C To +85°C , using Test Circuit shown in Figure 10.
Characteristics Sym Min TypMax Units Conditions
1
T
I
M
I
N
G
Tone present detect time tDP 5 11 14 ms Note 1
2 Tone absent detect time tDA 0.5 4 8.5 ms Note 1
3 Tone duration accept tREC 40 ms Note 2
4 Tone duration reject tREC 20 ms Note 2
5 Interdigit pause accept tID 40 ms Note 2
6 Interdigit pause reject tDO 20 ms Note 2
7
O
U
T
P
U
T
S
Propagation delay (St to Q) tPQ 811µs TOE=VDD
8 Propagation delay (St to StD) tPStD 12 16 µs TOE=VDD
9 Output data set up (Q to StD) tQStD 3.4 µs TOE=VDD
10 Propagation delay (TOE to Q ENABLE) tPTE 50 ns load of 10 k,
50 pF
11 Propagation delay (TOE to Q DISABLE) tPTD 300 ns load of 10 k,
50 pF
12 P
D
W
N
Power-up time tPU 30 ms Note 3
13 Power-down time tPD 20 ms
14
C
L
O
C
K
Crystal/clock frequency fC3.5759 3.5795 3.5831 MHz
15 Clock input rise time tLHCL 110 ns Ext. clock
16 Clock input fall time tHLCL 110 ns Ext. clock
17 Clock input duty cycle DCCL 40 50 60 % Ext. clock
18 Capacitive load (OSC2) CLO 30 pF
IN+
IN-
GS
VRef
INH
PDWN
OSC 1
OSC 2
VSS TOE
VDD
St/GT
ESt
StD
Q4
Q3
Q2
Q1
DTMF
Input
C1
R1
R2
X-tal
VDD
C2
R3
NOTES:
R1,R2=100KΩ ± 1%
R3=300KΩ ± 1%
C1,C2=100 nF ± 5%
X-tal=3.579545 MHz ± 0.1%
MT8870D/MT8870D-1
ISO2-CMOS MT8870D/MT8870D-1
4-21
Figure 11 - Timing Diagram
EXPLANATION OF EVENTS
EXPLANATION OF SYMBOLS
A) TONE BURSTS DETECTED, TONE DURATION INVALID, OUTPUTS NOT UPDATED.
B) TONE #n DETECTED, TONE DURATION VALID, TONE DECODED AND LATCHED IN OUTPUTS
C) END OF TONE #n DETECTED, TONE ABSENT DURATION VALID, OUTPUTS REMIAN LATCHED UNTIL NEXT VALID
TONE.
D) OUTPUTS SWITCHED TO HIGH IMPEDANCE STATE.
E) TONE #n + 1 DETECTED, TONE DURATION VALID, TONE DECODED AND LATCHED IN OUTPUTS (CURRENTLY
HIGH IMPEDANCE).
F) ACCEPTABLE DROPOUT OF TONE #n + 1, TONE ABSENT DURATION INVALID, OUTPUTS REMAIN LATCHED.
G) END OF TONE #n + 1 DETECTED, TONE ABSENT DURATION VALID, OUTPUTS REMAIN LATCHED UNTIL NEXT
VALID TONE.
Vin DTMF COMPOSITE INPUT SIGNAL.
ESt EARLY STEERING OUTPUT. INDICATES DETECTION OF VALID TONE FREQUENCIES.
St/GT STEERING INPUT/GUARD TIME OUTPUT. DRIVES EXTERNAL RC TIMING CIRCUIT.
Q1-Q44-BIT DECODED TONE OUTPUT.
StD DELAYED STEERING OUTPUT. INDICATES THAT VALID FREQUENCIES HAVE BEEN PRESENT/ABSENT FOR THE
REQUIRED GUARD TIME THUS CONSTITUTING A VALID SIGNAL.
TOE TONE OUTPUT ENABLE (INPUT). A LOW LEVEL SHIFTS Q1-Q4 TO ITS HIGH IMPEDANCE STATE.
tREC MAXIMUM DTMF SIGNAL DURATION NOT DETECED AS VALID
tREC MINIMUM DTMF SIGNAL DURATION REQUIRED FOR VALID RECOGNITION
tID MAXIMUM TIME BETWEEN VALID DTMF SIGNALS.
tDO MAXIMUM ALLOWABLE DROP OUT DURING VALID DTMF SIGNAL.
tDP TIME TO DETECT THE PRESENCE OF VALID DTMF SIGNALS.
tDA TIME TO DETECT THE ABSENCE OF VALID DTMF SIGNALS.
tGTP GUARD TIME, TONE PRESENT.
tGTA GUARD TIME, TONE ABSENT.
Vin
ESt
St/GT
Q1-Q4
StD
TOE
EVENTS ABC
D
EFG
t
REC tREC tID tDO
TONE #n TONE
#n + 1 TONE
#n + 1
tDP tDA
tGTP tGTA
tPQ tQStD
tPSrD
tPTD
tPTE
# n # (n + 1)
HIGH IMPEDANCE
DECODED TONE # (n-1)
VTSt
4-33
MT8880C/MT8880C-1
Integrated DTMF Transceiver
Features
Complete DTMF transmitter/receiver
Central office quality
Low power consumption
Microprocessor por t
Adjustable guard time
Automatic tone burst mode
Call progress mode
Applications
Credit card systems
Paging systems
Repeater systems/mobile radio
Interconnect dialers
Personal computers
Description
The MT8880C/C-1 is a monolithic DTMF transceiver
with call progress filter. It is fabricated in Mitel’s
ISO2-CMOS technology, which provides low power
dissipation and high reliability. The DTMF receiver is
based upon the industry standard MT8870
monolithic DTMF receiver; the transmitter utilizes a
switched capacitor D/A converter for low distortion,
high accuracy DTMF signalling. Internal counters
provide a burst mode such that tone bursts can be
transmitted with precise timing. A call progress filter
can be selected allowing a microprocessor to
analyze call progress tones. A standard
microprocessor bus is provided and is directly
compatible with 6800 series microprocessors. The
MT8880C-1 is functionally identical to the MT8880C
except for the performance of the receiver section,
which is enhanced to accept and reject lower signal
levels.
Ordering Information
MT8880CE/CE-1 20 Pin Plastic DIP
MT8880CC/CC-1 20 Pin Ceramic DIP
MT8880CS/CS-1 20 Pin SOIC
MT8880CN/CN-1 24 Pin SSOP
MT8880CP/CP-1 28 Pin Plastic LCC
-40°C to +85°C
Figure 1 - Functional Block Diagram
TONE
IN+
IN-
GS
OSC1
OSC2
VDD VRef VSS ESt St/GT
D0
D1
D2
D3
IRQ/CP
Φ2
CS
R/W
RS0
D/A
Converters Row and
Column
Counters Transmit Data
Register
Data
Bus
Buffer
Tone Burst
Gating Cct.
+
-
Oscillator
Circuit
Bias
Circuit
Control
Logic
Digital
Algorithm
and Code
Converter
Control
Logic
Steering
Logic
Status
Register
Control
Register
A
Control
Register
B
Receive Data
Register
Interrupt
Logic
I/O
Control
Low Group
Filter
High Group
Filter
Dial
Tone
Filter
ISSUE 3 September 1995
ISO2-CMOS
MT8880C/MT8880C-1 ISO2-CMOS
4-34
Figure 2 - Pin Connections
Pin Description
Pin # Name Description
20 24 28
1 1 1 IN+ Non-inverting op-amp input.
2 2 2 IN- Inverting op-amp input.
334 GSGain Select. Gives access to output of front end differential amplifier for connection of
feedback resistor.
446V
Ref Reference Voltage output, nominally VDD/2 is used to bias inputs at mid-rail (see Fig. 13).
557V
SS Ground input (0V).
6 6 8 OSC1 DTMF clock/oscillator input.
7 7 9 OSC2 Clock output. A 3.579545 MHz crystal connected between OSC1 and OSC2 completes the
internal oscillator circuit. Leave open circuit when OSC1 is clock input.
8 10 12 TONE Tone output (DTMF or single tone).
91113R/WRead/Write input. Controls the direction of data transfer to and from the MPU and the
transceiver registers. TTL compatible.
10 12 14 CS Chip Select, TTL input (CS=0 to select the chip).
11 13 15 RS0 Register Select input. See register decode table. TTL compatible.
12 14 17 Φ2System Clock input. TTL compatible. N.B. Φ2 clock input need not be active when the
device is not being accessed.
13 15 18 IRQ/
CP Interrupt Request to MPU (open drain output). Also, when call progress (CP) mode has
been selected and interrupt enabled the IRQ/CP pin will output a rectangular wave signal
representative of the input signal applied at the input op-amp. The input signal must be within
the bandwidth limits of the call progress filter. See Figure 8.
14-
17 18-
21 19-
22 D0-D3 Microprocessor Data Bus (TTL compatible). High impedance when CS = 1 or Φ2 is low.
18 22 26 ESt Early Steering output. Presents a logic high once the digital algorithm has detected a valid
tone pair (signal condition). Any momentary loss of signal condition will cause ESt to return to
a logic low.
19 23 27 St/GT Steering Input/Guard Time output (bidirectional). A voltage greater than VTSt detected at St
causes the device to register the detected tone pair and update the output latch. A voltage
less than VTSt frees the device to accept a new tone pair. The GT output acts to reset the
external steering time-constant; its state is a function of ESt and the voltage on St.
20 24 28 VDD Positive power supply input (+5V typical).
8,9
16,
17
3,5,
10,
11,
16,
23-
25
NC No Connection.
1
2
3
4
5
6
7
8
9
10 11
12
20
19
18
17
16
15
14
13
IN+
IN-
GS
VRef
VSS
OSC1
OSC2
TONE
R/W
CS
VDD
St/GT
ESt
D3
D2
D1
D0
IRQ/CP
Φ2
RS0
20 PIN CERDIP/PLASTIC DIP/SOIC 28 PIN PLCC
4
5
6
7
8
9
10
11
25
24
23
22
21
20
19
GS
NC
VRef
VSS
OSC1
OSC2
NC
NC
Φ2
3
2
1
28
27
26
12
13
14
15
16
17
18
NC
IN-
IN+
VDD
St/GT
EST
TONE
R/W
CS
RS0
NC
IRQ/CP
NC
NC
NC
D3
D2
D1
D0
1
2
3
4
5
6
7
8
9
10
11
12 13
14
15
16
24
23
22
21
20
19
18
17
IN+
IN-
GS
VRef
VSS
OSC1
OSC2
NC
TONE
R/W
CS
VDD
St/GT
ESt
D3
D2
D1
D0 NC
NC
NC
IRQ/CP
Φ2
RS0
24 PIN SSOP
ISO2-CMOS MT8880C/MT8880C-1
4-35
Functional Description
The MT8880C/C-1 Integrated DTMF Transceiver
architecture consists of a high performance DTMF
receiver with internal gain setting amplifier and a
DTMF generator which employs a burst counter such
that precise tone bursts and pauses can be
synthesized. A call progress mode can be selected
such that frequencies within the specified passband
can be detected. A standard microprocessor
interface allows access to an internal status register,
two control registers and two data registers.
Input Configuration
The input arrangement of the MT8880C/C-1 provides
a differential-input operational amplifier as well as a
bias source (VRef) which is used to bias the inputs at
VDD/2. Provision is made for connection of a
feedback resistor to the op-amp output (GS) for
adjustment of gain. In a single-ended configuration,
the input pins are connected as shown in Figure 3.
Figure 4 shows the necessary connections for a
differential input configuration.
Figure 3 - Single-Ended Input Configuration
Receiver Section
Separation of the low and high group tones is
achieved by applying the DTMF signal to the inputs
of two sixth-order switched capacitor bandpass
filters, the bandwidths of which correspond to the lo w
and high group frequencies (see Fig. 7). These filters
also incorporate notches at 350 Hz and 440 Hz for
exceptional dial tone rejection. Each filter output is
followed by a single order switched capacitor filter
section which smooths the signals prior to limiting.
Limiting is perfor med by high-gain comparators
Figure 4 - Differential Input Configuration
which are provided with hysteresis to prevent
detection of unwanted low-level signals. The outputs
of the comparators provide full r ail logic swings at the
frequencies of the incoming DTMF signals.
Following the filter section is a decoder employing
digital counting techniques to determine the
frequencies of the incoming tones and to verify that
they correspond to standard DTMF frequencies. A
complex averaging algorithm protects against tone
simulation by extraneous signals such as voice while
providing tolerance to small frequency deviations
and variations. This averaging algorithm has been
developed to ensure an optimum combination of
immunity to talk-off and tolerance to the presence of
interfering frequencies (third tones) and noise. When
the detector recognizes the presence of two valid
tones (this is referred to as the “signal condition” in
some industry specifications) the “Early Steering”
(ESt) output will go to an active state. Any
subsequent loss of signal condition will cause ESt to
assume an inactive state.
CRIN
RF
IN+
IN-
GS
VRef
VOLTAGE GAIN
(AV) = RF / RIN
MT8880C/C-1
C1
C2
R1
R2
R3
R4 R5
IN+
IN-
GS
VRef
MT8880C/C-1
DIFFERENTIAL INPUT AMPLIFIER
C1 = C2 = 10 nF
R1 = R4 = R5 = 100 k
R2 = 60k, R3 = 37.5 k
R3 = (R2R5)/(R2 + R5)
VOLTAGE GAIN
(AV diff) = R5/R1
INPUT IMPEDANCE
(ZINdiff) = 2 R12 + (1/ωC)2
MT8880C/MT8880C-1 ISO2-CMOS
4-36
Steering Circuit
Before registration of a decoded tone pair, the
receiver checks for a valid signal duration (referred to
as character recognition condition). This check is
perfor med by an external RC time constant dr iven by
ESt. A logic high on ESt causes vc (see Figure 5) to
rise as the capacitor discharges. Provided that the
signal condition is maintained (ESt remains high) for
the validation period (tGTP), vc reaches the threshold
(VTSt) of the steering logic to register the tone pair,
latching its corresponding 4-bit code (see Figure 7)
into the Receive Data Register. At this point the GT
output is activated and drives vcto VDD. GT
continues to drive high as long as ESt remains high.
Finally, after a short delay to allow the output latch to
settle, the delayed steering output flag goes high,
signalling that a received tone pair has been
registered. The status of the delayed steering flag
can be monitored by checking the appropriate bit in
the status register. If Interrupt mode has been
selected, the IRQ/CP pin will pull low when the
delayed steering flag is active.
The contents of the output latch are updated on an
active delayed steering transition. This data is
presented to the four bit bidirectional data bus when
the Receive Data Register is read. The steering
circuit works in reverse to validate the interdigit
pause between signals. Thus, as well as rejecting
signals too shor t to be considered valid, the receiver
will tolerate signal interruptions (drop out) too short
to be considered a valid pause. This facility, together
with the capability of selecting the steering time
constants externally, allows the designer to tailor
performance to meet a wide variety of system
requirements.
Figure 5 - Basic Steering Circuit
Guard Time Adjustment
The simple steering circuit shown in Figure 5 is
adequate for most applications. Component values
are chosen according to the formula:
t
REC
= t
DP
+t
GTP
t
ID
=t
DA
+t
GTA
The value of tDP is a device parameter (see AC
Electrical Characteristics) and tREC is the minimum
signal duration to be recognized by the receiver. A
value for C1 of 0.1 µF is recommended for most
applications, leaving R1 to be selected by the
designer. Different steering arrangements may be
used to select independently the guard times f or tone
present (tGTP) and tone absent (tGTA). This may be
necessary to meet system specifications which place
both accept and reject limits on both tone duration
and interdigital pause. Guard time adjustment also
allows the designer to tailor system parameters such
as talk off and noise immunity.
Figure 6 - Guard Time Adjustment
VDD
VDD
St/GT
ESt
C1
Vc
R1
MT8880C/C-1
tGTA = (R1C1) In (VDD / VTSt)
tGTP = (R1C1) In [VDD / (VDD-VTSt)]
VDD
St/GT
ESt
VDD
St/GT
ESt
C1
R1 R2
C1
R1 R2
tGTA = (R1C1) In (VDD/VTSt)
tGTP = (RPC1) In [VDD / (VDD-VTSt)]
RP = (R1R2) / (R1 + R2)
tGTA = (R
p
C1) In (VDD/VTSt)
tGTP = (R1C1) In [VDD / (VDD-VTSt)
RP = (R1R2) / (R1 + R2)
a) decreasing tGTP; (tGTP < tGTA)
b) decreasing tGTA; (tGTP > tGTA)
ISO2-CMOS MT8880C/MT8880C-1
4-37
Increasing tREC improves talk-off performance since
it reduces the probability that tones simulated by
speech will maintain a valid signal condition long
enough to be registered. Alternatively, a relatively
short tREC with a long tDO would be appropriate for
extremely noisy environments where fast acquisition
time and immunity to tone drop-outs are required.
Design information for guard time adjustment is
shown in Figure 6. The receiver timing is shown in
Figure 9 with a description of the events in Figure 11.
Call Progress Filter
A call progress mode, using the MT8880C/C-1, can
be selected allowing the detection of various tones
which identify the progress of a telephone call on the
network. The call progress tone input and DTMF
input are common, however, call progress tones can
only be detected when CP mode has been selected.
DTMF signals cannot be detected if CP mode has
been selected (see Table 5). Figure 8 indicates the
useful detect bandwidth of the call progress filter.
Frequencies presented to the input, which are within
the ‘accept’ bandwidth limits of the filter, are hard-
limited by a high gain comparator with the IRQ/CP
pin serving as the output. The squarewave output
obtained from the schmitt trigger can be analyzed by
a microprocessor or counter arrangement to
determine the nature of the call progress tone being
detected. Frequencies which are in the ‘reject’ area
will not be detected and consequently the IRQ/CP
pin will remain low.
DTMF Generator
The DTMF transmitter employed in the MT8880C/C-
1 is capable of generating all sixteen standard DTMF
tone pairs with low distortion and high accuracy. All
frequencies are derived from an external 3.579545
MHz crystal. The sinusoidal waveforms for the
individual tones are digitally synthesized using row
and column programmable dividers and switched
capacitor D/A converters. The row and column tones
are mixed and filtered providing a DTMF signal with
low total harmonic distortion and high accuracy. To
specify a DTMF signal, data conforming to the
encoding f ormat shown in Figure 7 must be written to
the transmit Data Register. Note that this is the same
as the receiver output code. The individual tones
which are generated (fLOW and fHIGH) are referred to
as Low Group and High Group tones. As seen from
the table, the low group frequencies are 697, 770,
852 and 941 Hz. The high group frequencies are
1209, 1336, 1477 and 1633 Hz. Typically, the high
group to low group amplitude ratio (pre-emphasis) is
2dB to compensate for high group attenuation on
long loops.
0= LOGIC LOW, 1= LOGIC HIGH
Figure 7 - Functional Encode/Decode Table
Figure 8 - Call Progress Response
The period of each tone consists of 32 equal time
segments. The period of a tone is controlled by
varying the length of these time segments. During
write operations to the Transmit Data Register the 4
bit data on the bus is latched and conver ted to 2 of 8
coding for use by the programmable divider circuitr y.
This code is used to specify a time segment length
which will ultimately determine the frequency of the
tone. When the divider reaches the appropriate
count, as determined by the input code, a reset pulse
is issued and the counter starts again. The number
FLOW FHIGH DIGIT D3D2D1D0
697 1209 1 0001
697 1336 2 0010
697 1477 3 0011
770 1209 4 0100
770 1336 5 0101
770 1477 6 0110
852 1209 7 0111
852 1336 8 1000
852 1477 9 1001
941 1336 0 1010
941 1209 * 1011
941 1477 # 1100
697 1633 A 1101
770 1633 B 1110
852 1633 C 1111
941 1633 D 0000
LEVEL
(dBm)
FREQUENCY (Hz)
-25
0 250 500 750
= Reject
= May Accept
= Accept
MT8880C/MT8880C-1 ISO2-CMOS
4-38
Figure 9 - Receiver Timing Diagram
Vin
ESt
St/GT
RX0-RX3
b3
b2
Read
Status
Register
IRQ/CP
EVENTS ABCDEF
t
REC tREC tID tDO
TONE #n TONE
#n + 1 TONE
#n + 1
tDP tDA
tGTP tGTA
tPStRX
tPStb3
DECODED TONE # (n-1) # n # (n + 1)
VTSt
of time segments is fixed at 32, however, by var ying
the segment length as described above the tone
output signal frequency will be varied. The divider
output clocks another counter which addresses the
sinewave lookup ROM.
The lookup table contains codes which are used by
the switched capacitor D/A converter to obtain
discrete and highly accurate DC voltage levels. Two
identical circuits are employed to produce row and
column tones which are then mixed using a low
noise summing amplifier. The oscillator described
needs no “start-up” time as in other DTMF
generators since the crystal oscillator is running
continuously thus providing a high degree of tone
burst accuracy. A bandwidth limiting filter is
incorporated and serves to attenuate distortion
products above 8 kHz. It can be seen from Figure 10
that the distortion products are very low in amplitude.
Figure 10 - Spectrum Plot
Scaling Information
10 dB/Div
Start Frequency = 0 Hz
Stop Frequency = 3400 Hz
Marker Frequency = 697 Hz and
1209 Hz