HIP6005BCB-T - Intersil Corporation

2-110

HIP6005B

Buck Pulse-Width Modulator (PWM)

Controller and Output Voltage Monitor

The HIP6005B provides complete control and protection for

a DC-DC converter optimized for high-performance

microprocessor applications. It is designed to drive an

N-Channel MOSFET in a standard buck topology. The

HIP6005B integrates all of the control, output adjustment,

monitoring and protection functions into a single package.

The output voltage of the converter is easily adjusted and

precisely regulated. The HIP6005B includes a fully

TTL-compatible 5-input digital-to-analog converter (DAC)

that adjusts the output voltage from 1.3VDC to 2.05VDC in

0.05V increments and from 2.1VDC to 3.5VDC in 0.1V steps.

The precision reference and voltage-mode regulator hold the

selected output voltage to within ±1% over temperature and

line voltage variations.

The HIP6005B provides simple , single f eedbac k loop, v oltage-

mode control with fast transient response. It includes a 200kHz

free-running triangle-wa ve oscillator that is adjustable from

below 50kHz to o v er 1MHz. The error amplifier f eatures a

15MHz gain-bandwidth product and 6V/µs slew r ate which

enables high con v erter bandwidth for f ast tr ansient

perf ormance. The resulting PWM duty ratio ranges from 0% to

100%.

The HIP6005B monitors the output voltage with a window

comparator that tracks the DAC output and issues a Power

Good signal when the output is within ±10%. The HIP6005B

protects against over-current and over-voltage conditions by

inhibiting PWM operation. Additional built-in over-voltage

protection triggers an external SCR to crowbar the input

supply. The HIP6005B monitors the current by using the

rDS(ON) of the upper MOSFET which eliminates the need for

a current sensing resistor.

Features

• Drives N-Channel MOSFET

• Operates from +5V or +12V Input

• Simple Single-Loop Control Design

- Voltage-Mode PWM Control

• Fast Transient Response

- High-Bandwidth Error Ampliﬁer

- Full 0% to 100% Duty Ratio

• Excellent Output Voltage Regulation

-±1% Over Line Voltage and Temperature

• TTL-Compatible 5-Bit Digital-to-Analog Output Voltage

Selection

- Wide Range . . . . . . . . . . . . . . . . . . . 1.3VDC to 3.5VDC

- 0.1V Binary Steps . . . . . . . . . . . . . . 2.1VDC to 3.5VDC

- 0.05V Binary Steps . . . . . . . . . . . . 1.3VDC to 2.05VDC

• Power-Good Output Voltage Monitor

• Over-Voltage and Over-Current Fault Monitors

- Does Not Require Extra Current Sensing Element,

Uses MOSFET’s rDS(ON)

• Small Converter Size

- Constant Frequency Operation

- 200kHz Free-Running Oscillator Progr ammable from

50kHz to over 1MHz

Applications

• Power Supply for Pentium®, Pentium Pro, Pentium II,

PowerPC™, K6™, 6X86™ and Alpha™ Microprocessors

•High-Power 5V to 3.xV DC-DC Regulators

•Low-Voltage Distributed Power Supplies

Pinout

HIP6005B

(SOIC, TSSOP)

TOP VIEW

6X86™ is a trademark of Cyrix Corporation.

Alpha Micro™ is a trademark of Digital Computer Equipment Corporation

K6™ is a trademark of Advanced Micro Devices.

Pentium® is a registered trademark of Intel Corporation.

PowerPC™ is a registered trademark of IBM.

Ordering Information

PART NUMBER TEMP.

RANGE (oC) PACKAGE PKG.

NO.

HIP6005BCB 0 to 70 20 Ld SOIC M20.3

HIP6005BCV 0 to 70 20 Ld TSSOP M20.173

NOTE: When ordering, use the entire part number. Add the sufﬁx T

to obtain the TSSOP variant in tape and reel, e.g., HIP6005BCV-T.

VSEN

OCSET

VID0

VID1

VID2

VID4

VID3

COMP

VCC

OVP

BOOT

UGATE

PHASE

PGOOD

GND

Data Sheet February 1999 File Number

4568.2

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

2-111

Typical Application

Block Diagram

+12V

+VOUT

HIP6005B

VSEN

COMP

PGOOD

GND

MONITOR AND

PROTECTION

OSC UGATE

OCSET

PHASE

BOOT

VCC VIN = +5V OR +12V

OVP

VID0

VID1

VID2

VID3 D/A

VID4

D/A

CONVERTER

(DAC)

OSCILLATOR

SOFT-

START

REFERENCE

POWER-ON

RESET (POR)

115%

110%

90%

INHIBIT

PWM

COMPARATOR

ERROR

AMP

VCC

PGOOD

PWM

OVP

RT GND

VSEN

OCSET

VID0

VID1

VID2

VID3

COMP

DACOUT

OVER-

VOLTAGE

OVER-

CURRENT

GATE

CONTROL

LOGIC

BOOT

UGATE

PHASE

200µA

10µA

VID4

HIP6005B

2-112

Absolute Maximum Ratings Thermal Information

Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +15V

Boot Voltage, VBOOT - VPHASE. . . . . . . . . . . . . . . . . . . . . . . . +15V

Input, Output or I/O Voltage . . . . . . . . . . . .GND -0.3V to VCC +0.3V

ESD Classiﬁcation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Class 2

Operating Conditions

Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . +12V ±10%

Ambient Temperature Range. . . . . . . . . . . . . . . . . . . . . 0oC to 70oC

Thermal Resistance (Typical, Note 1) θJA (oC/W)

SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

SOIC Package (with 3in2 of Copper) . . . . . . . . . . . . 86

TSSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . 150oC

Maximum Storage Temperature Range. . . . . . . . . . -65oC to 150oC

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC

(Lead Tips Only)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe

device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.

NOTE:

1. θJA is measured with the component mounted on an evaluation PC board in free air.

Electrical Speciﬁcations Recommended Operating Conditions, Unless Otherwise Noted

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

VCC SUPPLY CURRENT

Nominal Supply ICC UGATE Open - 5 - mA

POWER-ON RESET

Rising VCC Threshold VOCSET = 4.5V - - 10.4 V

Falling VCC Threshold VOCSET = 4.5V 8.2 - - V

Rising VOCSET Threshold - 1.26 - V

OSCILLATOR

Free Running Frequency RT = Open 185 200 215 kHz

Total Variation 6kΩ < RT to GND < 200kΩ-15 - +15 %

Ramp Amplitude ∆VOSC RT = Open - 1.9 - VP-P

REFERENCE AND DAC

DAC (VID0-VID4) Input Low Voltage - - 0.8 V

DAC (VID0-VID4) Input High Voltage 2.0 - - V

DACOUT Voltage Accuracy -1.0 - +1.0 %

ERROR AMPLIFIER

DC Gain -88- dB

Gain-Bandwidth Product GBW - 15 - MHz

Slew Rate SR COMP = 10pF - 6 - V/µs

GATE DRIVER

Upper Gate Source IUGATE VBOOT - VPHASE = 12V, VUGATE = 6V 350 500 - mA

Upper Gate Sink RUGATE - 5.5 10 W

PROTECTION

Over-Voltage Trip (VSEN/DACOUT) - 115 120 %

OCSET Current Source IOCSET VOCSET = 4.5V 170 200 230 µA

OVP Sourcing Current IOVP VSEN = 5.5V; VOVP = 0V 60 - - mA

Soft Start Current ISS -10- µA

POWER GOOD

Upper Threshold (VSEN/DACOUT) VSEN Rising 106 - 111 %

Lower Threshold (VSEN/DACOUT) VSEN Falling 89 - 94 %

Hysteresis (VSEN/DACOUT) Upper and Lower Threshold - 2 - %

PGOOD Voltage Low VPGOOD IPGOOD = -5mA - 0.5 - V

HIP6005B

2-113

Functional Pin Description

VSEN (Pin 1)

This pin is connected to the converters output voltage. The

PGOOD and OVP comparator circuits use this signal to

report output voltage status and for overvoltage protection.

OCSET (Pin 2)

Connect a resistor (ROCSET) from this pin to the drain of the

upper MOSFET. ROCSET, an internal 200µA current source

(IOCS), and the upper MOSFET on-resistance (rDS(ON)) set

the converter over-current (OC) trip point according to the

following equation:

An over-current trip cycles the soft-start function.

SS (Pin 3)

Connect a capacitor from this pin to ground. This capacitor,

along with an internal 10µA current source, sets the

soft-start interval of the converter.

VID0-4 (Pins 4-8)

VID0-4 are the input pins to the 5-bit DAC. The states of

these ﬁve pins program the internal voltage reference

(DACOUT). The level of DACOUT sets the converter output

voltage. It also sets the PGOOD and OVP thresholds. Table

1 speciﬁes DACOUT for the 32 combinations of DAC inputs.

COMP (Pin 9) and FB (Pin 10)

COMP and FB are the available external pins of the error

ampliﬁer. The FB pin is the inverting input of the error

ampliﬁer and the COMP pin is the error ampliﬁer output.

These pins are used to compensate the voltage-control

feedback loop of the converter.

GND (Pin 11)

Signal ground for the IC. All voltage levels are measured with

respect to this pin.

PGOOD (Pin 12)

PGOOD is an open collector output used to indicate the

status of the converter output voltage. This pin is pulled low

when the converter output is not within ±10% of the

DACOUT reference voltage. Exception to this behavior is

the ‘11111’ VID pin combination which disables the

converter; in this case PGOOD asserts a high level.

PHASE (Pin 13)

Connect the PHASE pin to the upper MOSFET source. This

pin is used to monitor the voltage drop across the MOSFET

for over-current protection. This pin also provides the return

path for the upper gate drive.

UGATE (Pin 14)

Connect UGATE to the upper MOSFET gate. This pin

provides the gate drive for the upper MOSFET.

Typical Performance Curves

FIGURE 1. RT RESISTANCE vs FREQUENCY FIGURE 2. BIAS SUPPLY CURRENT vs FREQUENCY

10 100 1000

SWITCHING FREQUENCY (kHz)

RESISTANCE (kΩ)

100

1000 RT PULLUP

RT PULLDOWN TO VSS

TO +12V

100 200 300 400 500 600 700 800 900 1000

ICC (mA)

SWITCHING FREQUENCY (kHz)

CUGATE = 3300pF

CUGATE = 1000pF

CUGATE = 10pF

VSEN

OCSET

VID0

VID1

VID2

VID4

VID3

COMP

VCC

OVP

BOOT

UGATE

PHASE

PGOOD

GND

IPEAK IOCSET xR

OCSET

rDS ON()

-----------------------------------------------------=

HIP6005B

2-114

BOOT (Pin 15)

This pin provides bias voltage to the upper MOSFET driver.

A bootstrap circuit may be used to create a BOOT voltage

suitable to drive a standard N-Channel MOSFET.

NC (Pin 16)

No connection.

NC (Pin 17)

No connection.

VCC (Pin 18)

Provide a 12V bias supply for the chip to this pin.

OVP (Pin 19)

The OVP pin can be used to drive an external SCR in the

event of an overvoltage condition. Output rising 15% more

than the DAC-set voltage triggers a high output on this pin

and disables PWM gate drive circuitry.

RT (Pin 20)

This pin provides oscillator switching frequency adjustment.

By placing a resistor (RT) from this pin to GND, the nominal

200kHz switching frequency is increased according to the

following equation:

Conversely, connecting a pull-up resistor (RT) from this pin

to VCC reduces the switching frequency according to the

following equation:

Functional Description

Initialization

The HIP6005B automatically initializes upon receipt of po wer.

Special sequencing of the input supplies is not necessary. The

Pow er-On Reset (POR) function continually monitors the input

supply voltages. The POR monitors the bias voltage at the VCC

pin and the input voltage (VIN) on the OCSET pin. The level on

OCSET is equal to VIN less a fix ed v oltage drop (see o v er-

current protection). The POR function initiates soft start

operation after both input supply v oltages e xceed their POR

thresholds. For operation with a single +12V power source, VIN

and VCC are equivalent and the +12V po w er source must

exceed the rising VCC threshold before POR initiates operation.

Soft Start

The POR function initiates the soft start sequence. An internal

10µA current source charges an e xternal capacitor (CSS) on

the SS pin to 4V. Soft start clamps the error amplifier output

(COMP pin) and ref erence input (+ terminal of error amp) to

the SS pin voltage. Figure 3 shows the soft start interval with

CSS = 0.1µF. Initially the clamp on the error amplifier (COMP

pin) controls the converter’s output v oltage . At t1 in Figure 3,

the SS voltage reaches the valley of the oscillator’s triangle

wa ve. The oscillator’s triangular wa veform is compared to the

ramping error amplifier v oltage. This generates PHASE

pulses of increasing width that charge the output capacitor(s).

This interv al of increasing pulse width contin ues to t2. With

sufficient output voltage, the clamp on the reference input

controls the output voltage. This is the interval between t2and

t3 in Figure 3. At t3 the SS voltage exceeds the DA COUT

voltage and the output voltage is in regulation. This method

provides a rapid and controlled output voltage rise. The

PGOOD signal toggles ‘high’ when the output voltage (VSEN

pin) is within ±5% of DACOUT. The 2% hysteresis b uilt into

the power good comparators prevents PGOOD oscillation due

to nominal output voltage ripple.

Over-Current Protection

The over-current function protects the converter from a

shorted output by using the upper MOSFET’s on-resistance,

rDS(ON) to monitor the current. This method enhances the

converter’s efﬁciency and reduces cost by eliminating a

current sensing resistor.

Fs 200kHz 5x10

TkΩ()

---------------------+≈(RT to GND)

Fs 200kHz 4x10

TkΩ()

---------------------–≈(RT to 12V)

TIME (5ms/DIV.)

SOFT-START

(1V/DIV.)

OUTPUT

(1V/DIV.)

VOLTAGE

t2t3

PGOOD

(2V/DIV.)

FIGURE 3. SOFT START INTERVAL

OUTPUT INDUCTOR SOFT-START

TIME (20ms/DIV.)

10A

15A

FIGURE 4. OVER-CURRENT OPERATION

HIP6005B

2-115

The over-current function cycles the soft-start function in a

hiccup mode to provide fault protection. A resistor (ROCSET)

programs the over-current trip level. An internal 200µA current

sink de velops a voltage across ROCSET that is ref erenced to

VIN. When the v oltage across the upper MOSFET (also

ref erenced to VIN) exceeds the v oltage across ROCSET, the

over-current function initiates a soft-start sequence. The soft-

start function discharges CSS with a 10µA current sink and

inhibits PWM operation. The soft-start function recharges

CSS, and PWM operation resumes with the error amplifier

clamped to the SS voltage. Should an ov erload occur while

recharging CSS, the soft start function inhibits PWM operation

while fully charging CSS to 4V to complete its cycle. Figure 4

shows this operation with an overload condition. Note that the

inductor current increases to over 15A during the CSS

charging interv al and causes an over-current trip. The

converter dissipates very little power with this method. The

measured input power for the conditions of Figure 4 is 2.5W.

The over-current function will trip at a peak inductor current

(IPEAK) determined by:

where IOCSET is the internal OCSET current source (200µA

typical). The OC trip point varies mainly due to the

MOSFET’s rDS(ON) variations. To avoid over-current tripping

in the normal operating load range, ﬁnd the ROCSET resistor

from the equation above with:

1. ThemaximumrDS(ON)atthehighestjunctiontemperature.

2. The minimum IOCSET from the speciﬁcation table.

3. Determine IPEAK for ,

where ∆I is the output inductor ripple current.

For an equation for the ripple current see the section under

component guidelines titled “Output Inductor Selection.”

A small ceramic capacitor should be placed in parallel with

ROCSET to smooth the voltage across ROCSET in the

presence of switching noise on the input voltage.

Output Voltage Program

The output voltage of a HIP6005B converter is programmed

to discrete levels between 1.8VDC and 3.5VDC. The voltage

identiﬁcation (VID) pins program an internal voltage

reference (DACOUT) with a TTL-compatible, 5-bit

digital-to-analog converter (DAC). The level of DACOUT also

sets the PGOOD and OVP thresholds. Table 1 speciﬁes the

DACOUT voltage for the 32 different combinations of

connections on the VID pins. The output voltage should not

be adjusted while the converter is delivering power. Remove

input power before changing the output voltage. Adjusting

the output voltage during operation could toggle the PGOOD

signal and exercise the overvoltage protection.

‘11111’ VID pin combination resulting in a 0V output setting

activates the Power-On Reset function and disables the gate

drive circuitry. For this specific VID combination, though,

PGOOD asserts a high level. This unusual behavior has been

implemented in order to allow for operation in

dual-microprocessor systems where AND-ing of the PGOOD

signals from two individual pow er converters is implemented.

Application Guidelines

Layout Considerations

As in any high frequency s witching con verter, la y out is v ery

important. Switching current from one power device to another

can generate v oltage transients across the impedances of the

interconnecting bond wires and circuit traces. These

interconnecting impedances should be minimized b y using

wide, short printed circuit traces. The critical components

should be located as close together as possible using g round

plane construction or single point grounding.

IPEAK IOCSET xR

OCSET

rDS ON()

-----------------------------------------------------=

IPEAK IOUT MAX()

∆I()2⁄+>

TABLE 1. OUTPUT VOLTAGE PROGRAM

PIN NAME NOMINAL OUTPUT

V OLTA GE DACOUT PIN NAME NOMINAL OUTPUT

V OLTA GE DACOUTVID4 VID3 VID2 VID1 VID0 VID4 VID3 VID2 VID1 VID0

0 1 1 1 1 1.30 1 1 1 1 1 0

0 1 1 1 0 1.35 1 1 1 1 0 2.1

0 1 1 0 1 1.40 1 1 1 0 1 2.2

0 1 1 0 0 1.45 1 1 1 0 0 2.3

0 1 0 1 1 1.50 1 1 0 1 1 2.4

0 1 0 1 0 1.55 1 1 0 1 0 2.5

0 1 0 0 1 1.60 1 1 0 0 1 2.6

0 1 0 0 0 1.65 1 1 0 0 0 2.7

0 0 1 1 1 1.70 1 0 1 1 1 2.8

0 0 1 1 0 1.75 1 0 1 1 0 2.9

0 0 1 0 1 1.80 1 0 1 0 1 3.0

0 0 1 0 0 1.85 1 0 1 0 0 3.1

0 0 0 1 1 1.90 1 0 0 1 1 3.2

0 0 0 1 0 1.95 1 0 0 1 0 3.3

0 0 0 0 1 2.00 1 0 0 0 1 3.4

0 0 0 0 0 2.05 1 0 0 0 0 3.5

NOTE: 0 = connected to GND or VSS, 1 = connected to VDD through pull-up resistors.

HIP6005B

2-116

Figure 5 shows the critical power components of the converter.

To minimiz e the v oltage o v ershoot the interconnecting wires

indicated by hea vy lines should be part of ground or power

plane in a printed circuit board. The components shown in

Figure 6 should be located as close together as possible .

Please note that the capacitors CIN and CO each represent

numerous ph ysical capacitors . Locate the HIP6005B within 3

inches of the MOSFET, Q1. The circuit tr aces f or the

MOSFET’s gate and source connections from the HIP6005B

must be sized to handle up to 1A peak current.

Figure 6 shows the circuit traces that require additional

layout consideration. Use single point and ground plane

construction for the circuits shown. Minimize any leakage

current paths on the SS PIN and locate the capacitor, Css

close to the SS pin because the internal current source is

only 10µA. Provide local VCC decoupling between VCC and

GND pins. Locate the capacitor, CBOOT as close as practical

to the BOOT and PHASE pins.

Feedback Compensation

Figure 7 highlights the voltage-mode control loop for a buck

converter. The output voltage (VOUT) is regulated to the

Reference voltage level. The error ampliﬁer (Error Amp)

output (VE/A) is compared with the oscillator (OSC)

triangular wave to provide a pulse-width modulated (PWM)

wave with an amplitude of VIN at the PHASE node. The

PWM wave is smoothed by the output ﬁlter (LO and CO).

The modulator transfer function is the small-signal transfer

function of VOUT/VE/A. This function is dominated by a DC

Gain and the output ﬁlter (LO and CO), with a double pole

break frequency at FLC and a zero at FESR. The DC Gain of

the modulator is simply the input voltage (VIN) divided by the

peak-to-peak oscillator voltage ∆VOSC.

Modulator Break Frequency Equations

The compensation network consists of the error amplifier

(internal to the HIP6005B) and the impedance networks ZIN

and ZFB. The goal of the compensation network is to provide a

closed loop transf er function with the highest 0dB crossing

frequency (f0dB) and adequate phase margin. Phase margin is

the diff erence between the closed loop phase at f0dB and 180

degrees. The equations below relate the compensation

network’ s poles , z eros and gain to the components (R1, R2,

R3, C1, C2, and C3) in Figure 8. Use these guidelines for

locating the poles and zeros of the compensation network:

1. Pick Gain (R2/R1) for desired converter bandwidth.

2. Place 1ST Zero Below Filter’s Doub le Pole (~75% FLC).

3. Place 2ND Zero at Filter’s Double Pole.

4. Place 1ST Pole at the ESR Zero.

5. Place 2ND Pole at Half the Switching Frequency.

6. Check Gain against Error Ampliﬁer’s Open-Loop Gain.

7. Estimate Phase Margin - Repeat if Necessary.

UGATE

PHASE

VIN

VOUT

RETURN

HIP6005B

CIN

LOAD

FIGURE 5. PRINTED CIRCUIT BOARD POWER AND GROUND

PLANES OR ISLANDS

HIP6005B

GND

VCC

BOOT D1LO

VOUT

LOAD

PHASE

FIGURE 6. PRINTED CIRCUIT BOARD SMALL SIGNAL

LAYOUT GUIDELINES

+VIN

CBOOT

CVCC

CSS

+12V

VOUT

OSC

REFERENCE

ESR

VIN

∆VOSC

ERROR

AMP

PWM DRIVER

(PARASITIC)

FIGURE 7. VOLTAGE-MODE BUCK CONVERTER

COMPENSATION DESIGN

ZIN

ZFB

DACOUT

R2C3

COMP

VOUT

ZFB

HIP6005B

ZIN

COMPARATOR

DETAILED COMPENSATION COMPONENTS

VE/A

-PHASE

FESR 1

2πx (ESR x CO)

------------------------------------------------=

FLC 1

2πxL

------------------------------------------=

HIP6005B

2-117

Compensation Break Frequency Equations

Figure 8 shows an asymptotic plot of the DC-DC con verter’s

gain vs frequency. The actual Modulator Gain has a high gain

peak due to the high Q f actor of the output filter and is not

shown in Figure 8. Using the abo ve guidelines should give a

Compensation Gain similar to the curv e plotted. The open

loop error amplifier gain bounds the compensation gain.

Check the compensation gain at FP2 with the capabilities of

the error amplifier. The Closed Loop Gain is constructed on

the log-log graph of Figure 8 by adding the Modulator Gain (in

dB) to the Compensation Gain (in dB). This is equivalent to

multiplying the modulator transfer function to the

compensation transfer function and plotting the gain.

The compensation gain uses external impedance networks

ZFB and ZIN to provide a stable, high bandwidth (BW) overall

loop. A stable control loop has a gain crossing with

-20dB/decade slope and a phase margin greater than 45

degrees. Include worst case component variations when

determining phase margin.

Component Selection Guidelines

Output Capacitor Selection

An output capacitor is required to ﬁlter the output and supply

the load transient current. The ﬁltering requirements are a

function of the switching frequency and the ripple current.

The load transient requirements are a function of the slew

rate (di/dt) and the magnitude of the transient load current.

These requirements are generally met with a mix of

capacitors and careful layout.

Modern microprocessors produce transient load rates abov e

1A/ns. High frequency capacitors initially supply the transient

and slow the current load rate seen by the bulk capacitors .

The bulk filter capacitor values are generally determined by

the ESR (Eff ective Series Resistance) and voltage rating

requirements rather than actual capacitance requirements.

High frequency decoupling capacitors should be placed as

close to the power pins of the load as physically possible. Be

careful not to add inductance in the circuit board wiring that

could cancel the usefulness of these low inductance

components. Consult with the manufacturer of the load on

speciﬁc decoupling requirements. For example, Intel

recommends that the high frequency decoupling for the

Pentium Pro be composed of at least forty (40) 1µF ceramic

capacitors in the 1206 surface-mount package.

Use only specialized lo w-ESR capacitors intended for

s witching-regulator applications for the bulk capacitors. The

bulk capacitor’s ESR will determine the output ripple voltage

and the initial voltage drop after a high slew-rate transient. An

aluminum electrolytic capacitor's ESR v alue is related to the

case size with lo w er ESR available in larger case sizes.

Howev er, the Equivalent Series Inductance (ESL) of these

capacitors increases with case size and can reduce the

usefulness of the capacitor to high slew-rate transient loading.

Unf ortunately, ESL is not a specified parameter. W ork with

your capacitor supplier and measure the capacitor’s

impedance with frequency to select a suitable component. In

most cases, multiple electrolytic capacitors of small case size

perf orm better than a single large case capacitor.

Output Inductor Selection

The output inductor is selected to meet the output voltage

ripple requirements and minimize the converter’s response

time to the load transient. The inductor value determines the

converter’s ripple current and the ripple voltage is a function

of the ripple current. The ripple voltage and current are

approximated by the following equations:

Increasing the value of inductance reduces the ripple current

and voltage. However, the large inductance values reduce

the converter’s response time to a load transient.

FZ2 1

2πx(R

+)xC

-------------------------------------------------------=

FP1 1

2πxR

2xC

1xC

1+C

----------------------







---------------------------------------------------------=

FP2 1

2πxR

3xC

------------------------------------=

FZ1 1

2πxR

2xC

------------------------------------=

100

-20

-40

-60

FP1

FZ2

10M1M100K10K1K10010

OPEN LOOP

ERROR AMP GAIN

FZ1 FP2

FLC FESR

COMPENSATION

GAIN (dB)

FREQUENCY (Hz)

GAIN

20LOG

(VIN/∆VOSC)

MODULATOR

GAIN

FIGURE 8. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN

20LOG

(R2/R1)

CLOSED LOOP

GAIN

∆IVIN VOUT

–

FSxL

-------------------------------- xVOUT

VIN

----------------

=∆VOUT ∆IxESR=

HIP6005B

2-118

One of the parameters limiting the conver ter’s response to

a load transient is the time required to change the inductor

current. Given a sufficiently fast control loop design, the

HIP6005B will provide either 0% or 100% duty cycle in

response to a load transient. The response time is the time

required to slew the inductor current from an initial current

value to the transient current level. During this interval the

difference between the inductor current and the transient

current level must be supplied by the output capacitor.

Minimizing the response time can minimize the output

capacitance required.

The response time to a transient is different for the

application of load and the removal of load. The following

equations give the approximate response time interval for

application and removal of a transient load:

where: ITRAN is the transient load current step, tRISE is the

response time to the application of load, and tFALL is the

response time to the removal of load. With a +5V input

source, the worst case response time can be either at the

application or removal of load and dependent upon the

DACOUT setting. Be sure to check both of these equations

at the minimum and maximum output levels for the worst

case response time. With a +12V input, and output voltage

level equal to DACOUT, tFALL is the longest response time.

Input Capacitor Selection

Use a mix of input bypass capacitors to control the v oltage

overshoot across the MOSFETs. Use small ceramic capacitors

for high frequency decoupling and bulk capacitors to supply the

current needed each time Q1turns on. Place the small ceramic

capacitors ph ysically close to the MOSFETs and between the

drain of Q1 and the anode of Schottky diode D2.

The important parameters for the bulk input capacitor are

the voltage rating and the RMS current rating. For reliable

operation, select the bulk capacitor with voltage and

current ratings above the maximum input voltage and

largest RMS current required by the circuit. The capacitor

voltage rating should be at least 1.25 times greater than the

maximum input voltage and a voltage rating of 1.5 times is

a conser vative guideline. The RMS current rating

requirement for the input capacitor of a buck regulator is

approximately 1/2 the DC load current.

F or a through hole design, se v er al electrolytic capacitors

(Panasonic HFQ series or Nichicon PL series or Sanyo MV-GX

or equivalent) may be needed. For surface mount designs, solid

tantalum capacitors can be used, but caution m ust be

e x ercised with regard to the capacitor surge current r ating.

These capacitors must be capab le of handling the surge-

current at power-up. The TPS series av ailab le from AVX, and

the 593D series from Sprague are both surge current tested.

MOSFET Selection/Considerations

The HIP6005B requires an N-Channel power MOSFET. It

should be selected based upon rDS(ON), gate supply

requirements, and thermal management requirements.

In high-current applications, the MOSFET po wer dissipation,

package selection and heatsink are the dominant design

f actors. The po w er dissipation includes two loss components;

conduction loss and s witching loss. The conduction losses are

the largest component of power dissipation for the MOSFET.

Switching losses also contribute to the ov er all MOSFET po wer

loss (see the equations below). These equations assume linear

voltage-current tr ansitions and are appro ximations . The gate-

charge losses are dissipated by the HIP6005B and do not heat

the MOSFET. Ho w e v er, large gate-charge increases the

s witching interval, tSW, which increases the upper MOSFET

s witching losses. Ensure that the MOSFET is within its

maximum junction temperature at high ambient temperature by

calculating the temperature rise according to package thermal-

resistance specifications. A separate heatsink may be

necessary depending upon MOSFET pow er, pac kage type ,

ambient temperature and air flow.

Where: D is the duty cycle = VOUT/VIN,

tSW is the switching interval, and

FS is the switching frequency

Standard-gate MOSFETs are normally recommended for

use with the HIP6005B. However, logic-level gate MOSFETs

can be used under special circumstances. The input voltage,

upper gate drive level, and the MOSFETs absolute

gate-to-source voltage rating determine whether logic-level

MOSFETs are appropriate.

Figure 9 shows the upper gate drive (BOOT pin) supplied by

a bootstrap circuit from VCC. The boot capacitor, CBOOT,

develops a ﬂoating supply voltage referenced to the PHASE

pin. This supply is refreshed each cycle to a voltage of VCC

less the boot diode drop (VD) when the Schottky diode, D2,

conducts. Logic-level MOSFETs can only be used if the

MOSFETs absolute gate-to-source voltage rating exceeds

the maximum voltage applied to VCC.

Figure 10 shows the upper gate drive supplied b y a direct

connection to VCC. This option should only be used in

conv erter systems where the main input voltage is +5VDC or

less. The peak upper gate-to-source v oltage is approximately

VCC less the input supply. For +5V main power and +12VDC for

the bias, the gate-to-source v oltage of Q1 is 7V. A logic-level

MOSFET is a good choice f or Q1 under these conditions.

tRISE LxI

TRAN

VIN VOUT

–

--------------------------------= tFALL LxI

TRAN

VOUT

----------------------------=

PCOND =I

2xr

DS(ON) xD

SW = 1/2 IOxV

IN xt

SW xF

HIP6005B

2-119

Schottky Selection

Rectifier D2 conducts when the upper MOSFET Q1 is off . The

diode should be a Schottky type f or low po w er losses. The

power dissipation in the Schottky rectifier is approximated b y:

In addition to power dissipation, package selection and

heat-sink requirements are the main design tradeoffs in

choosing the schottky rectifier. Since the three f actors are

interrelated, the selection process is an iterativ e procedure.

The maximum junction temperature of the rectifier m ust

remain below the manufacturer’s specified value, typically

125oC. By using the package thermal resistance specification

and the schottky power dissipation equation (shown abov e),

the junction temperature of the rectifier can be estimated. Be

sure to use the available airflo w and ambient temper ature to

determine the junction temperature rise.

+12V

HIP6005B

GND

UGATE

PHASE

BOOT

VCC

+5V OR +12

NOTE: VG-S ≈ VCC - VD.

FIGURE 9. UPPER GATE DRIVE - BOOTSTRAP OPTION

(NOTE)

CBOOT

DBOOT

+ VD -

+12V

HIP6005B

GND

UGATE

PHASE

BOOT

VCC

+5V OR LESS

FIGURE 10. UPPER GATE DRIVE - DIRECT VCC DRIVE OPTION

NOTE:

VG-S ≈VCC -5V

PCOND = I0 x Vf x (1 - D)

Where: D is the duty cycle = VOUT / VIN, and

Vfis the Schottky forward voltage drop.

HIP6005B

2-120

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HIP6005B DC-DC Converter Application Circuit

Figure 11 shows an application circuit of a DC-DC Converter

for an Intel Pentium Pro microprocessor. Detailed

information on the circuit, including a complete Bill-of-

Materials and circuit board description, can be found in

application note AN9706. Although the Application Note

details the HIP6005, the same evaluation platform can be

used to evaluate the HIP6005B. Intersil AnswerFAX

(407-724-7800) Doc. #99706.

+12V

+VO

HIP6005B

VSEN

COMP

VID0

VID1

VID2

VID3

OVP

SS PGOOD

D/A

GND

MONITOR

OSC

VCC

L1 - 1µH

CIN

COUT

0.1µF

2x 1µF

0.1µF

2.2nF

8.2nF 20K

7µH

5x 1000µF

9x 1000µF

0.082µF

UGATE

OCSET

PHASE

BOOT

2N6394

1.1K

1000pF

VIN = +5V

+12V

AND

PROTECTION

Component Selection Notes

COUT - Each 1000µF 6.3WVDC, Sanyo MV-GX or Equivalent.

CIN - Each 330µF 25WVDC, Sanyo MV-GX or Equivalent.

L2- Core: Micrometals T60-52; Each Winding: 14 Turns of 17A WG.

L1 - Core: Micrometals T50-52; Winding: 6 Turns of 18AWG.

D1 - 1N4148 or Equivalent.

D2 - 25A, 35V Schottky, Motorola MBR2535CTL or Equivalent.

Q1 - Intersil MOSFET; RFP70N03.

FIGURE 11. PENTIUM PRO DC-DC CONVERTER

VID4 8

HIP6005B