FUJITSU SEMICONDUCTOR
DATA SHEET
Copyright©2009-2011 FUJITSU SEMICONDUCTOR LIMITED All rights reserved
2011.3
ASSP for Power Management Applications
(General-Purpose DC/DC Converter)
2ch DC/DC converter IC
with synchronous rectification
MB39A138
■DESCRIPTION
MB39A138 is a 2ch step-down DC/DC converter equipped with a bottom detection comparator and N-ch/
N-ch synchronous rectification. It supports low on-duty operation to allow stable output of low voltages when
there is a large difference between input and output voltages. MB39A138 realizes ultra-rapid response and
high efficiency with built-in enhanced protection features.
■FEATURES
• High efficiency
• High accurate reference voltage : ±1.0% (indoor temperature )
• Input voltage range : 6 V to 24 V
• Output voltage setting range : CH1 0.7 V to 5.2 V
: CH2 2.0 V to 5.2 V
• Built-in diode for boot strap
• Built-in over voltage protection function
• Built-in under voltage protection function
• Built-in over current detection function
• Built-in over temperature protection function
• Built-in soft-start circuit without load dependence
• Built-in discharge control circuit
• Built-in synchronous rectification type output steps for N-ch MOS FET
• Standby current : 0 μA (Typ)
• Small package : TSSOP-24
■APPLICATIONS
• Digital TV
• Photocopiers
•STB
• BD, DVD players/recorders
•Projectors
Various other advanced devices
DS04–27270–2E
MB39A138
2DS04–27270–2E
■PIN ASSIGNMENT
(TOP VIEW)
(FPT-24P-M10)
24
23
22
21
20
19
18
17
16
15
14
13
CB1
DRVH1
LX1
DRVL1
VCC
VB
PGND
DRVL2
LX2
DRVH2
CB2
TEST
1
2
3
4
5
6
7
8
9
10
11
12
CTL1
CS1
FB1
VO1
ILIM1
GND
CVBLPF
CTL2
ILIM2
VO2
FB2
CS2
MB39A138
DS04–27270–2E 3
■PIN DESCRIPTIONS
Pin No. Pin Name I/O Description
1 CTL1 I CH1 control pin.
2 CS1 I CH1 start time setting capacitor connection pin.
3 FB1 I CH1 feedback pin for DC/DC output voltage.
4 VO1 I CH1 input pin for DC/DC output voltage.
5 ILIM1 I CH1 over current detection level setting voltage input pin.
6GND⎯Ground pin.
7 CVBLPF I Control circuit bias input pin.
8 CTL2 I CH2 control pin.
9 ILIM2 I CH2 over current detection level setting voltage input pin.
10 VO2 I CH2 input pin for DC/DC output voltage.
11 FB2 I CH2 feedback pin for DC/DC output voltage.
12 CS2 I CH2 soft-start time setting capacitor connection pin.
13 TEST I Pin for IC test. Connect to GND in the DC/DC operation.
14 CB2 ⎯CH2 connection pin for boot strap capacitor.
15 DRVH2 O CH2 output pin for external high-side FET drive.
16 LX2 ⎯CH2 inductor and external high-side FET source connection pin.
17 DRVL2 O CH2 output pin for external low-side FET gate drive.
18 PGND ⎯Ground pin for output circuit.
19 VB O Output circuit bias output pin.
20 VCC I Power supply pin for reference voltage and control circuit.
21 DRVL1 O CH1 output pin for external low-side FET gate drive.
22 LX1 ⎯CH1 inductor and external high-side FET source connection pin.
23 DRVH1 O CH1 output pin for external high-side FET gate drive.
24 CB1 ⎯CH1 connection pin for boot strap capacitor.
MB39A138
4DS04–27270–2E
■BLOCK DIAGRAM
3
<Error Comp.>
4
VO1
FB1
<CH1>
/CTL1
UVP,OTP
5 μA
VO
Control
INTREF1
2
CS1
/CTL1,/UVLO
UVP,OTP
<OVP Comp.>
ovp_q1
5
ILIM1
INTREF1
x 1.15 V
<UVP Comp.>
INTREF1
x 0.7 V
uvp_q1
<CH2>
11
10
VO2
FB2
9
ILIM2
12
CS2
6
GND
CB2
DRVH2
DRVL2
LX2
17
16
15
14
bias
7CVBLPF
UVLO
H:UVLO
release
OTP
50 μs
delay
1.7 ms
delay
R
S
Q
R
S
Q
ovp_q2uvp_q2
Drive
Logic
R
SQ
LX1
PGND
<ILIM Comp.>
10 μA
t
ON
Generator
VO1VCC
VCC
24
(5.2 V)
19
5.2 V Reg. VB
CB1
20
REF
CTL
8
CTL2
1
CTL1
Drv-1
Drv-2
18
21
22
23
PGND
DRVH1
DRVL1
LX1
bias
−
+
+
−
+
−
+
−
+
−
+
The configuration of a control circuit is the same as that of CH1.
MB39A138
DS04–27270–2E 5
■ABSOLUTE MAXIMUM RATINGS
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
Parameter Symbol Condition Rating Unit
Min Max
Power supply voltage VVCC ⎯⎯26 V
CB pin input voltage VCB CB1, CB2 pins ⎯32 V
LX pin input voltage VLX LX1, LX2 pins ⎯26 V
Voltage between
CB and LX VCBLX ⎯⎯7V
Control input voltage VICTL1, CTL2 pins ⎯26 V
Input voltage
VCVBLPF CVBLPF pin ⎯VB + 0.3 V
VFB FB1, FB2 pins ⎯VB + 0.3 V
VVO VO1, VO2 pins ⎯VB + 0.3 V
VCS CS1, CS2 pins ⎯VB + 0.3 V
VILIM ILIM1, ILIM2 pins ⎯VB + 0.3 V
VTEST TEST pin ⎯VB + 0.3 V
Output current IOUT DRVH1, DRVH2 pins,
DRVL1, DRVL2 pins ⎯60 mA
Power dissipation PDTa ≤ + 25 °C⎯1333 mW
Storage temperature TSTG ⎯ − 55 + 125 °C
MB39A138
6DS04–27270–2E
■RECOMMENDED OPERATING CONDITIONS
WARNING: The recommended operating conditions are required in order to ensure the normal operation of
the semiconductor device. All of the device's electrical characteristics are warranted when the
device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges.
Operation outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented
on the data sheet. Users considering application outside the listed conditions are advised to contact
their representatives beforehand.
Parameter Symbol Condition Value Unit
Min Typ Max
Power supply
voltage VVCC ⎯6⎯24 V
CB pin input voltage VCB ⎯⎯⎯30 V
Bias output current IVB ⎯ − 1 ⎯⎯mA
CTL pin input
voltage VICTL1, CTL2 pins 0 ⎯24 V
Input voltage
VCVBLPF CVBLPF pin 0 ⎯VB V
VFB FB1, FB2 pins 0 ⎯VB V
VVO VO1, VO2 pins 0 ⎯VB V
VILIM ILIM1, ILIM2 pins 30 ⎯200 mV
Peak output current IOUT
DRVH1, DRVH2 pins,
DRVL1, DRVL2 pins
Duty ≤ 5% (t = 1/fOSC × Duty)
− 1200 ⎯ + 1200 mA
Soft start capacitor CCS ⎯⎯0.018 ⎯μF
CB pin capacitor CCB ⎯⎯0.1 1.0 μF
Bias voltage output
capacitor CVB ⎯⎯2.2 10.0 μF
Bias voltage input
capacitor CCVBLPF ⎯⎯1.0 4.7 μF
Operating ambient
temperature Ta ⎯ − 30 + 25 + 85 °C
MB39A138
DS04–27270–2E 7
■ELECTRICAL CHARACTERISTICS
(Ta = + 25 °C, VCC pin = 12 V, CTL1, CTL2 pins = 5 V = CVBLPF pin : VB pin connected)
(Continued)
Parameter Sym-
bol Pin No. Condition Value Unit
Min Typ Max
Bias Voltage
Block
[VB Reg.]
Output voltage VVB 19 ⎯5.04 5.20 5.36 V
Input stability LINE 19 VCC pin = 6 V to 24 V ⎯10 100 mV
Load stability LOAD 19 VB pin = 0 A to −1 mA ⎯10 100 mV
Short-circuit
output current IOS 19 VB pin = 0 V − 200 − 140 − 100 mA
Under
voltage
Lockout
Protection
Circuit Block
[UVLO]
Threshold
voltage
VTLH 7 CVBLPF pin 4.0 4.2 4.4 V
VTHL 7 CVBLPF pin 3.4 3.6 3.8 V
Hysteresis
width VH7 CVBLPF pin ⎯0.6* ⎯V
Soft-Start/
Discharge
Block
[Soft-Start,
Discharge]
Charge current ICS 2, 12 CS1, CS2 pins = 0 V − 7.1 − 5.0 − 3.8 μA
Electrical
discharge
resistance
RD4, 10 CTL1, CTL2 pins = 0 V,
VO1, VO2 pins = 0.5 V ⎯35 70 Ω
Discharge end
voltage VVOVTH 4, 10 CTL1, CTL2 pins = 0 V,
VO1, VO2 pins 0.1 0.2 0.3 V
ON/OFF
Time
Generator
Block
[tON
Generator]
ON time
tON11 23 VCC pin = 12 V,
VO1 pin = 1.2 V 256 320 384 ns
tON12 15 VCC pin = 12 V,
VO2 pin = 3.3 V 470 587 704 ns
Minimum ON
time tONMIN 23, 15 VCC pin = 12 V,
VO1, VO2 pins = 0 V ⎯100 ⎯ns
Minimum OFF
time tOFFMIN 23, 15 ⎯⎯380 ⎯ns
Output
Voltage
Block
[VO
Control,
Error
Comp.]
Feedback
voltage (CH1)
VTH1 3Ta = + 25 °C 0.693 0.700 0.707 V
VTHT1 3Ta = 0 °C to + 85 °C 0.690* ⎯0.710* V
Feedback
voltage (CH2)
VTH2 11 Ta = + 25 °C 1.980 2.000 2.020 V
VTHT2 11 Ta = 0 °C to +85 °C 1.970* ⎯2.030* V
Bottom
detection
voltage (CH1)
VTH3 4Ta = + 25 °C 1.202 1.226 1.250 V
VTHT3 4Ta = 0 °C to + 85 °C 1.196 ⎯1.256 V
Bottom
detection
voltage (CH2)
VTH4 10 Ta = + 25 °C 3.381 3.450 3.519 V
VTHT4 10 Ta = 0 °C to + 85 °C 3.364 ⎯3.536 V
FB pin
input current IFB 3, 11 FB1, FB2 pins = 0.8 V − 0.1 0 + 0.1 μA
VO pin
input current
IVO1 4 VO1 pin = 1.226 V ⎯80 115 μA
IVO2 10 VO2 pin = 3.450 V ⎯225 325 μA
Over-volt-
age
Protection
Circuit Block
[OVP
Comp.]
Over-voltage
detecting
voltage
VOVP 3, 11
(4, 10) Error Comp. input INTREF
× 1.11
INTREF
× 1.15
INTREF
× 1.19 V
Over-voltage
detection time tOVP 3, 11
(4, 10) ⎯⎯50 ⎯μs
MB39A138
8DS04–27270–2E
(Ta = + 25 °C, VCC pin = 12 V, CTL1, CTL2 pins = 5 V = CVBLPF pin : VB pin connected)
(Continued)
Parameter Sym-
bol Pin No. Condition Value Unit
Min Typ Max
Under-volt-
age Protec-
tion Circuit
Block
[UVP
Comp.]
Under-volt-
age detect-
ing voltage
VUVP 3, 11
(4, 10) Error Comp. input INTREF
× 0.65
INTREF
× 0.70
INTREF
× 0.75 V
Under-volt-
age detec-
tion time
tUVP 3, 11
(4, 10) ⎯1.2* 1.7* 2.2* ms
Over-tem-
perature
Protection
Circuit
Block
[OTP]
Protection
tempera-
ture
TOTPH ⎯⎯⎯ + 150* ⎯ °C
TOTPL ⎯⎯⎯ + 125* ⎯ °C
Output
Block
[DRV]
High-side
output on-
resistance
ROH 23, 15 DRVH1, DRVH2 pins =
−100 mA ⎯57Ω
ROL 23, 15 DRVH1, DRVH2 pins =
100 mA ⎯1.5 2.5 Ω
Low-side
output on-
resistance
ROH 21, 17 DRVL1, DRVL2 pins =
−100 mA ⎯46Ω
ROL 21, 17 DRVL1, DRVL2 pins =
100 mA ⎯12Ω
Output
source
current
ISOURCE
23, 15
LX1, LX2 pins = 0 V,
CB1, CB2 pins = VB
DRVH1, DRVH2 pins = 2.5 V
Duty ≤ 5%
⎯− 0.4* ⎯A
21, 17
LX1, LX2 pins = 0 V,
CB1, CB2 pins = VB
DRVL1, DRVL2 pins = 2.5 V
Duty ≤ 5%
⎯− 0.5* ⎯A
Output
sink
current
ISINK
23, 15
LX1, LX2 pins = 0 V,
CB1, CB2 pins = VB
DRVH1, DRVH2 pins = 2.5 V
Duty ≤ 5%
⎯0.7* ⎯A
21, 17
LX1, LX2 pins = 0 V,
CB1, CB2 pins = VB
DRVL1, DRVL2 pins = 2.5 V
Duty ≤ 5%
⎯0.9* ⎯A
Dead time tD23, 21
15, 17
LX1, LX2 pins = 0 V,
CB1, CB2 pins = VB pin
DRVL1, DRVL2 pins-low to
DRVH1, DRVH2 pins-on
⎯40 ⎯ns
LX1, LX2 pins = 0 V,
CB1, CB2 pins = VB pin
DRVH1, DRVH2 pins-low to
DRVL1, DRVL2 pins-on
⎯80 ⎯ns
Diode
voltage VF24, 14 IF = 10 mA 0.7 0.8 0.9 V
Leak
current ILEAK 24, 14
CB1, CB2 pins = 30 V,
LX1, LX2 pins = 24 V
Ta = + 25 °C
⎯0.1 1 μA
MB39A138
DS04–27270–2E 9
(Continued)
(Ta = + 25 °C, VCC pin = 12 V, CTL1, CTL2 pins = 5 V = CVBLPF pin : VB pin connected)
* : This parameter is not be specified. This should be used as a reference to support designing the circuits.
Parameter Sym-
bol
Pin
No. Condition Value Unit
Min Typ Max
Over
Current
Detection
Block
[Current
Sense]
ILIM pin
source
current
IILIM 5, 9 ILIM1, ILIM2 pins = 0.1 V,
Ta = + 25 °C− 12.5 − 10.0 − 8.3 μA
ILIM pin
source
current
tempera-
ture slope
TILIM 5, 9 Ta = + 25 °C (reference) ⎯4200* ⎯ppm
/ °C
Over
current
detection
offset
voltage
VOFFILIM 5, 9 ILIMx − (PGND − LXx)
PGND − LXx = 60 mV − 20 0 + 20 mV
Over
current
detection
setting
range
VILIM 5, 9 ILIM pin input range 30 ⎯200 mV
Control
Block
[CTL1,
CTL2]
ON
condition VON 1, 8 CTL1, CTL2 pins 2 ⎯24 V
OFF
condition VOFF 1, 8 CTL1, CTL2 pins 0 ⎯0.8 V
Hysteresis
width VH1, 8 CTL1, CTL2 pins ⎯0.4* ⎯V
Input
current
ICTLH 1, 8 CTL1, CTL2 pins = 5 V ⎯25 40 μA
ICTLL 1, 8 CTL1, CTL2 pins = 0 V ⎯01μA
General
Standby
current ICCS 20 CTL1, CTL2 pins = 0 V ⎯010μA
Power
supply
current
ICC 20 LX1, LX2 pins = 0 V,
FB1, FB2 pins = 1.0 V ⎯1.5 2.0 mA
MB39A138
10 DS04–27270–2E
■TYPICAL CHARACTERISTICS
(Continued)
VB bias voltage vs.
Operating ambient temperature
VB bias voltage vs.
VB bias output current
VB bias voltage VVB (V )
VB bias voltage VVB (V)
Operating ambient temperature Ta ( °C) VB bias output current (mA)
Error Comp.1 Threshold voltage vs.
Operating ambient temperature
Error Comp.2 Threshold voltage vs.
Operating ambient temperature
Error Comp.1 Threshold voltage
VTHT1 (V)
Error Comp.2 Threshold voltage
VTHT2 (V)
Operating ambient temperature Ta ( °C) Operating ambient temperature Ta ( °C)
0
500
1000
1500
2000
−50 -25 0 +25 +50 +75 +100 +125
1333
Power dissipation vs.
Operating ambient temperature
Power dissipation PD (mW)
Operating ambient temperature Ta ( °C)
5.00
5.04
5.08
5.12
5.16
5.20
5.24
5.28
5.32
5.36
5.40
-40 -20 0 +20 +40 +60 +80 +100
VCC = 12 V
IVB = 0 A
5.0
5.1
5.2
5.3
5.4
0 5 10 15 20 25 30
Ta = +25 °C
VCC = 6 V
VCC = 12 V
VCC = 24 V
0.690
0.692
0.694
0.696
0.698
0.700
0.702
0.704
0.706
0.708
0.710
-40 -20 0 +20 +40 +60 +80 +100
1.97
1.98
1.99
2.00
2.01
2.02
2.03
-40 -20 0 +20 +40 +60 +80 +100
MB39A138
DS04–27270–2E 11
(Continued)
DRVH1 on time vs.
Operating ambient temperature
DRVH2 on time vs.
Operating ambient temperature
DRVH1 on time tON11 (ns)
DRVH2 on time tON12 (ns)
Operating ambient temperature Ta ( °C) Operating ambient temperature Ta ( °C)
Minimum off time vs.
Operating ambient temperature
Minimum off time vs.
Input voltage
Minimum off time tOFFMIN (ns)
Minimum off time tOFFMIN (ns)
Operating ambient temperature Ta ( °C) Input voltage VIN (V)
Dead time vs.
Operating ambient temperature Bootstrup diode IF vs. VF
Dead time (ns)
IF current IF (mA)
Operating ambient temperature Ta ( °C) VF voltage VF (V)
260
280
300
320
340
360
380
400
-40 -20 0 +20 +40 +60 +80 +100
VCC = 12 V
VO1 = 1.2 V
460
500
540
580
620
660
700
740
-40 -20 0 +20 +40 +60 +80 +100
VCC = 12 V
VO2 = 3.3 V
200
250
300
350
400
450
500
550
600
-40 -20 0 +20 +40 +60 +80 +100
VCC = 12 V
200
250
300
350
400
450
500
550
600
510152025
Ta = +25 °C
20
40
60
80
100
120
-40 -20 0 +20 +40 +60 +80 +100
LX = 0 V
VCB = VB
tD1
tD2
0
5
10
15
20
25
30
0.2 0.4 0.6 0.81 1.2
Ta = −30 °C
Ta = +25 °C
Ta = +85 °C
MB39A138
12 DS04–27270–2E
■FUNCTION
1. Bottom detection comparator system
The bottom detection comparator system uses fixed ON time (tON) and the switching ripple voltage which
superimposed the output voltage (VOUT).
The tON time is uniquely defined by the power supply voltage (VIN) and the output voltage (VOUT). During the
tON period, a current is supplied from the power supply voltage (VIN). This results in an increased inductor
current (ILX) and also an increased output voltage (VOUT) due to the parasitic resistance (ESR) of the output
capacitor.
And when the tOFF period arrives, the energy accumulated in the inductor is supplied to the load to decrease
the inductor current (ILX) gradually. Consequently, the output voltage (VOUT), which has been increasing due
to the parasitic resistance (ESR) of the output capacitor, also decreases. When the output voltage is below
a certain level, RS-FF is set and the tON period arrives again. Switching is repeated as described above.
Error Comp. is used to compare the reference voltage (INTREF) with the output period voltage VFB to control
the off-duty condition in order to stabilize the output voltage.
Bias
tON
generator
Drive
Logic
INTREF
VIN
ILX
S
VOUT
Bias
Reg.
Lo-side
Drive
FB −
+
RS-FF
<Error Comp.> RQ
Hi-side
Drive
RS out
Err out
VINVOUT
ESR
DRVH
DRVL
ton
toff
INTREF
FB
ILX
RS out
DRVH
MB39A138
DS04–27270–2E 13
(1) Bias Voltage Block (VB Reg.)
It outputs 5.2 V (Typ) for setting of the output circuit's power supply and the bootstrap voltage. The bias
power supply is supplied from the CVBLPF pin (pin 7) to the control circuit, which is smoothed with the RC
filter of the resistor and the capacitor connected outside of the IC.
(2) Under Voltage Lockout Protection Circuit Block (UVLO)
A bias voltage (VCVBLPF) of the control IC, a transitional state at startup, or a sudden drop leads to malfunction
of the control IC, causing system destruction/deterioration. To prevent such malfunction, the under voltage
lockout protection circuit detects a voltage drop at the CVBLPF pin (pin 7) and fixes DRVH1 pin (pin 23),
DRVH2 pin (pin 15) and DRVL1 pin (pin 21), DRVL2 pin (pin 17) to the "L" level. When voltages at the
CVBLPF pin exceed the threshold voltage of the under voltage lockout protection circuit, the system is
restored.
(3) Soft-start/Discharge Block (Soft-Start, Discharge)
The soft-start block is the circuit to prevent a rush current when turning power on.
When the CTL1 pin (pin 1) and CTL2 pin (pin 8) are set to the "H" level, the capacitor connected to the CS1
pin (pin 2) and, CS2 pin (pin 12) starts charging and its lamp voltage is input to the error comparator (Error
Comp.) of each channel. This allows for the setting of the soft-start time that does not depend on the output
load of the DC/DC converter.
The discharge block is the circuit to discharge electrical charges stored in an output capacitor at output stop.
When setting the CTL1 pin (pin 1) and the CTL2 pin (pin 8) "L" level, FET for discharge (RON = 35 Ω (Typ))
which is connected between the VO1 pin (pin 4), VO2 pin (pin 10), and GNDs will turn on and discharge the
output capacitors. When VO1 pin voltage and VO2 pin voltage go down below 0.2 V (Typ) after discharging
starts, FET for discharge is turned off and the discharge operation stops. Also, the discharge block works
when detecting low voltage at the under-voltage protection circuit block (UVP Comp.) and detecting IC
junction temperature increase at the over-temperature protection circuit block (OTP).
(4) ON/OFF Time Generator Block (tON Generator)
The ON/OFF time generator block (tON generator) contains a capacitor for timing setting and a resistor for
timing setting and generates ON time which depends on input voltage and output voltage. ON time for each
CH is obtained by the following formula.
The oscillation frequency of CH2 is set to 1.5 times that of CH1 to prevent the beat by the frequency difference
among channels.
tON11 (ns) = VVO1 × 3200 (fOSC1 ≈ 310 kHz)
VVCC
tON12 (ns) = VVO2 × 2133 (fOSC2 ≈ 465 kHz)
VVCC
MB39A138
14 DS04–27270–2E
(5) Output Voltage Setting Block (VO Control, Error Comp.)
The output voltage setting block (VO Control, Error Comp.) detects the bottom value of ripple voltage that
superimposed output voltage for DC/DC converter at the error comparator. The optional output voltage can
be set by connecting the external output voltage setting resistor to the FB1 pin (pin 3) and the FB2 pin (pin 11).
Also, the output setting resistor of the built-in IC can be used by connecting the FB1 pin and the FB2 pin to
the CVBLPF pin (pin 7).
Output Voltage Setting Table
(6) Over-voltage Protection Circuit Block (OVP Comp.)
It compares 1.15 times (Typ) of the internal reference voltage INTREF (CH1/CH2: 0.7V/2.0V) with the
feedback voltage that is input to the FB1 pin (pin 3) and the FB2 pin (pin 11). The RS latch is set and the
DRVH1 pin (pin 23) and the DRVH2 pin (pin 15) set to "L" level and the DRVL1 pin (pin 21) and the DRVL2
pin (pin 17) set to "H" level, when the feedback voltage detects a higher state at 50 μs (Typ) or more. The
voltage output stops to fixes the high-side FET to the off-state and the low-side FET to the on-state, of both
channels in the DC/DC converter.
The over-voltage protection state can be cancelled by setting the IC to standby state first and then resetting
the latch using the UVLO signal.
(7) Under-voltage Protection Circuit Block (UVP Comp.)
It compares 0.7 times (Typ) of the internal reference voltage INTREF (CH1/CH2: 0.7V/2.0V) with the feedback
voltage that is input to the FB1 pin (pin 3) and the FB2 pin (pin 11). The RS latch is set and the DRVH1 pin
(pin 23) and the DRVH2 pin (pin 15) go to "L" level and the DRVL1 pin (pin 21) and the DRVL2 pin (pin 17)
go to "L" level, when the feedback voltage detects a lower state at 1.7 ms (Typ) or more. The discharge
function internal in the IC operates and the voltage output of both channels stops, in synchronization with
setting the latch of under voltage protection.
The under-voltage protection state can be cancelled by setting the IC to standby state first and then resetting
the latch using the UVLO signal.
Connection state of FB1 and FB2
pins SW state Remarks
Connected to an external resistor SW1 : ON
SW2 : OFF
The DC/DC output voltage can be set freely by the exter-
nal resistor
Connected to CVBLPF pin (pin 7) SW1 : OFF
SW2 : ON
The external resistor for output voltage setting is unnec-
essary because DC/DC output voltage setting resistor
embedded in the IC is used.
Set VO1 = 1.23 V, VO2 = 3.45 V.
3
Error Comp.
INTREF
2.5 V
+
−
−
+
FB1
SW1
Comp.1
SW2
4
10
11
FB2
VO1
VO2
< VO Control >.
MB39A138
DS04–27270–2E 15
(8) Over-temperature Protection Circuit Block (OTP)
If the junction temperature reaches +150 °C, the over-temperature protection circuit block makes the dis-
charge function internal in the IC operate and makes voltage output of both channels stop. The soft start
activates again when the junction temperature goes down to +125 °C.
(9) Output Block (DRV1, DRV2)
The output circuit is configured in CMOS type for both of the high-side and the low-side, allowing the external
N-ch MOS FET to drive.
(10) Over Current Detection Block (ILIM)
The over current detection block (ILIM) compares the difference voltage between the PGND pin (pin 18) and
the LX1 pin (pin 22) during the synchronous rectification period with the ILIM1 pin (pin 5) voltage, and
compares the difference voltage between the PGND pin and the LX2 pin (pin 16) with the ILIM2 pin (pin 9)
voltage, and detects over current at each cycle.
The high-side FET remains the off state until the voltage difference between the PGND pin and the LXx pin
becomes below the ILIMx pin voltage and ON in the high-side FET is allowed after the voltage difference
has been below the ILIMx pin voltage. This protects a circuit from flowing over current. This protection
operates to drop the output voltage.
The difference voltage between PGND and LXx caused during the synchronous rectification period is de-
scribed as the voltage waveform by sensing the inductor current, as the ON-resistance of the low-side FET
is regarded as the sense resistor.
The optional limit value for over current can be set by setting a resistor to the ILIMx pin because IILIM current
which is 10 μA (Typ) is supplied from the ILIMx pin. As for IILIM current, the temperature slope which is 4200
ppm/ °C is set to compensate the temperature dependence characteristics of the low-side FET on-resistance.
Note: x is each channel number.
(11) Control Block (CTL)
On and off for CH1 is set by the CTL1 pin (pin 1) and on and off for CH2 is set by the CTL2 pin (pin 8). If
setting CTL1 and CTL2 to "L" level at the same time, this IC turns to the standby state. (The maximum power-
supply current at standby is 10 μA.)
Control Function Table
CTL1 CTL2 DC/DC converter (CH1) DC/DC converter (CH2)
LL OFF OFF
H L ON OFF
LH OFF ON
H H ON ON
MB39A138
16 DS04–27270–2E
■PROTECTION FUNCTION TABLE
The following table shows the state of DRVH1, DRVH2 pins (pin 23, pin 15) and DRVL1, DRVL2 pins (pin
21, pin 17) when each protection function operates.
Note: x is each channel number.
Protection function Detection condition
Output of each pin
after detection DC/DC output
dropping operation
VB DRVHx DRVLx
Under Voltage
Lockout Protection
(UVLO)
VCVBLPF < 3.6 V ⎯LL
Electrical discharge by
discharge function
Under Voltage
Protection
(UVP)
VFBx < INTREFx × 0.7 V 5.2 V L L Electrical discharge by
discharge function
Over Voltage
Protection
(OVP)
VFBx > INTREFx × 1.15 V 5.2 V L H 0 V clamping
Over Current
Protection
(ILIM)
VPGNDx – VLXx > VILIMx 5.2 V switching switching The voltage is dropped
by the constant current
Over Temperature
Protection
(OTP)
Tj > + 150 °C 5.2 V L L Electrical discharge by
discharge function
CONTROL
(CTL)
CTLx : H → L
(VOx > 0.2 V) 5.2 V L L Electrical discharge by
discharge function
MB39A138
DS04–27270–2E 17
■I/O PIN EQUIVALENT CIRCUIT DIAGRAM
(Continued)
GND
CTL1, CTL2
VCC
0.1 V +
−
CVBLPF
CS1, CS2
GND
GND
CVBLPF
FB1, FB2
2.5 V
+
−
GND
VO1, VO2
CVBLPF
GND
GND
CVBLPF
ILIM1, ILIM2
20
1,8
6
3,11
5,9
7
2,12
4,10
FB1, FB2 pins VO1, VO2 pins
CTL1, CTL2 pins CS1, CS2 pins
ILIM1, ILIM2 pins CVBLPF pin
ESD protection
element
MB39A138
18 DS04–27270–2E
(Continued)
GND
CVBLPF
TEST
LX1, LX2
DRVH1, DRVH2
CB1, CB2
PGND
VB
DRVL1, DRVL2
PGND
VB
VCC
PGND
VB
CB1, CB2
13
24,14
23,15
22,16
19
21,17
18
DRVL1, DRVL2 pins VB pin
TEST pin DRVH1, DRVH2, CB1, CB2 and LX1, LX2 pins
MB39A138
DS04–27270–2E 19
■EXAMPLE APPLICATION CIRCUIT
VB
TEST
7
13
4
3
1
5
2
10
11
8
9
12
6
CVBLPF
VB
VCC
VCC
VO1
VCC
VO2
12 V
1.2 V, 5 A
3.3 V, 5 A
C7
C8
C1-1
C1-2
C2-3
C2-1
C3-2
C3-1
C6
C4-3
C4-1
VO1
C9 R7
FB1
ILIM1
CTL1
CTL1
R2
R5
R4
R6
C13 C12
R1-2 R1-1
CS1
VO2
FB2
CTL2
CTL2
ILIM2
CS2
GND
VB
VCC 20
19 VB
PGND
VIN
D2
D1
7
G
G
2
Q1 S1
8
D2
C5
L1
D1
5
4
Q1 S3
6
24
23
22
21
14
15
16
17
18
CB1
LX1
CRVH1
DRVL1
CB2
DRVH2
DRVL2
LX2
PGND
L2
G
D2
D1
7
2
Q3 S1
8
G
D2
D1
5
4
Q3 S3
6
R3-2 R3-1
MB39A138
MB39A138
20 DS04–27270–2E
■PARTS LIST
RENESAS : Renesas Electronics Corporation
SANYO : SANYO Electric Co., Ltd.
TDK : TDK Corporation
SSM : SUSUMU Co.,Ltd.
KOA : KOA Corporation
Compo-
nent Item Specification Vendor Pack-
age Part number Remarks
Q1 N-ch FET VDS = 30 V, ID = 8 A,
Ron = 21 mΩRENESAS SO-8 μPA2755 Dual type
(2 elements)
Q3 N-ch FET VDS = 30 V, ID = 8 A,
Ron = 21 mΩRENESAS SO-8 μPA2755 Dual type
(2 elements)
L1 Inductor 1.5 μH (6.8 mΩ, 9.0 A) TDK ⎯VLF10045T-1R5N9R0
L2 Inductor 2.2 μH (10.2 mΩ, 7.4 A) TDK ⎯VLF10045T-2R2N7R4
C1-1 Ceramic
capacitor 10 μF (25 V) TDK 3216 C3216JB1E106K
C1-2 Ceramic
capacitor 10 μF (25 V) TDK 3216 C3216JB1E106K
C2-1 OS-CON 220 μF (6.3 V, 15 mΩ Max) SANYO C6 6SVPC220MV
C2-3 Ceramic
capacitor 1000 pF (50 V) TDK 1608 C1608CH1H102J
C3-1 Ceramic
capacitor 10 μF (25 V) TDK 3216 C3216JB1E106K
C3-2 Ceramic
capacitor 10 μF (25 V) TDK 3216 C3216JB1E106K
C4-1 OS-CON 220 μF (6.3 V, 15 mΩ Max) SANYO C6 6SVPC220MV
C4-3 Ceramic
capacitor 1000 pF (50 V) TDK 1608 C1608CH1H102J
C5 Ceramic
capacitor 0.1 μF (50 V) TDK 1608 C1608JB1H104K
C6 Ceramic
capacitor 0.1 μF (50 V) TDK 1608 C1608JB1H104K
C7 Ceramic
capacitor 0.1 μF (50 V) TDK 1608 C1608JB1H104K
C8 Ceramic
capacitor 2.2 μF (16 V) TDK 1608 C1608JB1C225K
C9 Ceramic
capacitor 1.0 μF (16 V) TDK 1608 C1608JB1C105K
C12 Ceramic
capacitor 0.015 μF (50 V) TDK 1608 C1608JB1H153K
C13 Ceramic
capacitor 4700 pF (50 V) TDK 1608 C1608JB1H472K
R1-1 Resistor 1 kΩSSM 1608 RR0816P102D
R1-2 Resistor 24 kΩSSM 1608 RR0816P243D
R2 Resistor 36 kΩSSM 1608 RR0816P363D
R3-1 Resistor 1.1 kΩSSM 1608 RR0816P112D
R3-2 Resistor 22 kΩSSM 1608 RR0816P223D
R4 Resistor 36 kΩSSM 1608 RR0816P363D
R5 Resistor 18 kΩSSM 1608 RR0816P183D
R6 Resistor 18 kΩSSM 1608 RR0816P183D
R7 Resistor 5.6 ΩKOA 1608 RK73H1JTTD5R6F
MB39A138
DS04–27270–2E 21
■APPLICATION NOTE
1. Setting Operating Conditions
Setting output voltages
1. When the output setting voltages are Vo1 = 1.23 V, Vo2 = 3.45 V:
They can be set by the internal preset function. In this case, the smallest number of parts is required for the
setting, as it is not necessary to use a resistor to set the output voltage.
2. When the output setting voltages are other Vo1 = 1.23 V, Vo2 = 3.45 V:
They can be set by adjusting the ratio of the output voltage setting resistor value. The output setting voltage
is calculated by the following formula.
The output ripple voltage value (ΔVOX) is calculated by the following formula.
Note: x is each channel number.
When not using the following feedback capacitor (CFB), select a resistor value that achieves R1//R2 ≤
15 kΩ as a target.
Set so that the on-time (tON) is more than 100 ns.
(For how to calculate the on-time, see (4) ON/OFF Time Generator Block in “■ FUNCTION”)
Pin connection Output voltage setting value (Vo)
CH1 FB1 = CVBLPF Vo1 = 1.23 V
CH2 FB2 = CVBLPF Vo2 = 3.45 V
VOX = R1 + R2 × INTREF + ΔVOX
R2 2
VOX : Output setting voltage [V]
INTREF : Internal reference voltage (CH1/CH2 : 0.7 V/2.0 V)
ΔVOX : Output ripple voltage value [V]
ΔVOX = ESR × VIN−VOX × VOX
LVIN × fOSC
ΔVOX : Output ripple voltage value [V]
L : Inductor value [H]
VIN : Power supply voltage [V]
VOX : Output setting voltage [V]
fOSC : Oscillation frequency [Hz] (CH1 : 310 kHz, CH2 : 465 kHz)
R1
V
OX
R2
VO
X
FB
X
MB39A138
22 DS04–27270–2E
As the output voltage gets higher, the resistor value ratio of output voltage setting is getting higher. Moreover,
the oscillation frequency may become unstable as a result. This occurs because the value of the ripple
voltage applied to the FB pin is reduced by the R1/R2 ratio. In this case, a stable oscillation frequency can
be achieved by increasing the output ripple voltage or adding a capacitor (CFB) in parallel to R1.
Select an additional capacitor using the following formula as a guide.
Moreover, adding a capacitor increases the output voltage according to the output ripple voltage.
The following formula is used to calculate the output voltage value to be increased.
Use the following formula to calculate the output setting voltage when considering the output setting voltage
offset value.
Note: x is each channel number.
CFB ≥ 10 × (R1 + R2)
2π × fosc × R1 × R2
CFB : Capacitor value of feedback capacitor [F]
R1, R2 : Output voltage setting resistor value [Ω]
fOSC : Oscillation frequency [Hz]
Vo_offset = (VO − INTREF) × ΔVO
2 × INTREF
Vo_offset : Output setting voltage offset value [V]
VO : Output setting voltage [V]
ΔVo : Output ripple voltage value [V]
INTREF : Internal reference voltage (CH1/CH2 : 0.7 V/2.0 V)
VOX = R1 + R2 × INTREF + ΔVOX + VO_offset
R2 2
VOX : Output setting voltage[V]
INTREF : Internal reference voltage (CH1/CH2 : 0.7 V/2.0 V)
ΔVOX : Output ripple voltage value [V]
VO_offset : Output setting voltage offset value [V]
R1
V
O
R2
VO
FB
C
FB
ΔVo
Vo_offset
Vo
V
t
MB39A138
DS04–27270–2E 23
Consideration of output ripple voltage
This device requires an output ripple voltage value as an operating principle. It must secure about 15 mV at
the FB pin. Calculate the output ripple voltage required for the output of the DC/DC converter by the following
formula.
A stable oscillation frequency can be achieved by increasing the output ripple voltage.
The output ripple voltage can be increased by selecting a larger output capacitor's ESR or a smaller inductor
value.
However, if the output ripple voltage is increased excessively, the slope of the output ripple voltage during
the off-period (tOFF) becomes steeper, which affects the bottom detection voltage more. As a result, it affects
the output voltage. This become prominent, if it increase on-duty. Ensure that the ripple voltage at the FB
pin is not excessively large.
ΔVOX ≥ K × 15 mV
ΔVOX : Output ripple voltage value [V]
K : Coefficient When CFB is used : K = 1;
CFB is not used : K = VO
INTREF
VO : Output setting voltage [V]
INTREF : Internal reference voltage (CH1/CH2 : 0.7 V/2.0 V)
MB39A138
24 DS04–27270–2E
Setting soft-start time
Calculate the soft-start time by the following formula.
Calculate the delay time until the soft-start activation by the following formula.
In almost all cases, no delay time is generated when the soft-start activates in the state that one side channel
has already activated (UVLO release: VB output already).
Note : Set the slew rate of 750 V/s or more to the input-signal to CTL1 and CTL2 pins.
ts = INTREF × CCS
5 × 10−6
ts : Soft-start time [s] (time until output reaches 100%)
INTREF : Internal reference voltage (CH1/CH2 : 0.7 V/2.0 V)
CCS : CS pin capacitor value [F]
td = 30 × (CVB + CCVBLPF)
td : VB voltage delay time [s]
CVB : VB capacitor value [F]
CCVBLPF : CVBLPF capacitor value [F]
0
50
100
150
200
250
300
350
400
510152025
C
VB
= 2.2 μF, C
CVBLPF
= 1 μF
Reference characteristics : Time until the soft-start activates vs. power supply voltage
Power supply voltage VIN [V]
Time until the soft-start activates
td [μs]
CTL1
CTL2
VO1
VO2
t
s1
t
d1
t
s2
MB39A138
DS04–27270–2E 25
Setting over current detection value
The over current detection value can be set by adjusting the over current detection resistor value connected
to the ILIM pin.
Calculate the resistor value by the following formula.
If the rate of inductor saturation current is small, the inductor value decreases and the ripple current of
inductor increase when the over-current flows. At that time there is a possibility that the limited output current
increases or is not limited, because the bottom of inductor current is detected. It is necessary to use the
inductor that has enough large rate of inductor saturation current to prevent the overlap current.
RON_Sync × (ILIM − ΔIL + VO × 260 × 10−9
)
RLIM = 2L
10 × 10−6
RLIM : Over current detection value setting resistor [Ω]
ILIM : Over current detection value [A]
ΔIL : Ripple current peak-to-peak value of inductor [A]
RON_Sync : ON resistance of low-side FET [Ω]
VO : Output setting voltage [V]
L : Inductor value [H]
ILIM
R
LIM
ΔI
L
I
O
I
LIM
0
Inductor current
Value to limit over
current
Time
MB39A138
26 DS04–27270–2E
The over current limit value is affected by ILIM pin source current and over current detection offset voltage
in the IC except for the on resistance of the low-side FET and the inductor value. The variation of dropped
over current limit value caused by IC characteristics is calculated by the following formula.
The over current detection value needs to set a sufficient margin against the maximum load current.
ΔILIM = − 1.7 × 10−6 × RLIM + 0.02
RON_Sync
ΔILIM : The variation of dropped over current limit value [A]
RLIM : Resistor to set over current limit [Ω]
RON_Sync : Low-side FET on resistance [Ω]
ΔILIM
IO
0
ILIM
ILIM’
Inductor current
Over current limit value
Time
Dropped over current limit value due to
IC's characteristics
MB39A138
DS04–27270–2E 27
VB Regulator
In the condition for which the potential difference between VCC and VB is insufficient, the decrease in the
voltage of VB happens because of power output on-resistance and load current (mean current of all external
FET gate driving current and load current of internal IC) of the VB regulator. Stop the switching operation
when the voltage of VB decreases and it reaches threshold voltage (VTHL) of the under voltage lockout
protection circuit.
Therefore, set oscillation frequency or external FET or I/O potential difference of the VB regulator using the
following formula as a target when you use this IC. When using it in the condition for which the I/O potential
difference is insufficient, check the operation on an actual device carefully during normal operation, startup
and shutdown.
Power dissipation and the thermal design
As for this IC, considerations of the power dissipation and thermal design are not necessary in most cases
because of its high efficiency. However, they are necessary for the use at the conditions of a high power
supply voltage, a high oscillation frequency, high load, and the high temperature. Calculate IC internal loss
by the following formula.
Calculate junction temperature (Tj) by the following formula.
VIN ≥ VB (VTHL) + (Qg × fOSC + ICC) × RVB
VB (VTHL) : Threshold voltage of under-voltage lockout protection circuit = 3.8 [V] Max
Qg : Total amount of gate charge of external FET [C]
fOSC : Oscillation frequency [Hz]
ICC : Power supply current = 2 × 10−3 [A] ( ≈ Load current of VB (LDO))
RVB : VB Output on-resistance = 75 [Ω] (The reference value at VIN = 6 V)
PIC = VCC × (ICC + Qg1 × fOSC1 + Qg2 × fOSC2)
PIC : IC internal loss [W]
VCC : Power supply voltage (VIN) [V]
ICC : Power supply current [A] (2 mA Max)
Qg1, Qg2 : Total quantity of charge for the high-side FET and the low-side FET of
each CH [C] (Total at Vgs = VB)
fOSC1, fOSC2 : Oscillation frequency of each CH [Hz]
Tj = Ta + θja × PIC
Tj : Junction temperature [ °C] ( + 125 °C Max)
Ta : Operation ambient temperature [ °C]
θja : TSSOP-24 Package thermal resistance ( + 75 °C/W)
PIC : IC internal loss [W]
MB39A138
28 DS04–27270–2E
Handling of the pins when using a single channel
Although this device is a 2-channel DC/DC converter control IC, it is also able to be used as a 1-channel
DC/DC converter by handling the pins of the unused channel as shown in the following diagram.
FBx
VOx
CSx
LXx
CTLx
DRVHx
CBx
DRVLx
ILIMx
Note: x is the unused channel number.
“Open”
“Open”
“Open”
“Open”
MB39A138
DS04–27270–2E 29
2. Selecting parts
Selection of smoothing inductor
The inductor value selects the value that the ripple current peak-to-peak value of the inductor is 50% or less
of the maximum load current as a rough standard. Calculate the inductor value in this case by the following
formula.
It is necessary to calculate the maximum current value that flows to the inductor to judge whether the electric
current that flows to the inductor is a rated value or less. Calculate the maximum current value of the inductor
by the following formula.
L ≥ VIN − VO
×
VO
LOR × IOMAX VIN × fOSC
L : Inductor value [H]
IOMAX : Maximum load current [A]
LOR : Ripple current peak-to-peak value of inductor / Maximum load current ratio (=0.5)
VIN : Power supply voltage [V]
VO : Output setting voltage [V]
fOSC : Oscillation frequency [Hz]
ILMAX ≥ IOMAX + ΔIL
2
ΔIL = VIN − VO
×
VO
LVIN × fOSC
ILMAX : Maximum current value of inductor [A]
IOMAX : Maximum load current [A]
ΔIL : Ripple current peak-to-peak value of inductor [A]
L : Inductor value [H]
VIN : Power supply voltage[V]
VO : Output setting voltage[V]
fOSC : Oscillation frequency [Hz]
I
OMAX
I
LMAX
0
ΔIL
Inductor current
Time
MB39A138
30 DS04–27270–2E
Selection of Switching FET
Select the low-side FET ON resistance from the below range in order to operate the over current limit function
normally.
The maximum value of the current that flows to the switching FET must be calculated in order to determine
whether the current flowing to the switching FET is within the rated value. Calculate the maximum value of
the current that flows to the switching FET by the following formula.
Moreover, it is necessary to calculate the loss of switching FET to judge whether a power dissipation of
switching FET is a rated value or less. Calculate the loss on high-side FET by the following formula.
High-side FET conduction loss
High-side FET switching loss
0.03 ≤ RON_Sync ≤ 0.2
(ILIM − ΔIL ) (ILIM − ΔIL )
22
RON_Sync : Low-side FET ON resistance [Ω]
ΔIL : Ripple current peak-to-peak value of inductor [A]
ILIM : Over current detection value [A]
ID = IOMAX + ΔIL
2
ID : Drain current [A]
IOMAX : Maximum load current [A]
ΔIL : Ripple current peak-to-peak value of inductor [A]
PMainFET = PRON_Main + PSW_Main
PMainFET : High-side FET loss [W]
PRON_Main : High-side FET conduction loss [W]
PSW_Main : High-side FET switching loss [W]
PRON_Main = IOMAX2 × VO × RON_Main
VIN
PRON_Main : High-side FET conduction loss [W]
IOMAX : Maximum load current[A]
VIN : Power supply voltage[V]
VO : Output voltage[V]
RON_Main : High-side FET ON resistance [Ω]
PSW_Main = VIN × fOSC × (Ibtm × tr + Itop × tf)
2
PSW_Main : Switching loss [W]
VIN : Power supply voltage [V]
fOSC : Oscillation frequency (Hz)
Ibtm : Ripple current bottom value of inductor [A]
Itop : Ripple current top value of inductor [A]
MB39A138
DS04–27270–2E 31
tr : Turn-on time on high-side FET [s]
tf : Turn-off time on high-side FET [s]
tr and tf is calculated by the following formula.
The loss of the low-side FET is calculated by the following formula. (The transition voltage of the voltage
between drain and source on low-side FET is generally small, and the switching loss is omitted here for the
small one as it is possible to disregard it.)
The gate drive power of switching FET is supplied by LDO in IC, therefore all of the allowable maximum total
gate charge (QgTotalMax) of all switching FET for 2 channels is calculated by the following formula.
Ibtm = IOMAX − ΔIL , Itop = IOMAX + ΔIL
22
ΔIL : Ripple current peak-to-peak value of inductor [A]
IOMAX : Maximum load current [A]
tr = Qgd × 4 , tf = Qgd × 1
VB − Vgs (on) Vgs (on)
Qgd : Quantity of charge between gate and drain on high-side FET [C]
Vgs (on) : Voltage between gate and sources in Qgd on high-side FET [V]
VB : VB voltage [V]
PSyncFET = RRon_Sync = IOMAX2 × (1 − VO) × Ron_Sync
VIN
PRon_Sync : Low-side FET conduction loss [W]
IOMAX : Maximum load current [A]
VIN : Power supply voltage [V]
VO : Output voltage [V]
Ron_Sync : Low-side FET on-resistance [Ω]
QgTo t a l M a x ≤ 140000
fOSC2
QgTotalMax : All of the allowable maximum total gate charge of all switching FET for
2 channels [nC]
fOSC2 : CH2 oscillation frequency [kHz]
MB39A138
32 DS04–27270–2E
Selection of fly-back diode
Fly-back diode is not needed in general. However, it is possible to enhance the conversion efficiency by
building in the fly-back diode, thought it is usually unnecessary. The effect is achieved in the condition where
the oscillation frequency is high or output voltage is lower. Select schottky barrier diode (SBD) that the forward
current is as small as possible. In this DC/DC control IC, the period for the electric current flows to fly-back
diode is limited to synchronous rectification period (120 [ns]) because of using the synchronous rectification
method. Therefore, select the one that the electric current of fly-back diode does not exceed ratings of forward
current surge peak (IFSM).Calculate the forward current surge peak ratings of fly-back diode by the following
formula.
Calculate ratings of the fly-back diode by the following formula:
Selection of output capacitor
A certain level of ESR is required for stable operation of this IC. Use a tantalum capacitor or polymer capacitor
as the output capacitor. If using a ceramic capacitor with low ESR, a resistor should be connected in series
with it to increase ESR equivalently.
Calculate the required ESR for the smoothing capacitor by the following formula.
Select the capacitance of the output capacitor with the following condition to a target.
When using a capacitor where the capacity demanded by the above formula is unfulfilled, use it after
intensively operation check that there is no problem with the jitter level.
IFSM ≥ IOMAX + ΔIL
2
IFSM : Forward current surge peak ratings of SBD [A]
IOMAX : Maximum load current [A]
ΔIL : Ripple current peak-to-peak value of inductor [A]
VR_Fly > VIN
VR_Fly : Reverse voltage of fly-back diode direct current [V]
VIN : Power supply voltage [V]
ESR ≥ ΔIL
ΔVO
ESR : Series resistance of output capacitor [Ω]
ΔVO : Output ripple voltage [V]
ΔIL : Ripple current peak-to-peak value of inductor [A]
CO ≥ 1
4 × fOSC × ESR
CO : Output capacitor value [F]
fOSC : Oscillation frequency [Hz]
ESR : Series resistance of output capacitor [Ω]
MB39A138
DS04–27270–2E 33
Moreover, the output capacitor values are also derived from the allowable amount of overshoot and under-
shoot. The following formula is represented as the worst condition in which the shift time for a sudden load
change is 0s. For a longer shift time, the smaller amount of output capacitor is acceptable than the value
calculated by the following formula.
Overshoot condition
Undershoot condition
The capacitor has frequency, operating temperature, and bias voltage characteristics, etc. Therefore, it must
be noted that its effective capacitor value may be significantly smaller, depending on the use conditions.
Calculate voltage rating of the output capacitor by the following formula.
Capacitor voltage rating should have a sufficient margin to withstand the output voltage.
Calculate the allowable ripple current of the output capacitor by the following formula.
CO ≥ ΔIO2 × L
2 × VO × ΔVO_OVER
CO ≥ ΔIO2 × L × (VO + VIN × fOSC × 380 × 109)
2 × VO × ΔVO_UNDER × (VIN − VO − VIN × fOSC × 380 × 109)
CO : Output capacitor value [F]
ΔVO_OVER : Allowable amount of output voltage overshoot [V]
ΔVO_UNDER : Allowable amount of output voltage undershoot [V]
ΔIO : Current difference in sudden load change [A]
L : Inductor value [H]
VIN : Power supply voltage [V]
VO : Output setting voltage[V]
fOSC : Oscillation frequency [Hz]
VCO > VO
VCO : Withstand voltage of the output capacitor [V]
VO : Output voltage [V]
Irms ≥ ΔIL
2
Irms : Allowable ripple current (effective value) [A]
ΔIL : Ripple current peak-to-peak value of inductor [A]
√3
MB39A138
34 DS04–27270–2E
Selection of input capacitor
Select the input capacitor whose ESR is as small as possible. The ceramic capacitor is an ideal. Use the
tantalum capacitor and the polymer capacitor of the low ESR when a mass capacitor is needed as the
ceramic capacitor can not support.
If a inductor is connected as a noise filter between the power supply and the input capacitor, and the cut-off
frequency for this inductor and input capacitor is set to a value lower than the oscillation frequency, the ripple
voltage by the switching operation of DC/DC is generated.
Discuss the lower bound of input capacitor according to an allowable ripple voltage. Calculate the ripple
voltage of the power supply from the following formula.
Capacitor has frequency characteristic, the temperature characteristic, and the bias voltage characteristic,
etc. The effective capacitor value might become extremely small depending on the use conditions. Note the
effective capacitor value in the use conditions.
Calculate ratings of the input capacitor by the following formula:
Select the capacitor voltages rating with withstand voltage with margin enough for the input voltage.
In addition, use the allowable ripple current with an enough margin, if it has a rating. Calculate an allowable
ripple current by the following formula.
ΔVIN = IOMAX × VO + ESR × (IOMAX + ΔIL )
CIN VIN × fOSC 2
ΔVIN : Power supply ripple voltage peak-to-peak value [V]
IOMAX : Maximum load current value [A]
CIN : Input capacitor value [F]
VIN : Power supply voltage [V]
VO : Output setting voltage [V]
fOSC : Oscillation frequency [Hz]
ESR : Series resistance component of input capacitor [Ω]
ΔIL : Ripple current peak-to-peak value of inductor [A]
VCIN > VIN
VCIN : Withstand voltage of the input capacitor [V]
VIN : Power supply voltage [V]
Irms ≥ IOMAX × VIN
Irms : Ripple current (effective value) [A]
IOMAX : Maximum load current value [A]
VIN : Power supply voltage [V]
VO : Output setting voltage [V]
MB39A138
DS04–27270–2E 35
Selection of boot strap capacitor
To drive the gate of high-side FET, the bootstrap capacitor must have enough stored charge. Therefore, a
minimum value as a target is assumed the capacitor which can store electric charge 10 times that of the Qg
on high-side FET. And select the boot strap capacitor.
Calculate ratings of the boot strap capacitor by the following formula:
VB pin capacitor
2.2 μF is assumed to be a standard, and when Qg of switching FET used is large, it is necessary to adjust
it. To drive the gate of high-side FET, the bootstrap capacitor must have enough stored charge. Therefore,
a minimum value as a target is assumed the capacitor value which can store electric charge 100 times that
of the Qg on switching FET. And select it.
Moreover, capacitor change may cause an overshoot when CTL was turned on.
Although the overshoot does not affect DC/DC operation, check that the VB pin does not exceed its rating
before applying the capacitors.
Calculate ratings of the VB pin capacitor by the following formula:
CVBLPF pin capacitor and resistor
LPF to power supply from the VB regulator (VB pin) to the control system power supply (CVBLPF pin) is
made by the CVBPF pin's capacitor and the resistor between the VB pin and the CVBPF pin. The cut-off
frequency is set to one tenth of oscillation frequency as a target (1 μF is the standard of the capacitor value).
Select as small a value as possible (the recommended value is about 5 Ω).
Because the voltages drop to the control system power supply is occurred when setting the resistor value
to extremely large value.
CBOOT ≥ 10 × Qg
VB
CBOOT : Boot strap capacitor value [F]
Qg : Amount of gate charge on high-side FET [C]
VB : VB voltage [V]
VCBOOT > VB
VCBOOT : Withstand voltage of the boot strap capacitor[V]
VB : VB voltage [V]
CVB ≥ 100 × Qg
VB
CVB : VB pin capacitor value [F]
Qg : Total amount of gate charge of high-side FET and low-side FET for 2ch [C]
VB : VB voltage [V]
VCVB > VB
VCVB : Withstand voltage of the VB pin capacitor [V]
VB : VB voltage [V]
MB39A138
36 DS04–27270–2E
3. Layout
Consider the points listed below and do the layout design.
• Provide the ground plane as much as possible on the IC mounted face. Connect bypass capacitor con-
nected with the VCC and VB pins, and GND pin of the switching system parts with switching system GND
(PGND). Connect other GND connection pins with control system GND (AGND), and separate each GND,
and try not to pass the heavy current path through the control system GND (AGND) as much as possible.
In that case, connect control system GND (AGND) and switching system GND (PGND) at the single point
of GND (PGND) in IC.
• Connect the switching system parts as much as possible on the surface. Avoid the connection through the
through-hole as much as possible.
• As for GND pins of the switching system parts, provide the through hole at the proximal place, and connect
it with GND of internal layer.
• Pay the most attention to the loop composed of input capacitor (CIN), switching FET, and fly-back diode
(SBD). Consider making the current loop as small as possible.
• Place the boot strap capacitor (CBOOT1, CBOOT2) proximal to CBx and LXx pins of IC as much as possible.
• Large electric current flows momentary in the net of DRVHx and DRVLx pins connected with the gate of
switching FET. Wire the linewidth of about 0.8 mm to be a standard, as short as possible.
• By-pass capacitor (CVBLPF, CVCC, CVB) connected with CVBLPF, VCC, and VB should be placed close to the
pin as much as possible. Also connect the GND pin of the bypass capacitor with GND of internal layer in
the proximal through-hole.
• Pull the feedback line to be connected to the VOx pin of the IC separately from near the output capacitor
pin, whenever possible, in order to feed back it to the IC more accurately. It is the ripple voltage which is
generated from ESR of the output capacitor. Consider the net connected with VOx and FBx pins to keep
away from a switching system parts as much as possible because it is sensitive to the noise.
Moreover, place the output voltage setting resistor connected with this net close to the IC as much as
possible, and try to make the net as short as possible. In addition, for the internal layer right under the
component mounting place, provide the control system GND (AGND) of few ripple and few spike noises,
or provide the ground plane of the power supply as much as possible.
Switching system parts : Input capacitor (CIN), Switching FET, Fly-back diode (SBD), Inductor (L),
Output capacitor (CO)
AGND
PGND
AGND
1pin
PGND
C
BOOT1
C
BOOT2
C
VB
C
VCC
C
VREF
CIN
CO
SBD
(option)
VIN
CIN
CO
PGND
SBD
(option)
Vo1 Vo2
LL
Layout example of IC peripheral Layout example of switching system parts
Through-hole
Connect AGND and PGND right under IC
Surface Internal
layer
High-side FET
To the LX1 pin
Low-side FET
Low-side FET
High-side FET
Through-hole
Output voltage
Vo1 feedback
Output voltage
Vo2 feedback
To the
LX2 pin
Output volt-
age setting
resistor lay-
out
MB39A138
DS04–27270–2E 37
■REFERENCE DATA
(Continued)
Conversion efficiency vs.
Load current
Conversion efficiency vs.
Load current
Conversion efficiency η(%)
Conversion efficiency η(%)
Load current IO(A) Load current IO(A)
Oscillation frequency vs.
Load current
Oscillation frequency vs.
Load current
Oscillation frequency
fosc (kHz)
Oscillation frequency
fosc (kHz)
Load current IO(A) Load current IO(A)
Output voltage vs.
Load current
Output voltage vs.
Load current
Output voltage VO (V)
Output voltage VO (V)
Load current IO(A) Load current IO(A)
50
60
70
80
90
100
01234
5
V
IN
=12 V
V
O1
=1.2 V
Ta = +25°C
50
60
70
80
90
100
012345
V
IN
= 12 V
V
O2
= 3.3 V
Ta = +25°C
190
250
310
370
430
012345
V
IN
=12 V
V
O1
=1.2 V
Ta = +25°C
340
400
460
520
580
012345
V
IN
= 12 V
V
O2
= 3.3 V
Ta = +25°C
1.10
1.15
1.20
1.25
1.30
012345
V
IN
= 12 V
V
O1
= 1.2 V
Ta = +25°C
3.00
3.15
3.30
3.45
3.60
012345
V
IN
= 12 V
V
O2
= 3.3 V
Ta = +25°C
MB39A138
38 DS04–27270–2E
(Continued)
I
O1
: 2 A/div
100 μs/div
5 A
0 A
V
IN
= 12 V, V
O1
= 1.2 V, SR SET = 0.75 A/μs
I
O2
= 0 A 5 A, Ta = + 25 °C
V
O1
: 50 mV/div
4
1
V
IN
= 12 V, V
O2
= 3.3 V, SR SET = 0.75 A/μs
I
O2
= 0 A 5 A, Ta = + 25 °C
100 μs/div
V
O2
: 50 mV/div
I
O2
: 2 A/div
5 A
0 A
1
4
1
2
V
IN
= 12 V, V
O1
= 1.2 V, I
O1
= 5 A, V
O2
= 3.3 V, I
O2
= 5 A,
Ta = + 25 °C
V
O1
: 50 mV/div (AC)
V
O2
: 50 mV/div (AC)
2.0 μs/div
CTL1 : 5 V/div
VIN = 12 V, VO1 = 1.2 V, IO1 = 5 A (0.24 Ω),
VO1 : 500 mV/div
VLX1 : 10 V/div
1 ms/div
1
4
2
V
IN
= 12 V, V
O2
= 3.3 V, I
O2
= 5 A (0.66 Ω),
CTL2 : 5V/div
V
O2
: 1V/div
V
LX2
: 10V/div
1 ms/div
1
4
2
Ripple Waveform
CH1 Load Sudden Change Waveform CH2 Load Sudden Change Waveform
CH1 CTL Startup Waveform CH2 CTL Startup Waveform
Softstart setting time = 2.1 ms, Ta = + 25 °CSoftstart setting time = 1.9 ms, Ta = + 25 °C
MB39A138
DS04–27270–2E 39
(Continued)
3
1
2
CTL1 : 5 V/div
100 μs/div
V
O1
: 500 mV/div
V
LX1
: 10 V/div
V
IN
= 12 V, V
O1
= 1.2 V, I
O1
= 5 A (0.24 Ω), Ta = + 25 °C
3
1
2
100 μs/div
CTL2 : 5 V/div
V
O2
: 1 V/div
V
LX2
: 10 V/div
V
IN
= 12 V, V
O2
= 3.3 V, I
O2
= 5 A (0.66 Ω), Ta
= + 25 °C
3
4
2
V
IN
= 12 V, V
O1
= 1.2 V, Ta
= + 25°C
V
LX1
: 10 V/div
l
O1
: 10 A/div
V
O1
: 500 mV/div
500 μs/div
3
4
2
V
IN
= 12 V
,
V
O2
= 3.3 V
,
Ta
= + 25°C
V
LX2
: 10 V/div
l
O2
: 10 A/div
V
O2
: 1 V/div
500 μs/div
CH1 CTL Shutdown Waveform CH2 CTL Shutdown Waveform
CH1 Output Over Current Waveform CH2 Output Over Current Waveform
Normal
operation
Over current
protection
Under voltage
protection
Normal
operation
Over current
protection
Under voltage
protection
MB39A138
40 DS04–27270–2E
■USAGE PRECAUTION
1. Do not configure the IC over the maximum ratings.
If the IC is used over the maximum ratings, the LSI may be permanently damaged.
It is preferable for the device to normally operate within the recommended usage conditions. Usage outside
of these conditions can have an adverse effect on the reliability of the LSI.
2. Use the device within the recommended operating conditions.
The recommended values guarantee the normal LSI operation under the recommended operating conditions.
The electrical ratings are guaranteed when the device is used within the recommended operating conditions
and under the conditions stated for each item.
3. Printed circuit board ground lines should be set up with consideration for common
impedance.
4. Take appropriate measures against static electricity.
• Containers for semiconductor materials should have anti-static protection or be made of conductive ma-
terial.
• After mounting, printed circuit boards should be stored and shipped in conductive bags or containers.
• Work platforms, tools, and instruments should be properly grounded.
• Working personnel should be grounded with resistance of 250 kΩ to 1 MΩ in serial body and ground.
5. Do not apply negative voltages.
The use of negative voltages below −0.3 V may make the parasitic transistor activated to the LSI, and can
cause malfunctions.
MB39A138
DS04–27270–2E 41
■ORDERING INFORMATION
■EV BOARD ORDERING INFORMATION
Part number Package Remarks
MB39A138PFT 24-pin plastic TSSOP
(FPT-24P-M10)
EV board number EV board version No. Remarks
MB39A138EVB-01 MB39A138EVB-01 Rev.2.0 TSSOP-24
MB39A138
42 DS04–27270–2E
■RoHS COMPLIANCE INFORMATION OF LEAD (Pb) FREE VERSION
The LSI products of FUJITSU SEMICONDUCTOR with “E1” are compliant with RoHS Directive, and has
observed the standard of lead, cadmium, mercury, Hexavalent chromium, polybrominated biphenyls (PBB)
, and polybrominated diphenyl ethers (PBDE) . A product whose part number has trailing characters “E1”
is RoHS compliant.
■MARKING FORMAT (Lead Free version)
XXXX
39A138
XXX
E1
INDEX
Lead Free version
MB39A138
DS04–27270–2E 43
■LABELING SAMPLE (Lead free version)
2006/03/01
ASSEMBLED IN JAPAN
G
QC PASS
(3N) 1MB123456P-789-GE1
1000
(3N)2 1561190005 107210
1,000
PCS
0605 - Z01A
1000
1/1
1561190005
MB123456P - 789 - GE1
MB123456P - 789 - GE1
MB123456P - 789 - GE1
Pb
Lead-free mark
JEITA logo JEDEC logo
The part number of a lead-free product has the trailing
characters “E1”.
MB39A138
44 DS04–27270–2E
■MB39A138PFT
RECOMMENDED CONDITIONS OF MOISTURE SENSITIVITY LEVEL
[FUJITSU SEMICONDUCTOR Recommended Mounting Conditions]
[Mounting Conditions]
(1) IR (infrared reflow)
(2) Manual soldering (partial heating method)
Temperature at the tip of an soldering iron: 400 °C max
Time: Five seconds or below per pin
Item Condition
Mounting Method IR (infrared reflow) , Manual soldering (partial heating method)
Mounting times 2 times
Storage period
Before opening Please use it within two years after
Manufacture.
From opening to the 2nd
reflow Less than 8 days
When the storage period after
opening was exceeded
Please process within 8 days
after baking (125 °C, 24h)
Storage conditions 5 °C to 30 °C, 70%RH or less (the lowest possible humidity)
260°C
(e)
(d')
(d)
255°C
170 °C
190 °C
RT (b)
(a)
(c)
to
Note: Temperature : on the top of the package body
“H” level : 260 °C Max
(a) Temperature increase gradient : Average 1 °C/s to 4 °C/s
(b) Preliminary heating : Temperature 170 °C to 190 °C, 60 s to 180 s
(c) Temperature increase gradient : Average 1 °C/s to 4 °C/s
(d) Peak temperature : Temperature 260 °C Max; 255 °C or more, 10 s or less
(d’) Main heating : Temperature 230 °C or more, 40 s or less
or
Temperature 225 °C or more, 60 s or less
or
Temperature 220 °C or more, 80 s or less
(e) Cooling : Natural cooling or forced cooling
Main heating
MB39A138
DS04–27270–2E 45
■PACKAGE DIMENSIONS
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
24-pin plastic TSSOP Lead pitch 0.65 mm
Package width
×
package length
4.40 mm × 7.80 mm
Lead shape Gullwing
Sealing method Plastic mold
Mounting height 1.20 mm MAX
Weight 0.10 g
24-pin plastic TSSOP
(FPT-24P-M10)
(FPT-24P-M10)
C
2008-2010 FUJITSU SEMICONDUCTOR LIMITED F24033S-c-1-2
7.80±0.10(.307±.004)
0.65(.026)
(.173±.004)
4.40±0.10
6.40±0.20
(.252±.008)
0.10(.004)
"A"
INDEX
#
#
BTM E-MARK
1 12
24 13
0.22
.008 0.10(.004)
.005
0.13
1.20(.047)
(.004±.002)
0.60±0.15
(.024±.006)
0~8°
Details of "A" part
(Stand off)
(Mounting height)
0.10±0.05
MAX
+0.07
+.003
–0.02
–.001
+0.06
+.002
–0.03
–.001
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Note 1) Pins width and pins thickness include plating thickness.
Note 2) Pins width do not include tie bar cutting remainder.
Note 3) #: These dimensions do not include resin protrusion.
MB39A138
46 DS04–27270–2E
MEMO
MB39A138
DS04–27270–2E 47
MEMO
MB39A138
FUJITSU SEMICONDUCTOR LIMITED
Nomura Fudosan Shin-yokohama Bldg. 10-23, Shin-yokohama 2-Chome,
Kohoku-ku Yokohama Kanagawa 222-0033, Japan
Tel: +81-45-415-5858
http://jp.fujitsu.com/fsl/en/
For further information please contact:
North and South America
FUJITSU SEMICONDUCTOR AMERICA, INC.
1250 E. Arques Avenue, M/S 333
Sunnyvale, CA 94085-5401, U.S.A.
Tel: +1-408-737-5600 Fax: +1-408-737-5999
http://us.fujitsu.com/micro/
Europe
FUJITSU SEMICONDUCTOR EUROPE GmbH
Pittlerstrasse 47, 63225 Langen, Germany
Tel: +49-6103-690-0 Fax: +49-6103-690-122
http://emea.fujitsu.com/semiconductor/
Korea
FUJITSU SEMICONDUCTOR KOREA LTD.
206 Kosmo Tower Building, 1002 Daechi-Dong,
Gangnam-Gu, Seoul 135-280, Republic of Korea
Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
http://kr.fujitsu.com/fmk/
Asia Pacific
FUJITSU SEMICONDUCTOR ASIA PTE. LTD.
151 Lorong Chuan,
#05-08 New Tech Park 556741 Singapore
Tel : +65-6281-0770 Fax : +65-6281-0220
http://www.fujitsu.com/sg/services/micro/semiconductor/
FUJITSU SEMICONDUCTOR SHANGHAI CO., LTD.
Rm. 3102, Bund Center, No.222 Yan An Road (E),
Shanghai 200002, China
Tel : +86-21-6146-3688 Fax : +86-21-6335-1605
http://cn.fujitsu.com/fss/
FUJITSU SEMICONDUCTOR PACIFIC ASIA LTD.
10/F., World Commerce Centre, 11 Canton Road,
Tsimshatsui, Kowloon, Hong Kong
Tel : +852-2377-0226 Fax : +852-2376-3269
http://cn.fujitsu.com/fsp/
Specifications are subject to change without notice. For further information please contact each office.
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose
of reference to show examples of operations and uses of FUJITSU SEMICONDUCTOR device; FUJITSU SEMICONDUCTOR does
not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating
the device based on such information, you must assume any responsibility arising out of such use of the information.
FUJITSU SEMICONDUCTOR assumes no liability for any damages whatsoever arising out of the use of the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use
or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU SEMICONDUCTOR or any
third party or does FUJITSU SEMICONDUCTOR warrant non-infringement of any third-party's intellectual property right or other right
by using such information. FUJITSU SEMICONDUCTOR assumes no liability for any infringement of the intellectual property rights or
other rights of third parties which would result from the use of information contained herein.
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured
as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect
to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in
nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in
weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).
Please note that FUJITSU SEMICONDUCTOR will not be liable against you and/or any third party for any claims or damages aris-
ing in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures
by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-
current levels and other abnormal operating conditions.
Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations
of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.
The company names and brand names herein are the trademarks or registered trademarks of their respective owners.
Edited: Sales Promotion Department