SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163
SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163
SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS
SDAS276A – DECEMBER 1994 – REVISED JULY 2000
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Internal Look-Ahead Circuitry for Fast
Counting
D
Carry Output for n-Bit Cascading
D
Synchronous Counting
D
Synchronously Programmable
D
Package Options Include Plastic
Small-Outline (D) and Shrink Small-Outline
(DB) Packages, Ceramic Chip Carriers (FK),
Standard Plastic (N) and Ceramic (J) DIPs
description
These synchronous, presettable, 4-bit decade
and binary counters feature an internal carry
look-ahead circuitry for application in high-speed
counting designs. The SN54ALS162B is a 4-bit
decade counter. The ’ALS161B, ’ALS163B,
’AS161, and ’AS163 devices are 4-bit binary
counters. Synchronous operation is provided by
having all flip-flops clocked simultaneously so that
the outputs change coincidentally with each other
when instructed by the count-enable (ENP, ENT)
inputs and internal gating. This mode of operation
eliminates the output counting spikes normally
associated with asynchronous (ripple-clock)
counters. A buffered clock (CLK) input triggers the
four flip-flops on the rising (positive-going) edge of
the clock input waveform.
These counters are fully programmable; they can
be preset to any number between 0 and 9 or 15.
Because presetting is synchronous, setting up a
low level at the load (LOAD) input disables the
counter and causes the outputs to agree with the
setup data after the next clock pulse, regardless
of the levels of the enable inputs.
The clear function for the ’ALS161B and ’AS161 devices is asynchronous. A low level at the clear (CLR) input
sets all four of the flip-flop outputs low, regardless of the levels of the CLK, LOAD, or enable inputs. The clear
function for the SN54ALS162B, ’ALS163B, and ’AS163 devices is synchronous, and a low level at CLR sets
all four of the flip-flop outputs low after the next clock pulse, regardless of the levels of the enable inputs. This
synchronous clear allows the count length to be modified easily by decoding the Q outputs for the maximum
count desired. The active-low output of the gate used for decoding is connected to CLR to synchronously clear
the counter to 0000 (LLLL).
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without
additional gating. ENP and ENT inputs and a ripple-carry (RCO) output are instrumental in accomplishing this
function. Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. RCO, thus enabled,
Copyright 2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
SN54ALS161B, SN54ALS162B, SN54ALS163B,
SN54AS161, SN54AS163 ...J PACKAGE
SN74ALS161B, SN74AS161,
SN74AS163 ...D OR N PACKAGE
SN74ALS163B . . . D, DB, OR N PACKAGE
(TOP VIEW)
3212019
910111213
4
5
6
7
8
18
17
16
15
14
QA
QB
NC
QC
QD
A
B
NC
C
D
SN54ALS161B, SN54ALS162B, SN54ALS163B,
SN54AS161, SN54AS163 . . . FK PACKAGE
(TOP VIEW)
CLK
CLR
NC
LOAD
ENT RCO
ENP
GND
NC
NC – No internal connection
VCC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CLR
CLK
A
B
C
D
ENP
GND
VCC
RCO
QA
QB
QC
QD
ENT
LOAD
SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163
SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163
SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS
SDAS276A – DECEMBER 1994 – REVISED JULY 2000
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description (continued)
produces a high-level pulse while the count is maximum (9 or 15, with QA high). The high-level overflow
ripple-carry pulse can be used to enable successive cascaded stages. T ransitions at ENP or ENT are allowed,
regardless of the level of CLK.
These counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD) that
modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of
the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the
stable setup and hold times.
The SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, and SN54AS163 are characterized for
operation over the full military temperature range of –55°C to 125°C. The SN74ALS161B, SN74ALS163B,
SN74AS161, and SN74AS163 are characterized for operation from 0°C to 70°C.
logic symbols†
14
13
12
11
CTRDIV10
LOAD
1, 5D
3
A4
B5
C6
D
5CT=0
1
M2
M1
9
C5/2,3,4+
G3
10
ENT RCO
15
3CT=9
QA
QB
QC
QD
G4
7
ENP 2
CLK
CLR
SN54ALS162B DECADE COUNTER
WITH SYNCHRONOUS CLEAR
14
13
12
11
CTRDIV16
LOAD
1, 5D
3
A4
B5
C6
D
CT=0
1
M2
M1
9
C5/2,3,4+
G3
10
ENT RCO
15
3CT=15
QA
QB
QC
QD
G4
7
ENP 2
CLK
CLR
[1]
[2]
[4]
[8]
’ALS161B AND ’AS161 BINAR Y COUNTERS
WITH DIRECT CLEAR
14
13
12
11
CTRDIV16
LOAD
1, 5D
3
A4
B5
C6
D
5CT=0
1
M2
M1
9
C5/2,3,4+
G3
10
ENT RCO
15
3CT=15
QA
QB
QC
QD
G4
7
ENP 2
CLK
CLR
’ALS163B AND ’AS163 BINAR Y COUNTERS
WITH SYNCHRONOUS CLEAR
[1]
[2]
[4]
[8]
[1]
[2]
[4]
[8]
†These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, DB, J, and N packages.
SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163
SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163
SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS
SDAS276A – DECEMBER 1994 – REVISED JULY 2000
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
1D
C1
1D
C1
1D
C1
1
9
10
7
2
3
4
5
15
14
13
12
CLR
LOAD
ENT
ENP
CLK
A
B
C
RCO
QA
QB
QC
SN54ALS162B
1D
C1
6
11 QD
D
Pin numbers shown are for the J package.
SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163
SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163
SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS
SDAS276A – DECEMBER 1994 – REVISED JULY 2000
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
1D
C1
1D
C1
1D
C1
1D
C1
1
9
10
7
2
3
4
5
6
15
14
13
12
11
CLR
LOAD
ENT
ENP
CLK
A
B
C
D
RCO
QA
QB
QC
QD
’ALS163B and ’AS163
Pin numbers shown are for the D, DB, J, and N packages.
’ALS161B and ’AS161 synchronous binary counters are similar; however, CLR is asynchronous.
SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163
SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163
SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS
SDAS276A – DECEMBER 1994 – REVISED JULY 2000
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
typical clear, preset, count, and inhibit sequences
SN54ALS162B
The following sequence is illustrated below:
1. Clear outputs to zero (SN54ALS162B is synchronous)
2. Preset to BCD 7
3. Count to 8, 9, 0, 1, 2, and 3
4. Inhibit
Data
Inputs
Data
Outputs
CLR
LOAD
A
B
C
D
CLK
ENP
ENT
RCO
QA
QB
QC
QD
Async
Clear
Sync
Clear Preset
Count Inhibit
78
90123
SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163
SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163
SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS
SDAS276A – DECEMBER 1994 – REVISED JULY 2000
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
typical clear, preset, count, and inhibit sequences
’ALS161B, ’AS161, ’ALS163B, and ’AS163
The following sequence is illustrated below:
1. Clear outputs to zero (’ALS161B and ’AS161 are asynchronous; ’ALS163B and ’AS163 are
synchronous.)
2. Preset to binary 12
3. Count to 13, 14, 15, 0, 1, and 2
4. Inhibit
Data
Inputs
Data
Outputs
CLR
LOAD
A
B
C
D
CLK
ENP
ENT
RCO
QA
QB
QC
QD
Async
Clear
Sync
Clear Preset
Count Inhibit
12 13 14 15 0 1 2
SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163
SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163
SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS
SDAS276A – DECEMBER 1994 – REVISED JULY 2000
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 1): D package 73°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DB package 82°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 67°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTE 1: The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions
SN54ALS161B
SN54ALS162B
SN54ALS163B
SN74ALS161B
SN74ALS163B UNIT
MIN NOM MAX MIN NOM MAX
VCC Supply voltage 4.5 5 5.5 4.5 5 5.5 V
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.7 0.8 V
IOH High-level output current –0.4 –0.4 mA
IOL Low-level output current 4 8 mA
TAOperating free-air temperature –55 125 0 70 °C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS
SN54ALS161B
SN54ALS162B
SN54ALS163B
SN74ALS161B
SN74ALS163B UNIT
MIN TYP‡MAX MIN TYP‡MAX
VIK VCC = 4.5 V, II = –18 mA –1.5 –1.5 V
VOH VCC = 4.5 V to 5.5 V, IOH = –0.4 mA VCC –2 VCC –2 V
VOL
VCC =45V
IOL = 4 mA 0.25 0.4 0.25 0.4
V
V
OL
V
CC =
4
.
5
V
IOL = 8 mA 0.35 0.5
V
IIVCC = 5.5 V, VI = 7 V 0.1 0.1 mA
IIH VCC = 5.5 V, VI = 2.7 V 20 20 µA
IIL VCC = 5.5 V, VI = 0.4 V –0.2 –0.2 mA
IO§VCC = 5.5 V, VO = 2.25 V –20 –112 –30 –112 mA
ICC VCC = 5.5 V 12 21 12 21 mA
‡All typical values are at VCC = 5 V, TA = 25°C.
§The output conditions have been chosen to produce a current that closely approximates one-half of the true short-circuit output current, IOS.
SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163
SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163
SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS
SDAS276A – DECEMBER 1994 – REVISED JULY 2000
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
timing requirements over recommended operating conditions (unless otherwise noted) (see
Figure 1)
SN54ALS161B
SN54ALS162B
SN54ALS163B
SN74ALS161B
SN74ALS163B UNIT
MIN MAX MIN MAX
fclock Clock frequency 22 40 MHz
t
Pulse duration
CLR high or low 20 12.5
ns
t
w
P
u
lse
d
u
ration
’ALS161B CLR low 20 15
ns
↑
A, B, C, D 50 15
↑
LOAD 20 15
↑
’ALS161B
ENP ENT
25 15
tsu Setup time, before CLK
↑
SN54ALS162B, ’ALS163B
ENP
,
ENT
20 15 ns
’ALS161B CLR inactive 10 10
SN54ALS162B
’
ALS163B
CLR low 20 15
SN54ALS162B
,
’ALS163B
CLR high 20 10
thHold time, all synchronous inputs after CLK↑0 0 ns
switching characteristics over recommended operating conditions (unless otherwise noted) (see
Figure 1)
PARAMETER
FROM TO SN54ALS161B SN74ALS161B
UNIT
PARAMETER
(INPUT) (OUTPUT) MIN MAX MIN MAX
UNIT
fmax 22 40 MHz
tPLH
CLK
RCO
5 34 5 20
ns
tPHL
CLK
RCO
5 27 5 20
ns
tPLH
CLK
Any Q
4 19 4 15
ns
tPHL
CLK
An
y
Q
6 25 6 20
ns
tPLH
ENT
RCO
3 18 3 13
ns
tPHL
ENT
RCO
3 17 3 13
ns
tPHL
CLR
Any Q 8 27 8 24
ns
t
PHL
CLR
RCO 11 32 11 23
ns
switching characteristics over recommended operating conditions (unless otherwise noted) (see
Figure 1)
PARAMETER FROM
(INPUT)
TO
(OUTPUT)
SN54ALS162B
SN54ALS163B SN74ALS163B UNIT
(INPUT)
(OUTPUT)
MIN MAX MIN MAX
fmax 22 40 MHz
tPLH
CLK
RCO
5 25 5 20
ns
tPHL
CLK
RCO
5 25 5 20
ns
tPLH
CLK
Any Q
4 18 4 15
ns
tPHL
CLK
An
y
Q
6 25 6 20
ns
tPLH
ENT
RCO
3 16 3 13
ns
tPHL
ENT
RCO
3 16 3 13
ns
SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163
SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163
SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS
SDAS276A – DECEMBER 1994 – REVISED JULY 2000
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions
SN54AS161
SN54AS163 SN74AS161
SN74AS163 UNIT
MIN NOM MAX MIN NOM MAX
VCC Supply voltage 4.5 5 5.5 4.5 5 5.5 V
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.8 0.8 V
IOH High-level output current –2 –2 mA
IOL Low-level output current 20 20 mA
TAOperating free-air temperature –55 125 0 70 °C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS SN54AS161
SN54AS163 SN74AS161
SN74AS163 UNIT
MIN TYP†MAX MIN TYP†MAX
VIK VCC = 4.5 V, II = –18 mA –1.2 –1.2 V
VOH VCC = 4.5 V to 5.5 V, IOH = –2 mA VCC –2 VCC –2 V
VOL VCC = 4.5 V, IOL = 20 mA 0.25 0.5 0.25 0.5 V
LOAD 0.3 0.3
IIENT VCC = 5.5 V, VI = 7 V 0.2 0.2 mA
All others 0.1 0.1
LOAD 60 60
IIH ENT VCC = 5.5 V, VI = 2.7 V 40 40 µA
All others 20 20
LOAD –1.5 –1.5
IIL ENT VCC = 5.5 V, VI = 0.4 V –1 –1 mA
All others –0.5 –0.5
IO‡VCC = 5.5 V, VO = 2.25 V –30 –112 –30 –112 mA
ICC VCC = 5.5 V 35 53 35 53 mA
†All typical values are at VCC = 5 V, TA = 25°C.
‡The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.
SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163
SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163
SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS
SDAS276A – DECEMBER 1994 – REVISED JULY 2000
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
timing requirements over recommended operating conditions (see Figure 1)
SN54AS161
SN54AS163 SN74AS161
SN74AS163 UNIT
MIN MAX MIN MAX
fclock Clock frequency 65 75 MHz
t
Pulse duration
CLR high or low 7.7 6.7
ns
t
w
P
u
lse
d
u
ration
’AS161 CLR low 10 8
ns
↑
A, B, C, D 10 8
↑
LOAD 10 8
t
Setu
p
time before CLK↑
ENP, ENT 10 8
ns
t
su
Set
u
p
time
,
before
CLK↑
’AS161 CLR inactive 10 8
ns
’
AS163
CLR low 14 12
’AS163
CLR high (inactive) 10 9
thHold time, all synchronous inputs after CLK↑2 0 ns
switching characteristics over recommended operating conditions (see Figure 1)
PARAMETER
FROM TO SN54AS161 SN74AS161
UNIT
PARAMETER
(INPUT) (OUTPUT) MIN MAX MIN MAX
UNIT
fmax 65* 75 MHz
tPLH
RCO (with LOAD high) 1 8.5 1 8
ns
t
PLH
RCO (with LOAD low) 3 17.5 3 16.5
ns
tPHL CLK RCO 2 14 2 12.5 ns
tPLH
1 7.5 1 7
ns
tPHL
y
2 14 2 13
ns
tPLH
1.5 10 1.5 9
ns
tPHL
1 9.5 1 8.5
ns
tPHL
Any Q 2 14 2 13
ns
t
PHL
RCO 2 14 2 12.5
ns
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
switching characteristics over recommended operating conditions (see Figure 1)
PARAMETER
FROM TO SN54AS163 SN74AS163
UNIT
PARAMETER
(INPUT) (OUTPUT) MIN MAX MIN MAX
UNIT
fmax 65* 75 MHz
tPLH
RCO (with LOAD high) 1 8.5 1 8
ns
t
PLH
RCO (with LOAD low) 3 17.5 3 16.5
ns
tPHL CLK RCO 2 14 2 12.5 ns
tPLH
1 7.5 1 7
ns
tPHL
y
2 14 2 13
ns
tPLH
1.5 10 1.5 9
ns
tPHL
1 9.5 1 8.5
ns
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163
SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163
SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS
SDAS276A – DECEMBER 1994 – REVISED JULY 2000
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
SERIES 54ALS/74ALS AND 54AS/74AS DEVICES
tPLZ
tPHL tPLH
0.3 V
tPZL
tPLH tPHL
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
From Output
Under Test Test
Point
S1
CL = 50 pF
(see Note A)
7 V
3 V
3 V
0 V
0 V
th
tsu
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Timing
Input
Data
Input
3 V
3 V
0 V
0 V
High-Level
Pulse
Low-Level
Pulse
tw
VOLTAGE WAVEFORMS
PULSE DURATIONS
Input
Out-of-Phase
Output
(see Note C)
3 V
3 V
0 V
0 V
VOL
VOH
VOH
VOL
Output
Control
(low-level
enabling)
W aveform 1
S1 Closed
(see Note B)
W aveform 2
S1 Open
(see Note B) ≈0 V
VOH
VOL
≈3 V
In-Phase
Output
0.3 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
VCC
Test
Point
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
LOAD CIRCUIT FOR
BI-STATE TOTEM-POLE OUTPUTS
From Output
Under Test Test
Point
CL = 50 pF
(see Note A) 500 Ω
500 Ω
500 Ω
500 Ω
1.5 V
1.5 V 1.5 V
1.5 V 1.5 V
1.5 V 1.5 V
tPHZ
tPZH
1.5 V 1.5 V
1.5 V
1.5 V
1.5 V 1.5 V
1.5 V 1.5 V
1.5 V 1.5 V
NOTES: A. CL includes probe and jig capacitance.
B. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
W aveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. When measuring propagation delay items of 3-state outputs, switch S1 is open.
D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%.
E. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163
SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163
SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS
SDAS276A – DECEMBER 1994 – REVISED JULY 2000
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
n-bit synchronous counters
This application demonstrates how the ripple-mode carry circuit (see Figure 2) and the carry look-ahead circuit
(see Figure 3) can be used to implement a high-speed n-bit counter. The SN54ALS162B counts in BCD. The
’ALS161B, ’AS161, ’ALS163B, and ’AS163 devices count in binary . When additional stages are added, the fmax
decreases in Figure 2, but remains unchanged in Figure 3.
Figure 2. Ripple-Mode Carry Circuit
LOAD
C5/T,3,4+
QA
QB
QC
QD
CLR
A
B
C
D
CTR
CT=0
M1
G3
G4
RCO
CLK
ENP
ENT 3CT=MAX
1,5D
LOAD
C5/T,3,4+
QA
QB
QC
QD
CLR
A
B
C
D
CTR
CT=0
M1
G3
G4
RCO
CLK
ENP
ENT 3CT=MAX
1,5D
LOAD
C5/T,3,4+
QA
QB
QC
QD
CLR
A
B
C
D
CTR
CT=0
M1
G3
G4
RCO
CLK
ENP
ENT 3CT=MAX
1,5D
LOAD
C5/T,3,4+
QA
QB
QC
QD
CLR
A
B
C
D
CTR
CT=0
M1
G3
G4
RCO
CLK
ENP
ENT 3CT=MAX
1,5D
LSB
To More Significant Stages
Clear (L)
Count (H)
Disable (L)
Load (L)
Count (H)
Disable (L)
Clock
fmax = 1/(CLK to RCO tPLH) + (ENT to RCO tPLH) (N – 2) + (ENT tsu)
Figure 3. Carry Look-Ahead Circuit
LOAD
C5/T,3,4+
QA
QB
QC
QD
CLR
A
B
C
D
CTR
CT=0
M1
G3
G4
RCO
CLK
ENP
ENT 3CT=MAX
1,5D
LOAD
C5/T,3,4+
QA
QB
QC
QD
CLR
A
B
C
D
CTR
CT=0
M1
G3
G4
RCO
CLK
ENP
ENT 3CT=MAX
1,5D
LOAD
C5/T,3,4+
QA
QB
QC
QD
CLR
A
B
C
D
CTR
CT=0
M1
G3
G4
RCO
CLK
ENP
ENT 3CT=MAX
1,5D
LOAD
C5/T,3,4+
QA
QB
QC
QD
CLR
A
B
C
D
CTR
CT=0
M1
G3
G4
RCO
CLK
ENP
ENT 3CT=MAX
1,5D
LSB
To More Significant Stages
Clear (L)
Count (H)
Disable (L)
Load (L)
Clock
fmax = 1/(CLK to RCO tPLH) + (ENP tsu)
PACKAGE OPTION ADDENDUM
www.ti.com 25-Jan-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
83022012A ACTIVE LCCC FK 20 1 TBD Call TI Call TI
8302201EA ACTIVE CDIP J 16 1 TBD Call TI Call TI
8302201FA ACTIVE CFP W 16 1 TBD Call TI Call TI
83022022A ACTIVE LCCC FK 20 1 TBD Call TI Call TI
8302202EA ACTIVE CDIP J 16 1 TBD Call TI Call TI
8302202FA OBSOLETE CFP W 16 TBD Call TI Call TI
JM38510/38001B2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
JM38510/38001BEA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type
JM38510/38002B2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
JM38510/38002BEA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type
M38510/38001B2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
M38510/38001BEA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type
M38510/38002B2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
M38510/38002BEA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type
SN54ALS161BJ ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type
SN54ALS163BJ ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type
SN54AS163J OBSOLETE CDIP J 16 TBD Call TI Call TI
SN74ALS161BD ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74ALS161BDE4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74ALS161BDG4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74ALS161BDR ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74ALS161BDRE4 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74ALS161BDRG4 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74ALS161BN ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
SN74ALS161BN3 OBSOLETE PDIP N 16 TBD Call TI Call TI
PACKAGE OPTION ADDENDUM
www.ti.com 25-Jan-2012
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
SN74ALS161BNE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
SN74ALS161BNSR ACTIVE SO NS 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74ALS161BNSRE4 ACTIVE SO NS 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74ALS161BNSRG4 ACTIVE SO NS 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74ALS163BD ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74ALS163BDE4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74ALS163BDG4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74ALS163BDR ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74ALS163BDRE4 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74ALS163BDRG4 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74ALS163BN ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
SN74ALS163BN3 OBSOLETE PDIP N 16 TBD Call TI Call TI
SN74ALS163BNE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
SN74ALS163BNSR ACTIVE SO NS 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74ALS163BNSRE4 ACTIVE SO NS 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74ALS163BNSRG4 ACTIVE SO NS 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AS161N ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
SN74AS161NE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
SN74AS161NSR ACTIVE SO NS 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AS161NSRE4 ACTIVE SO NS 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 25-Jan-2012
Addendum-Page 3
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
SN74AS161NSRG4 ACTIVE SO NS 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AS163D ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AS163DE4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AS163DG4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AS163N ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
SN74AS163NE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
SNJ54ALS161BFK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
SNJ54ALS161BJ ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type
SNJ54ALS161BW ACTIVE CFP W 16 1 TBD A42 N / A for Pkg Type
SNJ54ALS163BFK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
SNJ54ALS163BJ ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type
SNJ54AS161FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
SNJ54AS161J ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type
SNJ54AS163J OBSOLETE CDIP J 16 TBD Call TI Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
PACKAGE OPTION ADDENDUM
www.ti.com 25-Jan-2012
Addendum-Page 4
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN54ALS161B, SN54ALS163B, SN54AS161, SN54AS163, SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163 :
•Catalog: SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163
•Military: SN54ALS161B, SN54ALS163B, SN54AS161, SN54AS163
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
•Military - QML certified for Military and Defense Applications
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74ALS161BDR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
SN74ALS161BNSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
SN74ALS163BDR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
SN74ALS163BNSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
SN74AS161NSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74ALS161BDR SOIC D 16 2500 333.2 345.9 28.6
SN74ALS161BNSR SO NS 16 2000 367.0 367.0 38.0
SN74ALS163BDR SOIC D 16 2500 333.2 345.9 28.6
SN74ALS163BNSR SO NS 16 2000 367.0 367.0 38.0
SN74AS161NSR SO NS 16 2000 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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