A o MU Tal- mens joo M 7-1 ae) Features Configuration EPROMs for FLEX Devices Data Sheet Serial EPROM family for configuring FLEX devices Simple, easy-to-use 4-pin interface to FLEX devices Low current during configuration and near-zero standby current 5.0-V and 3.3-V operation Software design support with Alteras MAX+PLUS II development system for 486- and Pentium-based PCs, and Sun SPARCstation, HP 9000 Series 700, and IBM RISC System/6000 workstations Programming support with Alteras Master Programming Unit (MPU) and programming hardware from Data I/O and other manufacturers Available in compact, one-time-programmable (OTP) plastic packages (see Figure 1) - 8-pin plastic dual in-line package (PDIP) - 20-pin plastic J-lead chip carrier package (PLCC) 32-pin plastic thin quad flat pack (TOFP) Figure 1. Configuration EPROM Package Pin-Out Diagrams Package outlines not drawn to scale. vec vec nCASC GND 8-Pin PDIP EPC1 EPC1V EPC1064 EPC1064V EPC1213 Altera Corporation A-DS-EPROM-05 Eg az D DCLK N.C, N.C. N.C. 489 VCC nc. a4 N.C. Nc. 5 [I N.C. N.cC.c6 N.C. OE C7 OE DNC. Nc. ca 17D N.C 9 WW rouovoooo g2322 28232232 2 20-Pin PLCC 32-Pin TQFP EPC1 EPC1064 EPC1V EPC1064V EPC 1064 EPC1064V EPC1213 393 qQ i=] po | = ta) i= = set] ao a)Configuration EPROMs for FLEX Devices Data Sheet Functional In SRAM-based devices, configuration data must be reloaded each time age the system initializes, or whenever new configuration data is needed. Description Alteras serial Configuration EPROMs store configuration data for SRAM-based Altera FLEX devices. Table 1 lists the Configuration EPROMs provided by Altera. Table 1. Configuration EPROMs Device Description EPC1 1,046,496 x 1 bit device with 5.0-V operation EPC1V 1,046,496 x 1 bit device with 3.3-V operation EPC 1064 65,536 x 1 bit device with 5.0-V operation EPC1064V 65,536 x 1 bit device with 3.3-V operation EPC1213 212,942 x 1 bit device with 5.0-V operation Table 2 shows the appropriate Configuration EPROM for each FLEX device. Table 2. Appropriate Configuration EPROM for Each FLEX Device FLEX Device Configuration EPROM EPF10K10 EPC1 EPF10K20 EPC1 EPF10K30 EPC1 EPF10K40 EPC1 EPF10K50 EPC1 EPF10K70 EPC1 EPF10K100 Two EPC1 devices EPF8282A EPC1 or EPC1064 EPF8282AV EPC1V or EPC1064V EPF8452A EPC1 or EPC1064 EPF8636A EPC1 or EPC1213 EPF8820A EPC1 or EPC 1213 EPF81188A EPC1 or EPC1213 EPF81500A EPC1 or two EPC1213 devices 394 Altera CorporationConfiguration EPROMs for FLEX Devices Data Sheet Figure 2 shows block diagrams of the Configuration EPROM devices. Figure 2. Configuration EPROM Block Diagram EPC1 ; Note (1) ~ DCLK Oscillator CLK Address A L- | ENA Counter nRESET Oscillator Control Address Decode > Logic ncS [> rT) TT p> nCASC ) v EPROM Array { DATA Shift Register DATA EPC1064 & EPC1213 DCLK [> CLK Address r-} ENA Counter nRESET Address Decode > Logic ncs [ -> nCASC OE EPROM Array doar p| _ Shift DATA Register Note: (1) This output enable controls the operation of the DCLK pin on the EPC1 device. The operation of the DCLK pin is determined by the configuration mode programmed into the EPC1 device. Device The control signals for Configuration EPROMsnCs, OE, and DCLK . . interface directly to the FLEX device control signals. All FLEX devices can Configuration control the entire configuration process and retrieve data from the Configuration EPROM without requiring an external intelligent controller. Altera Corporation 395 Qo [=] ] al a 4 oad 1-8) Q aConfiguration EPROMs for FLEX Devices Data Sheet 396 The configuration EPROM devices OE and nCS pins control the tri-state buffer on the DATA output pin and enable the address counter (and the oscillator in the EPC1 device). When OE is driven low, the Configuration EPROM device resets the address counter and tri-states its DATA pin. For the EPC1, the device determines its operation mode and whether it should use FLEX 10K or FLEX 8000 protocols when OE is driven high again. The ncs pin controls timing. If nCs is held high after the OE reset pulse, the counter is disabled and the DATA output pin is tri-stated. When ncs is driven low, the counter and the DATA output pin are enabled. When OE is driven low again, the address counter is reset and the DATA output pin is tri-stated, regardless of the state of ncs. When the Configuration EPROM has driven out all of its data and ncASC is driven low, the device tri-states the DATA pin to avoid contention with other Configuration EPROMs. Upon power-up, the address counter is automatically reset. FLEX 10K Device Configuration FLEX 10K devices can be configured with the EPC1 Configuration EPROM. The EPC1 device stores configuration data in its EPROM array and clocks the data out serially with its internal oscillator. The OE, ncs, and DCLK pins supply the control signals for the address counter and the output tri-state buffer. The EPC1 device sends a serial bitstream of configuration data to its DATA pin, which is routed to the DATAO input pin on the FLEX 10K device. When configuration data for a FLEX 10K device exceeds the capacity of a single EPC1 device, multiple EPC1 devices can be linked together serially. When multiple EPC1 devices are required, the nCASC and nCs pins provide handshaking between the EPC] devices. The position of an EPC1 device in a chain determines its operation. The first EPC1 device in the Configuration EPROM chain is powered up or reset with ncs low and is configured for FLEX 10K protocol. The first EPC1 device supplies all clock pulses to one or more FLEX 10K devices and to any downstream EPC] devices during configuration. The first EPC1 device also provides the first stream of data to the FLEX 10K devices during multi-device configuration. Once this EPC] device finishes sending configuration data, it drives its nCASC pin low, which drives the nCs pin of the next EPC1 device in the chain low, activating the next EPC1 device. The first EPC1 device clocks all subsequent EPC1 devices until configuration is complete. Once all configuration data is transferred and nCs is driven high by CONF_DONE on the FLEX 10K device, the first EPC1 device clocks 16 additional cycles to initialize the FLEX 10K device, and then goes into Zero-power (idle) state. If nCs is driven high before all configuration data is transferred, the nSTATUS pin is pulled low, indicating a configuration error. Altera CorporationConfiguration EPROMs for FLEX Devices Data Sheet All downstream EPC1 devices in the Configuration EPROM chain are powered up or reset when nCS goes high and the device is configured for FLEX 10K protocol. Downstream EPC1 devices are clocked by the first EPC1 device. Each downstream EPC1 supplies configuration data after its nCs pin is driven low by the previous EPC1 devices nCASC pin. This EPC1 device then activates the next EPC1 device in the configuration chain. An inactive downstream EPC] device waits in a zero-power (idle) state. Table 3 describes EPC1 and EPC1V pin functions during FLEX 10K device configuration. Table 3. EPC1 & EPC1V Pin Funetions during FLEX 10K Device Configuration Pin Name Pin Number 8-Pin PDIP | 20-Pin PLCC Pin Type Description DATA 2 Output Seriat data output. DCLK 2 4 vO Clock output or clock input. Rising edges on DCLK increment the internal address counter and present the next bit of data to the DATA pin. The counter is incremented only if the OF input is held high, the ncs input is held low, and all configuration data has not been transferred to the target device (otherwise, in FLEX 10K master mode, the DCLK pin drives low.) OE Input Output enable (active high) and reset (active low). A low logic level resets the address counter. A high logic level enables DATA and permits the address counter to count. In FLEX 10K mode, if this pin is low (reset), the internal oscillator becomes inactive and DCLK drives low. ncs Input Chip select input (active low). A low input allows DCLK to increment the address counter and enables DATA to drive out. If the EPC1 is reset with ncs low, the device initializes as the first device in a daisy-chain. If the EPC1 is reset with ncs high, the device initializes as a subsequent EPC1 device in the chain. nCASC Output Cascade select output (active low). This output goes low when the address counter has reached its maximum value. In a daisy-chain of EPC1 devices, the ncasc pin of one device is usually connected to the ncs input pin of the next device in the chain, which permits DCLK to clock data from the next EPC1 device in the chain. GND Ground A 0.2-uF decoupling capacitor must be placed between the VCC and GND pins. vec 7,8 18, 20 Power Power pin. Altera Corporation 397 a i ms on: es ao = = o 7d =] aConfiguration EPROMs for FLEX Devices Data Sheet 398 FLEX 8000 Device Configuration FLEX 8000 devices have internal oscillators that can provide a DCLK signal to the Configuration EPROM. The Configuration EPROM device sends configuration data out as a serial bitstream on the DATA output pin. This data is routed into the FLEX 8000 device via the DATAO input pin. The nCASC and nCs pins provide handshaking between multiple Configuration EPROMs, allowing several linked Configuration EPROM devices to serially configure multiple FLEX devices. FLEX 8000 devices can be configured with the EPC1, EPC1064, or EPC1213 Configuration EPROMs. Configuration with EPC1 The EPC1 can replace the EPC1064 and EPC1213 Configuration EPROMs, which are also used to configure FLEX 8000 devices. EPC1 devices automatically emulate the EPC1064 or EPC1213 when it is programmed with the appropriate Programmer Object File (.pof). When the EPC] device is programmed with a POF, the FLEX 8000 device drives the EPC1 devices OE pin high and clocks the EPC1 device. One EPC] device can store more configuration data than either the EPC1064 or EPC1213 device. Therefore designers can use one type of Configuration EPROM, the EPC1, for all FLEX devices. Configuration with EPC 1064 & EPC1213 FLEX 8000 device configuration with EPC1064 and EPC1213 Configuration EPROMs is described under Device Configuration on page 395. Table 4 describes the pin functions of the EPC1, EPC1213, and EPC1064 during FLEX 8000 device configuration. Aitera CorporationConfiguration EPROMs for FLEX Devices Data Sheet Table 4. Configuration EPROM Pin Functions during FLEX 8000 Device Configuration Pin Pin Number Pin Description Name : : : Type 8-Pin | 20-Pin | 32-Pin | ? PDIP PLCC TOFP Note (7) DATA 1 2 31 Output | Serial data output. DCLK 2 4 2 Input Clock input. Rising edges on DCLK increment the internal address counter and cause the next bit of data to be presented on DATA. The counter is incremented only if the OE input is held high and the ncs input is held low. OE 3 8 7 Input Output enable (active high) and reset (active low). A low logic level resets the address counter. A high logic level enables DATA and permits the address counter to count. ncs 4 9 10 Input Chip-select input (active low). A low input allows DCLK to increment the address counter and enables DATA. nCASC 6 12 15 Output | Cascade-select output (active low). This output goes low when the address counter has reached its maximum value. The ncASc output is usually connected to the ncs input of the next Configuration EPROM in a daisy-chain, so the next DCLK clocks data out of the next Configuration EPROM. GND 5 10 12 Ground | A 0.2-uF decoupling capacitor must be placed between the vcc and GND pins. vec 7,8 18, 20 23,27 | Power | Power pin. Note: (1) EPC1064 and EPC1064V devices only. Active serial (AS) and multi-device sequential active serial (MD-SAS) configure them, see the following documents: configuration schemes use an EPC1 Configuration EPROM as a data o source for FLEX 8000 devices. = -@ = <2 For information on FLEX 10K and FLEX 8000 devices and how to RY = =a FLEX 10K Embedded Programmable Logic Family Data Sheet FLEX 8000 Programmable Logic Device Family Data Sheet Application Note 59 (Configuring FLEX 10K Devices) Application Note 33 (Configuring FLEX 8000 Devices) Application Note 38 (Configuring Multiple FLEX 8000 Devices) Altera Corporation 399Configuration EPROMs for FLEX Devices Data Sheet MAX+PLUS II Support 400 The MAX+PLUS I development system provides programming support for Altera Configuration EPROMs. The MAX+PLUS IT software automatically generates a Programmer Object File (.pof) for every Configuration EPROM in a project. In a multi-device project, MAX+PLUS II can combine the programming files for multiple FLEX devices into one or more Configuration EPROMs. MAX+PLUS II allows you to select the appropriate Configuration EPROM to most efficiently store the data for each FLEX device. The POF includes a preamble, cyclic redundancy code (CRC), and synchronization data that allow it to be used ina serial bitstream. The POF is programmed into the Configuration EPROM with MAX+PLUS II and a Configuration EPROM programming adapter. Many programming hardware manufacturers, including Data 1/O, support programming of Configuration EPROMs. For more information on programming hardware, see the Altera Programming Hardware Data Sheet and Programming Hardware Manufacturers in this data book. Altera CorporationConfiguration EPROMs for FLEX Devices Data Sheet Absolute Maximum Ratings _ Note (1) Symbol Parameter Conditions Min Max | Unit Voc Supply voltage With respect to GND -2.0 7.0 Vv V, DC input voltage Note (2) -2.0 7.0 Vv Imax DC Vec or GND current 20 mA lout DC output current, per pin -25 25 mA Po Power dissipation 100 mw Tste Storage temperature No bias 65 150 C Tams Ambient temperature Under bias -65 135 C Ty Junction temperature Under bias 135 C Recommended Operating Conditions Symboi Parameter Conditions Min Max | Unit Voc Supply voltage for 5.0-V device 4.76 5.25 Vv Supply voltage for 3.3-V device 3.0 3.6 v vi Input voltage With respect to GND, Note (2) 0 Vcc Vv Vo Output voltage 0 Voc v Ty Operating temperature For commercial use 0 70 c Ta Operating temperature For industrial use 40 85 C tp Input rise time 20 ns tg Input fall time 20 ns DC Operating Conditions _ Notes (3), (4) Symbol Parameter Conditions Min Max | Unit Vin High-level input voltage 2.0 Veo + 0.3) V Vit Low-level input voltage -0.3 0.8 Vv Vou 5.0-V device high-level TTL output loy = 4 mA DC, Note (5) 2.4 Vv Oo voltage = 3.3-V device high-level TTL output loy = -0.1 mA DC, Note (5) Vec - 0.2 7 voltage = Vor Low-level output voltage lo = 4 mA OC, Note (5) 0.45 v = I Input leakage current Vi = Voc or GND -10 10 pA oa loz Tri-state output off-state current Vo = Vec or GND 10 10 pA EPC1064, EPC1064V & EPC1213 Device Ipc Supply Current Values _- Note (6) Symbol Parameter Conditions Min Typ Max | Unit loco Voc supply current (standby) 100 HA lees Vec supply current DCLK = 6 MHz 10 mA (during configuration) Altera Corporation 401Configuration EPROMs for FLEX Devices Data Sheet EPC1 & EPC1V Device Iec Supply Current Values _Note (6) Symbol Parameter Conditions Min Typ Max | Unit loco Vcc supply current (standby) 50 100 pA lees Vcc supply current (during configuration) | DCLK = 10 MHz 10 50 mA Capacitance __Note (7) Symbol Parameter Conditions Min Max | Unit Cin Input pin capacitance Vin = OV, f = 1.0 MHz 10 pF Cout Output pin capacitance Vour = 0 V, f= 1.0 MHz 10 pF FLEX 10K Device Configuration Timing Parameters Using EPC1 _Note (6) Symbol Parameter Conditions Min Typ Max | Unit ter OE high to first clock delay 200 ns toezx OE high to data output enabled 160 ns tco DCLK to data out delay 30 ns tun DCLK high time in master mode 30 50 ns tuct DCLK low time in master mode 30 50 ns tscn DCLK high time in slave mode 30 ns tser DCLK low time in slave mode 30 ns teasc CLK rising edge to ncAsc 20 ns teca nCs to nCASC cascade delay 10 ns fepoe CLK to data enable/disable 30 ns toec OE low to CLK disable delay 45 ns ton DATA hold from CLK rising edge 0 10 ns twrcas | OE low (reset) to ncasc delay 25 ns turr OE low time (reset) minimum 100 ns 402 Altera CorporationConfiguration EPROMs for FLEX Devices Data Sheet FLEX 8000 Device Configuration Timing Parameters Using EPC1, EPC1V, EPC1064, EPC1064V & EPC1213 EPC1064 EPC1 EPC1V EPCI064V | Fbc1213 | Note (6) | Note (6) Symbol Parameter Conditions| Min | Max| Min | Max) Min | Max) Min | Max} Unit toezx OE high to DATA output enabled 75 50 50 ns teszx ncs low to DATA output enabled 75 50 50 ns tesxz ncs high to DATA output disabled 75 50 50 ns tess ncs low setup time to first DCLK rising 150 100 50 ns edge tosn ncCs low hold time after DCLK rising 0 0 0 ns edge tosu Data setup time before rising edge on 75 50 50 ns DCLK, Note (8) tou Data hold time after rising edge on 0 0 0 ns DCLK, Note (8) leo DCLK to DATA out delay, Note (6) 100 75 76 ns tex Clock period 240 160 100 ns fox Clock frequency 4 6 10 MHz tet DCLK low time 120 80 50 ns ton DCLK high time 120 80 50 ns tyz OE low or ncs high to DATA output 75 50 50 ns disabled toew OE pulse width to guarantee counter 150 100 100 ns reset tcasc Last DCLK + 1 to nCASc low delay 90 60 50 ns tonxz Last DCLK + 1 to DATA tri-state delay 75 50 50 ns teeour | ncs high to ncasc high delay 150 100 100 ns Notes to tables: (1) See Operating Requirements for Altera Devices Data Sheet in this data book. (2) Minimum DC input is -0.3 V. During transitions, the inputs may undershoot to 2.0 V or overshoot to 7.0 V for periods shorter than 20 ns under no-load conditions. (3) Typical values are for Ta = 25 C and Voc = 5.0 V. (4) Operating conditions: Voc = 5.0 V 5%, T 4 = 0 C to 70 C for commercial use. Vec = 5.0 V + 10%, Ta = -40 C to 85 C for industrial use. (5) The Ip} parameter refers to high-level TTL output current; the |p, parameter refers to low-level TTL output current. (6) Parameters for EPC1 devices are preliminary. Contact Altera Applications for information on EPC1V devices. (7) Capacitance is sample-tested only. (8) This parameter applies to FLEX 8000 devices. oa ao =a Pomel ro] Loy = tas] a | Altera Corporation 403