TLC0820AC, TLC0820AI
Advanced LinCMOSHIGH-SPEED 8-BIT ANALOG-TO-DIGITAL
CONVERTERS USING MODIFIED FLASH TECHNIQUES
SLAS064A – SEPTEMBER 1986 – REVISED JUNE 1994
2–1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Advanced LinCMOS Silicon-Gate
Technology
D
8-Bit Resolution
D
Differential Reference Inputs
D
Parallel Microprocessor Interface
D
Conversion and Access Time Over
Temperature Range
Read Mode...2.5 µs Max
D
No External Clock or Oscillator
Components Required
D
On-Chip Track and Hold
D
Single 5-V Supply
D
TLC0820A Is Direct Replacement for
National Semiconductor ADC0820C/CC and
Analog Devices AD7820K/B/T
description
The TLC0820AC and the TLC0820AI are
Advanced LinCMOS 8-bit analog-to-digital
converters each consisting of two 4-bit flash
converters, a 4-bit digital-to-analog converter, a
summing (error) amplifier, control logic, and a
result latch circuit. The modified flash technique
allows low-power integrated circuitry to complete
an 8-bit conversion in 1.18 µs over temperature.
The on-chip track-and-hold circuit has a 100-ns
sample window and allows these devices to
convert continuous analog signals having slew
rates of up to 100 mV/µs without external
sampling components. TTL-compatible 3-state
output drivers and two modes of operation allow
interfacing to a variety of microprocessors. Detailed information on interfacing to most popular microprocessors
is readily available from the factory.
AVAILABLE OPTIONS
TOTAL
PACKAGE
TA
TOTAL
UNADJUSTED
ERROR SSOP
(DB)
PLASTIC
SMALL OUTLINE
(DW)
PLASTIC
CHIP CARRIER
(FN)
PLASTIC DIP
(N)
0°C to 70°C±1 LSB TLC0820ACDB TLC0820ACDW TLC0820ACFN TLC0820ACN
–40°C to 85°C±1 LSB — TLC0820AIDW TLC0820AIFN TLC0820AIN
Copyright 1994, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
ANLG IN
(LSB) D0
D1
D2
D3
WR/RDY
MODE
RD
INT
GND
VCC
NC
OFLW
D7 (MSB)
D6
D5
D4
CS
REF+
REF–
DB, DW, OR N PACKAGE
(TOP VIEW)
3 2 1 20 19
910111213
4
5
6
7
8
18
17
16
15
14
OFLW
D7 (MSB)
D6
D5
D4
D2
D3
WR/RDY
MODE
RD
FN PACKAGE
(TOP VIEW)
D1
D0 (LSB)
ANLG IN
REF+
CS V
NC
INT
GND
REF –
NC–No internal connection
CC
Advanced LinCMOS is a trademark of Texas Instruments Incorporated.
TLC0820AC, TLC0820AI
Advanced LinCMOSHIGH-SPEED 8-BIT ANALOG-TO-DIGITAL
CONVERTERS USING MODIFIED FLASH TECHNIQUES
SLAS064A – SEPTEMBER 1986 – REVISED JUNE 1994
2–2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagram
4
4
44
RD 8
CS 13
WR/RDY 6
MODE 7
ANLG IN 1
11
REF–
12
REF+
+1
–1
4-Bit Flash
Analog-to-Digital
Converter
(4 MSBs)
INT
9
Timing
and
Control
Output
Latch
and
3-State
Buffers
Digital
Outputs
D7 (MSB)
D6
D5
D4
D3
D2
D1
D0 (LSB)
OFLW
17
16
15
14
5
4
3
2
18
4-Bit
Digital-to-Analog
Converter
4-Bit Flash
Analog-to-Digital
Converter
(4 LSBs)
Summing
Amplifier
TLC0820AC, TLC0820AI
Advanced LinCMOSHIGH-SPEED 8-BIT ANALOG-TO-DIGITAL
CONVERTERS USING MODIFIED FLASH TECHNIQUES
SLAS064A – SEPTEMBER 1986 – REVISED JUNE 1994
2–3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME NO.
I/O
DESCRIPTION
ANLG IN 1 I Analog input
CS 13 I Chip select. CS must be low in order for RD or WR to be recognized by the ADC.
D0 2 O Digital, 3-state output data, bit 1 (LSB)
D1 3 O Digital, 3-state output data, bit 2
D2 4 O Digital, 3-state output data, bit 3
D3 5 O Digital, 3-state output data, bit 4
D4 14 O Digital, 3-state output data, bit 5
D5 15 O Digital, 3-state output data, bit 6
D6 16 O Digital, 3-state output data, bit 7
D7 17 O Digital, 3-state output data, bit 8 (MSB)
GND 10 Ground
INT 9 O Interrupt. In the write-read mode, the interrupt output (INT) going low indicates that the internal count-down delay
time, td(int), is complete and the data result is in the output latch. The delay time td(int) is typically 800 ns starting
after the rising edge of WR (see operating characteristics and Figure 3). If RD goes low prior to the end of td(int),
INT goes low at the end of td(RIL) and the conversion results are available sooner (see Figure 2). INT is reset by
the rising edge of either RD or CS.
MODE 7 I Mode select. MODE is internally tied to GND through a 50-µA current source, which acts like a pulldown resistor .
When MODE is low, the read mode is selected. When MODE is high, the write-read mode is selected.
NC 19 No internal connection
OFLW 18 O Overflow . Normally OFL W is a logical high. However , if the analog input is higher than V ref+, OFL W will be low at
the end of conversion. It can be used to cascade two or more devices to improve resolution (9 or 10 bits).
RD 8 I Read. In the write-read mode with CS low, the 3-state data outputs D0 through D7 are activated when RD goes
low. RD can also be used to increase the conversion speed by reading data prior to the end of the internal
count-down delay time. As a result, the data transferred to the output latch is latched after the falling edge of RD.
In the read mode with CS low , the conversion starts with RD going low . RD also enables the 3-state data outputs
on completion of the conversion. RDY going into the high-impedance state and INT going low indicate completion
of the conversion.
REF– 11 I Reference voltage. REF– is placed on the bottom of the resistor ladder.
REF+ 12 I Reference voltage. REF+ is placed on the top of the resistor ladder.
VCC 20 Power supply voltage
WR/RDY 6 I/O Write ready. In the write-read mode with CS low, the conversion is started on the falling edge of the WR input signal.
The result of the conversion is strobed into the output latch after the internal count-down delay time, td(int), provided
that the RD input does not go low prior to this time. The delay time td(int) is approximately 800 ns. In the read mode,
RDY (an open-drain output) goes low after the falling edge of CS and goes into the high-impedance state when
the conversion is strobed into the output latch. It is used to simplify the interface to a microprocessor system.
TLC0820AC, TLC0820AI
Advanced LinCMOSHIGH-SPEED 8-BIT ANALOG-TO-DIGITAL
CONVERTERS USING MODIFIED FLASH TECHNIQUES
SLAS064A – SEPTEMBER 1986 – REVISED JUNE 1994
2–4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VCC (see Note 1) 10 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, all inputs (see Note 1) –0.2 V to VCC+0.2 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, all outputs (see Note 1) –0.2 V to VCC+0.2 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range: TLC0820AC 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TLC0820AI –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Case temperature for 10 seconds: FN package 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: DB, DW or N package 260°C. . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTE 1: All voltages are with respect to network GND.
recommended operating conditions
MIN NOM MAX UNIT
Supply voltage, VCC 4.5 5 8 V
Analog input voltage –0.1 VCC+0.1 V
Positive reference voltage, V ref+ Vref– VCC V
Negative reference voltage, V ref– GND Vref+ V
High level in
p
ut voltage VIH
VCC =475Vto525V
CS, WR/RDY, RD 2
V
High
-
le
v
el
inp
u
t
v
oltage
,
V
IH
V
CC =
4
.
75
V
to
5
.
25
V
MODE 3.5
V
Low level in
p
ut voltage VIL
VCC =475Vto525V
CS, WR/RDY, RD 0.8
V
Lo
w-
le
v
el
inp
u
t
v
oltage
,
V
IL
V
CC =
4
.
75
V
to
5
.
25
V
MODE 1.5
V
Pulse duration, write in write-read mode, tw(W) (see Figures 2, 3, and 4) 0.5 50 µs
O
p
erating free air tem
p
erature TA
TLC0820AC 0 70 °
C
Operating
free
-
air
temperat
u
re
,
T
ATLC0820AI –40 85
°C
TLC0820AC, TLC0820AI
Advanced LinCMOSHIGH-SPEED 8-BIT ANALOG-TO-DIGITAL
CONVERTERS USING MODIFIED FLASH TECHNIQUES
SLAS064A – SEPTEMBER 1986 – REVISED JUNE 1994
2–5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics at specified operating free-air temperature, VCC = 5 V (unless otherwise
noted)
PARAMETER TEST CONDITIONS TA†MIN TYP MAX UNIT
V
Hi h l l t t lt
D
0
–D7
,
INT
,
o
r
VCC = 4.75 V,
IOH = –360 µAFull range 2.4
VOH High-level output voltage
D0 D7
,
INT
,
or
OFLW V
CC
= 4.75 V, Full range 4.5 V
CC ,
IOH = –10 µA25°C 4.6
VOL
Low level out
p
ut voltage
D0–D7
,
OFLW
,
INT
,
V
CC
= 5.25 V, Full range 0.4
V
OL
Lo
w-
le
v
el
o
u
tp
u
t
v
oltage
D0 D7,
OFLW,
INT,
or WR/RDY
CC ,
IOL = 1.6 mA 25°C 0.34
CS or RD Full range 0.005 1
WR/RDY
Full range 3
IIH High-level input current
WR/RDY
VIH = 5 V 25°C 0.1 0.3 µA
MODE
Full range 200
MODE
25°C 50 170
IIL Low-level input current CS, WR/RDY, RD,
or MODE VIL = 0 Full range –0.005 –1 µA
VO=5V
Full range 3
IOZ
Off-state (high-impedance-state)
D0 D7 or WR/RDY
V
O =
5
V
25°C 0.1 0.3
I
OZ
(g )
output current
D0
–
D7
or
WR/RDY
VO=0
Full range –3 µ
V
O =
0
25°C –0.1 –0.3
CS at 5 V
VI=5V
Full range 3
II
Analog in
p
ut current
CS
at
5
V
,
V
I =
5
V
25°C 0.3
I
I
Analog
inp
u
t
c
u
rrent
CS at 5 V
VI=0
Full range –3 µ
CS
at
5
V
,
V
I =
0
25°C –0.3
D0–D7
,
OFLW
,
INT
,
VO=5V
Full range 7
D0 D7,
OFLW,
INT,
or WR/RDY
V
O =
5
V
25°C 8.4 14
IOS
Short circuit out
p
ut current
D0 D7 or OFLW
Full range –6
I
OS
Short
-
circ
u
it
o
u
tp
u
t
c
u
rrent
D0
–
D7
or
OFLW
VO=0
25°C –7.2 –12
INT
V
O =
0
Full range –4.5
INT
25°C – 5.3 –9
Rf
Reference resistance
Full range 1.25 6
R
ref
Reference
resistance
25°C 1.4 2.3 5.3
ICC
Su
pp
ly current
CS
,
WR/RDY
,
and Full range 15
I
CC
S
u
ppl
y
c
u
rrent
CS,
WR/RDY,
and
RD at 0 V 25°C 7.5 13
Ci
In
p
ut ca
p
acitance
D0–D7
Full range
5p
C
i
Inp
u
t
capacitance
ANLG IN
F
u
ll
range
45
CoOutput capacitance D0–D7 Full range 5 pF
†Full range is as specified in recommended operating conditions.
TLC0820AC, TLC0820AI
Advanced LinCMOSHIGH-SPEED 8-BIT ANALOG-TO-DIGITAL
CONVERTERS USING MODIFIED FLASH TECHNIQUES
SLAS064A – SEPTEMBER 1986 – REVISED JUNE 1994
2–6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
operating characteristics, VCC = 5 V , Vref+ = 5 V , Vref– = 0, tr = tf = 20 ns, T A = 25°C (unless otherwise
noted)
PARAMETER TEST CONDITIONS†MIN TYP MAX UNIT
kSVS Supply-voltage sensitivity VCC = 5 V ± 5%, TA = MIN to MAX ±1/16 ±1/4 LSB
Total unadjusted error‡MODE at 0 V, TA = MIN to MAX 1 LSB
tconv(R) Conversion time, read mode MODE at 0 V, See Figure 1 1.6 2.5 µs
ta(R) Access time, RD↓to data valid MODE at 0 V, See Figure 1 tconv(R)
+20 tconv(R)
+50 ns
t(R1)
Access time RD↓to data valid
MODE at 5 V,
td(WR) <t
d(i )
CL = 15 pF 190 280
ns
t
a(R1)
A
ccess
ti
me,
RD↓t
o
d
a
t
a va
lid
t
d(WR) <
t
d(int),
See Figure 2 CL = 100 pF 210 320
ns
t(R2)
Access time RD↓to data valid
MODE at 5 V,
td(WR) >t
d(i )
CL = 15 pF 70 120
ns
t
a(R2)
A
ccess
ti
me,
RD↓t
o
d
a
t
a va
lid
t
d(WR) >
t
d(int),
See Figure 3 CL = 100 pF 90 150
ns
ta(INT) Access time, INT↓to data valid MODE at 5 V, See Figure 4 20 50 ns
tdis
Disable time RD↑to data valid
RL = 1 kΩ, CL = 10 pF,
70
95
ns
tdi
s
Disable
time
,
RD↑to
data
valid
See Figures 1, 2, 3, and 5
70
95
ns
td(int)
Delay time WR/RDY↑to INT↓
MODE at 5 V, CL = 50 pF,
800
1300
ns
td(i
n
t)
Delay
time
,
WR/RDY↑
to
INT↓
See Figures 2, 3, and 4
800
1300
ns
td(NC) Delay time, to next conversion See Figures 1, 2, 3, and 4 500 ns
td(WR) Delay time, WR/RDY↑ to RD↓ in
write-read mode See Figure 2 0.4 µs
td(RDY)
Delay time CS↓to WR/RDY↓
MODE at 0 V, CL = 50 pF,
50
100
ns
td(RDY)
Delay
time
,
CS↓
to
WR/RDY↓
See Figure 1
50
100
ns
td(RIH) Delay time, RD↑ to INT↑CL = 50 pF, See Figures 1, 2, and 3 125 225 ns
td(RIL)
Delay time RD↓to INT↓
MODE at 5 V, td(WR) < td(int),
200
290
ns
td(RIL)
Delay
time
,
RD↓
to
INT↓
See Figure 2
200
290
ns
td(WIH)
Delay time WR/RDY↑to INT↑
MODE at 5 V, CL = 50 pF,
175
270
ns
td(WIH)
Delay
time
,
WR/RDY↑
to
INT↑
See Figure 4
175
270
ns
Slew-rate tracking 0.1 V/µs
†For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
‡Total unadjusted error includes offset, full-scale, and linearity errors.
TLC0820AC, TLC0820AI
Advanced LinCMOSHIGH-SPEED 8-BIT ANALOG-TO-DIGITAL
CONVERTERS USING MODIFIED FLASH TECHNIQUES
SLAS064A – SEPTEMBER 1986 – REVISED JUNE 1994
2–7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
CS
RD
WR/RDY
INT
D0–D7
tconv(R)
ta(R) tdis
td(RDY) td(RIH)
td(NC)
With External Pullup
50%
50% 50% 50%
50%
50% 50%
90%
10%
90%
10%
Figure 1. Read-Mode Waveforms (MODE Low)
D0–D7
INT
WR/RDY
RD
CS
tdis
ta(R1)
td(RIH)
td(int)
tw(W)
td(WR) td(NC)
td(RIL)
50%50% 50%
50% 50%
50% 50%
90%
10%
90%
10%
Figure 2. Write-Read-Mode Waveforms
[MODE High and td
(
WR
)
< td
(
int
)
]
tdi
s
ta(R2)
td(RI
H
td(NC)
td(int)
td(WR)
tw(W)
CS
RD
WR/RDY
INT
D0–D7
50%
50%
50% 50%
50% 50%
90%
10%
90%
10%
Figure 3. Write-Read-Mode Waveforms
[MODE High and td
(
WR
)
> td
(
int
)
]
TLC0820AC, TLC0820AI
Advanced LinCMOSHIGH-SPEED 8-BIT ANALOG-TO-DIGITAL
CONVERTERS USING MODIFIED FLASH TECHNIQUES
SLAS064A – SEPTEMBER 1986 – REVISED JUNE 1994
2–8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
Data Valid
ta(INT)
td(int)
td(NC)
td(WIH)
tw(W)
CS Low
RD Low
WR/RDY
INT
D0– D7
50%50% 50%
50% 50%
90%
10%
Figure 4. Write-Read-Mode Waveforms
(Stand-Alone Operation, MODE High, and RD Low)
RD
Data
Output
Dn = D0...D7
RD
tr = 20 ns
Data
Outputs 10%
tdis
10%
50%
90%
CL = 10 pF
tr
VOL
VCC
GND
VCC
VCC
TLC0820
Input
GND
Dn
RD
CS
CL
1 kΩ
Data
Outputs
tr = 20 ns
VCC
GND
VOH
GND
90%
tdis
10%
50%
90%
tr
CL = 10 pF
Input
TLC0820
GND
CS
RD Dn
CL1 kΩ
Data
Output
VCC
TEST CIRCUIT
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMSTEST CIRCUIT
Figure 5. Test Circuit and Voltage Waveforms
TLC0820AC, TLC0820AI
Advanced LinCMOSHIGH-SPEED 8-BIT ANALOG-TO-DIGITAL
CONVERTERS USING MODIFIED FLASH TECHNIQUES
SLAS064A – SEPTEMBER 1986 – REVISED JUNE 1994
2–9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
The TLC0820AC and TLC0820AI each employ a combination of sampled-data comparator techniques and flash
techniques common to many high-speed converters. Two 4-bit flash analog-to-digital conversions are used to give
a full 8-bit output.
The recommended analog input voltage range for conversion is –0.1 V to VCC + 0.1 V. Analog input signals that are
less than Vref– + 1/2 LSB or greater than Vref+ – 1/2 LSB convert to 00000000 or 11111111, respectively. The reference
inputs are fully differential with common-mode limits defined by the supply rails. The reference input values define
the full-scale range of the analog input. This allows the gain of the ADC to be varied for ratiometric conversion by
changing the Vref+ and V ref– voltages.
The device operates in two modes, read (only) and write-read, that are selected by MODE. The converter is set to
the read (only) mode when MODE is low. In the read mode, WR/RDY is used as an output and is referred to as the
ready terminal. In this mode, a low on WR/RDY while CS is low indicates that the device is busy. Conversion starts
on the falling edge of RD and is completed no more than 2.5 µs later when INT falls and WR/RDY returns to the
high-impedance state. Data outputs also change from high-impedance to active states at this time. After the data is
read, RD is taken high, INT returns high, and the data outputs return to their high-impedance states.
When MODE is high, the converter is set to the write-read mode and WR/RDY is referred to as the write terminal.
Taking CS and WR/RDY low selects the converter and initiates measurement of the input signal. Approximately
600 ns after WR/RDY returns high, the conversion is completed. Conversion starts on the rising edge of WR/RDY
in the write-read mode.
The high-order 4-bit flash ADC measures the input by means of 16 comparators operating simultaneously. A
high-precision 4-bit DAC then generates a discrete analog voltage from the result of that conversion. After a time
delay, a second bank of comparators does a low-order conversion on the analog difference between the input level
and the high-order DAC output. The results from each of these conversions enter an 8-bit latch and are output to the
3-state output buffers on the falling edge of RD.
TLC0820AC, TLC0820AI
Advanced LinCMOSHIGH-SPEED 8-BIT ANALOG-TO-DIGITAL
CONVERTERS USING MODIFIED FLASH TECHNIQUES
SLAS064A – SEPTEMBER 1986 – REVISED JUNE 1994
2–10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
ANLG 1
20
Bus
µP
CS
WR
RD
OFL
D0
D1
D2
D3
D4
D5
D6
D7
D8
13
6
8
2
3
4
5
14
15
16
17
18
18
17
16
15
14
5
4
3
2
8
0.1 µF
0.1 µF
10
11
CS
WR/RDY
RD
D0
D1
D2
D3
D4
D5
D6
D7
OFLW
VCC
IN
MODE
REF+
REF–
GND
125 V
7
65 V
13
10
11
12
7
1
20
5 V
5 V
0.1 µF
0.1 µF
ANLG
IN
5 V
GND
REF–
REF+
MODE
IN
ANLG
VCC
OFLW
D7
D6
D5
D4
D3
D2
D1
D0
RD
WR/RDY
CS
TLC0820
TLC0820
Figure 6. Configuration for 9-Bit Resolution
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TLC0820ACDB ACTIVE SSOP DB 20 70 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC0820ACDBG4 ACTIVE SSOP DB 20 70 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC0820ACDBR ACTIVE SSOP DB 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC0820ACDBRG4 ACTIVE SSOP DB 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC0820ACDW ACTIVE SOIC DW 20 25 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC0820ACDWG4 ACTIVE SOIC DW 20 25 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC0820ACDWR ACTIVE SOIC DW 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC0820ACDWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC0820ACFN ACTIVE PLCC FN 20 46 Green (RoHS &
no Sb/Br) CU SN Level-1-260C-UNLIM
TLC0820ACFNG3 ACTIVE PLCC FN 20 46 Green (RoHS &
no Sb/Br) CU SN Level-1-260C-UNLIM
TLC0820ACN ACTIVE PDIP N 20 20 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
TLC0820ACNE4 ACTIVE PDIP N 20 20 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
TLC0820AIDW ACTIVE SOIC DW 20 25 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC0820AIDWG4 ACTIVE SOIC DW 20 25 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC0820AIDWR ACTIVE SOIC DW 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC0820AIDWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC0820AIFN ACTIVE PLCC FN 20 46 Green (RoHS &
no Sb/Br) CU SN Level-1-260C-UNLIM
TLC0820AIFNG3 ACTIVE PLCC FN 20 46 Green (RoHS &
no Sb/Br) CU SN Level-1-260C-UNLIM
TLC0820AIN ACTIVE PDIP N 20 20 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
TLC0820AINE4 ACTIVE PDIP N 20 20 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
PACKAGE OPTION ADDENDUM
www.ti.com 25-May-2009
Addendum-Page 1
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 25-May-2009
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TLC0820ACDBR SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1
TLC0820ACDWR SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1
TLC0820AIDWR SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Jan-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TLC0820ACDBR SSOP DB 20 2000 367.0 367.0 38.0
TLC0820ACDWR SOIC DW 20 2000 367.0 367.0 45.0
TLC0820AIDWR SOIC DW 20 2000 367.0 367.0 45.0
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Jan-2013
Pack Materials-Page 2
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