4-Channel, Low Noise, Low Power, 24-Bit, Sigma-Delta ADC with PGA and Reference AD7124-4-EP Enhanced Product FEATURES Multiple filter options Sensor burnout detection Automatic channel sequencer Per channel configuration Power-down current: 5 A maximum 24-lead TSSOP 3-wire or 4-wire serial interface SPI, QSPI, MICROWIRE, and DSP compatible Schmitt trigger on SCLK 3 power modes RMS noise Low power: 24 nV rms at 1.17 SPS, gain = 128 (255 A typical) Mid power: 20 nV rms at 2.34 SPS, gain = 128 (355 A typical) Full power: 23 nV rms at 9.4 SPS, gain = 128 (930 A typical) Up to 22 noise free bits in all power modes (gain = 1) Output data rate Full power: 9.38 SPS to 19,200 SPS Mid power: 2.34 SPS to 4800 SPS Low power: 1.17 SPS to 2400 SPS Rail-to-rail analog inputs for gains > 1 Simultaneous 50 Hz/60 Hz rejection at 25 SPS (single cycle settling) Diagnostic functions (which aid safe integrity level (SIL) certification) Crosspoint multiplexed analog inputs 4 differential/7 pseudo differential inputs Programmable gain (1 to 128) Band gap reference with 10 ppm/C drift maximum (70 A) Matched programmable excitation currents Internal clock oscillator and temperature sensor On-chip bias voltage generator Low-side power switch ENHANCED PRODUCT FEATURES Supports defense and aerospace applications (AQEC standard) Full military temperature range: -55C to +125C Controlled manufacturing baseline 1 assembly/test site 1 fabrication site Product change notification Qualification data available on request APPLICATIONS Military and space Avionics Pressure measurement Instrumentation FUNCTIONAL BLOCK DIAGRAM 1.9V LDO REGCAPA REFOUT VBIAS BANDGAP REF AVDD AVSS CROSSPOINT MUX AIN2/IOUT/VBIAS/P1 BUF BURNOUT DETECT AIN4/IOUT/VBIAS AIN5/IOUT/VBIAS PGA1 24-BIT - ADC PGA2 BUF VARIABLE DIGITAL FILTER SERIAL INTERFACE AND CONTROL LOGIC X-MUX AIN6/IOUT/VBIAS/REFIN2(+) CHANNEL SEQUENCER GPOs TEMPERATURE SENSOR DIAGNOSTICS POWER SWITCH DOUT/RDY DIN SCLK CS ANALOG BUFFERS AVSS AIN7/IOUT/VBIAS/REFIN2(-) PSW 1.8V LDO REFERENCE BUFFERS AIN1/IOUT/VBIAS AIN3/IOUT/VBIAS/P2 REFIN2(+) REFIN2(-) AVSS AVDD AIN0/IOUT/VBIAS IOVDD REGCAPD REFIN1(+) REFIN1(-) AVDD SYNC DIAGNOSTICS COMMUNICATIONS POWER SUPPLY SIGNAL CHAIN DIGITAL EXCITATION CURRENTS INTERNAL CLOCK AD7124-4-EP AVSS AVSS DGND CLK 20190-001 AVDD Figure 1. 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Technical Support www.analog.com AD7124-4-EP Enhanced Product TABLE OF CONTENTS Features .............................................................................................. 1 Thermal Resistance .................................................................... 10 Enhanced Product Features ............................................................ 1 ESD Caution................................................................................ 10 Applications ....................................................................................... 1 Pin Configuration and Function Descriptions........................... 11 Functional Block Diagram .............................................................. 1 Typical Performance Characteristics ........................................... 13 Revision History ............................................................................... 2 Outline Dimensions ....................................................................... 17 General Description ......................................................................... 3 Ordering Guide .......................................................................... 17 Specifications..................................................................................... 4 Absolute Maximum Ratings.......................................................... 10 REVISION HISTORY 4/2019--Revision 0: Initial Version Rev. 0 | Page 2 of 17 Enhanced Product AD7124-4-EP GENERAL DESCRIPTION The AD7124-4-EP is a low power, low noise, completely integrated analog front end for high precision measurement applications. The device contains a low noise, 24-bit - analogto-digital converter (ADC), and can be configured to have four differential inputs or seven single-ended or pseudo differential inputs. The on-chip low gain stage ensures that signals of small amplitude can be interfaced directly to the ADC. One of the major advantages of the AD7124-4-EP is that it gives the user the flexibility to employ one of three integrated power modes. The current consumption, range of output data rates, and rms noise can be tailored with the power mode selected. The device also offers a multitude of filter options, ensuring that the user has the highest degree of flexibility. The AD7124-4-EP can achieve simultaneous 50 Hz and 60 Hz rejection when operating at an output data rate of 25 SPS (single cycle settling), with rejection in excess of 80 dB achieved at lower output data rates. The AD7124-4-EP establishes the highest degree of signal chain integration. The device contains a precision, low noise, low drift internal band gap reference, and also accepts an external differential reference, which can be internally buffered. Other key integrated features include programmable low drift excitation current sources, burnout currents, and a bias voltage generator, which sets the common-mode voltage of a channel to AVDD/2. The low-side power switch enables the user to power down bridge sensors between conversions, ensuring the absolute minimal power consumption of the system. The device also allows the user the option of operating with either an internal clock or an external clock. The integrated channel sequencer allows several channels to be enabled simultaneously, and the AD7124-4-EP sequentially converts on each enabled channel, simplifying communication with the device. As many as 16 channels can be enabled at any time; a channel being defined as an analog input or a diagnostic such as a power supply check or a reference check. This unique feature allows diagnostics to be interleaved with conversions. The AD7124-4-EP also supports per channel configuration. The device allows eight configurations or setups. Each configuration consists of gain, filter type, output data rate, buffering, and reference source. The user can assign any of these setups on a channel by channel basis. The AD7124-4-EP also has extensive diagnostic functionality integrated as part of its comprehensive feature set. These diagnostics include a cyclic redundancy check (CRC), signal chain checks, and serial interface checks, which lead to a more robust solution. These diagnostics reduce the need for external components to implement diagnostics, resulting in reduced board space needs, reduced design cycle times, and cost savings. The failure modes effects and diagnostic analysis (FMEDA) of a typical application has shown a safe failure fraction (SFF) greater than 90% according to IEC 61508. The device operates with a single analog power supply from 2.7 V to 3.6 V or a dual 1.8 V power supply. The digital supply has a range of 1.65 V to 3.6 V. It is specified for the full military temperature range of -55C to +125C. The AD7124-4-EP is housed in a 24-lead TSSOP package. Note that, throughout this data sheet, multifunction pins, such as DOUT/RDY, are referred to either by the entire pin name or by a single function of the pin, for example, RDY, when only that function is relevant. Additional application and technical information can be found in the AD7124-4 data sheet. Rev. 0 | Page 3 of 17 AD7124-4-EP Enhanced Product SPECIFICATIONS AVDD = 2.9 V to 3.6 V (full power mode), 2.7 V to 3.6 V (mid and low power mode), IOVDD = 1.65 V to 3.6 V, AVSS = DGND = 0 V, REFINx(+) = 2.5 V, REFINx(-) = AVSS, master clock = 614.4 kHz, all specifications TMIN to TMAX, unless otherwise noted. Table 1. Parameter1 ADC Output Data Rate, fADC Low Power Mode Mid Power Mode Full Power Mode No Missing Codes2 Resolution RMS Noise and Update Rates Integral Nonlinearity (INL) Min -4 -15 After Internal Calibration/System Calibration Offset Error Drift vs. Temperature6 Low Power Mode Mid Power Mode After Internal Calibration Mid Power Mode2 Full Power Mode Common-Mode Rejection8 At DC2 Sinc3, Sinc4 Filter2 At 50 Hz, 60 Hz At 50 Hz At 60 Hz Unit Test Conditions/Comments 2400 4800 19,200 SPS SPS SPS Bits Bits FS3 > 2, sinc4 filter FS3 > 8, sinc3 filter ppm of FSR ppm of FSR Gain = 12 Gain > 14 15 200/gain In order of noise V V Gain = 1 to 8 Gain = 16 to 128 10 80 40 10 40 20 10 nV/C nV/C nV/C nV/C nV/C nV/C nV/C Gain = 1 or gain > 16 Gain = 2 to 8 Gain = 16 Gain = 1 or gain > 16 Gain = 2 to 8 Gain = 16 % % % % Gain = 1, TA = 25C Gain > 1 Gain = 2 to 8, TA = 25C Gain = 16 to 128 1 2 -0.0025 -0.016 After System Calibration Gain Error Drift vs. Temperature Power Supply Rejection Low Power Mode Max 1.17 2.34 9.38 24 24 Offset Error5 Before Calibration Full Power Mode Gain Error5, 7 Before Internal Calibration Typ +4 +15 +0.0025 -0.3 +0.004 0.025 In order of noise 1 +0.016 2 87 96 92 100 99 85 105 1029, 2 115 1059, 2 ppm/C dB dB dB dB dB 90 115 120 120 120 120 Rev. 0 | Page 4 of 17 AIN = 1 V/gain, external reference Gain = 2 to 16 Gain = 1 or gain > 16 Gain = 2 to 16 Gain = 1 or gain > 16 dB dB dB dB dB AIN = 1 V, gain = 1 AIN = 1 V/gain, gain 2 or 4 AIN = 1 V/gain, gain 2 or 4 AIN = 1 V/gain, gain 8 AIN = 1 V/gain, gain 8 dB dB dB 10 SPS, 50 Hz 1 Hz, 60 Hz 1 Hz 50 SPS, 50 Hz 1 Hz 60 SPS, 60 Hz 1 Hz Enhanced Product Parameter1 Fast Settling Filters2 At 50 Hz At 60 Hz Post Filters2 At 50 Hz, 60 Hz Normal Mode Rejection2 Sinc4 Filter External Clock At 50 Hz, 60 Hz At 50 Hz At 60 Hz Internal Clock At 50 Hz, 60 Hz At 50 Hz At 60 Hz Sinc3 Filter External Clock At 50 Hz, 60 Hz At 50 Hz At 60 Hz Internal Clock At 50 Hz, 60 Hz At 50 Hz At 60 Hz Fast Settling Filters External Clock At 50 Hz At 60 Hz Internal Clock At 50 Hz At 60 Hz Post Filters External Clock At 50 Hz, 60 Hz Internal Clock At 50 Hz, 60 Hz AD7124-4-EP Min Typ Max Unit Test Conditions/Comments 115 115 dB dB First notch at 50 Hz, 50 Hz 1 Hz First notch at 60 Hz, 60 Hz 1 Hz 130 130 dB dB 20 SPS, 50 Hz 1 Hz, 60 Hz 1 Hz 25 SPS, 50 Hz 1 Hz, 60 Hz 1 Hz 120 80 dB dB 120 120 dB dB 10 SPS, 50 Hz 1 Hz, 60 Hz 1 Hz 50 SPS, REJ6010=1, 50 Hz 1 Hz, 60 Hz 1 Hz 50 SPS, 50 Hz 1 Hz 60 SPS, 60 Hz 1 Hz 98 66 dB dB 92 92 dB dB 100 65 dB dB 100 100 dB dB 73 52 dB dB 68 68 dB dB 10 SPS, 50 Hz 1 Hz, 60 Hz 1 Hz 50 SPS, REJ6010 = 1, 50 Hz 1 Hz, 60 Hz 1 Hz 50 SPS, 50 Hz 1 Hz 60 SPS, 60 Hz 1 Hz 40 40 dB dB First notch at 50 Hz, 50 Hz 0.5 Hz First notch at 60 Hz, 60 Hz 0.5 Hz 24.5 24.5 dB dB First notch at 50 Hz, 50 Hz 0.5 Hz First notch at 60 Hz, 60 Hz 0.5 Hz 86 62 dB dB 20 SPS, 50 Hz 1 Hz, 60 Hz 1 Hz 25 SPS, 50 Hz 1 Hz, 60 Hz 1 Hz 67 50 dB dB 20 SPS, 50 Hz 1 Hz, 60 Hz 1 Hz 25 SPS, 50 Hz 1 Hz, 60 Hz 1 Hz Rev. 0 | Page 5 of 17 10 SPS, 50 Hz 1 Hz, 60 Hz 1 Hz 50 SPS, REJ6010 = 1, 50 Hz 1 Hz, 60 Hz 1 Hz 50 SPS, 50 Hz 1 Hz 60 SPS, 60 Hz 1 Hz 10 SPS, 50 Hz 1 Hz, 60 Hz 1 Hz 50 SPS, REJ6010 = 1, 50 Hz 1 Hz, 60 Hz 1 Hz 50 SPS, 50 Hz 1 Hz 60 SPS, 60 Hz 1 Hz AD7124-4-EP Parameter1 ANALOG INPUTS11 Differential Input Voltage Ranges12 Absolute AIN Voltage Limits2 Gain = 1 (Unbuffered) Gain = 1 (Buffered) Gain > 1 Analog Input Current Gain > 1 or Gain = 1 (Buffered) Low Power Mode Absolute Input Current Differential Input Current Analog Input Current Drift Mid Power Mode Absolute Input Current Differential Input Current Analog Input Current Drift Full Power Mode Absolute Input Current Differential Input Current Analog Input Current Drift Gain = 1 (Unbuffered) Absolute Input Current Analog Input Current Drift REFERENCE INPUT Internal Reference Initial Accuracy Drift Output Current Load Regulation Power Supply Rejection External Reference External REFIN Voltage2 Absolute REFIN Voltage Limits2 Reference Input Current Buffered Low Power Mode Absolute Input Current Reference Input Current Drift Mid Power Mode Absolute Input Current Reference Input Current Drift Full Power Mode Absolute Input Current Reference Input Current Drift Unbuffered Absolute Input Current Reference Input Current Drift Normal Mode Rejection Common-Mode Rejection Enhanced Product Min Typ Max VREF/gain AVSS - 0.05 AVSS + 0.1 AVSS - 0.05 AVDD + 0.05 AVDD - 0.1 AVDD + 0.05 Unit Test Conditions/Comments V VREF = REFINx(+) - REFINx(-), or internal reference V V V 1 0.2 25 nA nA pA/C 1.2 0.4 25 nA nA pA/C 3.3 1.5 25 nA nA pA/C 2.65 1.1 A/V nA/V/C Current varies with input voltage 2.5 - 0.2% 2.5 2 2.5 + 0.2% 10 10 V ppm/C mA V/mA dB TA = 25C AVDD AVDD + 0.05 AVDD - 0.1 V V V REFIN = REFINx(+) - REFINx(-) Unbuffered Buffered 50 85 0.5 AVSS - 0.05 AVSS + 0.1 2.5 0.5 10 nA pA/C 1 10 nA pA/C 3 10 nA pA/C 12 6 A nA/C 100 dB Same as for analog inputs Rev. 0 | Page 6 of 17 Enhanced Product Parameter1 EXCITATION CURRENT SOURCES (IOUT0/IOUT1) Output Current AD7124-4-EP Min 5 2 0.2 Hysteresis Input Currents Input Capacitance % ppm/C % AVDD - 0.37 AVSS - 0.05 AVDD - 0.48 V 30 s/nF 0.5 13,584 C Codes/C 10 30 0.5/2/4 AVDD - 0.6 0.4 1.6 1.55 1 0.7 AVDD + 0.04 AVSS - 0.04 614.4 - 5% 614.4 50:50 614.4 + 5% 2.4576 45:55 to 55:45 0.3 x IOVDD 0.35 x IOVDD 0.7 0.7 x IOVDD 0.65 x IOVDD 1.7 2 0.2 -1 TA = 25C Matching between IOUT0 and IOUT1, VOUT = 0 V AVDD = 3 V 5% 50 A/100 A/250 A/500 A current sources, 2% accuracy 750 A and 1000 A current sources, 2% accuracy Available on any analog input pin V AVSS + (AVDD - AVSS)/2 6.7 7 Test Conditions/Comments Available on any analog input pin A AVSS - 0.05 VBIAS Generator Start-Up Time High, VINH Unit ppm/C %/V %/V V BIAS VOLTAGE (VBIAS) GENERATOR VBIAS TEMPERATURE SENSOR Accuracy Sensitivity LOW-SIDE POWER SWITCH On Resistance (RON) Allowable Current2 BURNOUT CURRENTS AIN Current DIGITAL OUTPUTS (P1 AND P2) Output Voltage High, VOH Low, VOL DIAGNOSTICS Power Supply Monitor Detect Level Analog Low Dropout Regulator (ALDO) Digital LDO (DLDO) Reference Detect Level AINM/AINP Overvoltage Detect Level AINM/AINP Undervoltage Detect Level INTERNAL/EXTERNAL CLOCK Internal Clock Frequency Duty Cycle External Clock Frequency Duty Cycle Range LOGIC INPUTS2 Input Voltage Low, VINL Max 50/100/250/ 500/750/1000 4 50 0.5 Initial Tolerance Drift Current Matching Drift Matching2 Line Regulation (AVDD) Load Regulation Output Compliance2 Typ 0.6 +1 10 Rev. 0 | Page 7 of 17 Dependent on the capacitance connected to AINx mA Continuous current A Analog inputs must be buffered V V ISOURCE = 100 A ISINK = 100 A V V V V V AVDD - AVSS 2.7 V IOVDD 1.75 V REF_DET_ERR bit active if VREF < 0.7 V kHz % MHz % Internal divide by 4 V V V V V V V V A pF 1.65 V IOVDD < 1.9 V 1.9 V IOVDD < 2.3 V 2.3 V IOVDD 3.6 V 1.65 V IOVDD < 1.9 V 1.9 V IOVDD < 2.3 V 2.3 V IOVDD < 2.7 V 2.7 V IOVDD 3.6 V 1.65 V IOVDD 3.6 V VIN = IOVDD or GND All digital inputs AD7124-4-EP Parameter1 LOGIC OUTPUTS (INCLUDING CLK) Output Voltage2 High, VOH Low, VOL Floating State Leakage Current Floating State Output Capacitance Data Output Coding SYSTEM CALIBRATION2 Calibration Limit Full Scale (FS) Zero Scale Input Span POWER SUPPLY VOLTAGES FOR ALL POWER MODES AVDD to AVSS Low Power Mode Mid Power Mode Full Power Mode IOVDD to GND AVSS to GND IOVDD to AVSS POWER SUPPLY CURRENTS11, 13 IAVDD, External Reference Low Power Mode Gain = 12 Gain = 1 IAVDD Increase per AINx Buffer2 Gain = 2 to 8 Gain = 16 to 128 IAVDD Increase per Reference Buffer2 Mid Power Mode Gain = 12 Gain = 1 IAVDD Increase per AINx Buffer2 Gain = 2 to 8 Gain = 16 to 128 IAVDD Increase per Reference Buffer2 Full Power Mode Gain = 12 Gain = 1 IAVDD Increase per AINx Buffer2 Gain = 2 to 8 Gain = 16 to 128 IAVDD Increase per Reference Buffer2 IAVDD Increase Due to Internal Reference2 Due to VBIAS2 Due to Diagnostics2 IIOVDD Low Power Mode Mid Power Mode Full Power Mode Enhanced Product Min Typ Max Unit Test Conditions/Comments 0.4 +1 V V A pF ISOURCE = 100 A ISINK = 100 A IOVDD - 0.35 -1 10 Offset binary 1.05 x FS 2.1 x FS V V V 3.6 3.6 3.6 3.6 0 5.4 V V V V V V 125 15 205 235 10 140 25 250 300 20 A A A A A All buffers off 150 30 275 330 20 170 40 345 430 30 A A A A A All buffers off 315 90 660 875 85 350 135 830 1200 120 A A A A A All buffers off 50 70 A 15 4 20 5 A A Independent of power mode; the reference buffers are not required when using this reference Independent of power mode 20 25 55 35 40 80 A A A -1.05 x FS 0.8 x FS 2.7 2.7 2.9 1.65 -1.8 Rev. 0 | Page 8 of 17 All gains All gains All gains Enhanced Product Parameter1 POWER-DOWN CURRENTS13 Standby Current IAVDD IIOVDD Power-Down Current IAVDD IIOVDD AD7124-4-EP Min Typ Max Unit Test Conditions/Comments Independent of power mode 7 8 15 20 A A LDOs on only 1 1 3 2 A A 1 Temperature range = -55C to +125C. These specifications are not production tested but are supported by characterization data at the initial product release. FS is the decimal equivalent of the FS[10:0] bits in the filter registers. 4 The integral nonlinearity is production tested in full power mode only. For other power modes, the specification is supported by characterization data at the initial product release. 5 Following a system or internal zero-scale calibration, the offset error is in the order of the noise for the programmed gain and output data rate selected. A system fullscale calibration reduces the gain error to the order of the noise for the programmed gain and output data rate. 6 Recalibration at any temperature removes these errors. 7 Gain error applies to both positive and negative full-scale. A factory calibration is performed at gain = 1, TA = 25C. 8 When gain > 1, the common-mode voltage is between (AVSS + 0.1 + 0.5/gain) and (AVDD - 0.1 - 0.5/gain). 9 Specification is for a wider common-mode voltage between (AVSS - 0.05 + 0.5/gain) and (AVDD - 0.1 - 0.5/gain). 10 REJ60 is a bit in the filter registers. When the first notch of the sinc filter is at 50 Hz, a notch is placed at 60 Hz when REJ60 is set to 1. This gives simultaneous 50 Hz and 60 Hz rejection. 11 When the gain is greater than 1, the analog input buffers are enabled automatically. The buffers can only be disabled when the gain equals 1. 12 When VREF = (AVDD - AVSS), the typical differential input equals 0.92 x VREF/gain for the low and mid power modes and 0.86 x VREF/gain for full power mode when gain > 1. 13 The digital inputs are equal to IOVDD or DGND with excitation currents and bias voltage generator disabled. 2 3 Rev. 0 | Page 9 of 17 AD7124-4-EP Enhanced Product ABSOLUTE MAXIMUM RATINGS TA = 25C, unless otherwise noted. THERMAL RESISTANCE Table 2. Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Careful attention to PCB thermal design is required. Parameter AVDD to AVSS IOVDD to DGND IOVDD to AVSS AVSS to DGND Analog Input Voltage to AVSS Reference Input Voltage to AVSS Digital Input Voltage to DGND Digital Output Voltage to DGND AINx/Digital Input Current Operating Temperature Range Storage Temperature Range Maximum Junction Temperature Lead Temperature, Soldering Reflow ESD Ratings Human Body Model (HBM) Field-Induced Charged Device Model (FICDM) Machine Model Rating -0.3 V to +3.96 V -0.3 V to +3.96 V -0.3 V to +5.94 V -1.98 V to +0.3 V -0.3 V to AVDD + 0.3 V -0.3 V to AVDD + 0.3 V -0.3 V to IOVDD + 0.3 V -0.3 V to IOVDD + 0.3 V 10 mA -55C to +125C -65C to +150C 150C JA is the natural convection, junction to ambient thermal resistance measured in a one cubic foot sealed enclosure. JC is the junction to case thermal resistance. Table 3. Thermal Resistance Package Type1 RU-24 1 JA 128 JC 42 Unit C/W Thermal impedance simulated values are based on a JEDEC 2S2P thermal test board. See JEDEC JESD51. ESD CAUTION 260C 4 kV 1250 V 400 V Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. 0 | Page 10 of 17 Enhanced Product AD7124-4-EP DIN 1 24 DOUT/RDY SCLK 2 23 SYNC CLK 3 22 AVDD CS 4 21 PSW 20 REGCAPA 19 AVSS REGCAPD 5 IOVDD 6 AD7124-4-EP TOP VIEW (Not to Scale) DGND 7 18 REFOUT AIN0/IOUT/VBIAS 8 17 AIN7/IOUT/VBIAS/REFIN2(-) AIN1/IOUT/VBIAS 9 16 AIN6/IOUT/VBIAS/REFIN2(+) AIN2/IOUT/VBIAS/P1 10 15 AIN5/IOUT/VBIAS AIN3/IOUT/VBIAS/P2 11 14 AIN4/IOUT/VBIAS REFIN1(+) 12 13 REFIN1(-) 20190-002 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 2. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 Mnemonic DIN 2 SCLK 3 CLK 4 CS 5 6 REGCAPD IOVDD 7 8 DGND AIN0/IOUT/VBIAS 9 AIN1/IOUT/VBIAS 10 AIN2/IOUT/VBIAS/P1 Description Serial Data Input to the Input Shift Register on the ADC. Data in the input shift register is transferred to the control registers within the ADC, with the register selection bits of the communications register identifying the appropriate register. Serial Clock Input. This serial clock input is for data transfers to and from the ADC. The SCLK pin has a Schmitttriggered input, making the interface suitable for opto-isolated applications. The serial clock can be continuous with all data transmitted in a continuous train of pulses. Alternatively, it can be a noncontinuous clock with the information being transmitted to or from the ADC in smaller batches of data. Clock Input/Clock Output. The internal clock can be made available at this pin. Alternatively, the internal clock can be disabled, and the ADC can be driven by an external clock. This allows several ADCs to be driven from a common clock, allowing simultaneous conversions to be performed. Chip Select Input. This is an active low logic input that selects the ADC. Use CS to select the ADC in systems with more than one device on the serial bus or as a frame synchronization signal in communicating with the device. CS can be hardwired low if the serial peripheral interface (SPI) diagnostics are unused, allowing the ADC to operate in 3-wire mode with SCLK, DIN, and DOUT interfacing with the device. Digital LDO Regulator Output. Decouple this pin to DGND with a 0.1 F capacitor. Serial Interface Supply Voltage, 1.65 V to 3.6 V. IOVDD is independent of AVDD. Therefore, the serial interface can operate at 1.65 V with AVDD at 3.6 V, for example. Digital Ground Reference Point. Analog Input 0/Output of Internal Excitation Current Source/Bias Voltage. This input pin is configured via the configuration registers to be the positive or negative terminal of a differential or pseudo differential input. Alternatively, the internal programmable excitation current source can be made available at this pin. Either IOUT0 or IOUT1 can be switched to this output. A bias voltage midway between the analog power supply rails can be generated at this pin. Analog Input 1/Output of Internal Excitation Current Source/Bias Voltage. This input pin is configured via the configuration registers to be the positive or negative terminal of a differential or pseudo differential input. Alternatively, the internal programmable excitation current source can be made available at this pin. Either IOUT0 or IOUT1 can be switched to this output. A bias voltage midway between the analog power supply rails can be generated at this pin. Analog Input 2/Output of Internal Excitation Current Source/Bias Voltage/General-Purpose Output 1. This input pin is configured via the configuration registers to be the positive or negative terminal of a differential or pseudo differential input. Alternatively, the internal programmable excitation current source can be made available at this pin. Either IOUT0 or IOUT1 can be switched to this output. A bias voltage midway between the analog power supply rails can be generated at this pin. This pin can also be configured as a general-purpose output bit, referenced between AVSS and AVDD. Rev. 0 | Page 11 of 17 AD7124-4-EP Pin No. 11 Mnemonic AIN3/IOUT/VBIAS/P2 12 REFIN1(+) 13 REFIN1(-) 14 AIN4/IOUT/VBIAS 15 AIN5/IOUT/VBIAS 16 AIN6/IOUT/VBIAS/ REFIN2(+) 17 AIN7/IOUT/VBIAS/ REFIN2(-) 18 19 REFOUT AVSS 20 21 22 23 REGCAPA PSW AVDD SYNC 24 DOUT/RDY Enhanced Product Description Analog Input 3/Output of Internal Excitation Current Source/Bias Voltage/General-Purpose Output 2. This input pin is configured via the configuration registers to be the positive or negative terminal of a differential or pseudo differential input. Alternatively, the internal programmable excitation current source can be made available at this pin. Either IOUT0 or IOUT1 can be switched to this output. A bias voltage midway between the analog power supply rails can be generated at this pin. This pin can also be configured as a general-purpose output bit, referenced between AVSS and AVDD. Positive Reference Input. An external reference can be applied between REFIN1(+) and REFIN1(-). REFIN1(+) can be anywhere between AVDD and AVSS + 0.5 V. The nominal reference voltage (REFIN1(+) - REFIN1(-)) is 2.5 V, but the device functions with a reference from 0.5 V to AVDD. Negative Reference Input. This reference input can be anywhere between AVSS and AVDD - 0.5 V. Analog Input 4/Output of Internal Excitation Current Source/Bias Voltage. This input pin is configured via the configuration registers to be the positive or negative terminal of a differential or pseudo differential input. Alternatively, the internal programmable excitation current source can be made available at this pin. Either IOUT0 or IOUT1 can be switched to this output. A bias voltage midway between the analog power supply rails can be generated at this pin. Analog Input 5/Output of Internal Excitation Current Source/Bias Voltage. This input pin is configured via the configuration registers to be the positive or negative terminal of a differential or pseudo differential input. Alternatively, the internal programmable excitation current source can be made available at this pin. Either IOUT0 or IOUT1 can be switched to this output. A bias voltage midway between the analog power supply rails can be generated at this pin. Analog Input 6/Output of Internal Excitation Current Source/Bias Voltage/Positive Reference Input. This input pin is configured via the configuration registers to be the positive or negative terminal of a differential or pseudo differential input. Alternatively, the internal programmable excitation current source can be made available at this pin. Either IOUT0 or IOUT1 can be switched to this output. A bias voltage midway between the analog power supply rails can be generated at this pin. This pin also functions as a positive reference input for REFIN2(). REFIN2(+) can be anywhere between AVDD and AVSS + 0.5 V. The nominal reference voltage (REFIN2(+) to REFIN2(-)) is 2.5 V, but the device functions with a reference from 0.5 V to AVDD. Analog Input 7/Output of Internal Excitation Current Source/Bias Voltage/Negative Reference Input. This input pin is configured via the configuration registers to be the positive or negative terminal of a differential or pseudo differential input. Alternatively, the internal programmable excitation current source can be made available at this pin. Either IOUT0 or IOUT1 can be switched to this output. A bias voltage midway between the analog power supply rails can be generated at this pin. This pin also functions as the negative reference input for REFIN2(). This reference input can be anywhere between AVSS and AVDD - 0.5 V. Internal Reference Output. The buffered output of the internal 2.5 V voltage reference is available on this pin. Analog Supply Voltage. The voltage on AVDD is referenced to AVSS. The differential between AVDD and AVSS must be between 2.7 V and 3.6 V in mid or low power mode and between 2.9 V and 3.6 V in full power mode. AVSS can be taken below 0 V to provide a dual power supply to the AD7124-4-EP. For example, AVSS can be tied to -1.8 V and AVDD can be tied to +1.8 V, providing a 1.8 V supply to the ADC. Analog LDO Regulator Output. Decouple this pin to AVSS with a 0.1 F capacitor. Low-Side Power Switch to AVSS. Analog Supply Voltage, Relative to AVSS. Synchronization Input. This pin is a logic input that allows synchronization of the digital filters and analog modulators when using a number of AD7124-4-EP devices. When SYNC is low, the nodes of the digital filter, the filter control logic, and the calibration control logic are reset, and the analog modulator is held in a reset state. SYNC does not affect the digital interface but does reset RDY to a high state if it is low. Serial Data Output/Data Ready Output. DOUT/RDY functions as a serial data output pin to access the output shift register of the ADC. The output shift register can contain data from any of the on-chip data or control registers. In addition, DOUT/RDY operates as a data ready pin, going low to indicate the completion of a conversion. If the data is not read after the conversion, the pin goes high before the next update occurs. The DOUT/RDY falling edge can also be used as an interrupt to a processor, indicating that valid data is available. With an external serial clock, the data can be read using the DOUT/RDY pin. When CS is low, the data/control word information is placed on the DOUT/RDY pin on the SCLK falling edge and is valid on the SCLK rising edge. Rev. 0 | Page 12 of 17 Enhanced Product AD7124-4-EP TYPICAL PERFORMANCE CHARACTERISTICS 60 0 -20 -40 -60 -55 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C) Figure 3. Input Referred Offset Error vs. Temperature (Gain = 8, Full Power Mode) 0 -20 -40 5 20 35 50 65 80 95 110 125 TEMPERATURE (C) Figure 4. Input Referred Offset Error vs. Temperature (Gain = 8, Mid Power Mode) -40 5 20 35 50 65 TEMPERATURE (C) 80 95 110 125 Figure 5. Input Referred Offset Error vs. Temperature (Gain = 8, Low Power Mode) 65 80 95 110 125 20 0 -20 -40 5 20 35 50 65 80 95 110 125 Figure 7. Input Referred Offset Error vs. Temperature (Gain = 16, Mid Power Mode) INPUT REFERRED OFFSET ERROR (V) -20 50 TEMPERATURE (C) 15 UNITS 40 20 0 -20 -40 -60 -55 -40 -25 -10 20190-005 INPUT REFERRED OFFSET ERROR (V) 0 35 40 60 20 20 15 UNITS -60 -55 -40 -25 -10 15 UNITS 40 5 Figure 6. Input Referred Offset Error vs. Temperature (Gain = 16, Full Power Mode) INPUT REFERRED OFFSET ERROR (V) 20 -60 -55 -40 -25 -10 -40 60 40 60 -20 TEMPERATURE (C) 15 UNITS -60 -55 -40 -25 -10 0 -60 -55 -40 -25 -10 20190-004 INPUT REFERRED OFFSET ERROR (V) 60 20 20190-007 20 40 5 20 35 50 65 TEMPERATURE (C) 80 95 110 125 20190-008 40 15 UNITS 20190-006 INPUT REFERRED OFFSET ERROR (V) 15 UNITS 20190-003 INPUT REFERRED OFFSET ERROR (V) 60 Figure 8. Input Referred Offset Error vs. Temperature (Gain = 16, Low Power Mode) Rev. 0 | Page 13 of 17 AD7124-4-EP 0.040 40 20 0 -20 -40 -60 -55 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C) 0.030 0.025 0.020 0.015 0.010 0.005 0 -0.005 -0.010 5 20 35 50 65 80 95 110 125 TEMPERATURE (C) Figure 12. Input Referred Gain Error vs. Temperature (Gain = 16) 0.0015 2.5020 INTERNAL REFERENCE VOLTAGE (V) 2.5015 0.0010 0.0005 0 -0.0005 -0.0010 2.5010 2.5005 2.5000 2.4995 2.4990 2.4985 2.4980 2.4975 2.4970 5 20 35 50 65 80 95 110 125 TEMPERATURE (C) 5 20 35 50 65 80 95 110 125 TEMPERATURE (C) Figure 13. Internal Reference Voltage vs. Temperature Figure 10. Input Referred Gain Error vs. Temperature (Gain = 1) 0.015 510 EXCITATION CURRENT DRIVE (A) 0.010 0.005 0 -0.005 -0.010 505 500 495 490 485 480 475 5 20 35 50 65 80 95 110 125 TEMPERATURE (C) Figure 11. Input Referred Gain Error vs. Temperature (Gain = 8) 470 -55 -40 -25 -10 15 UNITS 5 20 35 50 65 80 95 TEMPERATURE (C) Figure 14. Excitation Current Drift (500 A) Rev. 0 | Page 14 of 17 110 125 20190-014 15 UNITS 20190-011 -0.015 -55 -40 -25 -10 15 UNITS 2.4965 -55 -40 -25 -10 20190-013 15 UNITS 20190-010 -0.0015 -55 -40 -25 -10 INPUT REFERRED OFFSET ERROR (%) 15 UNITS -0.015 -55 -40 -25 -10 Figure 9. Input Referred Offset Error vs. Temperature (Gain = 1, Analog Input Buffers Enabled) INPUT REFERRED OFFSET ERROR (%) 0.035 20190-012 INPUT REFERRED OFFSET ERROR (%) 15 UNITS 20190-009 INPUT REFERRED OFFSET ERROR (V) 60 Enhanced Product Enhanced Product AD7124-4-EP 450 15 UNITS 400 -0.2 ANALOG CURRENT (A) -0.4 -0.6 -0.8 300 250 200 150 100 -1.0 5 20 35 50 65 80 95 110 125 TEMPERATURE (C) 0 -55 -40 -25 -10 350 GAIN = 1, AIN BUFFERS OFF GAIN = 2 TO 8 GAIN = 1, AIN BUFFERS ON GAIN = 16 TO 128 300 800 600 400 200 50 65 80 95 110 125 GAIN = 1, AIN BUFFERS OFF GAIN = 2 TO 8 GAIN = 1, AIN BUFFERS ON GAIN = 16 TO 128 250 200 150 100 5 20 35 50 65 80 95 110 125 TEMPERATURE (C) Figure 16. Analog Current vs. Temperature (Full Power Mode) 0 -55 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C) Figure 18. Analog Current vs. Temperature (Low Power Mode) Rev. 0 | Page 15 of 17 20190-018 50 20190-016 0 -55 -40 -25 -10 35 Figure 17. Analog Current vs. Temperature (Mid Power Mode) ANALOG CURRENT (A) 1000 20 TEMPERATURE (C) Figure 15. Excitation Current Drift Matching (500 A) 1200 5 20190-017 50 -1.2 -55 -40 -25 -10 ANALOG CURRENT (A) GAIN = 1, AIN BUFFERS OFF GAIN = 2 TO 8 GAIN = 1, AIN BUFFERS ON GAIN = 16 TO 128 350 20190-015 EXCITATION CURRENT MISMATCH (%) 0 AD7124-4-EP 50 40 30 20 0 -55 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C) 20190-019 10 Figure 19. Digital Current vs. Temperature 6 UNITS 1.0 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -55 -40 -25 -10 5 20 35 50 65 80 95 TEMPERATURE (C) 2 1 0 -1 -2 -3 -55 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C) Figure 21. Internal Oscillator Error vs. Temperature 110 125 20190-027 TEMPERATURE SENSOR ERROR (%) 1.2 15 UNITS Figure 20. Temperature Sensor Accuracy Rev. 0 | Page 16 of 17 20190-028 DIGITAL CURRENT (A) 60 3 FULL POWER MID POWER LOW POWER INTERNAL OSCILLATOR ERROR (%) 70 Enhanced Product Enhanced Product AD7124-4-EP OUTLINE DIMENSIONS 7.90 7.80 7.70 24 13 4.50 4.40 4.30 1 6.40 BSC 12 PIN 1 0.65 BSC 0.15 0.05 0.30 0.19 0.10 COPLANARITY 1.20 MAX SEATING PLANE 0.20 0.09 8 0 0.75 0.60 0.45 COMPLIANT TO JEDEC STANDARDS MO-153-AD Figure 22. 24-Lead Thin Shrink Small Outline Package [TSSOP] (RU-24) Dimensions shown in millimeters ORDERING GUIDE Model1 AD7124-4TRUZ-EP AD7124-4TRUZ-EP-R7 1 Temperature Range -55C to +125C -55C to +125C Package Description 24-Lead Thin Shrink Small Outline Package [TSSOP] 24-Lead Thin Shrink Small Outline Package [TSSOP] Z = RoHS Compliant Part. (c)2019 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D20190-0-4/19(0) Rev. 0 | Page 17 of 17 Package Option RU-24 RU-24