ASM2I99456-32-LR - Alliance Semiconductor

June 2005 ASM2I99456

rev 0.2

Alliance Semiconductor

2575, Augustine Drive • Santa Clara, CA • Tel: 408.855.4900 • Fax: 408.855.4999 • www.alsc.com

Notice: The information in this document is subject to change without notice.

3.3V/2.5V LVCMOS Clock Fanout Buffer

Features

 Configurable 10 outputs LVCMOS Clock

distribution buffer

 Compatible to single, dual and mixed 3.3V/2.5V

Voltage supply

 Wide range output clock frequency up to

250MHz

 Designed for mid-range to high-performance

telecom, networking and computer applications

 Supports high-performance differential clocking

applications

 Max. output skew of 200pS

(150pS within one bank)

 Selectable output configurations per output bank

 Tristatable outputs

 32 LQFP and TQFP Packages

 Ambient Operating temperature range of

-40 to 85°C

 Pin and Function compatible to MPC9456

Functional Description

The ASM2I99456 is a 2.5V and 3.3V compatible 1:10 clock

distribution buffer designed for low-Voltage mid-range to

high-performance telecom, networking and computing

applications. Both 3.3V, 2.5V and dual supply voltages are

supported for mixed-voltage applications. The ASM2I99456

offers 10 low-skew outputs and a differential LVPECL clock

input. The outputs are configurable and support 1:1 and 1:2

output to input frequency ratios. The ASM2I99456 is

specified for the extended temperature range of –40 to

85°C.

The ASM2I99456 is a full static design supporting clock

frequencies up to 250 MHz. The signals are generated and

retimed on-chip to ensure minimal skew between the three

output banks.

Each of the three output banks can be individually supplied

by 2.5V or 3.3V supporting mixed voltage applications. The

FSELx pins choose between division of the input reference

frequency by one or two. The frequency divider can be set

individually for each of the three output banks. The

ASM2I99456 can be reset and the outputs are disabled by

deasserting the MR/OE pin (logic high state). Asserting

MR/OE will enable the outputs.

All control inputs accept LVCMOS signals while the outputs

provide LVCMOS compatible levels with the capability to

drive terminated 50 transmission lines. The clock input is

low voltage PECL compatible for differential clock

distribution support. Please consult the ASM2I99446

specification for a full CMOS compatible device. For series

terminated transmission lines, each of the ASM2I99456

outputs can drive one or two traces giving the devices an

effective fanout of 1:20. The device is packaged in a

7x7 mm2 32-lead LQFP and TQFP Packages.

June 2005 ASM2I99456

rev 0.2

3.3V/2.5V LVCMOS Clock Fanout Buffer 2 of 14

Notice: The information in this document is subject to change without notice.

Block Diagram

Pin Configuration

0

1

CLK

CLK÷ 2

QA0

QA1

QA2

QB0

QB1

QB2

QC0

QC1

QC2

QC3

Bank A

Bank B

Bank C

25K

VCC/2

A

SM2I99456 Lo

g

ic Dia

g

ram

PCLK

FSELA

FSELB

FSELC

MR/OE

0

1

0

1

VCCA

QA2

GND

QA1

VCCA

QA0

GND

MR/OE

QC3 25

24

26

27

28

29

30

31

32

1 2345678

9

10

11

12

13

14

15

16

17181920212223

NC

VCC

PECL_CL

K

PCL_CL

K

FSEL

A

FSELB

FSELC

GND

QC2

VCCC

QC1

GND

QC0

VCCC

VCCB

QB2

GND

QB1

VCCB

QB0

GND

ASM2I99456

VCCB is internally connected to VCC

June 2005 ASM2I99456

rev 0.2

3.3V/2.5V LVCMOS Clock Fanout Buffer 3 of 14

Notice: The information in this document is subject to change without notice.

Table 1. Pin Configuration

Pin Number Pin I/O Type Function

3

4

PECL_CLK,

PECL_CLK Input LVPECL Differential Clock reference

Low Voltage positive ECL input

5,6,7 FSELA, FSELB,

FSELC Input LVCMOS Output bank divide select input

32

MR/OE Input LVCMOS Internal reset and output tristate control

8,11,15,20,24,27,31 GND Supply Negative Voltage supply output bank (GND)

25,29

18,22

9,13, 17

VCCA,

VCCB1,

VCCC

Supply Positive Voltage supply for output banks

2 VCC Supply Positive Voltage supply core (VCC)

30,28,26 QA0 - QA2 Output LVCMOS Bank A Outputs

23,21,19 QB0 - QB2 Output LVCMOS Bank B Outputs

10,12,14,16 QC0 - QC3 Output LVCMOS Bank C Outputs

1 NC - - No Connect

Note:1 VCCB is internally connected to VCC.

Table 2. Supported Single and Dual Supply Configurations

Supply voltage

configuration VCC1 VCCA2 VCCB3 VCCC4 GND

3.3V 3.3V 3.3V 3.3V 3.3V 0V

Mixed voltage supply 3.3V 3.3V or 2.5V 3.3V 3.3V or 2.5V 0 V

2.5V 2.5V 2.5V 2.5V 2.5V 0 V

Note: 1 VCC is the positive power supply of the device core and input circuitry. VCC voltage defines the input threshold and levels

2 VCCA is the positive power supply of the bank A outputs. VCCA voltage defines bank A output levels

3 VCCB is the positive power supply of the bank B outputs. VCCB voltage defines bank B output levels. VCCB is internally connected to VCC.

4 VCCC is the positive power supply of the bank C outputs. VCCC voltage defines bank C output levels

Table 3. Function Table (Controls)

Control Default 0 1

FSELA 0 fQA0:2 = fREF f

QA0:2 = fREF ÷2

FSELB 0 fQB0:2 = fREF f

QB0:2 = fREF ÷2

FSELC 0 fQC0:3 = fREF f

QC0:3 = fREF ÷2

MR/OE 0 Outputs enabled Internal reset

Outputs disabled (tristate)

Table 4. Absolute Maximum Ratings1

Symbol Characteristics Min Max Unit Condition

VCC Supply Voltage -0.3 4.6 V

VIN DC Input Voltage -0.3 VCC+0.3 V

VOUT DC Output Voltage -0.3 VCC+0.3 V

IIN DC Input Current ±20 mA

IOUT DC Output Current ±50 mA

TS Storage temperature -40 125 °C

Note: These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect

device reliability.

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3.3V/2.5V LVCMOS Clock Fanout Buffer 4 of 14

Notice: The information in this document is subject to change without notice.

Table 5. General Specifications

Symbol Characteristics Min Typ Max Unit Condition

VTT Output Termination Voltage VCC ÷2 V

MM ESD Protection (Machine Model) 200 V

HBM ESD Protection (Human Body Model) 2000 V

LU Latch–Up Immunity 200 mA

CPD Power Dissipation Capacitance 10 pF Per output

CIN Input Capacitance 4.0 pF

Table 6. DC Characteristics (VCC = VCCA = VCCB = VCCC = 3.3V ± 5%, TA = –40 to +85°C)

Symbol Characteristics Min Typ Max Unit Condition

VIH Input high voltage 2.0 VCC + 0.3 V LVCMOS

VIL Input low voltage -0.3 0.8 V LVCMOS

VPP Peak-to-peak input voltage PCLK 250 mV LVPECL

VCMR1 Common Mode Range PCLK 1.1 VCC-0.6 V LVPECL

IIN Input current2 200 µA VIN=GND or

VIN=VCC

VOH Output High Voltage 2.4 V IOH=-24 mA3

VOL Output Low Voltage 0.55

0.30

V

IOL= 24mA2

IOL= 12mA

ZOUT Output impedance 14 - 17 

ICCQ4 Maximum Quiescent Supply Current 2.0 mA All VCC Pins

Note: 1 VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR range and the input

swing lies within the VPP (DC) specification.

2 Input pull-up / pull-down resistors influence input current.

3 The ASM2I99456 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line to

a termination voltage of VTT. Alternatively, the device drives up to two 50 series terminated transmission lines.

4 ICCQ is the DC current consumption of the device with all outputs open and the input in its default state or open

June 2005 ASM2I99456

rev 0.2

3.3V/2.5V LVCMOS Clock Fanout Buffer 5 of 14

Notice: The information in this document is subject to change without notice.

Table 7. AC Characteristics (VCC = VCCA = VCCB = VCCC = 3.3V ± 5%, TA = –40 to +85°C)1

Symbol Characteristics Min Typ Max Unit Condition

fref Input Frequency 0 2502 MHz

MHz FSELx=0

fMAX Maximum Output

Frequency

÷1 output

÷2 output

0

0 2502

125 MHz FSELx=1

VPP Peak-to-peak input voltage PCLK 500 1000 mV LVPECL

VCMR3 Common Mode Range PCLK 1.3 VCC-0.8 V LVPECL

tP, REF Reference Input Pulse Width 1.4 nS

tr, tf PCLK Input Rise/Fall Time 1.04 nS 0.8 to 2.0V

tPLH nS

tPHL Propagation delay CCLK to any Q

CCLK to any Q

2.2

2.8

4.45

4.2 nS

tPLZ, HZ Output Disable Time 10 nS

tPZL, LZ Output Enable Time 10 nS

tsk(O)

Output-to-output Skew

Within one bank

Any output bank, same output divider

Any output, Any output divider

150

200

350

pS

tsk(PP) Device-to-device Skew 2.25 nS

tSK(P) Output pulse skew5 200 pS

DCQ Output Duty Cycle ÷1 output

÷2 output

47

45

50

53

55

%

DCREF = 50%

DCREF = 25%-75%

tr, tf Output Rise/Fall Time 0.1 1.0 nS 0.55 to 2.4V

Note: 1 AC characteristics apply for parallel output termination of 50 to VTT.

2 The ASM2I99456 is functional up to an input and output clock frequency of 350MHz and is characterized up to 250 MHz.

3 VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and the input

swing lies within the VPP (AC) specification.

4 Violation of the 1.0nS maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input pulse width,

output duty cycle and maximum frequency specifications.

5 Output pulse skew is the absolute difference of the propagation delay times: | tPLH - tPHL |.

Table 8. DC Characteristics (VCC = VCCA = VCCB = VCCC = 2.5V ± 5%, TA = –40 to +85°C)

Symbol Characteristics Min Typ Max Unit Condition

VIH Input high voltage 1.7 VCC + 0.3 V LVCMOS

VIL Input low voltage -0.3 0.7 V LVCMOS

VPP Peak-to-peak Input voltage PCLK 250 mV LVPECL

VCMR1 Common Mode Range PCLK 1.1 VCC-0.7 V LVPECL

VOH Output High Voltage 1.8 V IOH=-24 mA 2

VOL Output Low Voltage 0.6 V IOL= 15 mA

ZOUT Output impedance 17 - 202 

IIN Input current3 ±200 µA VIN=GND or VIN=VCC

ICCQ4 Maximum Quiescent Supply Current 2.0 mA All VCC Pins

Note:1 VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR range and the input

swing lies within the VPP (DC) specification.

2 The ASM2I99456 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated

transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 series terminated transmission lines.

3 Input pull-up / pull-down resistors influence input current.

4 ICCQ is the DC current consumption of the device with all outputs open and the input in its default state or open

June 2005 ASM2I99456

rev 0.2

3.3V/2.5V LVCMOS Clock Fanout Buffer 6 of 14

Notice: The information in this document is subject to change without notice.

Table 9. AC Characteristics (VCC = VCCA = VCCB = VCCC = 2.5V ± 5%, TA = –40 to +85°C)1

Symbol Characteristics Min Typ Max Unit Condition

fref Input Frequency 0 2502 MHz

fMAX Maximum Output Frequency ÷1 output

÷2 output

0

0 2502

125

MHz

FSELx=0

FSELx=1

VPP Peak-to-peak input voltage PCLK 500 1000 mV LVPECL

VCMR3 Common Mode Range PCLK 1.1 VCC-0.7 V LVPECL

tP, REF Reference Input Pulse Width 1.4 nS

tr, tf PCLK Input Rise/Fall Time 1.04 nS 0.7 to 1.7V

tPLH

tPHL Propagation delay PCLK to any Q

PCLK to any Q

2.6

2.6 5.6

5.5

nS

tPLZ, HZ Output Disable Time 10 nS

tPZL, LZ Output Enable Time 10 nS

tsk(O)

Output-to-output Skew

Within one bank

Any output bank, same output divider

Any output, Any output divider

150

200

350

pS

tsk(PP) Device-to-device Skew 3.0 nS

tSK(P) Output pulse skew5 200 pS

DCQ Output Duty Cycle ÷1 or ÷2 output 45 50 55 % DCREF = 50%

tr, tf Output Rise/Fall Time 0.1 1.0 nS 0.6 to 1.8V

Note: 1 AC characteristics apply for parallel output termination of 50 to VTT.

2 The ASM2I99456 is functional up to an input and output clock frequency of 350MHz and is characterized up to 250 MHz.

3 VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and the input

swing lies within the VPP (AC) specification.

4 Violation of the 1.0nS maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input pulse width,

output duty cycle and maximum frequency specifications.

5 Output pulse skew is the absolute difference of the propagation delay times: | tPLH - tPHL |.

Table 10. AC Characteristics (VCC = 3.3V ± 5%, VCCA = VCCB = VCCC = 2.5V ± 5% or 3.3V ± 5%,TA = –40 to +85°C),1,2

Symbol Characteristics Min Typ Max Unit Condition

tsk(O)

Output-to-output Skew Within one bank

Any output bank, same output divider

Any output, Any output divider

150

250

350

pS

tsk(PP) Device-to-device Skew 2.5 nS

tPLH,HL Propagation delay PCLK to any Q See 3.3V table

tSK(P) Output pulse skew3

250 pS

DCQ Output Duty Cycle ÷1 or ÷2 output 45 50 55 % DCREF = 50%

Note: 1 AC characteristics apply for parallel output termination of 50 to VTT.

2 For all other AC specifications, refer to 2.5V or 3.3V tables according to the supply voltage of the output bank.

3 Output pulse skew is the absolute difference of the propagation delay times: | tPLH - tPHL |.

June 2005 ASM2I99456

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3.3V/2.5V LVCMOS Clock Fanout Buffer 7 of 14

Notice: The information in this document is subject to change without notice.

Applications Information

Driving Transmission Lines

The ASM2I99456 clock driver was designed to drive high

speed signals in a terminated transmission line

environment. To provide the optimum flexibility to the

user the output drivers were designed to exhibit the

lowest impedance possible. With an output impedance of

less than 20Ω the drivers can drive either parallel or

series terminated transmission lines. In most high

performance clock networks point-to-point distribution of

signals is the method of choice. In a point-to-point

scheme either series terminated or parallel terminated

transmission lines can be used. The parallel technique

terminates the signal at the end of the line with a

50Ω resistance to VCC÷2.

This technique draws a fairly high level of DC current and

thus only a single terminated line can be driven by each

output of the ASM2I99456 clock driver. For the series

terminated case however there is no DC current draw,

thus the outputs can drive multiple series terminated

lines. Figure 1. “Single versus Dual Transmission Lines”

illustrates an output driving a single series terminated line

versus two series terminated lines in parallel. When taken

to its extreme the fanout of the ASM2I99456 clock driver

is effectively doubled due to its capability to drive multiple

lines.

Figure 1. Single versus Dual Transmission Lines

The waveform plots in Figure 2. “Single versus Dual Line

Termination Waveforms” show the simulation results of

an output driving a single line versus two lines. In both

cases the drive capability of the ASM2I99456 output

buffer is more than sufficient to drive 50Ω transmission

lines on the incident edge. Note from the delay

measurements in the simulations a delta of only 43pS

exists between the two differently loaded outputs. This

suggests that the dual line driving need not be used

exclusively to maintain the tight output-to-output skew of

the ASM2I99456. The output waveform in Figure 2.

“Single versus Dual Line Termination Waveforms” shows

a step in the waveform, this step is caused by the

impedance mismatch seen looking into the driver. The

parallel combination of the 36Ω series resistor plus the

output impedance does not match the parallel

combination of the line impedances. The voltage wave

launched down the two lines will equal:

VL = VS ( Z0 ÷ (RS+R0 +Z0))

Z0 = 50Ω || 50Ω

RS = 36Ω || 36Ω

R0 = 14Ω

VL = 3.0 ( 25 ÷ (18+14+25)

= 1.31V

At the load end the voltage will double, due to the near

unity reflection coefficient, to 2.5V. It will then increment

towards the quiescent 3.0V in steps separated by one

round trip delay (in this case 4.0nS).

Figure 2. Single versus Dual Waveforms

Since this step is well above the threshold region it will

not cause any false clock triggering, however designers

may be uncomfortable with unwanted reflections on the

line. To better match the impedances when driving

multiple lines the situation in Figure 3. “Optimized Dual

Line Termination” should be used. In this case the series

terminating resistors are reduced such that when the

parallel combination is added to the output buffer

impedance the line impedance is perfectly matched.

14Ω + 22Ω || 22Ω = 50Ω || 50Ω

25Ω = 25Ω

Figure 3. Optimized Dual Line Termination

ASM2I99456

OUTPUT BUFFER

14

Z0=50

RS=22

Z0=50

RS=22

ASM2I99456

OUTPUT BUFFER

14

Z0=50

RS=36

ASM2I99456

OUTPUT BUFFER

14

Z0=50

RS=36

Z0=50

RS=36

3.0

2.5

2.0

1.5

1.0

0.5

0

2

4

6

8

10

12

14

TIME (nS)

VOLTAGE

(

V

)

In

OutA

tD= 3.8956 OutB

tD = 3.9386

June 2005 ASM2I99456

rev 0.2

3.3V/2.5V LVCMOS Clock Fanout Buffer 8 of 14

Notice: The information in this document is subject to change without notice.

VCC

VCC ÷2

GND

DC (tP ÷T0  100%)

tP

T0

The time from the output controlled edge to the

non-controlled edge, divided by the time output

controlled edge, expressed as a percentage.

tR

VCC = 3.3V VCC = 2.5V

2.4 1.8V

0.55 0.6V

tF

Fi

g

ure 5. Out

p

ut Transition Time Test Reference

PCLK

QX

VPP

VCMR

VCC

VCC ÷2

GND

tP(LH) tP(HL)

Figure 6. Propagation Delay (tPD) Test Reference

Figure 7. Output Duty Cycle (DC)

tSK(LH) tSK(HL)

VOH

VCC ÷2

GND

VCC

VCC ÷2

GND

The pin-to-pin skew is defined as the worst case

difference in propagation delay between any similar

delay path within a single device

Figure 8. Output-to- Output Skew tSK(O)

tR

VCC = 3.3V VCC = 2.5V

2.4 1.8V

0.55 0.6V

tF

Fi

g

ure 9. Out

p

ut Transition Time Test Reference

Differential

Pulse Generator

Z=50Ω

Z0=50

Ω

RT=50Ω

VCC – 2V

VTT

RT=50Ω

Fi

g

ure 4. PCLK ASM2I99456 AC Test Reference for

V

CC = 3.3V and

V

CC = 2.5

V

Z0=50Ω

ASM2I99456 DUT

June 2005 ASM2I99456

rev 0.2

3.3V/2.5V LVCMOS Clock Fanout Buffer 9 of 14

Notice: The information in this document is subject to change without notice.

Power Consumption of the ASM2I99456 and

Thermal Management

The ASM2I99456 AC specification is guaranteed for the

entire operating frequency range up to 250MHz. The

ASM2I99456 power consumption and the associated

long-term reliability may decrease the maximum

frequency limit, depending on operating conditions such

as clock frequency, supply voltage, output loading,

ambient temperature, vertical convection and thermal

conductivity of package and board. This section

describes the impact of these parameters on the junction

temperature and gives a guideline to estimate the

ASM2I99456 die junction temperature and the associated

device reliability.

Table 11. Die junction temperature and MTBF

Junction temperature (°C) MTBF (Years)

100 20.4

110 9.1

120 4.2

130 2.0

Increased power consumption will increase the die

junction temperature and impact the device reliability

(MTBF). According to the system-defined tolerable

MTBF, the die junction temperature of the ASM2I99456

needs to be controlled and the thermal impedance of the

board/package should be optimized. The power

dissipated in the ASM2I99456 is represented in

equation 1.

Where ICCQ is the static current consumption of the

ASM2I99456, CPD is the power dissipation capacitance

per output, (Μ)ΣCL represents the external capacitive

output load, N is the number of active outputs (N is

always 12 in case of the ASM2I99456). The ASM2I99456

supports driving transmission lines to maintain high signal

integrity and tight timing parameters. Any transmission

line will hide the lumped capacitive load at the end of the

board trace, therefore, ΣCL is zero for controlled

transmission line systems and can be eliminated from

equation 1. Using parallel termination output termination

results in equation 2 for power dissipation.

In equation 2, P stands for the number of outputs with a

parallel or thevenin termination, VOL, IOL, VOH and IOH are

a function of the output termination technique and DCQ is

the clock signal duty cycle. If transmission lines are used

ΣCL is zero in equation 2 and can be eliminated. In

general, the use of controlled transmission line

techniques eliminates the impact of the lumped capacitive

loads at the end lines and greatly reduces the power

dissipation of the device. Equation 3 describes the die

junction temperature TJ as a function of the power

consumption.

Where Rthja is the thermal impedance of the package

(junction to ambient) and TA is the ambient temperature.

According to Table 11, the junction temperature can be

used to estimate the long-term device reliability. Further,

combining equation 1 and equation 2 results in a

maximum operating frequency for the ASM2I99456 in a

series terminated transmission line system, equation 4.

June 2005 ASM2I99456

rev 0.2

3.3V/2.5V LVCMOS Clock Fanout Buffer 10 of 14

Notice: The information in this document is subject to change without notice.

TJ,MAX should be selected according to the MTBF

system requirements and Table 11. Rthja can be derived

from Table 12. The Rthja represent data based on 1S2P

boards, using 2S2P boards will result in a lower thermal

impedance than indicated below.

Table 12. Thermal package impedance of the

32LQFP

Convection,

LFPM

Rthja (1P2S

board), °C/W

Rthja (2P2S

board), °C/W

Still air 86 61

100 lfpm 76 56

200 lfpm 71 54

300 lfpm 68 53

400 lfpm 66 52

500 lfpm 60 49

If the calculated maximum frequency is below 350 MHz, it

becomes the upper clock speed limit for the given

application conditions. The following eight derating charts

describe the safe frequency operation range for the

ASM2I99456. The charts were calculated for a maximum

tolerable die junction temperature of 110°C (120°C),

corresponding to an estimated MTBF of 9.1 years

(4 years), a supply voltage of 3.3V and series terminated

transmission line or capacitive loading. Depending on a

given set of these operating conditions and the available

device convection a decision on the maximum operating

frequency can be made.

June 2005 ASM2I99456

rev 0.2

3.3V/2.5V LVCMOS Clock Fanout Buffer 11 of 14

Notice: The information in this document is subject to change without notice.

Package Information

32-lead LQFP Package

SECTION A-A

Dimensions

Inches Millimeters

Symbol

Min Max Min Max

A …. 0.0630 … 1.6

A1 0.0020 0.0059 0.05 0.15

A2 0.0531 0.0571 1.35 1.45

D 0.3465 0.3622 8.8 9.2

D1 0.2717 0.2795 6.9 7.1

E 0.3465 0.3622 8.8 9.2

E1 0.2717 0.2795 6.9 7.1

L 0.0177 0.0295 0.45 0.75

L1 0.03937 REF 1.00 REF

T 0.0035 0.0079 0.09 0.2

T1 0.0038 0.0062 0.097 0.157

b 0.0118 0.0177 0.30 0.45

b1 0.0118 0.0157 0.30 0.40

R0 0.0031 0.0079 0.08 0.20

e 0.031 BASE 0.8 BASE

a 0° 7° 0° 7°

June 2005 ASM2I99456

rev 0.2

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Notice: The information in this document is subject to change without notice.

32-lead TQFP Package

SECTION A-A

Dimensions

Inches Millimeters

Symbol

Min Max Min Max

A …. 0.0472 … 1.2

A1 0.0020 0.0059 0.05 0.15

A2 0.0374 0.0413 0.95 1.05

D 0.3465 0.3622 8.8 9.2

D1 0.2717 0.2795 6.9 7.1

E 0.3465 0.3622 8.8 9.2

E1 0.2717 0.2795 6.9 7.1

L 0.0177 0.0295 0.45 0.75

L1 0.03937 REF 1.00 REF

T 0.0035 0.0079 0.09 0.2

T1 0.0038 0.0062 0.097 0.157

b 0.0118 0.0177 0.30 0.45

b1 0.0118 0.0157 0.30 0.40

R0 0.0031 0.0079 0.08 0.2

a 0° 7° 0° 7°

e 0.031 BASE 0.8 BASE

June 2005 ASM2I99456

rev 0.2

3.3V/2.5V LVCMOS Clock Fanout Buffer 13 of 14

Notice: The information in this document is subject to change without notice.

Ordering Information

Part Number Marking Package Type Operating Range

ASM2I99456-32-LT ASM2I99456L 32-pin LQFP, Tray Industrial

ASM2I99456-32-LR ASM2I99456L 32-pin LQFP –Tape and Reel Industrial

ASM2I99456G-32-LT ASM2I99456GL 32-pin LQFP, Tray, Green Industrial

ASM2I99456G-32-LR ASM2I99456GL 32-pin LQFP –Tape and Reel, Green Industrial

ASM2I99456-32-ET ASM2I99456E 32-pin TQFP, Tray Industrial

ASM2I99456-32-ER ASM2I99456E 32-pin TQFP –Tape and Reel Industrial

ASM2I99456G-32-ET ASM2I99456GE 32-pin TQFP, Tray, Green Industrial

ASM2I99456G-32-ER ASM2I99456GE 32-pin TQFP –Tape and Reel, Green Industrial

Device Ordering Information

ASM2I99456G-32-LR

Licensed under US patent #5,488,627, #6,646,463 and #5,631,920.

O = SOT U = MSOP

S = SOIC E = TQFP

T = TSSOP L = LQFP

A = SSOP U = MSOP

V = TVSOP P = PDIP

B = BGA D = QSOP

Q

=

Q

FN X = SC-70

DEVICE PIN COUNT

X= Automotive I= Industrial P or n/c = Commercial

(-40C to +125C) (-40C to +85C) (0C to +70C)

1 = Reserved 6 = Power Management

2 = Non PLL based 7 = Power Management

3 = EMI Reduction 8 = Power Management

4 = DDR support products 9 = Hi Performance

5

=

STD Zero Delay Buffer

0

=

Reserved

ALLIANCE SEMICONDUCTOR MIXED SIGNAL PRODUCT

PART NUMBER

F = LEAD FREE AND RoHS COMPLIANT PART

G = GREEN PACKAGE

R = Tape & reel, T = Tube or Tray

June 2005 ASM2I99456

rev 0.2

3.3V/2.5V LVCMOS Clock Fanout Buffer 14 of 14

Notice: The information in this document is subject to change without notice.

trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their

respective companies. Alliance reserves the right to make changes to this document and its products at any time without

notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein

represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this

data at any time, without notice. If the product described herein is under development, significant changes to these

specifications are possible. The information in this product data sheet is intended to be general descriptive information for

potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or

customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product

described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products

including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual

property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance).

All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of

products from Alliance does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any

other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical

components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant

injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer

assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use.

Alliance Semiconductor Corporation

2575, Augustine Drive,

Santa Clara, CA 95054

Tel# 408-855-4900

Fax: 408-855-4999

www.alsc.com

Part Number: ASM2I99456

Document Version: 0.2

Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to Alliance Semiconductor, dated 11-11-2003