1. General description
The 74HC164; 74HCT 164 are hig h- speed Si-g ate CMOS d evices and ar e pin co mpatible
with Low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC164; 74HCT164 ar e 8-bit edge-triggered shift registers with serial data entry
and an output from each of the eight stages. Data is entered serially through one of two
inputs (DSA or DSB); either input can be used as an active HIGH enable for data entry
through the other input. Both inputs must be connected togethe r or an unu se d input must
be tied HIGH.
Data shifts one place to the right on each LOW-to-HIGH transition of the clock (CP) input
and enters into Q0, which is the logical AND o f the two data inputs (DSA and DSB) that
existed one set-up time prior to the rising clock edge.
A LOW level on the master reset (MR) input overrides all other inputs and clears the
register asynchronously, forcing all outputs LOW.
2. Features
Input levels:
For 74HC164: CMOS level
For 74HCT164: TTL level
Gated serial dat a inputs
Asynchronous master reset
Complies with JEDEC standard no. 7A
ESD protection:
HBM JESD22-A114F exceeds 2 000 V
MM JESD22-A115-A exceed s 200 V.
Multiple package options
Specifie d from −40 °C to +85 °C and −40 °C to +125 °C.
74HC164; 74HCT164
8-bit serial-in, parallel-out shift register
Rev. 04 — 2 February 2010 Product data sheet
74HC_HCT164_4 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 04 — 2 February 2010 2 of 20
NXP Semiconductors 74HC164; 74HCT164
8-bit serial-in, parallel-out shift register
3. Ordering information
4. Functional diagram
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74HC164N −40 °C to +125 °CDIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1
74HCT164N
74HC164D −40 °C to +125 °CSO14 plastic small outlin e package; 14 leads; body width
3.9 mm SOT108-1
74HCT164D
74HC164DB −40 °C to +125 °CSSOP14 plastic shrink small outline package; 14 leads; body
width 5.3 mm SOT337-1
74HCT164DB
74HC164PW −40 °C to +125 °CTSSOP14 plastic thin shrink small outline package; 14 leads;
body width 4.4 mm SOT402-1
74HCT164PW
74HC164BQ −40 °C to +125 °CDHVQFN14 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 14 terminals;
body 2.5 × 3 × 0.85 mm
SOT762-1
74HCT164BQ
Fig 1. Logic symbol Fig 2. IEC logic symbol
001aac423
3
1
24
5
6
10
11
12
13
8
9
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
CP
DSB
DSA
MR
001aac424
9
8
&3
1
2
4
5
6
10
11
13
12
R
C1/
1D
SRG8
Fig 3. Logic diag ra m
001aac42
5
1
2
310136412511
8
9
Q0 Q1 Q2
8-BIT SERIAL−IN/PARALLEL−OUT
SHIFT REGISTER
Q3 Q4 Q5 Q6 Q7
DSB
CP
MR
DSA
74HC_HCT164_4 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 04 — 2 February 2010 3 of 20
NXP Semiconductors 74HC164; 74HCT164
8-bit serial-in, parallel-out shift register
5. Pinning information
5.1 Pinning
Fig 4. Functional di ag ram
001aac61
6
Q0
D
FF1
Q
CP
RD
CP
DSB
DSA
MR
Q1
D
FF2
Q
CP
RD
Q2
D
FF3
Q
CP
RD
Q3
D
FF4
Q
CP
RD
Q4
D
FF5
Q
CP
RD
Q5
D
FF6
Q
CP
RD
Q6
D
FF7
Q
CP
RD
Q7
D
FF8
Q
CP
RD
(1) The substrate is attached to this pad using conductive
die attach material. It can not be used as supply pin or
input. It is recommended that no connection is made at
all.
Fig 5. Pin configuratio n DIP14, SO14, (T)SSOP14 Fig 6. Pin configuration DHVQFN14
74HC164
74HCT164
DSA VCC
DSB Q7
Q0 Q6
Q1 Q5
Q2 Q4
Q3 MR
GND CP
001aal390
1
2
3
4
5
6
78
10
9
12
11
14
13
001aal39
1
74HC164
74HCT164
GND
(1)
Transparent top view
Q3 MR
Q2 Q4
Q1 Q5
Q0 Q6
DSB Q7
GND
CP
DSA
V
CC
6 9
5 10
4 11
3 12
2 13
7
8
1
14
terminal 1
index area
74HC_HCT164_4 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 04 — 2 February 2010 4 of 20
NXP Semiconductors 74HC164; 74HCT164
8-bit serial-in, parallel-out shift register
5.2 Pin description
6. Functional description
[1] H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition
L = LOW voltage level
I = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition
q = lower case letters indicate the state of the referenced input one set-up time prior to the LOW-to-HIGH clock transition
↑ = LOW-to-HIGH clock transition
7. Limiting values
Table 2. Pin description
Symbol Pin Description
DSA 1data input
DSB 2data input
Q0 to Q7 3, 4, 5, 6, 10, 11, 12, 13 output
GND 7 ground (0 V)
CP 8clock input (LOW-to-HIGH, edge-triggered)
MR 9master reset input (active LOW)
VCC 14 positive supply voltage
Table 3. Function table[1]
Operating
modes Input Output
MR CP DSA DSB Q0 Q1 to Q7
Reset (clear) L X X X L L to L
Shift H↑l l L q0 to q6
H↑l h L q0 to q6
H↑hl Lq0 to q6
H↑h h H q0 to q6
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage −0.5 +7 V
IIK input clamping current VI < −0.5 V or VI > VCC + 0.5 V [1] -±20 mA
IOK output clamping current VO < −0.5 V or VO > VCC + 0.5 V [1] -±20 mA
IOoutput curren t −0.5 V < VO < VCC + 0.5 V - ±25 mA
ICC supply current -50 mA
IGND ground current −50 -mA
Tstg storage temperature −65 +150 °C
74HC_HCT164_4 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 04 — 2 February 2010 5 of 20
NXP Semiconductors 74HC164; 74HCT164
8-bit serial-in, parallel-out shift register
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For DIP14 package: Ptot derates linearly with 12 mW/K above 70 °C.
For SO14 package: Ptot derates linearly with 8 mW/K above 70 °C.
For (T)SSOP14 packages: Ptot derates linearly with 5.5 mW/K above 60 °C.
For DHVQFN14 packages: Ptot derates linearly with 4.5 mW/K above 60 °C.
8. Recommended operating conditions
9. Static characteristics
Ptot total power dissipation [2]
DIP14 package -750 mW
SO14, (T)SSOP14 and
DHVQFN14 packages -500 mW
Table 4. Limiting values …continued
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
Table 5. Recommended operating con ditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter Conditions 74HC164 74HCT164 Unit
Min Typ Max Min Typ Max
VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V
VIinput voltage 0 - VCC 0 - VCC V
VOoutput voltage 0 - VCC 0 - VCC V
Tamb ambient temperature −40 +25 +125 −40 +25 +125 °C
Δt/ΔVinput transition rise and fall rate VCC = 2.0 V --625 ---ns/V
VCC = 4.5 V -1.67 139 -1.67 139 ns/V
VCC = 6.0 V --83 ---ns/V
Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 25 °C−40 °C to +85 °C−40 °C to +125 °CUnit
Min Typ Max Min Max Min Max
74HC164
VIH HIGH-level
input voltage VCC = 2.0 V 1.5 1.2 -1.5 -1.5 - V
VCC = 4.5 V 3.15 2.4 -3.15 -3.15 - V
VCC = 6.0 V 4.2 3.2 -4.2 -4.2 - V
VIL LOW-level
input voltage VCC = 2.0 V - 0.8 0.5 -0.5 -0.5 V
VCC = 4.5 V - 2.1 1.35 -1.35 -1.35 V
VCC = 6.0 V - 2.8 1.8 -1.8 -1.8 V
74HC_HCT164_4 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 04 — 2 February 2010 6 of 20
NXP Semiconductors 74HC164; 74HCT164
8-bit serial-in, parallel-out shift register
VOH HIGH-level
output voltage VI = VIH or VIL
IO = −20 μA; VCC = 2.0 V 1.9 2.0 -1.9 -1.9 - V
IO = −20 μA; VCC = 4.5 V 4.4 4.5 -4.4 -4.4 - V
IO = −20 μA; VCC = 6.0 V 5.9 6.0 -5.9 -5.9 - V
IO = −4.0 mA; VCC = 4.5 V 3.98 4.32 -3.84 -3.7 - V
IO = −5.2 mA; VCC = 6.0 V 5.48 5.81 -5.34 -5.2 - V
VOL LOW-level
output voltage VI = VIH or VIL
IO = 20 μA; VCC = 2.0 V - 0 0.1 -0.1 -0.1 V
IO = 20 μA; VCC = 4.5 V - 0 0.1 -0.1 -0.1 V
IO = 20 μA; VCC = 6.0 V - 0 0.1 -0.1 -0.1 V
IO = 4.0 mA; VCC = 4. 5 V - 0.15 0.26 -0.33 -0.4 V
IO = 5.2 mA; VCC = 6. 0 V - 0.16 0.26 -0.33 -0.4 V
IIinput leakage
current VI = VCC or GND;
VCC = 6.0 V - - ±0.1 -±1 - ±1μA
ICC supply current VI = VCC or GND; IO = 0 A;
VCC = 6.0 V - - 8.0 -80 -160 μA
CIinput
capacitance -3.5 - - - - - pF
74HCT164
VIH HIGH-level
input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 -2.0 -2.0 - V
VIL LOW-level
input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 -0.8 -0.8 V
VOH HIGH-level
output voltage VI = VIH or VIL; VCC = 4.5 V
IO = −20 μA4.4 4.5 -4.4 -4.4 - V
IO = −4.0 mA 3.98 4.32 -3.84 -3.7 - V
VOL LOW-level
output voltage VI = VIH or VIL; VCC = 4.5 V
IO = 20 μA; VCC = 4.5 V - 0 0.1 -0.1 -0.1 V
IO = 5.2 mA; VCC = 6. 0 V - 0.15 0.26 -0.33 -0.4 V
IIinput leakage
current VI = VCC or GND;
VCC = 6.0 V - - ±0.1 -±1 - ±1μA
ICC supply current VI = VCC or GND; IO = 0 A;
VCC = 6.0 V - - 8 - 80 -160 μA
ΔICC additional
supply current per input pin;
VI = VCC − 2.1 V; IO = 0 A;
other inputs at VCC or GND;
VCC = 4.5 V to 5.5 V
-100 360 -450 -490 μA
CIinput
capacitance -3.5 - - - - - pF
Table 6. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GN D (ground = 0 V).
Symbol Parameter Conditions 25 °C−40 °C to +85 °C−40 °C to +125 °CUnit
Min Typ Max Min Max Min Max
74HC_HCT164_4 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 04 — 2 February 2010 7 of 20
NXP Semiconductors 74HC164; 74HCT164
8-bit serial-in, parallel-out shift register
10. Dynamic characteristics
Table 7. Dynamic characteristics
GND = 0 V; tr = tf = 6 ns; CL = 50 pF; test circuit see Figure 10; unless otherwise specified
Symbol Parameter Conditions 25 °C−40 °C to +85 °C−40 °C to +125 °CUnit
Min Typ Max Min Max Min Max
74HC164
tpd propagation
delay CP to Qn; see Figure 7 [1]
VCC = 2.0 V -41 170 -215 -255 ns
VCC = 4.5 V -15 34 -43 -51 ns
VCC = 5.0 V; CL = 15 pF -12 - - - - - ns
VCC = 6.0 V -12 29 -37 -43 ns
tPHL HIGH to LOW
propagation
delay
MR to Qn; see Figure 8
VCC = 2.0 V -39 140 -175 -210 ns
VCC = 4.5 V -14 28 -35 -42 ns
VCC = 5.0 V; CL = 15 pF -11 - - - - - ns
VCC = 6.0 V -11 24 -30 -36 ns
tttransition time see Figure 7 [2]
VCC = 2.0 V -19 75 -95 -110 ns
VCC = 4.5 V - 7 15 -19 -22 ns
VCC = 6.0 V - 6 13 -16 -19 ns
tWpulse width CP HIGH or LOW;
see Figure 7
VCC = 2.0 V 80 14 -100 -120 -ns
VCC = 4.5 V 16 5 - 20 -24 -ns
VCC = 6.0 V 14 4 - 17 -20 -ns
MR LOW; see Figure 8
VCC = 2.0 V 60 17 -75 -90 -ns
VCC = 4.5 V 12 6 - 15 -18 -ns
VCC = 6.0 V 10 5 - 13 -15 -ns
trec recovery time MR to CP; see Figure 8
VCC = 2.0 V 60 17 -75 -90 -ns
VCC = 4.5 V 12 6 - 15 -18 -ns
VCC = 6.0 V 10 5 - 13 -15 -ns
tsu set-up time DSA, and DSB to CP;
see Figure 9
VCC = 2.0 V 60 8 - 75 -90 -ns
VCC = 4.5 V 12 3 - 15 -18 -ns
VCC = 6.0 V 10 2 - 13 -15 -ns
thhold time DSA, and DSB to CP;
see Figure 9
VCC = 2.0 V +4 −6 - 4 - 4 - ns
VCC = 4.5 V +4 −2 - 4 - 4 - ns
VCC = 6.0 V +4 −2 - 4 - 4 - ns
74HC_HCT164_4 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 04 — 2 February 2010 8 of 20
NXP Semiconductors 74HC164; 74HCT164
8-bit serial-in, parallel-out shift register
fmax maximum
frequency for Cp, see Figure 7
VCC = 2.0 V 623 - 5 - 4 - MHz
VCC = 4.5 V 30 71 -24 -20 -MHz
VCC = 5.0 V; CL = 15 pF -78 - - - - - MHz
VCC = 6.0 V 35 85 -28 -24 -MHz
CPD power
dissipation
capacitance
per package;
VI = GND to VCC
[3] -40 - - - - - pF
74HCT164
tpd propagation
delay CP to Qn; see Figure 7 [1]
VCC = 4.5 V -17 36 -45 -54 ns
VCC = 5.0 V; CL = 15 pF -14 - - - - - ns
tPHL HIGH to LOW
propagation
delay
MR to Qn; see Figure 8
VCC = 4.5 V -19 38 -48 -57 ns
VCC = 5.0 V; CL = 15 pF -16 - - - - - ns
tttransition time see Figure 7 [2]
VCC = 4.5 V - 7 15 -19 -22 ns
tWpulse width CP HIGH or LOW;
see Figure 7
VCC = 4.5 V 18 7 - 23 -27 -ns
MR LOW; see Figure 8
VCC = 4.5 V 18 10 -23 -27 -ns
trec recovery time MR to CP; see Figure 8
VCC = 4.5 V 16 7 - 20 -24 -ns
tsu set-up time DSA, and DSB to CP;
see Figure 9
VCC = 4.5 V 12 6 - 15 -18 -ns
thhold time DSA, and DSB to CP;
see Figure 9
VCC = 4.5 V +4 −2 - 4 - 4 - ns
fmax maximum
frequency for Cp, see Figure 7
VCC = 4.5 V 27 55 -22 -18 -MHz
VCC = 5.0 V; CL = 15 pF -61 - - - - - MHz
Table 7. Dynamic characteristics
GND = 0 V; tr = tf = 6 ns; CL = 50 pF; test circuit see Figure 10; unless otherwise specified
Symbol Parameter Conditions 25 °C−40 °C to +85 °C−40 °C to +125 °CUnit
Min Typ Max Min Max Min Max
74HC_HCT164_4 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 04 — 2 February 2010 9 of 20
NXP Semiconductors 74HC164; 74HCT164
8-bit serial-in, parallel-out shift register
[1] tpd is the same as tPHL and tPLH.
[2] tt is the same as tTHL and tTLH.
[3] CPD is used to determine the dynamic power dissipation (PD in μW):
PD = CPD × VCC2 × fi × N + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
∑ (CL × VCC2 × fo) = sum of outputs.
CPD power
dissipation
capacitance
per package;
VI = GND to VCC − 1.5 V [3] -40 - - - - - pF
Table 7. Dynamic characteristics
GND = 0 V; tr = tf = 6 ns; CL = 50 pF; test circuit see Figure 10; unless otherwise specified
Symbol Parameter Conditions 25 °C−40 °C to +85 °C−40 °C to +125 °CUnit
Min Typ Max Min Max Min Max
(1) Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 7. Waveforms showing the clock (CP) to output (Qn) propagation delays, the clock pulse width, the output
transition times and the maximum clock frequency
001aal39
2
CP input
Qn output
t
PHL
t
PLH
t
THL
t
TLH
t
W
V
OH
V
I
GND
V
OL
V
M
V
M
V
X
V
Y
1/f
max
Table 8. Measurement points
Type Input Output
VMVMVXVY
74HC164 0.5VCC 0.5VCC 0.1VCC 0.9VCC
74HCT164 1.3 V 1.3 V 0.1VCC 0.9VCC
74HC_HCT164_4 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 04 — 2 February 2010 10 of 20
NXP Semiconductors 74HC164; 74HCT164
8-bit serial-in, parallel-out shift register
(1) Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 8. Waveforms showing the master reset (MR) p ulse width, the master reset to output (Qn) propagation
delays and the master reset to clock (CP) re moval time
001aac42
7
MR input
CP input
Qn output
tPHL
tWfrec
VM
VI
GND
VI
VOH
VOL
GND
VM
VM
(1) Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
The shaded areas indicate when the input is permitted to change for predictable output performance.
Fig 9. Waveforms showing the data set-up and hold times for Dn inputs
001aac42
8
GND
GND
th
tsu
th
tsu
VM
VM
VM
VI
VOH
VOL
VI
Qn output
CP input
Dn input
74HC_HCT164_4 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 04 — 2 February 2010 11 of 20
NXP Semiconductors 74HC164; 74HCT164
8-bit serial-in, parallel-out shift register
Test data is given in Table 9.
Definitions test circuit:
RT = termination resistance should be equal to output impedance Zo of the pulse generator.
CL = load capacitance including jig and probe capacitance.
Fig 10. Test circuit for measuring switching times
001aah7
68
tW
tW
tr
tr
tf
VM
VI
negative
pulse
GND
VI
positive
pulse
GND
10 %
90 %
90 %
10 %
VMVM
VM
tf
VCC
DUT
RT
VIVO
CL
G
Table 9. Test data
Type Input Load Test
VItr, tfCL
74HC164 VCC 6.0 ns 15 pF, 50 pF tPLH, tPHL
74HCT164 3.0 V 6.0 ns 15 pF, 50 pF tPLH, tPHL
74HC_HCT164_4 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 04 — 2 February 2010 12 of 20
NXP Semiconductors 74HC164; 74HCT164
8-bit serial-in, parallel-out shift register
11. Package outline
Fig 11. Package outline SOT27-1 (DIP14)
UNIT A
max. 1 2 (1) (1)
b1cD (1)
Z
Ee M
H
L
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm
inches
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
SOT27-1 99-12-27
03-02-13
A
min. A
max. bmax.
w
ME
e1
1.73
1.13
0.53
0.38
0.36
0.23
19.50
18.55
6.48
6.20
3.60
3.05 0.2542.54 7.62 8.25
7.80
10.0
8.3 2.24.2 0.51 3.2
0.068
0.044
0.021
0.015
0.77
0.73
0.014
0.009
0.26
0.24
0.14
0.12 0.010.1 0.3 0.32
0.31
0.39
0.33 0.0870.17 0.02 0.13
050G04 MO-001 SC-501-14
MH
c
(e )
1
ME
A
L
seating plane
A1
wM
b1
e
D
A2
Z
14
1
8
7
b
E
pin 1 index
0 5 10 mm
scale
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
D
IP14: plastic dual in-line package; 14 leads (300 mil) SOT27
-1
74HC_HCT164_4 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 04 — 2 February 2010 13 of 20
NXP Semiconductors 74HC164; 74HCT164
8-bit serial-in, parallel-out shift register
Fig 12. Package outline SOT108-1 (SO14)
UNIT A
max. A1A2A3bpcD
(1) E(1) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm
inches
1.75 0.25
0.10
1.45
1.25 0.25 0.49
0.36
0.25
0.19
8.75
8.55
4.0
3.8 1.27 6.2
5.8
0.7
0.6
0.7
0.3 8
0
o
o
0.25 0.1
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
1.0
0.4
SOT108-1
X
wM
θ
A
A1
A2
bp
D
HE
Lp
Q
detail X
E
Z
e
c
L
vMA
(A )
3
A
7
8
1
14
y
076E06 MS-012
pin 1 index
0.069 0.010
0.004
0.057
0.049 0.01 0.019
0.014
0.0100
0.0075
0.35
0.34
0.16
0.15 0.05
1.05
0.041
0.244
0.228
0.028
0.024
0.028
0.012
0.01
0.25
0.01 0.004
0.039
0.016
99-12-27
03-02-19
0 2.5 5 mm
scale
O14: plastic small outline package; 14 leads; body width 3.9 mm SOT108
74HC_HCT164_4 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 04 — 2 February 2010 14 of 20
NXP Semiconductors 74HC164; 74HCT164
8-bit serial-in, parallel-out shift register
Fig 13. Package outline SOT337-1 (SSOP14)
UNIT A1A2A3bpcD
(1) E(1) eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.21
0.05
1.80
1.65 0.25 0.38
0.25
0.20
0.09
6.4
6.0
5.4
5.2 0.65 1.25 0.2
7.9
7.6
1.03
0.63
0.9
0.7
1.4
0.9
8
0
o
o
0.13 0.1
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
SOT337-1 99-12-27
03-02-19
(1)
wM
bp
D
HE
E
Z
e
c
vMA
X
A
y
17
14 8
θ
A
A1
A2
Lp
Q
detail X
L
(A )
3
MO-150
pin 1 index
0 2.5 5 mm
scale
SOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337
A
max.
2
74HC_HCT164_4 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 04 — 2 February 2010 15 of 20
NXP Semiconductors 74HC164; 74HCT164
8-bit serial-in, parallel-out shift register
Fig 14. Package outline SOT402-1 (TSSOP14)
UNIT A1A2A3bpcD
(1) E(2) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3 0.65 6.6
6.2
0.4
0.3
0.72
0.38
8
0
o
o
0.13 0.10.21
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
0.75
0.50
SOT402-1 MO-153 99-12-27
03-02-18
wM
bp
D
Z
e
0.25
17
14 8
θ
A
A1
A2
Lp
Q
detail X
L
(A )
3
HE
E
c
vMA
X
A
y
0 2.5 5 mm
scale
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402
A
max.
1.1
pin 1 index
74HC_HCT164_4 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 04 — 2 February 2010 16 of 20
NXP Semiconductors 74HC164; 74HCT164
8-bit serial-in, parallel-out shift register
Fig 15. Package outline SOT762-1 (DHVQFN14)
terminal 1
index area
0.51
A1Eh
b
UNIT ye
0.2
c
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 3.1
2.9
Dh
1.65
1.35
y1
2.6
2.4
1.15
0.85
e1
2
0.30
0.18
0.05
0.00 0.05 0.1
DIMENSIONS (mm are the original dimensions)
SOT762-1 MO-241 - - -- - -
0.5
0.3
L
0.1
v
0.05
w
0 2.5 5 mm
scale
SOT762-
1
D
HVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
1
4 terminals; body 2.5 x 3 x 0.85 mm
A(1)
max.
A
A1
c
detail X
y
y1C
e
L
Eh
Dh
e
e1
b
26
13 9
8
7
1
14
X
D
E
C
BA
02-10-17
03-01-27
terminal 1
index area
AC
C
B
vM
wM
E(1)
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
D(1)
74HC_HCT164_4 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 04 — 2 February 2010 17 of 20
NXP Semiconductors 74HC164; 74HCT164
8-bit serial-in, parallel-out shift register
12. Abbreviations
13. Revision history
Table 10. Abbreviations
Acronym Description
CMOS Complementary Metal-Oxide Semiconductor
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model
LSTTL Low-power Schottky Transistor-Transistor Logic
MM Machine Model
TTL Transistor-Transistor Logic
Table 11. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74HC_HCT164_4 20100202 Product data sheet -74HC_HCT164_3
Modifications: •The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
•Legal texts have been adapted to the new company name where appropriate.
•Added type number 74HC164BQ (DHVQFN14 / SOT762-1 package).
•For type numbers 74HC164D and 74HCT164D: sot number SOT108-2 changed to
SOT108-1.
74HC_HCT164_3 20050404 Product data sheet -74HC_HCT164_ CNV_2
74HC_HCT164_CNV_2 19901201 Product specification - -
74HC_HCT164_4 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 04 — 2 February 2010 18 of 20
NXP Semiconductors 74HC164; 74HCT164
8-bit serial-in, parallel-out shift register
14. Legal information
14.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of de vice(s) descr ibed in th is document m ay have cha nged since thi s document w as publish ed and may di ffe r in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
14.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not b e relied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semicond uctors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall pre va il.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to off er functions and qualities beyond those described in the
Product data sheet.
14.3 Disclaimers
General — In formation in this document is believed to be accura te and
reliable. However, NXP Semiconductors does not give any repr esenta tions or
warranties, expressed or impli ed, as to the accuracy or completeness of such
information and shall have no liability for th e co nsequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applica tions that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modifi cation.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause pe rmanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other co nditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may af fect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between inf ormation in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing i n this document may be interpreted or
construed as an of fer t o sell product s that is open for accept ance or the gr ant,
conveyance or implication of any license under any copyrights, patents or
other industrial or inte llectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulatio ns. Export might require a prior
authorization from national authorities.
Export control — This document as well as the item(s) described herein
may be subject to export control regulatio ns. Export might require a prior
authorization from national authorities.
Non-automotive qualified products — Unless the data sheet of an NXP
Semiconductors product expressly states that the product is auto motive
qualified, the product is not suitable for automotive use. It is neither qualified
nor tested in acco rdan ce wit h au to moti ve testin g or app lication requi remen ts.
NXP Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualifie d products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and st andards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconduct ors for an y
liability, damages or failed product claims resulting from custome r design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
14.4 Trademarks
Notice: All referenced b rands, produc t names, service names and trademarks
are the property of their respective ow ners.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.
Product [short] dat a sheet Production This document cont ains the product specification.
74HC_HCT164_4 © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 04 — 2 February 2010 19 of 20
NXP Semiconductors 74HC164; 74HCT164
8-bit serial-in, parallel-out shift register
15. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors 74HC164; 74HCT164
8-bit serial-in, parallel-out shift register
© NXP B.V. 2010 . All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 2 February 2010
Document identifier: 74HC_HCT164_4
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
16. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
6 Functional description . . . . . . . . . . . . . . . . . . . 4
7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
8 Recommended operating conditions. . . . . . . . 5
9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7
11 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12
12 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 17
13 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 17
14 Legal information. . . . . . . . . . . . . . . . . . . . . . . 18
14.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18
14.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
14.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 18
14.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 18
15 Contact information. . . . . . . . . . . . . . . . . . . . . 19
16 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20