1
Data sheet acquired from Harris Semiconductor
SCHS163F
Features
• Synchronous Counting and Asynchronous
Loading
• Two Outputs for N-Bit Cascading
• Look-Ahead Carry for High-Speed Counting
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating T emperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il≤1µA at VOL, VOH
Description
The ’HC192, ’HC193 and ’HCT193 are asynchronously
presettable BCD Decade and Binary Up/Down synchronous
counters, respectively.
Pinout
CD54HC192, CD54HC193, CD54HCT193 (CERDIP)
CD74HC192 (PDIP, SOP, TSSOP)
CD74HC193 (PDIP, SOIC)
CD74HCT193 (PDIP)
TOP VIEW
Presetting the counter to the number on the preset data inputs
(P0-P3) is accomplished by a LOW asynchronous parallel
load input (PL). The counter is incremented on the low-to-high
transition of the Clock-Up input (and a high level on the Clock-
Down input) and decremented on the low to high transition of
the Clock-Down input (and a high level on the Clock-up input).
A high level on the MR input overrides any other input to clear
the counter to its zero state. The Terminal Count up (carry)
goes low half a clock period before the zero count is reached
and returns to a high level at the zero count. The Terminal
Count Down (borrow) in the count down mode likewise goes
low half a clock period before the maximum count (9 in the
192 and 15 in the 193) and returns to high at the maximum
count. Cascading is effected by connecting the carry and
borrow outputs of a less significant counter to the Clock-Up
and Clock-Down inputs, respectively, of the next most
significant counter.
If a decade counter is preset to an illegal state or assumes an
illegal state when power is applied, it will return to the normal
sequence in one count as shown in state diagr am.
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
P1
Q1
Q0
CPD
CPU
Q2
GND
Q3
VCC
MR
TCD
TCU
PL
P2
P3
P0
Ordering Information
PART NUMBER TEMP. RANGE
(oC) PACKAGE
CD54HC192F3A -55 to 125 16 Ld CERDIP
CD54HC193F3A -55 to 125 16 Ld CERDIP
CD54HCT193F3A -55 to 125 16 Ld CERDIP
CD74HC192E -55 to 125 16 Ld PDIP
CD74HC192NSR -55 to 125 16 Ld SOP
CD74HC192PW -55 to 125 16 Ld TSSOP
CD74HC192PWR -55 to 125 16 Ld TSSOP
CD74HC192PWT -55 to 125 16 Ld TSSOP
CD74HC193E -55 to 125 16 Ld PDIP
CD74HC193M -55 to 125 16 Ld SOIC
CD74HC193MT -55 to 125 16 Ld SOIC
CD74HC193M96 -55 to 125 16 Ld SOIC
CD74HCT193E -55 to 125 16 Ld PDIP
NOTE: When ordering, use the entire part number. The suffixes 96
and R denote tape and reel. The suffix T denotes a small-quantity
reel of 250.
September 1997 - Revised October 2003
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
CD54/74HC192,
CD54/74HC193, CD54/74HCT193
High-Speed CMOS Logic
Presettable Synchronous 4-Bit Up/Down Counters
[
/Title
(
CD74
H
C192
,
C
D74
H
C193
,
C
D74
H
CT19
3
)
/
Sub-
j
ect
(
High
S
peed
C
MOS
L
ogic
P
reset-
2
Functional Diagram
TRUTH TABLE
CLOCK UP CLOCK
DOWN RESET PARALLEL
LOAD FUNCTION
↑H L H Count Up
H↑L H Count Down
X X H X Reset
X X L L Load Preset Inputs
H = High Voltage Level, L = Low Voltage Level, X = Don’t Care, ↑= Transition from Low to
High Level
ASYN.
MASTER
CLOCK UP
11
14
5
4
15 1 10 9
3
6
7
12
13
Q0
Q1
Q2
Q3
TERMINAL
P0 P1 P2 P3
LOAD
CLOCK DOWN
2
TERMINAL
COUNT UP
BCD (192)
BINARY (193)
OUTPUTS
BCD/BINARY
PRESET
ENABLE
PARALLEL PL
RESET
COUNT DOWN
CD54/74HC192, CD54/74HC193, CD54/74HCT193
3
Absolute Maximum Ratings Thermal Information
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, ICC or IGND . . . . . . . . . . . . . . . . . .±50mA
Operating Conditions
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
Package Thermal Impedance, θJA (see Note 1):
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67oC/W
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73oC/W
NS (SOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64oC/W
PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . 108oC/W
Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
PARAMETER SYMBOL
TEST
CONDITIONS 25oC -40oC TO 85oC -55oC TO 125oC
UNITSVI(V) IO(mA) VCC (V) MIN TYP MAX MIN MAX MIN MAX
HC TYPES
High Level Input
Voltage VIH - - 2 1.5 - - 1.5 - 1.5 - V
4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V
Low Level Input
Voltage VIL - - 2 - - 0.5 - 0.5 - 0.5 V
4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V
High Level Output
Voltage
CMOS Loads
VOH VIH or
VIL -0.02 2 1.9 - - 1.9 - 1.9 - V
-0.02 4.5 4.4 - - 4.4 - 4.4 - V
-0.02 6 5.9 - - 5.9 - 5.9 - V
High Level Output
Voltage
TTL Loads
-4 4.5 3.98 - - 3.84 - 3.7 - V
-5.2 6 5.48 - - 5.34 - 5.2 - V
Low Level Output
Voltage
CMOS Loads
VOL VIH or
VIL 0.02 2 - - 0.1 - 0.1 - 0.1 V
0.02 4.5 - - 0.1 - 0.1 - 0.1 V
0.02 6 - - 0.1 - 0.1 - 0.1 V
Low Level Output
Voltage
TTL Loads
4 4.5 - - 0.26 - 0.33 - 0.4 V
5.2 6 - - 0.26 - 0.33 - 0.4 V
Input Leakage
Current IIVCC or
GND -6--±0.1 - ±1-±1µA
Quiescent Device
Current ICC VCC or
GND 0 6 - - 8 - 80 - 160 µA
CD54/74HC192, CD54/74HC193, CD54/74HCT193
4
HCT TYPES
High Level Input
Voltage VIH - - 4.5 to
5.5 2-- 2 - 2 - V
Low Level Input
Voltage VIL - - 4.5 to
5.5 - - 0.8 - 0.8 - 0.8 V
High Level Output
Voltage
CMOS Loads
VOH VIH or
VIL -0.02 4.5 4.4 - - 4.4 - 4.4 - V
High Level Output
Voltage
TTL Loads
-4 4.5 3.98 - - 3.84 - 3.7 - V
Low Level Output
Voltage
CMOS Loads
VOL VIH or
VIL 0.02 4.5 - - 0.1 - 0.1 - 0.1 V
Low Level Output
Voltage
TTL Loads
4 4.5 - - 0.26 - 0.33 - 0.4 V
Input Leakage
Current IIVCC to
GND - 5.5 - - ±0.1 - ±1-±1µA
Quiescent Device
Current ICC VCC or
GND - 5.5 - - 8 - 80 - 160 µA
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
∆ICC
(Note 2) VCC
- 2.1 - 4.5 to
5.5 - 100 360 - 450 - 490 µA
NOTE:
2. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.
DC Electrical Specifications (Continued)
PARAMETER SYMBOL
TEST
CONDITIONS 25oC -40oC TO 85oC -55oC TO 125oC
UNITSVI(V) IO(mA) VCC (V) MIN TYP MAX MIN MAX MIN MAX
HCT Input Loading Table
INPUT UNIT LOADS
P0-P3 0.4
MR 1.45
PL 0.85
CPU, CPD 1.45
NOTE: Unit Load is ∆ICC limit specified in DC Electrical
Specifications table, e.g. 360µA max at 25oC.
CD54/74HC192, CD54/74HC193, CD54/74HCT193
5
Prerequisite For Switching Specifications
PARAMETER SYMBOL VCC
(V)
25oC -40oC TO 85oC -55oC TO 125oC
UNITSMIN TYP MAX MIN MAX MIN MAX
HC TYPES
Pulse Width tW2 115 - - 145 - 175 - ns
CPU, CPD 4.5 23 - - 29 - 35 - ns
192 6 20 - - 25 - 30 - ns
tW2 100 - - 125 - 150 - ns
CPU, CPD 4.5 20 - - 25 - 30 - ns
193 6 17 - - 21 - 26 - ns
PL tW2 80 - - 100 - 120 - ns
4.5 16 - - 20 - 24 - ns
6 14 - - 17 - 20 - ns
MR tW2 100 - - 125 - 150 - ns
4.5 20 - - 25 - 30 - ns
6 17 - - 21 - 26 - ns
Set-up Time tSU 2 80 - - 100 - 120 - ns
Pn to PL 4.5 16 - - 20 - 24 - ns
6 14 - - 17 - 20 - ns
Hold Time tH2 0--0-0-ns
Pn to PL 4.5 0 - - 0 - 0 - ns
6 0--0-0-ns
Hold Time tH2 80 - - 100 - 120 - ns
CPD to CPU or 4.5 16 - - 20 - 24 - ns
CPU to CPD 6 14 - - 17 - 20 - ns
Recovery Time tREC 2 80 - - 100 - 120 - ns
PL to CPU, CPD 4.5 16 - - 20 - 24 - ns
6 14 - - 17 - 20 - ns
MR to CPU, CPD tREC 2 5--5-5-ns
4.5 5--5-5-ns
6 5--5-5-ns
Maximum Frequency fMAX 2 5--4-3-MHz
CPU, CPD 4.5 22 - - 18 - 15 - MHz
192 6 24 - - 21 - 18 - MHz
fMAX 2 5--4-3-MHz
CPU, CPD 4.5 25 - - 20 - 17 - MHz
193 6 29 - - 24 - 20 - MHz
HCT TYPES
Pulse Width tW2 -------ns
CPU, CPD 4.5 23 - - 29 - 35 - ns
192 6 -------ns
CPU, CPD tW2 -------ns
193 4.5 23 - - 29 - 35 - ns
6 -------ns
CD54/74HC192, CD54/74HC193, CD54/74HCT193
6
PL tW2 -------ns
4.5 16 - - 20 - 24 - ns
6 -------ns
MR tW2 -------ns
4.5 20 - - 25 - 30 - ns
6 -------ns
Set-up Time tSU 2 -------ns
Pn to PL 4.5 15 - - 19 - 22 - ns
6 -------ns
Hold Time tH2 -------ns
Pn to PL 4.5 0 - - 0 - 0 - ns
6 -------ns
Hold Time tH2 -------ns
CPD to CPU or 4.5 16 - - 20 - 24 - ns
CPU to CPD 6 - - - - - - - ns
Recovery Time tREC 2 -------ns
PL to CPU, CPD 4.5 15 - - 19 - 22 - ns
6 -------ns
MR to CPU, CPD tREC 2 -------ns
4.5 5--5-5-ns
6 -------ns
Maximum Frequency fMAX 2 -------MHz
CPU, CPD 4.5 22 - - 18 - 15 - MHz
192 6 -------MHz
CPU, CPD fMAX 2 -------MHz
193 4.5 22 - - 18 - 15 - MHz
6 -------MHz
Switching Specifications Input tr, tf = 6ns
PARAMETER SYMBOL TEST
CONDITIONS VCC
(V)
25oC -40oC TO 85oC -55oC TO 125oC
UNITSMIN TYP MAX MIN MAX MIN MAX
HC TYPES
Propagation Delay tPLH, tPHL CL= 50pF 2 - - 125 - 155 - 190 ns
CPU to TCU CL= 50pF 4.5 - - 25 - 31 - 38 ns
CL= 15pF 5 - 10 - ----ns
CL= 50pF 6 - 21 - 26 - 32 ns
CPD to TCD tPLH, tPHL CL= 50pF 2 - - 125 - 155 - 190 ns
CL= 50pF 4.5 - - 25 - 31 - 38 ns
CL= 15pF 5 - 10 - ----ns
CL= 50pF 6 - - 21 - 26 - 32 ns
CPU to QntPLH, tPHL CL= 50pF 2 - - 220 - 270 - 325 ns
CL= 50pF 4.5 - - 43 - 54 - 65 ns
CL= 15pF 5 - 18 - ----ns
CL= 50pF 6 - - 37 - 46 - 55 ns
Prerequisite For Switching Specifications (Continued)
PARAMETER SYMBOL VCC
(V)
25oC -40oC TO 85oC -55oC TO 125oC
UNITSMIN TYP MAX MIN MAX MIN MAX
CD54/74HC192, CD54/74HC193, CD54/74HCT193
7
CPD to QntPLH, tPHL CL= 50pF 2 - - 220 - 270 - 325 ns
CL= 50pF 4.5 - - 43 - 54 - 65 ns
CL= 15pF 5 - 18 - - - - ns
CL= 50pF 6 - - 37 - 46 - 55 ns
PL to QntPLH, tPHL CL= 50pF 2 - - 220 - 275 - 330 ns
CL= 50pF 4.5 - - 44 - 55 - 66 ns
CL= 15pF 5 - 18 - ----ns
CL= 50pF 6 - - 37 - 47 - 56 ns
MR to Qn tPHL CL= 50pF 2 - - 200 - 250 - 300 ns
CL= 50pF 4.5 - - 40 - 50 - 60 ns
CL= 15pF 5 - 17 - ----ns
CL= 50pF 6 - - 34 - 43 - 51 ns
Transition Time tTLH, tTHL CL= 50pF 2 - - 75 - 95 - 110 ns
Q, TCU, TCD 4.5 - - 15 - 19 - 22 ns
6 - - 13 - 16 - 19 ns
Input Capacitance CIN CL= 50pF - - - 10 - 10 - 10 pF
Power Dissipation Capacitance
(Notes 3, 4) CPD CL= 15pF 5 - 40 - ----pF
HCT TYPES
Propagation Delay tPLH, tPHL CL= 50pF 4.5 - - 27 - 34 - 41 ns
CPU to TCU CL= 15pF 5 - 11 - ----ns
CPU to TCD tPLH, tPHL CL= 50pF 4.5 - - 27 - 34 - 41 ns
CL= 15pF 5 - 11 - ----ns
CPU to QntPLH, tPHL CL= 50pF 4.5 - - 40 - 50 - 60 ns
CL= 15pF 5 - 17 - ----ns
CPD to QntPLH, tPHL CL= 50pF 4.5 - - 40 - 50 - 60 ns
CL= 15pF 5 - 17 - ----ns
PL to QntPLH, tPHL CL= 50pF 4.5 - - 46 - 58 - 69 ns
CL= 15pF 5 - 21 - ----ns
MR to Qn tPHL CL= 50pF 4.5 - - 43 - 54 - 65 ns
CL= 15pF 5 - 18 - ----ns
Transition Time tTLH, tTHL CL= 50pF
Q, TCU, TCD 4.5 - - 15 - 19 - 22 ns
Input Capacitance CIN CL= 50pF - - - 10 - 10 - 10 pF
Power Dissipation Capacitance
(Notes 3, 4) CPD CL= 15pF 5 - 50 - ----pF
NOTES:
3. CPD is used to determine the dynamic power consumption, per gate.
4. PD = VCC2 fi + ∑(CL VCC2) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.
Switching Specifications Input tr, tf = 6ns (Continued)
PARAMETER SYMBOL TEST
CONDITIONS VCC
(V)
25oC -40oC TO 85oC -55oC TO 125oC
UNITSMIN TYP MAX MIN MAX MIN MAX
CD54/74HC192, CD54/74HC193, CD54/74HCT193
8
Test Circuits and Waveforms
FIGURE 1. ’HC192 SYNCHRONOUS DECADE COUNTERS, TYPICAL RESET, PRESET AND COUNT SEQUENCES
MASTER RESET
ASYNCHRONOUS PARALLEL LOAD
PRESET DATA
P0
P1
P2
P3
CLOCK UP
CLOCK DOWN
OUTPUTS
Q0
Q1
Q2
Q3
TERMINAL COUNT UP
TERMINAL COUNT DOWN
07 89012
COUNT DOWNCOUNT UPRESET
10987
PRESET
SEQUENCES:
1. RESET OUTPUTS TO ZERO.
2. LOAD (PRESET) TO BCD SEVEN.
TERMINAL COUNT UP, ZERO,
3. COUNT UP TO EIGHT, NINE,
ONE AND TWO.
4. COUNT DOWN TO ONE, ZERO,
TERMINAL COUNT DOWN, NINE,
EIGHT AND SEVEN.
CD54/74HC192, CD54/74HC193, CD54/74HCT193
9
FIGURE 2. ’HC193 SYNCHRONOUS BINARY COUNTERS, TYPICAL RESET, PRESET AND COUNT SEQUENCES
FIGURE 3. CLOCK TO OUTPUT DELAYS AND CLOCK PULSE
WIDTH FIGURE 4. CLOCK TO TERMINAL COUNT DELAYS
FIGURE 5. PARALLEL LOAD PULSE WIDTH, PARALLEL
LOAD TO OUTPUT DELAYS, AND PARALLEL
LOAD TO CLOCK RECOVERY TIME
FIGURE 6. MASTER RESET PULSE WIDTH, MASTER RESET
TO OUTPUT DELAY AND MASTER RESET TO
CLOCK RECOVERY TIME
Test Circuits and Waveforms (Continued)
MASTER RESET
ASYNCHRONOUS PARALLEL LOAD
PRESET DATA
P0
P1
P2
P3
CLOCK UP
CLOCK DOWN
OUTPUTS
Q0
Q1
Q2
Q3
TERMINAL COUNT UP
TERMINAL COUNT DOWN
013
14 15 0 1 2
COUNT DOWNCOUNT UPRESET
1 0 15 14 13
PRESET
SEQUENCES:
1. RESET OUTPUTS TO ZERO.
2. LOAD (PRESET) TO BINARY THIRTEEN.
3. COUNT UP TO FOURTEEN,
FIFTEEN, TERMINAL COUNT UP,
ZERO, ONE AND TWO.
4. COUNT DOWN TO ONE, ZERO,
TERMINAL COUNT DOWN,
FIFTEEN, FOURTEEN AND
THIRTEEN.
NOTES:
1. Master reset overrides load data and clock inputs.
2. When counting up, clock-down input must be high.
When counting down, clock-up input must be high.
CPU OR CPD l/fMAX INPUT LEVEL
VSVSVS
tPHL tPLH
VS
QnVS
tW
INPUT LEVEL
TCU OR TCD
tPHL tPLH
VSVS
CPU OR CPD VSVS
INPUT LEVEL
INPUT LEVE
L
INPUT LEVEL
CPU OR CPD
VSVS
tPLH
Qn
VS
tWVSVSVS
tW
Pn
PL
tPHL
tREC VS
MR
CPU OR CPD
Qn
tPHL
VSVS
INPUT LEVEL
tREC
INPUT LEVEL
VS
VS
tW
CD54/74HC192, CD54/74HC193, CD54/74HCT193
10
FIGURE 7. SET-UP AND HOLD TIMES DATA TO PARALLEL LOAD (PL)
FIGURE 8. CASCADED UP/DOWN COUNTER WITH PARALLEL LOAD
NOTE: Illegal states in BCD counters corrected in one count. NOTE: Illegal states in BCD counters corrected in one or two counts.
FIGURE 9. ’HC192, ’HCT193 STATE DIAGRAMS
Test Circuits and Waveforms (Continued)
INPUT LEVEL
INPUT LEVEL
Q = p
VS
tH
tSU(L)
Q = p
Qn
PL
Pn tSU(H)
VS
VS
tH
P0 P1 P2 P3
TCU
TCD
MR
Q0Q1Q2Q3
CPU
CPD
PL
UP CLOCK
DOWN CLOCK
ASYNCHRONOUS,
PARALLEL LOAD
RESET
OUTPUT
CARRY
BORROW
DATA INPUT
P0 P1 P2 P3
TCU
TCD
MR
Q0Q1Q2Q3
CPU
CPD
PL
234
5
6
7
89101112
13
14
15
10
COUNT UP
234
5
6
7
89101112
13
14
15
10
COUNT DOWN
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
5962-8780801EA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8780801EA
CD54HC192F3A
5962-9084801MEA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9084801ME
A
CD54HCT193F3A
9084801MEAS2035 OBSOLETE CDIP J 16 TBD Call TI Call TI -55 to 125
CD54HC192F3A ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8780801EA
CD54HC192F3A
CD54HC193F3A ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8772401EA
CD54HC193F3A
CD54HCT193F3A ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9084801ME
A
CD54HCT193F3A
CD74HC192E ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type -55 to 125 CD74HC192E
CD74HC192EE4 ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type -55 to 125 CD74HC192E
CD74HC192NSR ACTIVE SO NS 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC192M
CD74HC192NSRE4 ACTIVE SO NS 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC192M
CD74HC192NSRG4 ACTIVE SO NS 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC192M
CD74HC192PWR ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ192
CD74HC192PWRE4 ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ192
CD74HC192PWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ192
CD74HC192PWT ACTIVE TSSOP PW 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ192
CD74HC192PWTE4 ACTIVE TSSOP PW 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ192
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 2
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
CD74HC192PWTG4 ACTIVE TSSOP PW 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ192
CD74HC193E ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type -55 to 125 CD74HC193E
CD74HC193EE4 ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type -55 to 125 CD74HC193E
CD74HC193M ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC193M
CD74HC193M96 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC193M
CD74HC193M96E4 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC193M
CD74HC193M96G4 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC193M
CD74HC193ME4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC193M
CD74HC193MG4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC193M
CD74HC193MT ACTIVE SOIC D 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC193M
CD74HC193MTE4 ACTIVE SOIC D 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC193M
CD74HC193MTG4 ACTIVE SOIC D 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC193M
CD74HCT193E ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type -55 to 125 CD74HCT193E
CD74HCT193EE4 ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type -55 to 125 CD74HCT193E
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 3
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF CD54HC192, CD54HC193, CD54HCT193, CD74HC192, CD74HC193, CD74HCT193 :
•Catalog: CD74HC192, CD74HC193, CD74HCT193
•Military: CD54HC192, CD54HC193, CD54HCT193
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
•Military - QML certified for Military and Defense Applications
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
CD74HC192NSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
CD74HC192PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
CD74HC192PWT TSSOP PW 16 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
CD74HC193M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CD74HC192NSR SO NS 16 2000 367.0 367.0 38.0
CD74HC192PWR TSSOP PW 16 2000 367.0 367.0 35.0
CD74HC192PWT TSSOP PW 16 250 367.0 367.0 35.0
CD74HC193M96 SOIC D 16 2500 333.2 345.9 28.6
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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