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ADC12D1000RF, ADC12D1600RF

SNAS519H –JULY 2011–REVISED AUGUST 2015

ADC12D1x00RF 12-Bit, 3.2-GSPS and 2-GSPS RF-Sampling ADC

1 Device Overview

1.1 Features

• Excellent Noise and Linearity up to and Above fIN = • Key Specifications

2.7 GHz – Resolution 12 Bits

• Configurable to Either 3.2 or 2 GSPS Interleaved – Interleaved 3.2- and 2-GSPS ADC

or 1600 or 1000 MSPS Dual ADC • IMD3(Fin = 2.7 GHz at –13 dBFS) –63.7/–73

• New DESCLKIQ Mode for High Bandwidth, High dBFS (Typical)

Sampling Rate Apps • IMD3(Fin = 2.7 GHz at –16 dBFS) –66.7/–85

• Pin-Compatible With ADC10D1x00, ADC12D1x00 dBFS (Typical)

• AutoSync Feature for Multi-Chip Synchronization • Noise Floor –154.6/–154 dBm/Hz (Typical)

• Internally Terminated, Buffered, Differential Analog • Power 3.94/3.42 W (Typical)

Inputs – Dual 1600/1000 MSPS ADC, Fin = 498 MHz

• Interleaved Timing Automatic and Manual Skew • ENOB 9.2/9.4 Bits (Typical)

Adjust • SNR 58.2/58.8 dB (Typical)

• Test Patterns at Output for System Debug • SFDR 66.7/71.9 dBc (Typical)

• Time Stamp Feature to Capture External Trigger • Power per Channel 1.97/1.71 W (Typical)

• Programmable Gain, Offset, and tAD Adjust

Feature

• 1:1 Non-Demuxed or 1:2 Demuxed LVDS Outputs

1.2 Applications

• 3G/4G Wireless Basestations • SIGINT

– Receive Path • RADAR and LIDAR

– DPD Path • Wideband Communications

• Wideband Microwave Backhaul • Consumer RFs

• RF Sampling Software Defined Radios • Tests and Measurements

• Military Communications

1.3 Description

The 12-bit 3.2- and 2-GSPS ADC12D1x00RF is an RF-sampling GSPS ADC that can directly sample

input frequencies up to and above 2.7 GHz. The ADC12D1x00RF augments the very large Nyquist zone

of TI’s GSPS ADCs with excellent noise and linearity performance at RF frequencies, extending its usable

range beyond the 3rd Nyquist zone

The ADC12D1x00RF provides a flexible LVDS interface which has multiple SPI programmable options to

facilitate board design and FPGA/ASIC data capture. The LVDS outputs are compatible with IEEE 1596.3-

1996 and supports programmable common-mode voltage. The product is packaged in a lead-free 292-ball

thermally enhanced BGA package over the rated industrial temperature range of –40°C to 85°C.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE

ADC12D1000RF BGA (40) 27.00 mm × 27.00 mm

ADC12D1600RF

(1) For more information, see Section 10,Mechanical Packaging and Orderable Information.

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

ADC12D1000RF, ADC12D1600RF

SNAS519H –JULY 2011–REVISED AUGUST 2015

www.ti.com

1.4 Functional Block Diagram

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SNAS519H –JULY 2011–REVISED AUGUST 2015

Table of Contents

1 Device Overview ......................................... 15 Detailed Description ................................... 35

1.1 Features .............................................. 15.1 Overview ............................................ 35

1.2 Applications........................................... 15.2 Functional Block Diagram........................... 35

1.3 Description............................................ 15.3 Feature Description ................................. 36

1.4 Functional Block Diagram ............................ 25.4 Device Functional Modes ........................... 44

2 Revision History ......................................... 35.5 Programming........................................ 45

3 Pin Configuration and Functions..................... 45.6 Register Maps....................................... 50

3.1 Pin Attributes ......................................... 56 Application and Implementation .................... 56

4 Specifications........................................... 14 6.1 Application Information.............................. 56

4.1 Absolute Maximum Ratings......................... 14 6.2 Typical Application .................................. 65

4.2 ESD Ratings ........................................ 14 7 Power Supply Recommendations .................. 68

4.3 Recommended Operating Conditions............... 15 7.1 System Power-on Considerations................... 68

4.4 Thermal Information................................. 15 7.2 Supply Voltage ...................................... 70

4.5 Electrical Characteristics: Static Converter ......... 16 8 Layout .................................................... 71

4.6 Electrical Characteristics: Dynamic Converter...... 17 8.1 Layout Guidelines ................................... 71

4.7 Electrical Characteristics: Analog Input/Output and 8.2 Layout Example..................................... 73

Reference ........................................... 21 8.3 Thermal Management............................... 75

4.8 Electrical Characteristics: I-Channel to Q-Channel .22 9 Device and Documentation Support ............... 77

4.9 Electrical Characteristics: Sampling Clock.......... 22 9.1 Device Support...................................... 77

4.10 Electrical Characteristics: AutoSync Feature ....... 22 9.2 Documentation Support ............................. 79

4.11 Electrical Characteristics: Digital Control and Output 9.3 Related Links........................................ 80

Pin................................................... 23 9.4 Community Resources.............................. 80

4.12 Electrical Characteristics: Power Supply............ 24 9.5 Trademarks.......................................... 80

4.13 Electrical Characteristics: AC ....................... 25 9.6 Electrostatic Discharge Caution..................... 80

4.14 Timing Requirements: Serial Port Interface......... 26 9.7 Glossary............................................. 80

4.15 Timing Requirements: Calibration .................. 26 10 Mechanical, Packaging, and Orderable

4.16 Typical Characteristics.............................. 30 Information .............................................. 80

2 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision G (April 2013) to Revision H Page

• Added ESD Ratings table, Feature Description section, Device Functional Modes,Application and

Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation

Support section, and Mechanical, Packaging, and Orderable Information section .......................................... 1

Changes from Revision F (April 2013) to Revision G Page

• Changed layout of National Data Sheet to TI format........................................................................... 55

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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

AGND V_A SDO TPM NDM V_A GND V_E GND_E DId0+ V_DR DId3+ GND_DR DId6+ V_DR DId9+ GND_DR DId11+ DId11- GND_DR A

BVbg GND ECEb SDI CalRun V_A GND GND_E V_E DId0- DId2+ DId3- DId5+ DId6- DId8+ DId9- DId10+ DI0+ DI1+ DI1- B

CRtrim+ Vcmo Rext+ SCSb SCLK V_A NC V_E GND_E DId1+ DId2- DId4+ DId5- DId7+ DId8- DId10- DI0- V_DR DI2+ DI2- C

DDNC Rtrim- Rext- GND GND CAL DNC V_A V_A DId1- V_DR DId4- GND_DR DId7- V_DR GND_DR V_DR DI3+ DI4+ DI4- D

EV_A Tdiode+ DNC GND GND_DR DI3- DI5+ DI5- E

FV_A GND_TC Tdiode- DNC GND_DR DI6+ DI6- GND_DR F

GV_TC GND_TC V_TC V_TC DI7+ DI7- DI8+ DI8- G

HVinI+ V_TC GND_TC V_A GND GND GND GND GND GND DI9+ DI9- DI10+ DI10- H

JVinI- GND_TC V_TC VbiasI GND GND GND GND GND GND V_DR DI11+ DI11- V_DR J

KGND VbiasI V_TC GND_TC GND GND GND GND GND GND ORI+ ORI- DCLKI+ DCLKI- K

LGND VbiasQ V_TC GND_TC GND GND GND GND GND GND ORQ+ ORQ- DCLKQ+ DCLKQ- L

MVinQ- GND_TC V_TC VbiasQ GND GND GND GND GND GND GND_DR DQ11+ DQ11- GND_DR M

NVinQ+ V_TC GND_TC V_A GND GND GND GND GND GND DQ9+ DQ9- DQ10+ DQ10- N

PV_TC GND_TC V_TC V_TC DQ7+ DQ7- DQ8+ DQ8- P

RV_A GND_TC V_TC V_TC V_DR DQ6+ DQ6- V_DR R

TV_A GND_TC GND_TC GND V_DR DQ3- DQ5+ DQ5- T

UGND_TC CLK+ PDI GND GND RCOut1- DNC V_A V_A DQd1- V_DR DQd4- GND_DR DQd7- V_DR V_DR GND_DR DQ3+ DQ4+ DQ4- U

VCLK- DCLK

_RST+ PDQ CalDly DES RCOut2+ RCOut2- V_E GND_E DQd1+ DQd2- DQd4+ DQd5- DQd7+ DQd8- DQd10- DQ0- GND_DR DQ2+ DQ2- V

WDCLK

_RST- GND DNC DDRPh RCLK- V_A GND GND_E V_E DQd0- DQd2+ DQd3- DQd5+ DQd6- DQd8+ DQd9- DQd10+ DQ0+ DQ1+ DQ1- W

YGND V_A FSR RCLK+ RCOut1+ V_A GND V_E GND_E DQd0+ V_DR DQd3+ GND_DR DQd6+ V_DR DQd9+ GND_DR DQd11+ DQd11- GND_DR Y

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

ADC12D1000RF, ADC12D1600RF

SNAS519H –JULY 2011–REVISED AUGUST 2015

www.ti.com

3 Pin Configuration and Functions

BGA Package

292-Pin NXA

Top-View

The center ground pins are for thermal dissipation and must be soldered to a ground plane to ensure rated

performance. See Section 8.1 for more information.

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AGND

100 VBIAS

50k

AGND

100

AGND

100 VBIAS

50k

ADC12D1000RF, ADC12D1600RF

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SNAS519H –JULY 2011–REVISED AUGUST 2015

3.1 Pin Attributes

Table 3-1. Analog Front-End and Clock Balls

PIN I/O EQUIVALENT CIRCUIT DESCRIPTION

NAME NO.

Differential Converter Sampling Clock. In

the Non-DES Mode, the analog inputs

are sampled on the positive transitions of

CLK+/- U2/V1 I this clock signal. In the DES Mode, the

selected input is sampled on both

transitions of this clock. This clock must

be AC-coupled.

Differential DCLK Reset. A positive pulse

on this input is used to reset the DCLKI

and DCLKQ outputs of two or more

ADC12D1x00RFs to synchronize them

with other ADC12D1x00RFs in the

system. DCLKI and DCLKQ are always in

phase with each other, unless one

DCLK_RST+/- V2/W1 I channel is powered down, and do not

require a pulse from DCLK_RST to

become synchronized. The pulse applied

here must meet timing relationships with

respect to the CLK input. Although

supported, this feature has been

superseded by AutoSync.

Reference Clock Input. When the

AutoSync feature is active, and the

ADC12D1x00RF is in Slave Mode, the

internal divided clocks are synchronized

RCLK+/- Y4/W5 I with respect to this input clock. The delay

on this clock may be adjusted when

synchronizing multiple ADCs. This

feature is available in ECM through

Control Register (Addr: Eh).

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GND

Tdiode_P

Tdiode_N

GND

A GND

100:100:

ADC12D1000RF, ADC12D1600RF

SNAS519H –JULY 2011–REVISED AUGUST 2015

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Table 3-1. Analog Front-End and Clock Balls (continued)

PIN I/O EQUIVALENT CIRCUIT DESCRIPTION

NAME NO.

Reference Clock Output 1 and 2. These

signals provide a reference clock at a

rate of CLK/4, when enabled,

independently of whether the ADC is in

Master or Slave Mode. They are used to

drive the RCLK of another

ADC12D1x00RF, to enable automatic

synchronization for multiple ADCs

RCOut1+/- Y5/U6 O (AutoSync feature). The impedance of

RCOut2+/- V6/V7 each trace from RCOut1 and RCOut2 to

the RCLK of another ADC12D1x00RF

should be 100-Ωdifferential. Having two

clock outputs allows the auto-

synchronization to propagate as a binary

tree. Use the DOC Bit (Addr: Eh, Bit 1) to

enable or disable this feature; default is

disabled.

External Reference Resistor terminals. A

3.3-kΩ±0.1% resistor should be

connected between Rext+/-. The Rext

resistor is used as a reference to trim

Rext+/- C3/D3 I/O internal circuits which affect the linearity

of the converter; the value and precision

of this resistor should not be

compromised.

Input Termination Trim Resistor

terminals. A 3.3-kΩ±0.1% resistor should

be connected between Rtrim+/-. The

Rtrim resistor is used to establish the

calibrated 100-Ωinput impedance of VinI,

Rtrim+/- C1/D2 I/O VinQ and CLK. These impedances may

be fine tuned by varying the value of the

resistor by a corresponding percentage;

however, the tuning range and

performance is not specified for such an

alternate value.

Temperature Sensor Diode Positive

(Anode) and Negative (Cathode)

Tdiode+/- E2/F3 Passive Terminals. This set of pins is used for die

temperature measurements. It has not

been fully characterized.

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50k

AGND

50k

Control from VCMO

VCMO

100

GND

200k

8 pF

VCMO

Enable AC

Coupling

GND

ADC12D1000RF, ADC12D1600RF

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SNAS519H –JULY 2011–REVISED AUGUST 2015

Table 3-1. Analog Front-End and Clock Balls (continued)

PIN I/O EQUIVALENT CIRCUIT DESCRIPTION

NAME NO.

Bandgap Voltage Output or LVDS

Common-mode Voltage Select. This pin

provides a buffered version of the

bandgap output voltage and is capable of

sourcing or sinking 100 µA and driving a

VBG B1 O load of up to 80 pF. Alternately, this pin

may be used to select the LVDS digital

output common-mode voltage. If tied to

logic-high, the 1.2-V LVDS common-

mode voltage is selected; 0.8 V is the

default.

Common-Mode Voltage Output or Signal

Coupling Select. If AC-coupled operation

at the analog inputs is desired, this pin

should be held at logic-low level. This pin

is capable of sourcing or sinking up to

100 µA. For DC-coupled operation, this

VCMO C2 I/O pin should be left floating or terminated

into high impedance. In DC-coupled

Mode, this pin provides an output voltage

which is the optimal common-mode

voltage for the input signal and should be

used to set the common-mode voltage of

the driving buffer.

Differential signal I- and Q-inputs. In the

Non-Dual Edge Sampling (Non-DES)

Mode, each I- and Q-input is sampled

and converted by its respective channel

with each positive transition of the CLK

input. In Non-ECM (Non-Extended

Control Mode) and DES Mode, both

channels sample the I-input. In Extended

Control Mode (ECM), the Q-input may

optionally be selected for conversion in

DES Mode by the DEQ Bit (Addr: 0h, Bit

6).

Each I- and Q-channel input has an

internal common-mode bias that is

disabled when DC-coupled Mode is

VinI+/- H1/J1 I selected. Both inputs must be either AC-

VinQ+/- N1/M1 or DC-coupled. The coupling mode is

selected by the VCMO Pin.

In Non-ECM, the full-scale range of these

inputs is determined by the FSR Pin;

both I- and Q-channels have the same

full-scale input range. In ECM, the full-

scale input range of the I- and Q-channel

inputs may be independently set through

the Control Register (Addr: 3hand Addr:

Bh). The high and low full-scale input

range setting in Non-ECM corresponds to

the mid and minimum full-scale input

range in ECM.

The input offset may also be adjusted in

ECM.

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SNAS519H –JULY 2011–REVISED AUGUST 2015

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Table 3-2. Control and Status Balls

PIN I/O EQUIVALENT CIRCUIT DESCRIPTION

NAME NO.

Calibration cycle initiate. The user can

command the device to execute a self-

calibration cycle by holding this input high

a minimum of tCAL_H after having held it

low a minimum of tCAL_L. If this input is

held high at the time of power on, the

automatic power-on calibration cycle is

CAL D6 I inhibited until this input is cycled low-then-

high. This pin is active in both ECM and

Non-ECM. In ECM, this pin is logically

OR'd with the CAL Bit (Addr: 0h, Bit 15)

in the Control Register. Therefore, both

pin and bit must be set low and then

either can be set high to execute an on-

command calibration.

Calibration Delay select. By setting this

input logic-high or logic-low, the user can

select the device to wait a longer or

shorter amount of time, respectively,

CalDly V4 I before the automatic power-on self-

calibration is initiated. This feature is pin-

controlled only and is always active

during ECM and Non-ECM.

Calibration Running indication. This

output is logic-high while the calibration

CalRun B5 O sequence is executing. This output is

logic-low otherwise.

DDR Phase select. This input, when

logic-low, selects the 0° Data-to-DCLK

phase relationship. When logic-high, it

selects the 90° Data-to-DCLK phase

relationship, that is, the DCLK transition

indicates the middle of the valid data

DDRPh W4 I outputs. This pin only has an effect when

the chip is in 1:2 Demuxed Mode, that is,

the NDM pin is set to logic-low. In ECM,

this input is ignored and the DDR phase

is selected through the Control Register

by the DPS Bit (Addr: 0h, Bit 14); the

default is 0° Mode.

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GND

50 k:

GND

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SNAS519H –JULY 2011–REVISED AUGUST 2015

Table 3-2. Control and Status Balls (continued)

PIN I/O EQUIVALENT CIRCUIT DESCRIPTION

NAME NO.

Dual Edge Sampling (DES) Mode select.

In the Non-Extended Control Mode (Non-

ECM), when this input is set to logic-high,

the DES Mode of operation is selected,

meaning that the VinI input is sampled by

both channels in a time-interleaved

manner. The VinQ input is ignored. When

DES V5 I this input is set to logic-low, the device is

in Non-DES Mode, that is, the I- and Q-

channels operate independently. In the

Extended Control Mode (ECM), this input

is ignored and DES Mode selection is

controlled through the Control Register by

the DES Bit (Addr: 0h, Bit 7); default is

Non-DES Mode operation.

Do Not Connect. These pins are used for

D1, D7, E3, internal purposes and should not be

DNC — NONE

F4, W3, U7 connected, that is, left floating. Do not

ground.

Extended Control Enable bar. Extended

feature control through the SPI interface

is enabled when this signal is asserted

(logic-low). In this case, most of the direct

control pins have no effect. When this

ECE B3 I signal is deasserted (logic-high), the SPI

interface is disabled, all SPI registers are

reset to their default values, and all

available settings are controlled through

the control pins.

Full-Scale input Range select. In Non-

ECM, when this input is set to logic-low or

logic-high, the full-scale differential input

range for both I- and Q-channel inputs is

set to the lower or higher FSR value,

respectively. In the ECM, this input is

FSR Y3 I ignored and the full-scale range of the I-

and Q-channel inputs is independently

determined by the setting of Addr: 3hand

Addr: Bh, respectively. The high (lower)

FSR value in Non-ECM corresponds to

the mid (minimum) available selection in

ECM; the FSR range in ECM is greater.

Not Connected. This pin is not bonded

NC C7 — NONE and may be left floating or connected to

any potential.

Non-Demuxed Mode select. Setting this

input to logic-high causes the digital

output bus to be in the 1:1 Non-Demuxed

Mode. Setting this input to logic-low

NDM A5 I causes the digital output bus to be in the

1:2 Demuxed Mode. This feature is pin-

controlled only and remains active during

ECM and Non-ECM.

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GND

100 k:

GND

100 k:

GND

100 k:

GND

50 k:

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SNAS519H –JULY 2011–REVISED AUGUST 2015

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Table 3-2. Control and Status Balls (continued)

PIN I/O EQUIVALENT CIRCUIT DESCRIPTION

NAME NO.

Power Down I- and Q-channel. Setting

either input to logic-high powers down the

respective I- or Q-channel. Setting either

input to logic-low brings the respective I-

or Q-channel to a operational state after a

PDI U3 finite time delay. This pin is active in both

PDQ V3 ECM and Non-ECM. In ECM, each Pin is

logically OR'd with its respective Bit.

Therefore, either this pin or the PDI and

PDQ Bit in the Control Register can be

used to power down the I- and Q-channel

(Addr: 0h, Bit 11 and Bit 10), respectively.

Serial Clock. In ECM, serial data is shifted

into and out of the device synchronously

to this clock signal. This clock may be

SCLK C5 I disabled and held logic-low, as long as

timing specifications are not violated

when the clock is enabled or disabled.

Serial Chip Select bar. In ECM, when this

signal is asserted (logic-low), SCLK is

used to clock in serial data which is

SCS C4 I present on SDI and to source serial data

on SDO. When this signal is deasserted

(logic-high), SDI is ignored and SDO is in

tri-stated.

Serial Data-In. In ECM, serial data is

SDI B4 I shifted into the device on this pin while

SCS signal is asserted (logic-low).

Serial Data-Out. In ECM, serial data is

shifted out of the device on this pin while

SDO A3 O SCS signal is asserted (logic-low). This

output is tri-stated when SCS is

deasserted.

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GND

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SNAS519H –JULY 2011–REVISED AUGUST 2015

Table 3-2. Control and Status Balls (continued)

PIN I/O EQUIVALENT CIRCUIT DESCRIPTION

NAME NO.

Test Pattern Mode select. With this input

at logic-high, the device continuously

outputs a fixed, repetitive test pattern at

the digital outputs. In the ECM, this input

TPM A4 I is ignored and the Test Pattern Mode can

only be activated through the Control

12).

Table 3-3. Power and Ground Balls

PIN I/O EQUIVALENT CIRCUIT DESCRIPTION

NAME NO.

A1, A7, B2,

B7, D4, D5,

E4, K1, L1, T4,

GND — NONE Ground Return for the Analog circuitry.

U4, U5, W2,

W7, Y1, Y7,

H8:N13

A13, A17, A20,

D13, D16,

E17, F17, F20,

GNDDR M17, M20, — NONE Ground Return for the Output Drivers.

U13, U17,

V18, Y13, Y17,

Y20

A9, B8, C9,

GNDE— NONE Ground Return for the Digital Encoder.

V9, W8, Y9

F2, G2, H3,

J2, K4, L4, M2, Ground Return for the Track-and-Hold

GNDTC — NONE

N3, P2, R2, and Clock circuitry.

T2, T3, U1

A2, A6, B6,

C6, D8, D9, Power Supply for the Analog circuitry.

E1, F1, H4, This supply is tied to the ESD ring.

VA— NONE

N4, R1, T1, Therefore, it must be powered up before

U8, U9, W6, or with any other supply.

Y2, Y6 Bias Voltage I-channel. This is an

externally decoupled bias voltage for the

I-channel. Each pin should individually be

VbiasI J4, K2 — NONE decoupled with a 100-nF capacitor

through a low-resistance, low-inductance

path to GND.

Bias Voltage Q-channel. This is an

externally decoupled bias voltage for the

Q-channel. Each pin should individually

VbiasQ L2, M4 — NONE be decoupled with a 100-nF capacitor

through a low-resistance, low-inductance

path to GND.

A11, A15,

C18, D11,

D15, D17, J17,

VDR J20, R17, R20, — NONE Power Supply for the Output Drivers.

T17, U11,

U15, U16,

Y11, Y15

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VDR

DR GND

VDR

DR GND

ADC12D1000RF, ADC12D1600RF

SNAS519H –JULY 2011–REVISED AUGUST 2015

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Table 3-3. Power and Ground Balls (continued)

PIN I/O EQUIVALENT CIRCUIT DESCRIPTION

NAME NO.

A8, B9, C8,

VE— NONE Power Supply for the Digital Encoder.

V8, W9, Y8

G1, G3, G4,

H2, J3, K3, L3, Power Supply for the Track-and-Hold and

VTC — NONE

M3, N2, P1, Clock circuitry.

P3, P4, R3, R4

Table 3-4. High-Speed Digital Outputs

PIN I/O EQUIVALENT CIRCUIT DESCRIPTION

NAME NO.

Data Clock Output for the I- and Q-

channel data bus. These differential clock

outputs are used to latch the output data

and, if used, should always be terminated

with a 100-Ωdifferential resistor placed as

closely as possible to the differential

receiver. Delayed and non-delayed data

DCLKI+/- K19/K20 outputs are supplied synchronously to this

DCLKQ+/- L19/L20 signal. In 1:2 Demux Mode or Non-

Demux Mode, this signal is at ¼ or ½ the

sampling clock rate, respectively. DCLKI

and DCLKQ are always in phase with

each other, unless one channel is

powered down, and do not require a

pulse from DCLK_RST to become

synchronized.

DI11+/- J18/J19

DI10+/- H19/H20

DI9+/- H17/H18

DI8+/- G19/G20

DI7+/- G17/G18

DI6+/- F18/F19 I- and Q-channel Digital Data Outputs. In

DI5+/- E19/E20 Non-Demux Mode, this LVDS data is

DI4+/- D19/D20 transmitted at the sampling clock rate. In

DI3+/- D18/E18 Demux Mode, these outputs provide ½

DI2+/- C19/C20 the data at ½ the sampling clock rate,

DI1+/- B19/B20 synchronized with the delayed data, that

DI0+/- B18/C17 is, the other ½ of the data which was

· · O sampled one clock cycle earlier.

DQ11+/- M18/M19 Compared with the DId and DQd outputs,

DQ10+/- N19/N20 these outputs represent the later time

DQ9+/- N17/N18 samples. If used, each of these outputs

DQ8+/- P19/P20 should always be terminated with a 100-Ω

DQ7+/- P17/P18 differential resistor placed as closely as

DQ6+/- R18/R19 possible to the differential receiver.

DQ5+/- T19/T20

DQ4+/- U19/U20

DQ3+/- U18/T18

DQ2+/- V19/V20

DQ1+/- W19/W20

DQ0+/- W18/V17

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DR GND

VDR

DR GND

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Table 3-4. High-Speed Digital Outputs (continued)

PIN I/O EQUIVALENT CIRCUIT DESCRIPTION

NAME NO.

DId11+/- A18/A19

DId10+/- B17/C16

DId9+/- A16/B16

DId8+/- B15/C15

DId7+/- C14/D14

DId6+/- A14/B14 Delayed I- and Q-channel Digital Data

DId5+/- B13/C13 Outputs. In Non-Demux Mode, these

DId4+/- C12/D12 outputs are tri-stated. In Demux Mode,

DId3+/- A12/B12 these outputs provide ½ the data at ½ the

DId2+/- B11/C11 sampling clock rate, synchronized with

DId1+/- C10/D10 the non-delayed data, that is, the other ½

DId0+/- A10/B10 of the data which was sampled one clock

· · O cycle later. Compared with the DI and DQ

DQd11+/- Y18/Y19 outputs, these outputs represent the

DQd10+/- W17/V16 earlier time samples. If used, each of

DQd9+/- Y16/W16 these outputs should always be

DQd8+/- W15/V15 terminated with a 100-Ωdifferential

DQd7+/- V14/U14 resistor placed as closely as possible to

DQd6+/- Y14/W14 the differential receiver.

DQd5+/- W13/V13

DQd4+/- V12/U12

DQd3+/- Y12/W12

DQd2+/- W11/V11

DQd1+/- V10/U10

DQd0+/- Y10/W10

Out-of-Range Output for the I- and Q-

channel. This differential output is

asserted logic-high while the over- or

under-range condition exists, that is, the

differential signal at each respective

ORI+/- K17/K18 analog input exceeds the full-scale value.

ORQ+/- L17/L18 Each OR result refers to the current Data,

with which it is clocked out. If used, each

of these outputs should always be

terminated with a 100-Ωdifferential

resistor placed as closely as possible to

the differential receiver. ORQ.(1)

(1) This pin and bit functionality is not tested in production test; performance is tested in the specified and default mode only.

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4 Specifications

4.1 Absolute Maximum Ratings(1)(2)

MIN MAX UNIT

Supply Voltage (VA, VTC, VDR, VE) 2.2 V

Supply Difference - max(VA/TC/DR/E) - min(VA/TC/DR/E) 0 100 mV

Voltage on Any Input Pin (except VIN±) –0.15 (VA+ 0.15) V

VIN± Voltage –0.5 2.5 V

Ground Difference - max(GNDTC/DR/E) – min(GNDTC/DR/E) 0 100 mV

Input Current at Any Pin(3) ±50 mA

ADC12D1x00RF Package Power Dissipation at TA≤85°C(3) 3.45 W

Storage Temperature –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are measured with respect to GND = GNDTC = GNDDR = GNDE= 0 V, unless otherwise specified.

(3) When the input voltage at any pin exceeds the power supply limits, that is, less than GND or greater than VA, the current at that pin

should be limited to 50 mA. In addition, overvoltage at a pin must adhere to the maximum voltage limits. Simultaneous overvoltage at

multiple pins requires adherence to the maximum package power dissipation limits. These dissipation limits are calculated using JEDEC

JESD51-7 thermal model. Higher dissipation may be possible based on specific customer thermal situation and specified package

thermal resistances from junction to case.

4.2 ESD Ratings

VALUE UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(2) ±2500

Electrostatic

V(ESD) Charged device model (CDM), per JEDEC specification JESD22-C101(3) ±1000 V

discharge(1) Machine model (MM) ±250

(1) Human body model is 100-pF capacitor discharged through a 1.5-kΩresistor. Machine model is 220 pF discharged through 0 Ω.

Charged device model simulates a pin slowly acquiring charge (such as from a device sliding down the feeder in an automated

assembler) then rapidly being discharged.

(2) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(3) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

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4.3 Recommended Operating Conditions(1)(2)

MIN NOM MAX UNIT

Ambient Temperature, TAADC12D1x00RF (Standard JEDEC thermal model) –40 85 °C

Junction Temperature, TJ140 °C

Supply Voltage (VA, VTC, VE) 1.8 2 V

Driver Supply Voltage (VDR) 1.8 VAV

VIN± Voltage(3) DC-coupled –0.4 2.4 V

DC-coupled at 100% duty cycle 1

VIN± Differential Voltage(4) DC-coupled at 20% duty cycle 2 V

DC-coupled at 10% duty cycle 2.8

VIN± Current(3) AC-coupled –50 50 mA

Maintaining common-mode voltage, AC-coupled 15.3

VIN± Power dBm

Not maintaining common-mode voltage, AC- 17.1

coupled

Ground Difference – max(GNDTC/DR/E) -min(GNDTC/DR/E) 0 V

CLK± Voltage 0 VAV

Differential CLK Amplitude 0.4 2 VP-P

VCMI Common-Mode Input Voltage VCMO – 150 VCMO +150 mV

(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. There is no specification of operation at the

Absolute Maximum Ratings.Recommended Operating Conditions indicate conditions for which the device is functional, but do not

ensure specific performance limits. For ensured specifications and test conditions, see the Electrical Characteristics. The ensured

specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated

under the listed test conditions.

(2) All voltages are measured with respect to GND = GNDTC = GNDDR = GNDE = 0 V, unless otherwise specified.

(3) Proper common-mode voltage must be maintained to ensure proper output codes, especially during input overdrive.

(4) This rating is intended for DC-coupled applications; the voltages and duty cycles listed may be safely applied to VIN+/- for the lifetime of

the part.

4.4 Thermal Information

ADC12D1x00RF

THERMAL METRIC(1) NXA [BGA] UNIT

40 PINS

RθJA Junction-to-ambient thermal resistance 16 °C/W

RθJC(top) Junction-to-case (top) thermal resistance 2.9 °C/W

RθJC(bot) Junction-to-case (bottom) thermal resistance 2.5 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

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4.5 Electrical Characteristics: Static Converter

Unless otherwise specified, the following apply after calibration for VA= VDR = VTC = VE= 1.9 V; I- and Q-channels, AC-

coupled, unused channel terminated to AC ground, FSR Pin = High; CL= 10 pF; Differential, AC-coupled Sine Wave

Sampling Clock, fCLK = 1600/1000 MHz at 0.5 VP-P with 50% duty cycle (as specified); VBG = Floating; Non-Extended Control

Mode; Rext = Rtrim = 3300 Ω± 0.1%; Analog Signal Source Impedance = 100-ΩDifferential; Non-Demux Non-DES Mode;

Duty Cycle Stabilizer on. All other limits TA= 25°C, unless otherwise noted.(1)(2)(3)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Resolution with No Missing Codes TA= TMIN to TMAX 12 bits

Integral Non-Linearity (Best fit) 1 MHz DC-coupled over-ranged sine wave,

INL ±2.5 ±7.25 LSB

TA= 25°C

1 MHz DC-coupled over-ranged sine wave,

DNL Differential Non-Linearity ±0.4 ±0.96 LSB

TA= TMIN to TMAX

VOFF Offset Error 5 LSB

VOFF_ADJ Input Offset Adjustment Range Extended Control Mode ±45 mV

PFSE Positive Full-Scale Error See (4) ±25 mV

NFSE Negative Full-Scale Error See (4) ±25 mV

(VIN+) −(VIN−) > + Full Scale, 4095

TA= TMIN to TMAX

Out-of-Range Output Code(5) (VIN+) −(VIN−) < −Full Scale, 0

TA= TMIN to TMAX

(1) The analog inputs, labeled "I/O", are protected as shown below. Input voltage magnitudes beyond the Absolute Maximum Ratings may

damage this device.

(2) To ensure accuracy, it is required that VA, VTC, VEand VDR be well-bypassed. Each supply pin must be decoupled with separate bypass

capacitors.

(3) Typical figures are at TA= 25°C, and represent most likely parametric norms. Test limits are specified to TI's AOQL (Average Outgoing

Quality Level).

(4) Calculation of Full-Scale Error for this device assumes that the actual reference voltage is exactly its nominal value. Full-Scale Error for

this device, therefore, is a combination of Full-Scale Error and Reference Voltage Error. See Figure 4-8. For relationship between Gain

Error and Full-Scale Error, see Specification Definitions for Gain Error.

(5) This parameter is specified by design and is not tested in production.

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4.6 Electrical Characteristics: Dynamic Converter(1)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

DESIQ MODE

–3 dB(2) 1.75 GHz

–6 dB 2.7 GHz

DESI, DESQ MODE

–3 dB(2) 1.2 GHz

–6 dB 2.3 GHz

Bandwidth –9 dB 2.7 GHz

–12 dB 3 GHz

NON-DES MODE, DESCLKIQ MODE

–3 dB(2) 2.7 GHz

–6 dB 3.1 GHz

–9 dB 3.5 GHz

–12 dB 4 GHz

NON-DES MODE

D.C. to Fs/2 ±0.3 dB

ADC12D1600RF ±0.8

D.C. to Fs dB

ADC12D1000RF ±0.4

ADC12D1600RF ±1

D.C. to 3Fs/2 dB

ADC12D1000RF ±0.8

ADC12D1600RF ±3.6

D.C. to 2Fs dB

ADC12D1000RF ±0.9

DESI, DESQ MODE

ADC12D1600RF ±2.2

D.C. to Fs/2 dB

ADC12D1000RF ±1

Gain Flatness ADC12D1600RF ±7.4

D.C. to Fs dB

ADC12D1000RF ±2.7

DESIQ MODE

ADC12D1600RF ±0.9

D.C. to Fs/2 dB

ADC12D1000RF ±0.7

ADC12D1600RF ±5.4

D.C. to Fs dB

ADC12D1000RF ±1.3

DESCLKIQ MODE

ADC12D1600RF ±0.7

D.C. to Fs/2 ADC12D1000RF ±0.6

ADC12D1600RF ±4.2

D.C. to Fs ADC12D1000RF ±0.9

Error/

CER Code Error Rate 10–18 Sample

(1) This parameter is specified by design and/or characterization and is not tested in production.

(2) The –3 dB point is the traditional Full-Power Bandwidth (FPBW) specification. Although the insertion loss is approximately half at this

frequency, the dynamic performance of the ADC does not necessarily begin to degrade to a level below which it may be effectively used

in an application. The ADC may be used at input frequencies above the –3 dB FPBW point, for example for the ADC12D1000RF, into

the 5th Nyquist zone. Depending on system requirements, it is only necessary to compensate for the insertion loss.

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Electrical Characteristics: Dynamic Converter(1) (continued)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

DES MODE

–76.7 dBFS

ADC12D1600RF –63.7 dBc

FIN = 2670 MHz ± 2.5 MHz

at –13 dBFS –73 dBFS

ADC12D1000RF –60 dBc

–78.6 dBFS

ADC12D1600RF –65.6 dBc

FIN = 2070 MHz ± 2.5 MHz

at –13 dBFS –77 dBFS

ADC12D1000RF

3rd order Intermodulation

IMD3–64 dBc

Distortion –82.7 dBFS

ADC12D1600RF –66.7 dBc

FIN = 2670 MHz ± 2.5 MHz

at –16 dBFS –85 dBFS

ADC12D1000RF –69 dBc

–80.1 dBFS

ADC12D1600RF –64.1 dBc

FIN = 2070 MHz ± 2.5 MHz

at –16 dBFS –83 dBFS

ADC12D1000RF –67 dBc

–154.6 dBm/Hz

ADC12D1600RF –153.6 dBFS/Hz

50-Ωsingle-ended termination,

Noise Floor Density DES Mode –154 dBm/Hz

ADC12D1000RF –153 dBFS/Hz

NON-DES MODE(3)(4)(5)

ADC12D1600RF 9.4

AIN = 125 MHz at –0.5 dBFS bits

ADC12D1000RF 9.6

ADC12D1600RF 9.3

AIN = 248 MHz at –0.5 dBFS bits

ADC12D1000RF 9.6

ADC12D1600RF 8.6(6) 9.2

ENOB Effective Number of Bits AIN = 498 MHz at –0.5 dBFS bits

ADC12D1000RF 8.7(6) 9.4

ADC12D1600RF 9

AIN = 998 MHz at –0.5 dBFS bits

ADC12D1000RF 9.3

ADC12D1600RF 8.8

AIN = 1448 MHz at –0.5 dBFS bits

ADC12D1000RF 9

ADC12D1600RF 58

AIN = 125 MHz at –0.5 dBFS dB

ADC12D1000RF 59.7

ADC12D1600RF 57.5 dB

AIN = 248 MHz at –0.5 dBFS ADC12D1000RF 59.7 dB

ADC12D1600RF 53.5(6) 57.4

Signal-to-Noise Plus Distortion

SINAD AIN = 498 MHz at –0.5 dBFS dB

Ratio ADC12D1000RF 54.1(6) 58.6

ADC12D1600RF 55.9

AIN = 998 MHz at –0.5 dBFS dB

ADC12D1000RF 57.6

ADC12D1600RF 54.9

AIN = 1448 MHz at –0.5 dBFS dB

ADC12D1000RF 55.9

(3) The Dynamic Specifications are ensured for room to hot ambient temperature only (25°C to 85°C). Refer to the plots of the dynamic

performance vs. temperature in Typical Characteristics to see typical performance from cold to room temperature (–40°C to 25°C).

(4) The Fs/2 spur was removed from all the dynamic performance specifications.

(5) Typical dynamic performance is only tested at Fin = 498 MHz; other input frequencies are specified by design and / or characterization

and are not tested in production.

(6) TA= TMIN to TMAX

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Electrical Characteristics: Dynamic Converter(1) (continued)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

ADC12D1600RF 59

AIN = 125 MHz at –0.5 dBFS dB

ADC12D1000RF 60.1

ADC12D1600RF 58.6

AIN = 248 MHz at –0.5 dBFS dB

ADC12D1000RF 60

ADC12D1600RF 54.6(6) 58.2

SNR Signal-to-Noise Ratio AIN = 498 MHz at –0.5 dBFS dB

ADC12D1000RF 55.1(6) 58.8

ADC12D1600RF 57

AIN = 998 MHz at –0.5 dBFS dB

ADC12D1000RF 58.2

ADC12D1600RF 55.4

AIN = 1448 MHz at –0.5 dBFS dB

ADC12D1000RF 56.1

ADC12D1600RF –65

AIN = 125 MHz at –0.5 dBFS dB

ADC12D1000RF –69.7

ADC12D1600RF –64

AIN = 248 MHz at –0.5 dBFS dB

ADC12D1000RF –71.9

ADC12D1600RF –64.9 –60(6)

THD Total Harmonic Distortion AIN = 498 MHz at –0.5 dBFS dB

ADC12D1000RF –72 –61(6)

ADC12D1600RF –62.4 8

AIN = 998 MHz at –0.5 dBFS dB

ADC12D1000RF –66.

ADC12D1600RF –64.1

AIN = 1448 MHz at –0.5 dBFS dB

ADC12D1000RF –69

ADC12D1600RF –78.6

AIN = 125 MHz at –0.5 dBFS dBc

ADC12D1000RF –79.3

ADC12D1600RF –83

AIN = 248 MHz at –0.5 dBFS dBc

ADC12D1000RF –91.6

ADC12D1600RF –74

2nd Harm Second Harmonic Distortion AIN = 498 MHz at –0.5 dBFS dBc

ADC12D1000RF –86.3

ADC12D1600RF –70.6

AIN = 998 MHz at –0.5 dBFS dBc

ADC12D1000RF –73

ADC12D1600RF –71

AIN = 1448 MHz at –0.5 dBFS dBc

ADC12D1000RF –73.7

ADC12D1600RF –67.5

AIN = 125 MHz at –0.5 dBFS dBc

ADC12D1000RF –71.9

ADC12D1600RF –64.4

AIN = 248 MHz at –0.5 dBFS dBc

ADC12D1000RF –75.4

ADC12D1600RF –71

3rd Harm Third Harmonic Distortion AIN = 498 MHz at –0.5 dBFS dBc

ADC12D1000RF –74.8

ADC12D1600RF –63.2

AIN = 998 MHz at –0.5 dBFS dBc

ADC12D1000RF –68.9

ADC12D1600RF –75.7

AIN = 1448 MHz at –0.5 dBFS dBc

ADC12D1000RF –73.5

ADC12D1600RF 67.9

AIN = 125 MHz at –0.5 dBFS dBc

ADC12D1000RF 71.4

ADC12D1600RF 64.5

AIN = 248 MHz at –0.5 dBFS dBc

ADC12D1000RF 75

ADC12D1600RF 58(6) 66.7

SFDR Spurious-Free Dynamic Range AIN = 498 MHz at –0.5 dBFS dBc

ADC12D1000RF 61(6) 71.9

ADC12D1600RF 63.8

AIN = 998 MHz at –0.5 dBFS dBc

ADC12D1000RF 68.4

ADC12D1600RF 67.3

AIN = 1448 MHz at –0.5 dBFS dBc

ADC12D1000RF 66.5

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Electrical Characteristics: Dynamic Converter(1) (continued)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

DES MODE(3)(7)(5)

ADC12D1600RF 9.3

AIN = 125 MHz at –0.5 dBFS bits

ADC12D1000RF 9.5

ADC12D1600RF 9.3

AIN = 248 MHz at –0.5 dBFS bits

ADC12D1000RF 9.4

ENOB Effective Number of Bits AIN = 498 MHz at –0.5 dBFS 9.3 bits

ADC12D1600RF 8.9

AIN = 998 MHz at –0.5 dBFS bits

ADC12D1000RF 8.8

AIN = 1448 MHz at –0.5 dBFS 8.7 bits

ADC12D1600RF 57.9

AIN = 125 MHz at –0.5 dBFS dB

ADC12D1000RF 58.7

ADC12D1600RF 57.5

AIN = 248 MHz at –0.5 dBFS dB

ADC12D1000RF 58.2

Signal-to-Noise Plus Distortion

SINAD ADC12D1600RF 57.5

Ratio AIN = 498 MHz at –0.5 dBFS dB

ADC12D1000RF 57.7

ADC12D1600RF 55.1

AIN = 998 MHz at –0.5 dBFS dB

ADC12D1000RF 54.8

AIN = 1448 MHz at –0.5 dBFS 54.1 dB

ADC12D1600RF 58.8 dB

AIN = 125 MHz at –0.5 dBFS ADC12D1000RF 59.2

AIN = 248 MHz at –0.5 dBFS 58.5 dB

ADC12D1600RF 58.1

SNR Signal-to-Noise Ratio AIN = 498 MHz at –0.5 dBFS dB

ADC12D1000RF 58

ADC12D1600RF 55.9

AIN = 998 MHz at –0.5 dBFS dB

ADC12D1000RF 55

AIN = 1448 MHz at –0.5 dBFS 54.3 dB

ADC12D1600RF –65.2

AIN = 125 MHz at –0.5 dBFS dB

ADC12D1000RF –68.1

ADC12D1600RF –64.2

AIN = 248 MHz at –0.5 dBFS dB

ADC12D1000RF –68.4

THD Total Harmonic Distortion ADC12D1600RF –66.2

AIN = 498 MHz at –0.5 dBFS dB

ADC12D1000RF –68.3

ADC12D1600RF –62.9

AIN = 998 MHz at –0.5 dBFS dB

ADC12D1000RF –66.4

AIN = 1448 MHz at –0.5 dBFS –67 dB

ADC12D1600RF –81.5

AIN = 125 MHz at –0.5 dBFS dBc

ADC12D1000RF –87.4

ADC12D1600RF –84.2

AIN = 248 MHz at –0.5 dBFS dBc

ADC12D1000RF –77.1

2nd Harm Second Harmonic Distortion ADC12D1600RF –69.7

AIN = 498 MHz at –0.5 dBFS dBc

ADC12D1000RF –73.4

ADC12D1600RF –70.5

AIN = 998 MHz at –0.5 dBFS dBc

ADC12D1000RF –76.4

AIN = 1448 MHz at –0.5 dBFS –73.6 dBc

(7) These measurements were taken in Extended Control Mode (ECM) with the DES Timing Adjust feature enabled (Addr: 7h). This feature

is used to reduce the interleaving timing spur amplitude, which occurs at fs/2-fin, and thereby increase the SFDR, SINAD and ENOB.

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Electrical Characteristics: Dynamic Converter(1) (continued)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

ADC12D1600RF –66

AIN = 125 MHz at –0.5 dBFS dBc

ADC12D1000RF –69.3

ADC12D1600RF –63.8

AIN = 248 MHz at –0.5 dBFS dBc

ADC12D1000RF –73.3

3rd Harm Third Harmonic Distortion ADC12D1600RF –69.7

AIN = 498 MHz at –0.5 dBFS dBc

ADC12D1000RF –72.6

ADC12D1600RF –63.5

AIN = 998 MHz at –0.5 dBFS dBc

ADC12D1000RF –69.9

AIN = 1448 MHz at –0.5 dBFS –67.1 dBc

ADC12D1600RF 66.9

AIN = 125 MHz at –0.5 dBFS dBc

ADC12D1000RF 69

ADC12D1600RF 65

AIN = 248 MHz at –0.5 dBFS dBc

ADC12D1000RF 67.1

SFDR Spurious-Free Dynamic Range ADC12D1600RF 70.4

AIN = 498 MHz at –0.5 dBFS dBc

ADC12D1000RF 65

ADC12D1600RF 64.1

AIN = 998 MHz at –0.5 dBFS dBc

ADC12D1000RF 61.7

AIN = 1448 MHz at –0.5 dBFS 61.3 dBc

4.7 Electrical Characteristics: Analog Input/Output and Reference

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

ANALOG INPUTS

NON-EXTENDED CONTROL MODE

FSR Pin Low 540(1) 600 660(1) mVP-P

FSR Pin High 740(1) 800 860(1) mVP-P

VIN_FSR Analog Differential Input Full Scale Range EXTENDED CONTROL MODE

FM(14:0) = 0000h600 mVP-P

FM(14:0) = 4000h(default) 800 mVP-P

FM(14:0) = 7FFFh1000 mVP-P

Differential 0.02 pF

Analog Input Capacitance, Non-DES Mode(2)(3) Each input pin to ground 1.6 pF

CIN Differential 0.08 pF

Analog Input Capacitance, DES Mode(2)(3) Each input pin to ground 2.2 pF

RIN Differential Input Resistance 91(1) 100 109(1) Ω

COMMON-MODE OUTPUT

VCMO Common-Mode Output Voltage ICMO = ±100 µA 1.15(1) 1.25 1.35(1) V

TC_VCMO Common-Mode Output Voltage Temperature Coefficient ICMO = ±100 µA(4) 38 ppm/°C

VCMO_LVL VCMO input threshold to set DC-coupling Mode See (4) 0.63 V

CL_VCMO Maximum VCMO Load Capacitance See (2) 80(1) pF

BANDGAP REFERENCE

VBG Bandgap Reference Output Voltage IBG = ±100 µA 1.15(1) 1.25 1.35(1) V

TC_VBG Bandgap Reference Voltage Temperature Coefficient IBG = ±100 µA(4) 32 ppm/°C

CL_VBG Maximum Bandgap Reference load Capacitance See (2) 80(1) pF

(1) TA= TMIN to TMAX

(2) This parameter is specified by design and is not tested in production.

(3) The differential and pin-to-ground input capacitances are lumped capacitance values from design.

(4) This parameter is specified by design and/or characterization and is not tested in production.

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4.8 Electrical Characteristics: I-Channel to Q-Channel

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Offset Match See (1) 2 LSB

Positive Full-Scale Match Zero offset selected in Control Register 2 LSB

Negative Full-Scale Match Zero offset selected in Control Register 2 LSB

Phase Matching (I, Q) fIN = 1.0 GHz(1) < 1 Degree

Crosstalk from I-channel (Aggressor) to Aggressor = 867 MHz F.S., –70 dB

Q-channel (Victim) Victim = 100 MHz F.S.

X-TALK Crosstalk from Q-channel (Aggressor) to Aggressor = 867 MHz F.S., –70 dB

I-channel (Victim) Victim = 100 MHz F.S.

(1) This parameter is specified by design and/or characterization and is not tested in production.

4.9 Electrical Characteristics: Sampling Clock

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Sine Wave Clock Differential Peak-to-Peak 0.4(2) 0.6 2(2) VP-P

VIN_CLK Differential Sampling Clock Input Level(1) Square Wave Clock Differential Peak-to-Peak 0.4(2) 0.6 2(2)

Differential 0.1 pF

CIN_CLK Sampling Clock Input Capacitance(3) Each input to ground 1 pF

RIN_CLK Sampling Clock Differential Input Resistance See (1) 100 Ω

(1) This parameter is specified by design and/or characterization and is not tested in production.

(2) TA= TMIN to TMAX

(3) This parameter is specified by design and is not tested in production.

4.10 Electrical Characteristics: AutoSync Feature

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VIN_RCLK Differential RCLK Input Level(1) Differential Peak-to-Peak 360 mVP-P

Differential 0.12 pF

CIN_RCLK RCLK Input Capacitance(1) Each input to ground 1 pF

RIN_RCLK RCLK Differential Input Resistance See (1) 100 Ω

IIH_RCLK Input Leakage Current; VIN = VA22 µA

IIL_RCLK Input Leakage Current; VIN = GND 33 µA

VO_RCOUT Differential RCOut Output Voltage –360 mVP-P

(1) This parameter is specified by design and/or characterization and is not tested in production.

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4.11 Electrical Characteristics: Digital Control and Output Pin

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

DIGITAL CONTROL PINS (DES, CalDly, CAL, PDI, PDQ, TPM, NDM, FSR, DDRPh, ECE, SCLK, SDI, SCS)

VIH Logic High Input Voltage 0.7×VA(1) V

VIL Logic Low Input Voltage 0.3×VA(1) V

IIH Input Leakage Current; VIN = VA0.02 μA

FSR, CalDly, CAL, NDM, TPM, DDRPh, DES –0.02 μA

IIL Input Leakage Current; VIN = GND SCS, SCLK, SDI –17 μA

PDI, PDQ, ECE –38 μA

CIN_DIG Digital Control Pin Input Capacitance(2) Measured from each control pin to GND 1.5 pF

DIGITAL OUTPUT PINS (Data, DCLKI, DCLKQ, ORI, ORQ)

VBG = Floating, OVS = High 400(1) 630 800(1) mVP-P

VBG = Floating, OVS = Low 230(1) 460 630(1) mVP-P

VOD LVDS Differential Output Voltage VBG = VA, OVS = High 670 mVP-P

VBG = VA, OVS = Low 500 mVP-P

Change in LVDS Output Swing Between Logic

ΔVO DIFF ±1 mV

Levels

VBG = Floating 0.8 V

VOS Output Offset Voltage(3) VBG = VA1.2 V

Output Offset Voltage Change Between Logic

ΔVOS See (3) ±1 mV

Levels

VBG = Floating;

IOS Output Short-Circuit Current(3) ±4 mA

D+ and D−connected to 0.8 V

ZODifferential Output Impedance See (3) 100 Ω

CalRun, IOH =−100 µA,(3)

VOH Logic High-Output Level 1.65 V

SDO, IOH =−400 µA(3)

CalRun, IOL = 100 µA,(3)

VOL Logic Low-Output Level 0.15 V

SDO, IOL = 400 µA(3)

VCMI_DRST DCLK_RST Common-Mode Input Voltage See (3) 1.25 V

VIN_CL

VID_DRST Differential DCLK_RST Input Voltage See (3) VP-P

RIN_DRST Differential DCLK_RST Input Resistance See (3) 100 Ω

(1) TA= TMIN to TMAX

(2) This parameter is specified by design and is not tested in production.

(3) This parameter is specified by design and/or characterization and is not tested in production.

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4.12 Electrical Characteristics: Power Supply

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

ADC12D1600RF 1225

PDI = PDQ = Low mA

ADC12D1000RF 1140

ADC12D1600RF 670

PDI = Low; PDQ = High mA

IAAnalog Supply Current ADC12D1000RF 625

ADC12D1600RF 670

PDI = High; PDQ = Low mA

ADC12D1000RF 625

PDI = PDQ = High 2.7 mA

ADC12D1600RF 490

PDI = PDQ = Low mA

ADC12D1000RF 410

ADC12D1600RF 290

PDI = Low; PDQ = High mA

Track-and-Hold and Clock Supply

ITC ADC12D1000RF 250

Current ADC12D1600RF 290

PDI = High; PDQ = Low mA

ADC12D1000RF 250

PDI = PDQ = High 0.65 µA

PDI = PDQ = Low 270 mA

PDI = Low; PDQ = High 140 mA

IDR Output Driver Supply Current PDI = High; PDQ = Low 140 mA

PDI = PDQ = High 6 µA

ADC12D1600RF 105

PDI = PDQ = Low mA

ADC12D1000RF 55

ADC12D1600RF 50

PDI = Low; PDQ = High mA

IEDigital Encoder Supply Current ADC12D1000RF 30

ADC12D1600RF 50

PDI = High; PDQ = Low mA

ADC12D1000RF 30

PDI = PDQ = High 34 µA

ADC12D1600RF 2090 2310(1)

1:2 DEMUX MODE mA

PDI = PDQ = Low ADC12D1000RF 1875 2105(1)

ITOTAL Total Supply Current ADC12D1600RF 2075

NON-DEMUX MODE mA

PDI = PDQ = Low ADC12D1000RF 1800

1:2 DEMUX MODE

ADC12D1600RF 4 4.4(1)

PDI = PDQ = Low W

ADC12D1000RF 3.6 4(1)

ADC12D1600RF 2.2

PDI = Low; PDQ = High W

ADC12D1000RF 2

PCPower Consumption ADC12D1600RF 2.2

PDI = High; PDQ = Low W

ADC12D1000RF 2

PDI = PDQ = High 6.4 mW

NON-DEMUX MODE

ADC12D1600RF 3.94

PDI = PDQ = Low W

ADC12D1000RF 3.42

(1) TA= TMIN to TMAX

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4.13 Electrical Characteristics: AC

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SAMPLING CLOCK (CLK)

ADC12D1600RF 1.6(1)

Maximum Sampling Clock

fCLK (max) GHz

Frequency ADC12D1000RF 1(1)

Non-DES Mode; LFS = 0b300(1) MHz

fCLK (min) Minimum Sampling Clock Frequency Non-DES Mode; LFS = 1b150(1) MHz

DES Mode 500(1) MHz

Sampling Clock Duty Cycle fCLK(min) ≤fCLK ≤fCLK(max)(2) 20%(1) 50% 80%(1)

ADC12D1600RF 200(1) 500

tCL Sampling Clock Low Time See (3) ps

ADC12D1000RF 125(1) 312.5

ADC12D1600RF 200(1) 500

tCH Sampling Clock High Time See (3) ps

ADC12D1000RF 125(1) 312.5

DATA CLOCK (DCLKI, DCLKQ)

DCLK Duty Cycle See (3) 45%(1) 50% 55%(1)

tSR Setup Time DCLK_RST± See (2) 45 ps

tHR Hold Time DCLK_RST± See (2) 45 ps

Sampling

tPWR Pulse Width DCLK_RST± See (3) 5(1) Clock

Cycles

90° Mode(3) 4(1) Sampling

tSYNC_DLY DCLK Synchronization Delay Clock

0° Mode(3) 5(1) Cycles

Differential Low-to-High Transition

tLHT 10%-to-90%, CL= 2.5 pF(2) 200 ps

Time

Differential High-to-Low Transition

tHLT 10%-to-90%, CL= 2.5 pF(2) 200 ps

Time

ADC12D1600RF 500

tSU Data-to-DCLK Setup Time DDR 90° Mode(3) ps

ADC12D1000RF 870

ADC12D1600RF 500

tHDCLK-to-Data Hold Time DDR 90° Mode(3) ps

ADC12D1000RF 870

50% of DCLK transition to 50% of Data transition

tOSK DCLK-to-Data Output Skew ±50 ps

DDR 0° Mode, SDR Mode (3)

DATA INPUT-TO-OUTPUT

tAD Aperture Delay(2) Sampling CLK+ Rise to Acquisition of Data 1.29 ns

tAJ Aperture Jitter See (2) 0.2 ps (rms)

Sampling Clock-to Data Output 50% of Sampling Clock transition to 50% of Data

tOD 3.2 ns

Delay (in addition to Latency) transition(2)

DI, DQ Outputs 34(1)

Latency in 1:2 Demux Non-DES

Mode(3) DId, DQd Outputs 35(1)

DI Outputs 34(1)

DQ Outputs 34.5(1)

Latency in 1:4 Demux DES Mode(3) Sampling

DId Outputs 35(1)

tLAT Clock

DQd Outputs 35.5(1) Cycles

DI Outputs 34(1)

Latency in Non-Demux Non-DES

Mode(3) DQ Outputs 34(1)

DI Outputs 34(1)

Latency in Non-Demux DES Mode(3) DQ Outputs 34.5(1)

Sampling

Differential VIN step from ±1.2 V to 0 V to accurate

tORR Over Range Recovery Time (2) 1 Clock

conversion Cycles

Non-DES Mode(3) 500 ns

Wake-Up Time (PDI/PDQ low to

tWU Rated Accuracy Conversion) DES Mode(3) 1 µs

(1) TA= TMIN to TMAX

(2) This parameter is specified by design and/or characterization and is not tested in production.

(3) This parameter is specified by design and is not tested in production.

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tOD

tAD

Sample N

Sample N+1

DId

Sample N-1

VINI+/-

CLK+

DCLKI+/-

(0° Phase)

DId, DI Sample N-35 and Sample N-34

Sample N-37 and Sample N-36

Sample N-39 and

Sample N-38

tOSK

tSU tH

DCLKI+/-

(90° Phase)

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4.14 Timing Requirements: Serial Port Interface

PARAMETER TEST CONDITIONS MIN NOM MAX UNIT

fSCLK Serial Clock Frequency See (1) 15 MHz

Serial Clock Low Time 30(2) ns

Serial Clock High Time 30(2) ns

tSSU Serial Data-to-Serial Clock Rising Setup Time See (1) 2.5 ns

tSH Serial Data-to-Serial Clock Rising Hold Time See (1) 1 ns

tSCS SCS-to-Serial Clock Rising Setup Time See (3) 2.5 ns

tHCS SCS-to-Serial Clock Falling Hold Time See (3) 1.5 ns

tBSU Bus turnaround time See (3) 10 ns

(1) This parameter is specified by design and is not tested in production.

(2) TA= TMIN to TMAX

(3) This parameter is specified by design and/or characterization and is not tested in production.

4.15 Timing Requirements: Calibration

PARAMETER TEST CONDITIONS MIN NOM MAX UNIT

Non-ECM Sampling

tCAL Calibration Cycle Time ECM CSS = 0bClock

4.1×107Cycles

ECM CSS = 1b

tCAL_L CAL Pin Low Time See (1) 1280(2) Sampling

Clock

tCAL_H CAL Pin High Time See (1) 1280(2) Cycles

Sampling

CalDly = Low 224(2)

tCalDly Calibration delay determined by CalDly Pin(1) Clock

CalDly = High 230(2) Cycles

(1) This parameter is specified by design and is not tested in production.

(2) TA= TMIN to TMAX

The timing for these figures is shown for the one input only (I or Q). However, both I- and Q-inputs may be used. For

this case, the I-channel functions precisely the same as the Q-channel, with VinI, DCLKI, DId and DI instead of VinQ,

DCLKQ, DQd and DQ. Both I- and Q-channel use the same CLK.

Figure 4-1. Clocking in 1:2 Demux Non-DES Mode

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tOD

tAD

Sample N

Sample N+1

DId

Sample N-1

VINQ+/-

CLK+/-

DCLKQ+/-

(0° Phase)

DQd, DId,

DQ, DI Sample N-35.5, N-35,

N-34.5, N-34

Sample N-37.5, N-37,

N-36.5, N-36

Sample N-39.5, N-39,

N-38.5, N-38

tOSK

tSU tH

DCLKQ+/-

(90° Phase)

Sample N-0.5

Sample

N-1.5

DQd

tOD

tAD

Sample N

Sample N+1

Sample N-1

VINQ+/-

CLK+

DCLKQ+/-

(0° Phase)

DQ Sample N-35

Sample N-36

tOSK

Sample N-34 Sample N-33

Sample N-37

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The timing for these figures is shown for the one input only (I or Q). However, both I- and Q-inputs may be used. For

this case, the I-channel functions precisely the same as the Q-channel, with VinI, DCLKI, DId and DI instead of VinQ,

DCLKQ, DQd and DQ. Both I- and Q-channel use the same CLK.

Figure 4-2. Clocking in Non-Demux Non-DES Mode

The timing for these figures is shown for the one input only (I or Q). However, both I- and Q-inputs may be used. For

this case, the I-channel functions precisely the same as the Q-channel, with VinI, DCLKI, DId and DI instead of VinQ,

DCLKQ, DQd and DQ. Both I- and Q-channel use the same CLK.

Figure 4-3. Clocking in 1:4 Demux DES Mode

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CalRun

POWER

SUPPLY

CAL

tCAL

Calibration Delay

determined by

CalDly (Pin V4)

tCalDly

tCAL_L

tCAL_H

CLK

Synchronizing Edge

DCLKI+

DCLKQ+

tHR

DCLK_RST-

tPWR

tSR

DCLK_RST+ tOD

tSYNC_DLY

tOD

tAD

Sample N

Sample N+1

Sample N-1

VINQ+/-

CLK+

DCLKQ+/-

(0° Phase)

DQ, DI Sample N-35.5, N-35

tOSK

Sample N-34.5, N-34 Sample N-33.5, N-33

Sample N-36.5, N-36Sample N-37.5, N-37

Sample N + 0.5

Sample N - 0.5

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The timing for these figures is shown for the one input only (I or Q). However, both I- and Q-inputs may be used. For

this case, the I-channel functions precisely the same as the Q-channel, with VinI, DCLKI, DId and DI instead of VinQ,

DCLKQ, DQd and DQ. Both I- and Q-channel use the same CLK.

Figure 4-4. Clocking in Non-Demux Mode DES Mode

Figure 4-5. Data Clock Reset Timing (Demux Mode)

Figure 4-6. Power-on and On-Command Calibration Timing

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ACTUAL

POSITIVE

FULL-SCALE

TRANSITION

-VIN/2

ACTUAL NEGATIVE

FULL-SCALE TRANSITION

1111 1111 1111 (4095)

1111 1111 1110 (4094)

1111 1111 1101 (4093)

MID-SCALE

TRANSITION

(VIN+) < (VIN-) (VIN+) > (VIN-)

0.0V

Differential Analog Input Voltage (+VIN/2) - (-VIN/2)

Output

Code

OFFSET

ERROR

1000 0000 0000 (2048)

0111 1111 1111 (2047)

IDEAL

POSITIVE

FULL-SCALE

TRANSITION

POSITIVE

FULL-SCALE

ERROR

NEGATIVE

FULL-SCALE

ERROR

IDEAL NEGATIVE

FULL-SCALE TRANSITION

+VIN/2

0000 0000 0000 (0)

0000 0000 0001 (1)

0000 0000 0010 (2)

SCLK

18 9 24

Single Register Access

SCS

SDI Command Field

MSB LSB

Data Field

tSSU

tSH

tSCS

tHCS

SDO

read mode)

MSB LSB

Data Field

tBSU

High Z High Z

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Figure 4-7. Serial Interface Timing

Figure 4-8. Input / Output Transfer Characteristic

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0 4095

-0.75

-0.50

-0.25

0.00

0.25

0.50

0.75

DNL (LSB)

OUTPUT CODE

0 4095

-0.75

-0.50

-0.25

0.00

0.25

0.50

0.75

DNL (LSB)

OUTPUT CODE

-50 0 50 100

-1.0

-0.5

0.0

0.5

1.0

INL (LSB)

TEMPERATURE (°C)

+INL

-INL

-50 0 50 100

-1.0

-0.5

0.0

0.5

1.0

INL (LSB)

TEMPERATURE (°C)

+INL

-INL

0 4095

-3

-2

-1

INL (LSB)

OUTPUT CODE

0 4095

-3

-2

-1

INL (LSB)

TEMPERATURE (°C)

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4.16 Typical Characteristics

VA= VDR = VTC = VE= 1.9 V, fCLK = 1600 MHz / 1000 MHz for the ADC12D1600RF / ADC12D1000RF,

respectively, fIN = 498 MHz, TA= 25°C, I-channel, Demux Non-DES Mode, unless otherwise stated.

Figure 4-9. INL vs Code (ADC12D1600RF) Figure 4-10. INL vs Code (ADC12D1000RF)

Figure 4-11. INL vs Temperature (ADC12D1600RF) Figure 4-12. INL vs Temperature (ADC12D1000RF)

Figure 4-13. DNL vs Code (ADC12D1600RF) Figure 4-14. DNL vs Code (ADC12D1000RF)

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0 1000 2000 3000

ENOB

INPUT FREQUENCY (MHz)

NON-DES MODE

DES MODE

0.75 1.00 1.25 1.50 1.75

ENOB

VCMI(V)

NON-DES MODE

DES MODE

-50 0 50 100

ENOB

TEMPERATURE (°C)

NON-DES MODE

DES MODE

1.8 1.9 2.0 2.1 2.2

ENOB

VA(V)

NON-DES MODE

DES MODE

-50 0 50 100

-0.50

-0.25

0.00

0.25

0.50

DNL (LSB)

TEMPERATURE (°C)

+DNL

-DNL

-50 0 50 100

-0.50

-0.25

0.00

0.25

0.50

DNL (LSB)

TEMPERATURE (°C)

+DNL

-DNL

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Typical Characteristics (continued)

Figure 4-15. DNL vs Temperature (ADC12D1600RF) Figure 4-16. DNL vs Temperature (ADC12D1000RF)

Figure 4-17. ENOB vs Temperature (ADC12D1600RF) Figure 4-18. ENOB vs Supply Voltage (ADC12D1600RF)

Figure 4-19. ENOB vs Input Frequency (ADC12D1600RF) Figure 4-20. ENOB vs VCMI (ADC12D1600RF)

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-50 0 50 100

-80

-70

-60

-50

-40

THD (dBc)

TEMPERATURE (°C)

NON-DES MODE

DES MODE

1.8 1.9 2.0 2.1 2.2

-80

-70

-60

-50

-40

THD (dBc)

VA(V)

NON-DES MODE

DES MODE

1.8 1.9 2.0 2.1 2.2

SNR (dB)

VA(V)

NON-DES MODE

DES MODE

0 1000 2000 3000

SNR (dB)

INPUT FREQUENCY (MHz)

NON-DES MODE

DES MODE

0.75 1.00 1.25 1.50 1.75

ENOB

VCMI(V)

NON-DES MODE

DES MODE

-50 0 50 100

SNR (dB)

TEMPERATURE (°C)

NON-DES MODE

DES MODE

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Typical Characteristics (continued)

Figure 4-21. ENOB vs VCMI (ADC12D1000RF) Figure 4-22. SNR vs Temperature (ADC12D1600RF)

Figure 4-23. SNR vs Supply Voltage (ADC12D1600RF) Figure 4-24. SNR vs Input Frequency (ADC12D1600RF)

Figure 4-25. THD vs Temperature (ADC12D1600RF) Figure 4-26. THD vs Supply Voltage (ADC12D1600RF)

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0 1000 2000 3000

-100

-90

-80

-70

-60

-50

-40

CROSSTALK (dBFS)

AGGRESSOR INPUT FREQUENCY (MHz)

NON-DES MODE

0 1000 2000 3000

-100

-90

-80

-70

-60

-50

-40

CROSSTALK (dBFS)

AGGRESSOR INPUT FREQUENCY (MHz)

NON-DES MODE

1.8 1.9 2.0 2.1 2.2

SFDR (dBc)

VA(V)

NON-DES MODE

DES MODE

0 1000 2000 3000

SFDR (dBc)

INPUT FREQUENCY (MHz)

NON-DES MODE

DES MODE

0 1000 2000 3000

-80

-70

-60

-50

-40

THD (dBc)

INPUT FREQUENCY (MHz)

NON-DES MODE

DES MODE

-50 0 50 100

SFDR (dBc)

TEMPERATURE (°C)

NON-DES MODE

DES MODE

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Typical Characteristics (continued)

Figure 4-27. THD vs Input Frequency (ADC12D1600RF) Figure 4-28. SFDR vs Temperature (ADC12D1600RF)

Figure 4-29. SFDR vs Supply Voltage (ADC12D1600RF) Figure 4-30. SFDR vs Input Frequency (ADC12D1600RF)

Figure 4-31. CROSSTALK vs Source Frequency (ADC12D1600RF) Figure 4-32. CROSSTALK vs Source Frequency (ADC12D1000RF)

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0 250 500 750 1000

2.0

2.5

3.0

3.5

4.0

4.5

5.0

POWER (W)

CLOCK FREQUENCY (MHz)

DEMUX MODE

NON-DEMUX MODE

0 1000 2000 3000 4000

-15

-12

-9

-6

-3

SIGNAL GAIN (dB)

INPUT FREQUENCY (MHz)

DESI MODE

DESIQ MODE

NON-DES, DESCLKIQ MODE

0 400 800 1200 1600

2.0

2.5

3.0

3.5

4.0

4.5

5.0

POWER (W)

CLOCK FREQUENCY (MHz)

DEMUX MODE

NON-DEMUX MODE

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Typical Characteristics (continued)

Figure 4-33. Insertion Loss (ADC12D1x00RF) Figure 4-34. Power Consumption vs Clock Frequency

(ADC12D1600RF)

Figure 4-35. Power Consumption vs Clock Frequency (ADC12D1000RF)

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5 Detailed Description

5.1 Overview

The ADC12D1x00RF device is a versatile A/D converter with an innovative architecture which permits

very high-speed operation. The controls available ease the application of the device to circuit solutions.

Optimum performance requires adherence to the provisions discussed here and in Application Information.

This section covers an overview, a description of control modes (Extended Control Mode and Non-

Extended Control Mode), and features.

The ADC12D1x00RF uses a calibrated folding and interpolating architecture that achieves a high Effective

Number of Bits (ENOB). The use of folding amplifiers greatly reduces the number of comparators and

power consumption. Interpolation reduces the number of front-end amplifiers required, minimizing the load

on the input signal and further reducing power requirements. In addition to correcting other non-idealities,

ON-chip calibration reduces the INL bow often seen with folding architectures. The result is an extremely

fast, high performance, low power converter.

The analog input signal (which is within the converter's input voltage range) is digitized to twelve bits at

speeds of 150/150 MSPS to 3.2/2.0 GSPS, typical. Differential input voltages below negative full-scale will

cause the output word to consist of all zeroes. Differential input voltages above positive full-scale will

cause the output word to consist of all ones. Either of these conditions at the I- or Q-input will cause the

Out-of-Range I-channel or Q-channel output (ORI or ORQ), respectively, to output a logic-high signal.

In ECM, an expanded feature set is available through the Serial Interface. The ADC12D1x00RF builds

upon previous architectures, introducing a new DES Mode timing adjust feature, AutoSync feature for

multi-chip synchronization and increasing to 15-bit for gain and 12-bit plus sign for offset the independent

programmable adjustment for each channel.

Each channel has a selectable output demultiplexer which feeds two LVDS buses. If the 1:2 Demux Mode

is selected, the output data rate is reduced to half the input sample rate on each bus. When Non-Demux

Mode is selected, the output data rate on each channel is at the same rate as the input sample clock and

only one 12-bit bus per channel is active.

5.2 Functional Block Diagram

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5.3 Feature Description

The ADC12D1x00RF offers many features to make the device convenient to use in a wide variety of

applications. Table 5-1 is a summary of the features available, as well as details for the control mode

chosen. "N/A" means "Not Applicable."

Table 5-1. Features and Modes

CONTROL PIN

FEATURE NON-ECM ACTIVE IN ECM DEFAULT ECM STATE

ECM

INPUT CONTROL AND ADJUST

Selected through VCMO

AC/DC-coupled Mode Selection Yes Not available N/A

(Pin C2) Selected through the Config

Selected through FSR

Input Full-scale Range Adjust No Reg Mid FSR value

(Pin Y3) (Addr: 3hand Bh)

Selected through the Config

Input Offset Adjust Setting Not available N/A Reg Offset = 0 mV

(Addr: 2hand Ah)

DES / Non-DES Mode Selected through DES Selected through the DES Bit

No Non-DES Mode

Selection (Pin V5) (Addr: 0h; Bit: 7)

Selected through the DEQ, DIQ

DES Mode Input Selection Not available N/A Bits N/A

(Addr: 0h; Bits: 6:5)

Selected through the DCK Bit

DESCLKIQ Mode Not available N/A N/A

(Addr: Eh; Bit: 6)

Selected through the DES

DES Timing Adjust Not available N/A Timing Adjust Reg Mid skew offset

(Addr: 7h)

Selected through the Config

Sampling Clock Phase Adjust Not available N/A Reg tAD adjust disabled

(Addr: Chand Dh)

OUTPUT CONTROL AND ADJUST

Selected through Selected through the DPS Bit

DDR Clock Phase Selection No 0° Mode

DDRPh (Pin W4) (Addr: 0h; Bit: 14)

Selected through the SDR Bit

DDR / SDR DCLK Selection Not available N/A DDR Mode

(Addr: 0h; Bit: 2)

SDR Rising / Falling DCLK Selected through the DPS Bit

Not available N/A N/A

Selection (Addr: 0h; Bit: 14)

LVDS Differential Voltage Selected through the OVS Bit

Higher amplitude only N/A Higher amplitude

Amplitude Selection (Addr: 0h; Bit: 13)

LVDS Common-Mode Voltage Selected through VBG Yes Not available N/A

Amplitude Selection (Pin B1) Selected through the 2SC Bit

Output Formatting Selection Offset Binary only N/A Offset Binary

(Addr: 0h; Bit: 4)

Selected through TPM Selected through the TPM Bit

Test Pattern Mode at Output No TPM disabled

(Pin A4) (Addr: 0h; Bit: 12)

Demux/Non-Demux Mode Selected through NDM Yes Not available N/A

Selection (Pin A5) Selected through the Config Master Mode,

AutoSync Not available N/A Reg RCOut1/2 disabled

(Addr: Eh)

Selected through the Config

DCLK Reset Not available N/A Reg DCLK Reset disabled

(Addr: Eh; Bit: 0)

Selected through the TSE Bit

Time Stamp Not available N/A Time Stamp disabled

(Addr: 0h; Bit: 3)

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Table 5-1. Features and Modes (continued)

CONTROL PIN

FEATURE NON-ECM ACTIVE IN ECM DEFAULT ECM STATE

ECM

CALIBRATION

Selected through CAL Selected through the CAL Bit N/A

On-command Calibration Yes

(Pin D6) (Addr: 0h; Bit: 15) (CAL = 0)

Selected through

Power-on Calibration Delay CalDly Yes Not available N/A

Selection (Pin V4) Selected through the Config

Calibration Adjust Not available N/A Reg tCAL

(Addr: 4h)

Selected through the SSC Bit R/W calibration values

Read/Write Calibration Settings Not available N/A (Addr: 4h; Bit: 7) disabled

POWER DOWN

Selected through PDI Selected through the PDI Bit

Power-down I-channel Yes I-channel operational

(Pin U3) (Addr: 0h; Bit: 11)

Selected through PDQ Selected through the PDQ Bit

Power-down Q-channel Yes Q-channel operational

(Pin V3) (Addr: 0h; Bit: 10)

5.3.1 Input Control and Adjust

There are several features and configurations for the input of the ADC12D1x00RF so that it may be used

in many different applications. This section covers AC/DC-coupled Mode, input full-scale range adjust,

input offset adjust, DES/Non-DES Mode, and sampling clock phase adjust.

5.3.1.1 AC- and DC-coupled Mode

The analog inputs may be AC- or DC-coupled. See AC/DC-Coupled Mode Pin (VCMO) for information on

how to select the desired mode and DC-coupled Input Signals and AC-coupled Input Signals for

applications information.

5.3.1.2 Input Full-Scale Range Adjust

The input full-scale range for the ADC12D1x00RF may be adjusted through Non-ECM or ECM. In Non-

ECM, a control pin selects a higher or lower value; see Full-Scale Input Range Pin (FSR). In ECM, the

input full-scale range may be adjusted with 15-bits of precision. See VIN_FSR in Electrical Characteristics:

Analog Input/Output and Reference for electrical specification details. The higher and lower full-scale input

range settings in Non-ECM correspond to the mid and min full-scale input range settings in ECM. It is

necessary to execute an on-command calibration following a change of the input full-scale range. See

Memory for information about the registers.

5.3.1.3 Input Offset Adjust

The input offset adjust for the ADC12D1x00RF may be adjusted with 12-bits of precision plus sign through

ECM. See Memory for information about the registers.

5.3.1.4 DES Timing Adjust

The performance of the ADC12D1x00RF in DES Mode depends on how well the two channels are

interleaved, that is, that the clock samples either channel with precisely a 50% duty-cycle, each channel

has the same offset (nominally code 2047/2048), and each channel has the same full-scale range. The

ADC12D1x00RF includes an automatic clock phase background adjustment in DES Mode to automatically

and continuously adjust the clock phase of the I- and Q-channels. In addition to this, the residual fixed

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timing skew offset may be further manually adjusted, and further reduce timing spurs for specific

applications. See the DES Timing Adjust (Addr: 7h). As the DES Timing Adjust is programmed from 0dto

127d, the magnitude of the Fs/2-Fin timing interleaving spur will decrease to a local minimum and then

increase again. The default, nominal setting of 64dmay or may not coincide with this local minimum. The

user may manually skew the global timing to achieve the lowest possible timing interleaving spur.

5.3.1.5 Sampling Clock Phase Adjust

The sampling clock (CLK) phase may be delayed internally to the ADC up to 825 ps in ECM. This feature

is intended to help the system designer remove small imbalances in clock distribution traces at the board

level when multiple ADCs are used, or to simplify complex system functions such as beam steering for

phase array antennas.

Additional delay in the clock path also creates additional jitter when using the sampling clock phase adjust.

Because the sampling clock phase adjust delays all clocks, including the DCLKs and output data, the user

is strongly advised to use the minimal amount of adjustment and verify the net benefit of this feature in his

system before relying on it.

5.3.2 Output Control and Adjust

There are several features and configurations for the output of the ADC12D1x00RF so that it may be used

in many different applications. This section covers DDR clock phase, LVDS output differential and

common-mode voltage, output formatting, Demux/Non-demux Mode, Test Pattern Mode, and Time Stamp.

5.3.2.1 SDR / DDR Clock

The ADC12D1x00RF output data can be delivered in Double Data Rate (DDR) or Single Data Rate

(SDR). For DDR, the DCLK frequency is half the data rate and data is sent to the outputs on both edges

of DCLK; see Figure 5-1. The DCLK-to-Data phase relationship may be either 0° or 90°. For 0° Mode, the

Data transitions on each edge of the DCLK. Any offset from this timing is tOSK; see Electrical

Characteristics: AC for details. For 90° Mode, the DCLK transitions in the middle of each Data cell. Setup

and hold times for this transition, tSU and tH, may also be found in Electrical Characteristics: AC. The

DCLK-to-Data phase relationship may be selected through the DDRPh Pin in Non-ECM (see Dual Data

Rate Phase Pin (DDRPh)) or the DPS bit in the Configuration Register (Addr: 0h; Bit: 14) in ECM.

Figure 5-1. DDR DCLK-to-Data Phase Relationship

For SDR, the DCLK frequency is the same as the data rate and data is sent to the outputs on a single

edge of DCLK; see SDR DCLK-to-Data Phase Relationship. The Data may transition on either the rising

or falling edge of DCLK. Any offset from this timing is tOSK; see Electrical Characteristics: AC for details.

The DCLK rising / falling edge may be selected through the SDR bit in the Configuration Register (Addr:

0h; Bit: 2) in ECM only.

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DCLK

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DCLK

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Figure 5-2. SDR DCLK-to-Data Phase Relationship

5.3.2.2 LVDS Output Differential Voltage

The ADC12D1x00RF is available with a selectable higher or lower LVDS output differential voltage. This

parameter is VOD and may be found in Electrical Characteristics: Digital Control and Output Pin. The

desired voltage may be selected through the OVS Bit (Addr: 0h, Bit 13). For many applications, in which

the LVDS outputs are very close to an FPGA on the same board, for example, the lower setting is

sufficient for good performance; this will also reduce the possibility for EMI from the LVDS outputs to other

signals on the board. See Memory for more information.

5.3.2.3 LVDS Output Common-Mode Voltage

The ADC12D1x00RF is available with a selectable higher or lower LVDS output common-mode voltage.

This parameter is VOS and may be found in Electrical Characteristics: Digital Control and Output Pin. See

LVDS Output Common-mode Pin (VBG) for information on how to select the desired voltage.

5.3.2.4 Output Formatting

The formatting at the digital data outputs may be either offset binary or two's complement. The default

formatting is offset binary, but two's complement may be selected through the 2SC Bit (Addr: 0h, Bit 4);

see Memory for more information.

5.3.2.5 Test Pattern Mode

The ADC12D1x00RF can provide a test pattern at the four output buses independently of the input signal

to aid in system debug. In Test Pattern Mode, the ADC is disengaged and a test pattern generator is

connected to the outputs, including ORI and ORQ. The test pattern output is the same in DES Mode or

Non-DES Mode. Each port is given a unique 12-bit word, alternating between 1's and 0's. When the part is

programmed into the Demux Mode, the test pattern’s order is described in Table 5-2. If the I- or Q-channel

is powered down, the test pattern will not be output for that channel.

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Table 5-2. Test Pattern by Output Port in Demux Mode

TIME Qd Id Q I ORQ ORI COMMENTS

T0 000h004h008h010h0b0b

T1 FFFhFFBhFF7hFEFh1b1bPattern

T2 000h004h008h010h0b0bSequence

T3 FFFhFFBhFF7hFEFh1b1b

T4 000h004h008h010h0b0b

T5 000h004h008h010h0b0b

T6 FFFhFFBhFF7hFEFh1b1bPattern

T7 000h004h008h010h0b0bSequence

n+1

T8 FFFhFFBhFF7hFEFh1b1b

T9 000h004h008h010h0b0b

T10 000h004h008h010h0b0bPattern

T11 FFFhFFBhFF7hFEFh1b1bSequence

T12 000h004h008h010h0b0bn+2

T13 ... ... ... ... ... ...

When the part is programmed into the Non-Demux Mode, the test pattern’s order is described in Table 5-

Table 5-3. Test Pattern by Output Port in Non-Demux Mode

TIME Q I ORQ ORI COMMENTS

T0 000h004h0b0b

T1 000h004h0b0b

T2 FFFhFFBh1b1b

T3 FFFhFFBh1b1b

T4 000h004h0b0bPattern Sequence

T5 FFFhFFBh1b1b

T6 000h004h0b0b

T7 FFFhFFBh1b1b

T8 FFFhFFBh1b1b

T9 FFFhFFBh1b1b

T10 000h004h0b0b

T11 000h004h0b0bPattern Sequence

T12 FFFhFFBh1b1bn+1

T13 FFFhFFBh1b1b

T14 ... ... ... ...

5.3.2.6 Time Stamp

The Time Stamp feature enables the user to capture the timing of an external trigger event, relative to the

sampled signal. When enabled through the TSE Bit (Addr: 0h; Bit: 3), the LSB of the digital outputs (DQd,

DQ, DId, DI) captures the trigger information. In effect, the 12-bit converter becomes an 11-bit converter

and the LSB acts as a 1-bit converter with the same latency as the 11-bit converter. The trigger should be

applied to the DCLK_RST input. It may be asynchronous to the ADC sampling clock.

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5.3.3 Calibration Feature

The ADC12D1x00RF calibration must be run to achieve specified performance. The calibration procedure

is exactly the same regardless of how it was initiated or when it is run. Calibration trims the analog input

differential termination resistors, the CLK input resistor, and sets internal bias currents which affect the

linearity of the converter. This minimizes full-scale error, offset error, DNL, and INL, which results in the

maximum dynamic performance, as measured by: SNR, THD, SINAD (SNDR) and ENOB.

5.3.3.1 Calibration Control Pins and Bits

Table 5-4 is a summary of the pins and bits used for calibration. See Ball Descriptions and Equivalent

Circuits for complete pin information and Figure 4-6 for the timing diagram.

Table 5-4. Calibration Pins

PIN (BIT) NAME FUNCTION

D6 CAL Initiate calibration

(Addr: 0h; Bit 15) (Calibration)

CalDly

V4 Select power-on calibration delay

(Calibration Delay)

(Addr: 4h) Calibration Adjust Adjust calibration sequence

CalRun

B5 Indicates while calibration is running

(Calibration Running)

Rtrim+/- External resistor used to calibrate analog and

C1/D2 (Input termination trim resistor) CLK inputs

Rext+/- External resistor used to calibrate internal

C3/D3 (External Reference resistor) linearity

5.3.3.2 How to Execute a Calibration

Calibration may be initiated by holding the CAL pin low for at least tCAL_L clock cycles, and then holding it

high for at least another tCAL_H clock cycles, as defined in Electrical Characteristics: Calibration. The

minimum tCAL_L and tCAL_H input clock cycle sequences are required to ensure that random noise does not

cause a calibration to begin when it is not desired. The time taken by the calibration procedure is specified

as tCAL. The CAL Pin is active in both ECM and Non-ECM. However, in ECM, the CAL Pin is logically

OR'd with the CAL Bit, so both the pin and bit are required to be set low before executing another

calibration through either pin or bit.

5.3.3.3 Power-on Calibration

For standard operation, power-on calibration begins after a time delay following the application of power,

as determined by the setting of the CalDly Pin and measured by tCalDly (see Electrical Characteristics:

Calibration). This delay allows the power supply to come up and stabilize before the power-on calibration

takes place. The best setting (short or long) of the CalDly Pin depends upon the settling time of the power

supply.

TI strongly recommends setting CalDly Pin (to either logic-high or logic-low) before powering the device on

because this pin affects the power-on calibration timing. This may be accomplished by setting CalDly

through an external 1-kΩresistor connected to GND or VA. If the CalDly Pin is toggled while the device is

powered-on, it can execute a calibration even though the CAL Pin/Bit remains logic-low.

The power-on calibration will be not be performed if the CAL pin is logic-high at power-on. In this case, the

calibration cycle will not begin until the on-command calibration conditions are met. The ADC12D1x00RF

will function with the CAL pin held high at power up, but no calibration will be done and performance will

be impaired.

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If it is necessary to toggle the CalDly Pin before the system power-up sequence, then the CAL Pin/Bit

must be set to logic-high during the toggling and afterwards for 109Sampling Clock cycles. This will

prevent the power-on calibration, so an on-command calibration must be executed or the performance will

be impaired.

5.3.3.4 On-Command Calibration

In addition to the power-on calibration, TI recommends executing an on-command calibration whenever

the settings or conditions to the device are altered significantly, to obtain optimal parametric performance.

Some examples include: changing the FSR through either ECM or Non-ECM, power-cycling either

channel, and switching into or out of DES Mode. For best performance, TI also recommends that an on-

command calibration be run 20 seconds or more after application of power and whenever the operating

temperature changes significantly, relative to the specific system performance requirements.

Due to the nature of the calibration feature, TI recommends avoiding unnecessary activities on the device

while the calibration is taking place. For example, do not read or write to the Serial Interface or use the

DCLK Reset feature while calibrating the ADC. Doing so will impair the performance of the device until it is

re-calibrated correctly. Also, TI recommends not applying a strong narrow-band signal to the analog inputs

during calibration because this may impair the accuracy of the calibration; broad spectrum noise is

acceptable.

5.3.3.5 Calibration Adjust

The sequence of the calibration event itself may be adjusted. This feature can be used if a shorter

calibration time than the default is required; see tCAL in Electrical Characteristics: Calibration. However, the

performance of the device, when using this feature is not ensured.

The calibration sequence may be adjusted through CSS (Addr: 4h, Bit 14). The default setting of CSS =

1bexecutes both RIN and RIN_CLK Calibration (using Rtrim) and internal linearity Calibration (using Rext).

Executing a calibration with CSS = 0bexecutes only the internal linearity Calibration. The first time that

Calibration is executed, it must be with CSS = 1bto trim RIN and RIN_CLK. However, once the device is at

its operating temperature and RIN has been trimmed at least one time, it will not drift significantly. To save

time in subsequent calibrations, trimming RIN and RIN_CLK may be skipped, that is, by setting CSS = 0b.

5.3.3.6 Read/Write Calibration Settings

When the ADC performs a calibration, the calibration constants are stored in an array which is accessible

through the Calibration Values register (Addr: 5h). To save the time which it takes to execute a calibration,

tCAL, or to allow re-use of a previous calibration result, these values can be read from and written to the

can be used to load a previously determined set of values. For the calibration values to be valid, the ADC

must be operating under the same conditions, including temperature, at which the calibration values were

originally determined by the ADC.

To read calibration values from the SPI, do the following:

1. Set ADC to desired operating conditions.

2. Set SSC (Addr: 4h, Bit 7) to 1.

3. Read exactly 240 times the Calibration Values register (Addr: 5h). The register values are R0, R1, R2...

R239 where R0 is a dummy value. The contents of R<239:1> should be stored.

4. Set SSC (Addr: 4h, Bit 7) to 0.

5. Continue with normal operation.

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To write calibration values to the SPI, do the following:

1. Set ADC to operating conditions at which Calibration Values were previously read.

2. Set SSC (Addr: 4h, Bit 7) to 1.

3. Write exactly 239 times the Calibration Values register (Addr: 5h). The registers should be written with

stored register values R1, R2... R239.

4. Make two additional dummy writes of 0000h.

5. Set SSC (Addr: 4h, Bit 7) to 0.

6. Continue with normal operation.

5.3.3.7 Calibration and Power Down

If PDI and PDQ are simultaneously asserted during a calibration cycle, the ADC12D1x00RF will

immediately power down. The calibration cycle will continue when either or both channels are powered

back up, but the calibration will be compromised due to the incomplete settling of bias currents directly

after power up. Therefore, a new calibration should be executed upon powering the ADC12D1x00RF back

up. In general, the ADC12D1x00RF should be recalibrated when either or both channels are powered

back up, or after one channel is powered down. For best results, this should be done after the device has

stabilized to its operating temperature.

5.3.3.8 Calibration and the Digital Outputs

During calibration, the digital outputs (including DI, DId, DQ, DQd, and OR) are set logic-low, to reduce

noise. The DCLK runs continuously during calibration. After the calibration is completed and the CalRun

signal is logic-low, it takes an additional 60 Sampling Clock cycles before the output of the

ADC12D1x00RF is valid converted data from the analog inputs. This is the time it takes for the pipeline to

flush, as well as for other internal processes.

5.3.4 Power Down

On the ADC12D1x00RF, the I- and Q-channels may be powered down individually. This may be

accomplished through the control pins, PDI and PDQ, or through ECM. In ECM, the PDI and PDQ pins

are logically OR'd with the Control Register setting. See Power-Down I-channel Pin (PDI) and Power-

Down Q-channel Pin (PDQ) for more information.

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5.4 Device Functional Modes

5.4.1 DES and Non-DES Mode

The ADC12D1x00RF can operate in Dual-Edge Sampling (DES) or Non-DES Mode. The DES Mode

allows for a single analog input to be sampled by both I- and Q-channels. One channel samples the input

on the rising edge of the sampling clock and the other samples the same input signal on the falling edge

of the sampling clock. A single input is thus sampled twice per clock cycle, resulting in an overall sample

rate of twice the sampling clock frequency, for example, 3.2/2.0 GSPS with a 1600/1000 MHz sampling

clock. Because DES Mode uses both I- and Q-channels to process the input signal, both channels must

be powered up for the DES Mode to function properly.

In Non-ECM, only the I-input may be used for the DES Mode input. See Dual Edge Sampling Pin (DES)

for information on how to select the DES Mode. In ECM, either the I- or Q-input may be selected by first

using the DES bit (Addr: 0h, Bit 7) to select the DES Mode. The DEQ Bit (Addr: 0h, Bit: 6) is used to

select the Q-input, but the I-input is used by default. Also, both I- and Q-inputs may be driven externally,

that is, DESIQ Mode, by using the DIQ bit (Addr: 0h, Bit 5). See The Analog Inputs for more information

about how to drive the ADC in DES Mode.

In DESCLKIQ Mode, the I- and Q-channels sample their inputs 180° out-of-phase with respect to one

another, similar to the other DES Modes. DESCLKIQ Mode is similar to the DESIQ Mode, except that the

I- and Q-channels remain electrically separate internal to the ADC12D1x00RF. For this reason, both I- and

Q-inputs must be externally driven for the DESCLKIQ Mode. The DCK Bit (Addr: Eh, Bit: 6) is used to

select the 180° sampling clock mode.

The DESCLKIQ Mode results in the best bandwidth for the interleaved modes. In general, the bandwidth

decreases from Non-DES Mode to DES Mode (specifically, DESI or DESQ) because both channels are

sampling off the same input signal and non-ideal effects introduced by interleaving the two channels lower

the bandwidth. Driving both I- and Q-channels externally (DESIQ Mode and DESCLKIQ Mode) results in

better bandwidth because each channel is being driven, which reduces routing losses. The DESCLKIQ

Mode has better bandwidth than the DESIQ Mode because the routing internal to the ADC12D1600/1000

is simpler, which results in less insertion loss.

In the DES Mode, the outputs must be carefully interleaved to reconstruct the sampled signal. If the device

is programmed into the 1:4 Demux DES Mode, the data is effectively demultiplexed by 1:4. If the sampling

clock is 1600/1000 MHz, the effective sampling rate is doubled to 3.2/2.0 GSPS and each of the 4 output

buses has an output rate of 800/500 MSPS. All data is available in parallel. To properly reconstruct the

sampled waveform, the four bytes of parallel data that are output with each DCLK must be correctly

interleaved. The sampling order is as follows, from the earliest to the latest: DQd, DId, DQ, DI. See

Figure 4-3. If the device is programmed into the Non-Demux DES Mode, two bytes of parallel data are

output with each edge of the DCLK in the following sampling order, from the earliest to the latest: DQ, DI.

See Figure 4-4.

5.4.2 Demux and Non-Demux Mode

The ADC12D1x00RF may be in one of two demultiplex modes: Demux Mode or Non-Demux Mode (also

sometimes referred to as 1:1 Demux Mode). In Non-Demux Mode, the data from the input is simply output

at the sampling rate on one 12-bit bus. In Demux Mode, the data from the input is output at half the

sampling rate, on twice the number of buses. Demux and Non-Demux Mode may only be selected by the

NDM pin. In Non-DES Mode, the output data from each channel may be demultiplexed by a factor of 1:2

(1:2 Demux Non-DES Mode) or not demultiplexed (Non-Demux Non-DES Mode). In DES Mode, the

output data from both channels interleaved may be demultiplexed (1:4 Demux DES Mode) or not

demultiplexed (Non-Demux DES Mode).

See Table 5-5 for a selection of available modes.

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Table 5-5. Supported Demux, Data Rate Modes

NON-DEMUX MODE 1:2 DEMUX MODE

DDR 0° Mode only 0° Mode / 90° Mode

SDR Not available Rising / Falling Mode

5.5 Programming

5.5.1 Control Modes

The ADC12D1x00RF may be operated in one of two control modes: Non-extended Control Mode (Non-

ECM) or Extended Control Mode (ECM). In the simpler Non-ECM (also sometimes referred to as Pin

Control Mode), the user affects available configuration and control of the device through the control pins.

The ECM provides additional configuration and control options through a serial interface and a set of 16

registers, most of which are available to the customer.

5.5.1.1 Non-Extended Control Mode

In Non-extended Control Mode (Non-ECM), the Serial Interface is not active and all available functions are

controlled through various pin settings. Non-ECM is selected by setting the ECE Pin to logic-high. For the

control pins, "logic-high" and "logic-low" refer to VAand GND, respectively. Nine dedicated control pins

provide a wide range of control for the ADC12D1x00RF and facilitate its operation. These control pins

provide DES Mode selection, Demux Mode selection, DDR Phase selection, execute Calibration,

Calibration Delay setting, Power-down I-channel, Power-down Q-channel, Test Pattern Mode selection,

and Full-Scale Input Range selection. In addition to this, two dual-purpose control pins provide for AC/DC-

coupled Mode selection and LVDS output common-mode voltage selection. See Table 5-6 for a summary.

Table 5-6. Non-ECM Pin Summary

PIN NAME LOGIC-LOW LOGIC-HIGH FLOATING

DEDICATED CONTROL PINS

DES

DES Non-DES Mode Not valid

Mode

Demux

NDM Non-Demux Mode Not valid

Mode

DDRPh 0° Mode / Falling Mode 90° Mode / Rising Mode Not valid

CAL See Calibration Pin (CAL) Not valid

CalDly Shorter delay Longer delay Not valid

Power Down Power Down

PDI I-channel active I-channel I-channel

Power Down Power Down

PDQ Q-channel active Q-channel Q-channel

TPM Non-Test Pattern Mode Test Pattern Mode Not valid

FSR Lower FS input Range Higher FS input Range Not valid

DUAL-PURPOSE CONTROL PINS

VCMO AC-coupled operation Not allowed DC-coupled operation

Higher LVDS common-mode Lower LVDS common-mode

VBG Not allowed voltage voltage

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5.5.1.1.1 Dual Edge Sampling Pin (DES)

The Dual Edge Sampling (DES) Pin selects whether the ADC12D1x00RF is in DES Mode (logic-high) or

Non-DES Mode (logic-low). DES Mode means that a single analog input is sampled by both I- and Q-

channels in a time-interleaved manner. One of the ADCs samples the input signal on the rising sampling

clock edge (duty cycle corrected); the other ADC samples the input signal on the falling sampling clock

edge (duty cycle corrected). In Non-ECM, only the I-input may be used for DES Mode, a.k.a. DESI Mode.

In ECM, the Q-input may be selected through the DEQ Bit (Addr: 0h, Bit: 6), a.k.a. DESQ Mode. In ECM,

both the I- and Q-inputs may be selected, a.k.a. DESIQ or DESCLKIQ Mode.

To use this feature in ECM, use the DES bit in the Configuration Register (Addr: 0h; Bit: 7). See

DES/Non-DES Mode for more information.

5.5.1.1.2 Non-Demultiplexed Mode Pin (NDM)

The Non-Demultiplexed Mode (NDM) Pin selects whether the ADC12D1x00RF is in Demux Mode (logic-

low) or Non-Demux Mode (logic-high). In Non-Demux Mode, the data from the input is produced at the

sampled rate at a single 12-bit output bus. In Demux Mode, the data from the input is produced at half the

sampled rate at twice the number of output buses. For Non-DES Mode, each I- or Q-channel will produce

its data on one or two buses for Non-Demux or Demux Mode, respectively. For DES Mode, the selected

channel will produce its data on two or four buses for Non-Demux or Demux Mode, respectively.

This feature is pin-controlled only and remains active during both Non-ECM and ECM. See Demux/Non-

demux Mode for more information.

5.5.1.1.3 Dual Data Rate Phase Pin (DDRPh)

The Dual Data Rate Phase (DDRPh) Pin selects whether the ADC12D1x00RF is in 0° Mode (logic-low) or

90° Mode (logic-high) for DDR Mode. If the device is in SDR Mode, then the DDRPh Pin selects whether

the ADC12D1x00RF is in Falling Mode (logic-low) or Rising Mode (logic-high). For DDR Mode, the Data

may transition either with the DCLK transition (0° Mode) or halfway between DCLK transitions (90° Mode).

The DDRPh Pin selects the mode for both the I-channel: DI- and DId-to-DCLKI phase relationship and for

the Q-channel: DQ- and DQd-to-DCLKQ phase relationship.

To use this feature in ECM, use the DPS bit in the Configuration Register (Addr: 0h; Bit: 14). See SDR /

DDR Clock for more information.

5.5.1.1.4 Calibration Pin (CAL)

The Calibration (CAL) Pin may be used to execute an on-command calibration or to disable the power-on

calibration. The effect of calibration is to maximize the dynamic performance. To initiate an on-command

calibration through the CAL pin, bring the CAL pin high for a minimum of tCAL_H input clock cycles after it

has been low for a minimum of tCAL_L input clock cycles. Holding the CAL pin high upon power on will

prevent execution of the power-on calibration. In ECM, this pin remains active and is logically OR'd with

the CAL bit.

To use this feature in ECM, use the CAL bit in the Configuration Register (Addr: 0h; Bit: 15). See

Calibration Feature for more information.

5.5.1.1.5 Calibration Delay Pin (CalDly)

The Calibration Delay (CalDly) Pin selects whether a shorter or longer delay time is present, after the

application of power, until the start of the power-on calibration. The actual delay time is specified as tCalDly

and may be found in Electrical Characteristics: Calibration. This feature is pin-controlled only and remains

active in ECM. TI recommends selecting the desired delay time before power-on and not dynamically alter

this selection.

See Calibration Feature for more information.

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5.5.1.1.6 Power-Down I-channel Pin (PDI)

The Power-down I-channel (PDI) Pin selects whether the I-channel is powered down (logic-high) or active

(logic-low). The digital data output pins, DI and DId, (both positive and negative) are put into a high

impedance state when the I-channel is powered down. Upon return to the active state, the pipeline will

contain meaningless information and must be flushed. The supply currents (typicals and limits) are

available for the I-channel powered down or active and may be found in Electrical Characteristics: Power

Supply. The device should be recalibrated following a power-cycle of PDI (or PDQ).

This pin remains active in ECM. In ECM, either this pin or the PDI bit (Addr: 0h; Bit: 11) in the Control

5.5.1.1.7 Power-Down Q-channel Pin (PDQ)

The Power-down Q-channel (PDQ) Pin selects whether the Q-channel is powered down (logic-high) or

active (logic-low). This pin functions similarly to the PDI pin, except that it applies to the Q-channel. The

PDI and PDQ pins function independently of each other to control whether each I- or Q-channel is

powered down or active.

This pin remains active in ECM. In ECM, either this pin or the PDQ bit (Addr: 0h; Bit: 10) in the Control

5.5.1.1.8 Test Pattern Mode Pin (TPM)

The Test Pattern Mode (TPM) Pin selects whether the output of the ADC12D1x00RF is a test pattern

(logic-high) or the converted analog input (logic-low). The ADC12D1x00RF can provide a test pattern at

the four output buses independently of the input signal to aid in system debug. In TPM, the ADC is

disengaged and a test pattern generator is connected to the outputs, including ORI and ORQ. See Test

Pattern Mode for more information.

5.5.1.1.9 Full-Scale Input Range Pin (FSR)

The Full-Scale Input Range (FSR) Pin selects whether the full-scale input range for both the I- and Q-

channel is higher (logic-high) or lower (logic-low). The input full-scale range is specified as VIN_FSR in

Electrical Characteristics: Analog Input/Output and Reference. In Non-ECM, the full-scale input range for

each I- and Q-channel may not be set independently, but it is possible to do so in ECM. The device must

be calibrated following a change in FSR to obtain optimal performance.

To use this feature in ECM, use the Configuration Registers (Addr: 3hand Bh). See Input Control and

Adjust for more information.

5.5.1.1.10 AC- and DC-Coupled Mode Pin (VCMO)

The VCMO Pin serves a dual purpose. When functioning as an output, it provides the optimal common-

mode voltage for the DC-coupled analog inputs. When functioning as an input, it selects whether the

device is AC-coupled (logic-low) or DC-coupled (floating). This pin is always active, in both ECM and Non-

ECM.

5.5.1.1.11 LVDS Output Common-mode Pin (VBG)

The VBG Pin serves a dual purpose. When functioning as an output, it provides the bandgap reference.

When functioning as an input, it selects whether the LVDS output common-mode voltage is higher (logic-

high) or lower (floating). The LVDS output common-mode voltage is specified as VOS and may be found in

Electrical Characteristics: Digital Control and Output Pin. This pin is always active, in both ECM and Non-

ECM.

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5.5.1.2 Extended Control Mode

In Extended Control Mode (ECM), most functions are controlled through the Serial Interface. In addition to

this, several of the control pins remain active. See Table 5-1 for details. ECM is selected by setting the

ECE Pin to logic-low. If the ECE Pin is set to logic-high (Non-ECM), then the registers are reset to their

default values. So, a simple way to reset the registers is by toggling the ECE pin. Four pins on the

ADC12D1x00RF control the Serial Interface: SCS, SCLK, SDI and SDO. This section covers the Serial

Interface. The Register Definitions are located at the end of the data sheet so that they are easy to find,

see Memory.

5.5.1.2.1 The Serial Interface

The ADC12D1x00RF offers a Serial Interface that allows access to the sixteen control registers within the

device. The Serial Interface is a generic 4-wire (optionally 3-wire) synchronous interface that is compatible

with SPI type interfaces that are used on many micro-controllers and DSP controllers. Each serial

interface access cycle is exactly 24 bits long. A register-read or register-write can be accomplished in one

cycle. The signals are defined in such a way that the user can opt to simply join SDI and SDO signals in

his system to accomplish a single, bidirectional SDI/O signal. A summary of the pins for this interface may

be found in Table 5-7. See Figure 4-7 for the timing diagram and Electrical Characteristics: Serial Port

Interface for timing specification details. Control register contents are retained when the device is put into

power-down mode. If this feature is unused, the SCLK, SDI, and SCS pins may be left floating because

they each have an internal pullup.

Table 5-7. Serial Interface Pins

PIN NAME

C4 SCS (Serial Chip Select bar)

C5 SCLK (Serial Clock)

B4 SDI (Serial Data In)

A3 SDO (Serial Data Out)

SCS: Each assertion (logic-low) of this signal starts a new register access, that is, the SDI command field

must be ready on the following SCLK rising edge. The user is required to deassert this signal after the

24th clock. If the SCS is deasserted before the 24th clock, no data read/write will occur. For a read

operation, if the SCS is asserted longer than 24 clocks, the SDO output will hold the D0 bit until SCS is

deasserted. For a write operation, if the SCS is asserted longer than 24 clocks, data write will occur

normally through the SDI input upon the 24th clock. Setup and hold times, tSCS and tHCS, with respect to

the SCLK must be observed. SCS must be toggled in between register access cycles.

SCLK: This signal is used to register the input data (SDI) on the rising edge; and to source the output

data (SDO) on the falling edge. The user may disable the clock and hold it at logic-low. There is no

minimum frequency requirement for SCLK; see fSCLK in Electrical Characteristics: Serial Port Interface for

more details.

SDI: Each register access requires a specific 24-bit pattern at this input, consisting of a command field

and a data field. If the SDI and SDO wires are shared (3-wire mode), then during read operations, it is

necessary to tri-state the master which is driving SDI while the data field is being output by the ADC on

SDO. The master must be tri-stated before the falling edge of the 8th clock. If SDI and SDO are not shared

(4-wire mode), then this is not necessary. Setup and hold times, tSH and tSSU, with respect to the SCLK

must be observed.

SDO: This output is normally tri-stated and is driven only when SCS is asserted, the first 8 bits of

command data have been received and it is a READ operation. The data is shifted out, MSB first, starting

with the 8th clock's falling edge. At the end of the access, when SCS is deasserted, this output is tri-stated

once again. If an invalid address is accessed, the data sourced will consist of all zeroes. If it is a read

operation, there will be a bus turnaround time, tBSU, from when the last bit of the command field was read

in until the first bit of the data field is written out.

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SDI

SDO

R/W 1 0 A3 A2 A1 A0 X D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

21 43 65 87 109 1211 1413 1615 1817 2019 2221 2423 25

SCLK

SCSb

SDI

SDO

R/W 1 0 A3 A2 A1 A0 X

D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0D15

21 43 65 87 109 1211 1413 1615 1817 2019 2221 2423 25

*Only required to be tri-stated in 3-wire mode.

SCLK

SCSb

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Table 5-8 shows the Serial Interface bit definitions.

Table 5-8. Command and Data Field Definitions

BIT NO. NAME COMMENTS

1bindicates a read operation

1 Read/Write (R/W) 0bindicates a write operation

2-3 Reserved Bits must be set to 10b

16 registers may be

4-7 A<3:0> addressed. The order is MSB

first

8 X This is a "don't care" bit

Data written to or read from

9-24 D<15:0> addressed register

The serial data protocol is shown for a read and write operation in Figure 5-3 and Figure 5-4, respectively.

Figure 5-3. Serial Data Protocol - Read Operation

Figure 5-4. Serial Data Protocol - Write Operation

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5.6 Register Maps

Eleven read/write registers provide several control and configuration options in the Extended Control

Mode. These registers have no effect when the device is in the Non-extended Control Mode. Each register

description below also shows the Power-On Reset (POR) state of each control bit. See Table 5-9 for a

summary.

Table 5-9. Register Addresses

A3 A2 A1 A0 HEX REGISTER ADDRESSED

00000hConfiguration Register 1

00011hReserved

00102hI-channel Offset Adjust

00113hI-channel Full-Scale Range Adjust

01004hCalibration Adjust

01015hCalibration Values

01106hReserved

01117hDES Timing Adjust

10008hReserved

10019hReserved

1010AhQ-channel Offset Adjust

1011BhQ-channel Full-Scale Range Adjust

1100ChAperture Delay Coarse Adjust

1101DhAperture Delay Fine Adjust

1110EhAutoSync

1111FhReserved

Table 5-10. Configuration Register 1

Addr: 0h(0000b) POR state: 2000h

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name CAL DPS OVS TPM PDI PDQ Res LFS DES DEQ DIQ 2SC TSE SDR Res

POR 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 CAL: Calibration Enable. When this bit is set to 1b, an on-command calibration is initiated. This bit is not reset automatically

upon completion of the calibration. Therefore, the user must reset this bit to 0band then set it to 1bagain to execute another

calibration. This bit is logically OR'd with the CAL Pin; both bit and pin must be set to 0bbefore either is used to execute a

calibration.

Bit 14 DPS: DCLK Phase Select. In DDR, set this bit to 0bto select the 0° Mode DDR Data-to-DCLK phase relationship and to 1bto

select the 90° Mode. In SDR, set this bit to 0bto transition the data on the Rising edge of DCLK; set this bit to 1bto transition

the data on the Falling edge of DCLK. (1)

Bit 13 OVS: Output Voltage Select. This bit sets the differential voltage level for the LVDS outputs including Data, OR, and DCLK. 0b

selects the lower level and 1bselects the higher level. See VOD in Electrical Characteristics: Digital Control and Output Pin for

details.

Bit 12 TPM: Test Pattern Mode. When this bit is set to 1b, the device will continually output a fixed digital pattern at the digital Data

and OR outputs. When set to 0b, the device will continually output the converted signal, which was present at the analog

inputs. See Test Pattern Mode for details about the TPM pattern.

Bit 11 PDI: Power-down I-channel. When this bit is set to 0b, the I-channel is fully operational; when it is set to 1b, the I-channel is

powered-down. The I-channel may be powered-down through this bit or the PDI Pin, which is active, even in ECM.

Bit 10 PDQ: Power-down Q-channel. When this bit is set to 0b, the Q-channel is fully operational; when it is set to 1b, the Q-channel

is powered down. The Q-channel may be powered down through this bit or the PDQ Pin, which is active, even in ECM.

Bit 9 Reserved. Must be set as shown.

Bit 8 LFS: Low-Frequency Select. If the sampling clock (CLK) is at or below 300 MHz, set this bit to 1bfor improved performance.

Bit 7 DES: Dual-Edge Sampling Mode select. When this bit is set to 0b, the device will operate in the Non-DES Mode; when it is set

to 1b, the device will operate in the DES Mode. See DES/Non-DES Mode for more information.

(1) This pin and bit functionality is not tested in production test; performance is tested in the specified and default mode only.

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Bit 6 DEQ: DES Q-input select, a.k.a. DESQ Mode. When the device is in DES Mode, this bit selects the input that the device will

operate on. The default setting of 0bselects the I-input and 1bselects the Q-input.

Bit 5 DIQ: DES I- and Q-input, a.k.a. DESIQ Mode. When in DES Mode, setting this bit to 1bshorts the I- and Q-inputs internally to

the device. If the bit is left at its default 0b, the I- and Q-inputs remain electrically separate. In this mode, both the I- and Q-

inputs must be externally driven; see DES/Non-DES Mode for more information.(2)

The allowed DES Modes settings are shown below. For DESCLKIQ Mode, see Addr Eh.

Mode Addr 0h, Bit<7:5> Addr Eh, Bit<6>

Non-DES Mode 000b0b

DESI Mode 100b0b

DESQ Mode 110b0b

DESIQ Mode 101b0b

DESCLKIQ Mode 000b1b

Bit 4 2SC: Two's Complement output. For the default setting of 0b, the data is output in Offset Binary format; when set to 1b, the

data is output in Two's Complement format.(1)

Bit 3 TSE: Time Stamp Enable. For the default setting of 0b, the Time Stamp feature is not enabled; when set to 1b, the feature is

enabled. See Output Control and Adjust for more information about this feature.

Bit 2 SDR: Single Data Rate. For the default setting of 0b, the data is clocked in Dual Data Rate; when set to 1b, the data is clocked

in Single Data Rate. See Output Control and Adjust for more information about this feature. See Table 5-5 for a selection of

available modes.

Bits 1:0 Reserved. Must be set as shown.

(2) This feature functionality is not tested in production test; performance is tested in the specified/default mode only.

Table 5-11. Reserved

Addr: 1h(0001b) POR state: 2907h

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Res

POR 0 0 1 0 1 0 0 1 0 0 0 0 0 1 1 1

Bits 15:0 Reserved. Must be set as shown.

Table 5-12. I-channel Offset Adjust

Addr: 2h(0010b) POR state: 0000h

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Res OS OM(11:0)

POR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bits 15:13 Reserved. Must be set to 0b.

Bit 12 OS: Offset Sign. The default setting of 0bincurs a positive offset of a magnitude set by Bits 11:0 to the ADC output. Setting

this bet to 1bincurs a negative offset of the set magnitude.

Bits 11:0 OM(11:0): Offset Magnitude. These bits determine the magnitude of the offset set at the ADC output (straight binary coding).

The range is from 0 mV for OM(11:0) = 0dto 45 mV for OM(11:0) = 4095din steps of approximately 11 µV. Monotonicity is

specified by design only for the 9 MSBs.

Code Offset [mV]

0000 0000 0000 (default) 0

1000 0000 0000 22.5

1111 1111 1111 45

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Table 5-13. I-channel Full Scale Range Adjust

Addr: 3h(0011b) POR state: 4000h

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Res FM(14:0)

POR 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 Reserved. Must be set to 0b.

Bits 14:0 FM(14:0): FSR Magnitude. These bits increase the ADC full-scale range magnitude (straight binary coding.) The range is from

600 mV (0d) to 1000 mV (32767d) with the default setting at 800 mV (16384d). Monotonicity is specified by design only for the

9 MSBs. The mid-range (low) setting in ECM corresponds to the nominal (low) setting in Non-ECM. A greater range of FSR

values is available in ECM, that is, FSR values greater than 800 mV. See VIN_FSR in Electrical Characteristics: Analog

Input/Output and Reference for characterization details.

Code FSR [mV]

000 0000 0000 0000 600

100 0000 0000 0000 (default) 800

111 1111 1111 1111 1000

Table 5-14. Calibration Adjust

Addr: 4h(0100b) POR state: DB4Bh

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Res CSS Res SSC Res

POR 1 1 0 1 1 0 1 1 0 1 0 0 1 0 1 1

Bit 15 Reserved. Must be set as shown.

Bit 14 CSS: Calibration Sequence Select. The default 1bselects the following calibration sequence: reset all previously calibrated

elements to nominal values, do RIN Calibration, do internal linearity Calibration. Setting CSS = 0bselects the following

calibration sequence: do not reset RIN to its nominal value, skip RIN calibration, do internal linearity Calibration. The calibration

must be completed at least one time with CSS = 1bto calibrate RIN. Subsequent calibrations may be run with CSS = 0b(skip

RIN calibration) or 1b(full RIN and internal linearity Calibration).

Bits 13:8 Reserved. Must be set as shown.

Bit 7 SSC: SPI Scan Control. Setting this control bit to 1ballows the calibration values, stored in Addr: 5h, to be read/written. When

not reading/writing the calibration values, this control bit should left at its default 0bsetting. See Calibration Feature for more

information.

Bits 6:0 Reserved. Must be set as shown.

Table 5-15. Calibration Values

Addr: 5h(0101b) POR state: XXXXh

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name SS(15:0)

POR X X X X X X X X X X X X X X X X

Bits 15:0 SS(15:0): SPI Scan. When the ADC performs a self-calibration, the values for the calibration are stored in this register and may

be read from/ written to it. Set SSC (Addr: 4h, Bit 7) to read/write. See Calibration Feature for more information.

Table 5-16. Reserved

Addr: 6h(0110b) POR state: 1C2Eh

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Res

POR 0 0 0 1 1 1 0 0 0 0 1 0 1 1 1 0

Bits 15:0 Reserved. Must be set as shown.

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Table 5-17. DES Timing Adjust

Addr: 7h(0111b) POR state: 8142h

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name DTA(6:0) Res

POR 1 0 0 0 0 0 0 1 0 1 0 0 0 0 1 0

Bits 15:9 DTA(6:0): DES Mode Timing Adjust. In the DES Mode, the time at which the falling edge sampling clock samples relative to

the rising edge of the sampling clock may be adjusted; the automatic duty cycle correction continues to function. See Input

Control and Adjust for more information. The nominal step size is 30fs.

Bits 8:0 Reserved. Must be set as shown.

Table 5-18. Reserved

Addr: 8h(1000b) POR state: 0F0Fh

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Res

POR 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

Bits 15:0 Reserved. Must be set as shown.

Table 5-19. Reserved

Addr: 9h(1001b) POR state: 0000h

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Res

POR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bits 15:0 Reserved. Must be set as shown.

Table 5-20. Q-channel Offset Adjust

Addr: Ah(1010b) POR state: 0000h

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Res OS OM(11:0)

POR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bits 15:13 Reserved. Must be set to 0b.

Bit 12 OS: Offset Sign. The default setting of 0bincurs a positive offset of a magnitude set by Bits 11:0 to the ADC output. Setting

this bet to 1bincurs a negative offset of the set magnitude.

Bits 11:0 OM(11:0): Offset Magnitude. These bits determine the magnitude of the offset set at the ADC output (straight binary coding).

The range is from 0 mV for OM(11:0) = 0dto 45 mV for OM(11:0) = 4095din steps of approximately 11 µV. Monotonicity is

specified by design only for the 9 MSBs.

Code Offset [mV]

0000 0000 0000 (default) 0

1000 0000 0000 22.5

1111 1111 1111 45

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Table 5-21. Q-channel Full-Scale Range Adjust

Addr: Bh(1011b) POR state: 4000h

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Res FM(14:0)

POR 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 Reserved. Must be set to 0b.

Bits 14:0 FM(14:0): FSR Magnitude. These bits increase the ADC full-scale range magnitude (straight binary coding.) The range is from

600 mV (0d) to 1000 mV (32767d) with the default setting at 800 mV (16384d). Monotonicity is specified by design only for the

9 MSBs. The mid-range (low) setting in ECM corresponds to the nominal (low) setting in Non-ECM. A greater range of FSR

values is available in ECM, that is, FSR values greater than 800 mV. See VIN_FSR in Electrical Characteristics: Analog

Input/Output and Reference for characterization details.

Code FSR [mV]

000 0000 0000 0000 600

100 0000 0000 0000 (default) 800

111 1111 1111 1111 1000

Table 5-22. Aperture Delay Coarse Adjust

Addr: Ch(1100b) POR state: 0004h

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name CAM(11:0) STA DCC Res

POR 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0

Bits 15:4 CAM(11:0): Coarse Adjust Magnitude. This 12-bit value determines the amount of delay that will be applied to the input CLK

signal. The range is 0 ps delay for CAM(11:0) = 0dto a maximum delay of 825 ps for CAM(11:0) = 2431d(±95 ps due to PVT

variation) in steps of approximately 340 fs. For code CAM(11:0) = 2432dand above, the delay saturates and the maximum

delay applies. Additional, finer delay steps are available in register Dh. The STA (Bit 3) must be selected to enable this

function.

Bit 3 STA: Select tAD Adjust. Set this bit to 1bto enable the tAD adjust feature, which will make both coarse and fine adjustment

settings, that is, CAM(11:0) and FAM(5:0), available.

Bit 2 DCC: Duty Cycle Correct. This bit can be set to 0bto disable the automatic duty-cycle stabilizer feature of the chip. This

feature is enabled by default.

Bits 1:0 Reserved. Must be set to 0b.

Table 5-23. Aperture Delay Fine Adjust

Addr: Dh(1101b) POR state: 0000h

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name FAM(5:0) Res Res

POR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bits 15:10 FAM(5:0): Fine Aperture Adjust Magnitude. This 6-bit value determines the amount of additional delay that will be applied to

the input CLK when the Clock Phase Adjust feature is enabled through STA (Addr: Ch, Bit 3). The range is straight binary from

0 ps delay for FAM(5:0) = 0dto 2.3 ps delay for FAM(5:0) = 63d(±300 fs due to PVT variation) in steps of approximately 36 fs.

Bits 9:0 Reserved. Must be set as shown.

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Table 5-24. AutoSync(1)

Addr: Eh(1110b) POR state: 0003h

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name DRC(8:0) DCK Res SP(1:0) ES DOC DR

POR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1

(1) This feature functionality is not tested in production test; performance is tested in the specified/default mode only.

Bits 15:7 DRC(8:0): Delay Reference Clock (8:0). These bits may be used to increase the delay on the input reference clock when

synchronizing multiple ADCs. The delay may be set from a minimum of 0s (0d) to a maximum of 1200 ps (319d). The delay

remains the maximum of 1200 ps for any codes above or equal to 319d. See Synchronizing Multiple ADC12D1600/1000RFS

in a System for more information.

Bit 6 DCK: DESCLKIQ Mode. Set this bit to 1bto enable Dual-Edge Sampling, in which the Sampling Clock samples the I- and Q-

channels 180º out of phase with respect to one another, that is, the DESCLKIQ Mode. To select the DESCLKIQ Mode, Addr:

0h, Bits <7:5> must also be set to 000b. See Input Control and Adjust for more information. (1)

Bit 5 Reserved. Must be set as shown.

Bits 4:3 SP(1:0): Select Phase. These bits select the phase of the reference clock which is latched. The codes correspond to the

following phase shift:

00 = 0°

01 = 90°

10 = 180°

11 = 270°

Bit 2 ES: Enable Slave. Set this bit to 1bto enable the Slave Mode of operation. In this mode, the internal divided clocks are

synchronized with the reference clock coming from the master ADC. The master clock is applied on the input pins RCLK. If this

bit is set to 0b, then the device is in Master Mode.

Bit 1 DOC: Disable Output reference Clocks. Setting this bit to 0bsends a CLK/4 signal on RCOut1 and RCOut2. The default

setting of 1bdisables these output drivers. This bit functions as described, regardless of whether the device is operating in

Master or Slave Mode, as determined by ES (Bit 2).

Bit 0 DR: Disable Reset. The default setting of 1bleaves the DCLK_RST functionality disabled. Set this bit to 0bto enable

DCLK_RST functionality.

(1) This feature functionality is not tested in production test; performance is tested in the specified/default mode only.

Table 5-25. Reserved

Addr: Fh(1111b) POR state: 001Dh

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Res

POR 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1

Bits 15:0 Reserved. This address is read only.

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6 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

6.1 Application Information

6.1.1 The Analog Inputs

The ADC12D1x00RF will continuously convert any signal which is present at the analog inputs, as long as

a CLK signal is also provided to the device. This section covers important aspects related to the analog

inputs including: acquiring the input, driving the ADC in DES Mode, the reference voltage and FSR, out-of-

range indication, AC- and DC-coupled signals, and single-ended input signals.

6.1.1.1 Acquiring the Input

The Aperture Delay, tAD, is the amount of delay, measured from the sampling edge of the clock input, after

which signal present at the input pin is sampled inside the device. Data is acquired at the rising edge of

CLK+ in Non-DES Mode and both the falling and rising edges of CLK+ in DES Mode. In Non-DES Mode,

the I- and Q-channels always sample data on the rising edge of CLK+. In DES Mode, that is, DESI,

DESQ, DESIQ, and DESCLKIQ, the I-channel samples data on the rising edge of CLK+ and the Q-

channel samples data on the falling edge of CLK+. The digital equivalent of that data is available at the

digital outputs a constant number of sampling clock cycles later for the DI, DQ, DId and DQd output

buses, a.k.a. Latency, depending on the demultiplex mode which is selected. In addition to the Latency,

there is a constant output delay, tOD, before the data is available at the outputs. See tOD in the timing

diagrams. See tLAT, tAD, and tODin Electrical Characteristics: AC.

6.1.1.2 Driving the ADC in DES Mode

The ADC12D1x00RF can be configured as either a 2-channel, 1600/1000 GSPS device (Non-DES Mode)

or a 1-channel 3.2/2.0 GSPS device (DES Mode). When the device is configured in DES Mode, there is a

choice for with which input to drive the single-channel ADC. These are the 3 options:

DES – externally driving the I-channel input only. This is the default selection when the ADC is configured

in DES Mode. It may also be referred to as “DESI” for added clarity.

DESQ – externally driving the Q-channel input only.

DESIQ, DESCLKIQ – externally driving both the I- and Q-channel inputs. VinI+ and VinQ+ should be

driven with the exact same signal. VinI- and VinQ- should be driven with the exact same signal, which is

the differential compliment to the one driving VinI+ and VinQ+.

The input impedance for each I- and Q-input is 100-Ωdifferential (or 50-Ωsingle-ended), so the trace to

each VinI+, VinI-, VinQ+, and VinQ- should always be 50-Ωsingle-ended. If a single I- or Q-input is being

driven, then that input will present a 100-Ωdifferential load. For example, if a 50-Ωsingle-ended source is

driving the ADC, then a 1:2 balun will transform the impedance to 100-Ωdifferential. However, if the ADC

is being driven in DESIQ Mode, then the 100-Ωdifferential impedance from the I-input will appear in

parallel with the Q-input for a composite load of 50-Ωdifferential and a 1:1 balun would be appropriate.

See Figure 6-1 for an example circuit driving the ADC in DESIQ Mode. A recommended part selection is

using the Mini-Circuits TC1-1-13MA+ balun with Ccouple = 0.22 µF.

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VINI+

50:

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VINI-

1:1 Balun

Ccouple

100:

VINQ+

VINQ-

100:

Ccouple

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Figure 6-1. Driving DESIQ Mode

In the case that only one channel is used in Non-DES Mode or that the ADC is driven in DESI or DESQ

Mode, the unused analog input should be terminated to reduce any noise coupling into the ADC. See

Table 6-1 for details.* The timing for these figures is shown for the one input only (I or Q). However, both

I- and Q-inputs may be used. For this case, the I-channel functions precisely the same as the Q-channel,

with VinI, DCLKI, DId, and DI instead of VinQ, DCLKQ, DQd, and DQ. Both I- and Q-channel use the

same CLK.

Table 6-1. Unused Analog Input Recommended

Termination

MODE POWER COUPLING RECOMMENDED

DOWN TERMINATION

Non-DES Yes AC/DC Tie Unused+ and Unused- to

Vbg

DES/Non- No DC Tie Unused+ and Unused- to

DES Vbg

DES/Non- No AC Tie Unused+ to Unused-

DES

6.1.1.3 FSR and the Reference Voltage

The full-scale analog differential input range (VIN_FSR) of the ADC12D1x00RF is derived from an internal

bandgap reference. In Non-ECM, this full-scale range has two settings controlled by the FSR Pin; see

Full-Scale Input Range Pin (FSR). The FSR Pin operates on both I- and Q-channels. In ECM, the full-

scale range may be independently set for each channel through Addr:3hand Bhwith 15 bits of precision;

see Memory. The best SNR is obtained with a higher full-scale input range, but better distortion and SFDR

are obtained with a lower full-scale input range. It is not possible to use an external analog reference

voltage to modify the full-scale range, and this adjustment should only be done digitally, as described.

A buffered version of the internal bandgap reference voltage is made available at the VBG Pin for the user.

The VBG pin can drive a load of up to 80 pF and source or sink up to 100 μA. It should be buffered if more

current than this is required. This pin remains as a constant reference voltage regardless of what full-scale

range is selected and may be used for a system reference. VBG is a dual-purpose pin and it may also be

used to select a higher LVDS output common-mode voltage; see LVDS Output Common-mode Pin (VBG).

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VIN-

VCMO

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6.1.1.4 Out-Of-Range Indication

Differential input signals are digitized to 12 bits, based on the full-scale range. Signal excursions beyond

the full-scale range, that is, greater than +VIN_FSR/2 or less than -VIN_FSR/2, will be clipped at the output. An

input signal which is above the FSR will result in all 1's at the output and an input signal which is below

the FSR will result in all 0's at the output. When the conversion result is clipped for the I-channel input, the

Out-of-Range I-channel (ORI) output is activated such that ORI+ goes high and ORI- goes low while the

signal is out of range. This output is active as long as accurate data on either or both of the buses would

be outside the range of 000hto FFFh. The Q-channel has a separate ORQ which functions similarly.

6.1.1.5 Maximum Input Range

The recommended operating and absolute maximum input range may be found in Recommended

Operating Condtions and Absolute Maximum Ratings, respectively. Under the stated allowed operating

conditions, each Vin+ and Vin- input pin may be operated in the range from 0 V to 2.15 V if the input is a

continuous 100% duty cycle signal and from 0 V to 2.5 V if the input is a 10% duty cycle signal. The

absolute maximum input range for Vin+ and Vin- is from –0.15 V to 2.5 V. These limits apply only for input

signals for which the input common-mode voltage is properly maintained.

6.1.1.6 AC-Coupled Input Signals

The ADC12D1x00RF analog inputs require a precise common-mode voltage. This voltage is generated

on-chip when AC-coupling Mode is selected. See AC/DC-Coupled Mode Pin (VCMO) for more information

about how to select AC-coupled Mode.

In AC-coupled Mode, the analog inputs must of course be AC-coupled. For an ADC12D1x00RF used in a

typical application, this may be accomplished by on-board capacitors, as shown in Figure 6-2. For the

ADC12D1600RFRB, the SMA inputs on the Reference Board are directly connected to the analog inputs

on the ADC12D1600RF, so this may be accomplished by DC blocks (included with the hardware kit).

When the AC-coupled Mode is selected, an analog input channel that is not used (for example, in DES

Mode) should be connected to AC ground, for example, through capacitors to ground. Do not connect an

unused analog input directly to ground.

Figure 6-2. AC-Coupled Differential Input

The analog inputs for the ADC12D1x00RF are internally buffered, which simplifies the task of driving

these inputs and the RC pole which is generally used at sampling ADC inputs is not required. If the user

desires to place an amplifier circuit before the ADC, care should be taken to choose an amplifier with

adequate noise and distortion performance, and adequate gain at the frequencies used for the application.

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CLK-

ADC12D1600/1000RF

Ccouple

ADC12D1600/1000RF

VIN+

50:

Source

VIN-

1:2 Balun

Ccouple

100:

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6.1.1.7 DC-Coupled Input Signals

In DC-coupled Mode, the ADC12D1x00RF differential inputs must have the correct common-mode

voltage. This voltage is provided by the device itself at the VCMO output pin. TI recommends using this

voltage because the VCMO output potential will change with temperature and the common-mode voltage of

the driving device should track this change. Full-scale distortion performance falls off as the input

common-mode voltage deviates from VCMO. Therefore, TI recommends keeping the input common-mode

voltage within 100 mV of VCMO (typical), although this range may be extended to ±150 mV (maximum).

See VCMI in Electrical Characteristics: Analog Input/Output and Reference and ENOB vs. VCMI in Typical

Characteristics . Performance in AC- and DC-coupled Mode are similar, provided that the input common-

mode voltage at both analog inputs remains within 100 mV of VCMO.

6.1.1.8 Single-Ended Input Signals

The analog inputs of the ADC12D1x00RF are not designed to accept single-ended signals. The best way

to handle single-ended signals is to first convert them to differential signals before presenting them to the

ADC. The easiest way to accomplish single-ended to differential signal conversion is with an appropriate

balun-transformer, as shown in Figure 6-3.

Figure 6-3. Single-Ended to Differential Conversion Using a Balun

When selecting a balun, it is important to understand the input architecture of the ADC. The impedance of

the analog source should be matched to the ADC12D1x00RF's ON-chip 100-Ωdifferential input

termination resistor. The range of this termination resistor is specified as RIN in Electrical Characteristics:

Analog Input/Output and Reference.

6.1.2 The Clock Inputs

The ADC12D1x00RF has a differential clock input, CLK+ and CLK-, which must be driven with an AC-

coupled, differential clock signal. This provides the level shifting necessary to allow for the clock to be

driven with LVDS, PECL, LVPECL, or CML levels. The clock inputs are internally terminated to 100-Ω

differential and self-biased. This section covers coupling, frequency range, level, duty-cycle, jitter, and

layout considerations.

6.1.2.1 CLK Coupling

The clock inputs of the ADC12D1x00RF must be capacitively coupled to the clock pins as indicated in

Figure 6-4.

Figure 6-4. Differential Input Clock Connection

The choice of capacitor value will depend on the clock frequency, capacitor component characteristics and

other system economic factors. For example, on the ADC12D1600RFRB, the capacitors have the value

Ccouple = 4.7 nF which yields a highpass cutoff frequency, fc= 677.2 kHz.

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6.1.2.2 CLK Frequency

Although the ADC12D1x00RF is tested and its performance is ensured with a differential 1- or 1.6-GHz

sampling clock, it will typically function well over the input clock frequency range; see fCLK(min) and

fCLK(max) in Electrical Characteristics: AC. Operation up to fCLK(max) is possible if the maximum ambient

temperatures indicated are not exceeded. Operating at sample rates above fCLK(max) for the maximum

ambient temperature may result in reduced device reliability and product lifetime. This is due to the fact

that higher sample rates results in higher power consumption and die temperatures. If fCLK < 300 MHz,

enable LFS in the Control Register (Addr: 0h, Bit 8).

6.1.2.3 CLK Level

The input clock amplitude is specified as VIN_CLK in Electrical Characteristics: Sampling Clock. Input clock

amplitudes above the max VIN_CLK may result in increased input offset voltage. This would cause the

converter to produce an output code other than the expected 2047/2048 when both input pins are at the

same potential. Insufficient input clock levels will result in poor dynamic performance. Both of these results

may be avoided by keeping the clock input amplitude within the specified limits of VIN_CLK.

6.1.2.4 CLK Duty Cycle

The duty cycle of the input clock signal can affect the performance of any A/D converter. The

ADC12D1x00RF features a duty cycle clock correction circuit which can maintain performance over the

20%-to-80% specified clock duty-cycle range. This feature is enabled by default and provides improved

ADC clocking, especially in the Dual-Edge Sampling (DES) Mode.

6.1.2.5 CLK Jitter

High speed, high performance ADCs such as the ADC12D1x00RF require a very stable input clock signal

with minimum phase noise or jitter. ADC jitter requirements are defined by the ADC resolution (number of

bits), maximum ADC input frequency and the input signal amplitude relative to the ADC input full scale

range. The maximum jitter (the sum of the jitter from all sources) allowed to prevent a jitter-induced

reduction in SNR is found to be tJ(MAX) =(VIN(P-P)/ VFSR) × (1/(2(N+1) ×π× fIN))

where

• tJ(MAX) is the rms total of all jitter sources in seconds

• VIN(P-P) is the peak-to-peak analog input signal

• VFSR is the full-scale range of the ADC

• "N" is the ADC resolution in bits and fIN is the maximum input frequency, in Hertz, at the ADC analog

input. (1)

tJ(MAX) is the square root of the sum of the squares (RSS) of the jitter from all sources, including: the ADC

input clock, system, input signals and the ADC itself. Because the effective jitter added by the ADC is

beyond user control, TI recommends keeping the sum of all other externally added jitter to a minimum.

6.1.2.6 CLK Layout

The ADC12D1x00RF clock input is internally terminated with a trimmed 100-Ωresistor. The differential

input clock line pair should have a characteristic impedance of 100 Ωand (when using a balun), be

terminated at the clock source in that (100 Ω) characteristic impedance.

It is a good practice to keep the ADC input clock line as short as possible, tightly coupled, keep it well

away from any other signals, and treat it as a transmission line. Otherwise, other signals can introduce

jitter into the input clock signal. Also, the clock signal can introduce noise into the analog path if it is not

properly isolated.

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6.1.3 The LVDS Outputs

The Data, ORI, ORQ, DCLKI and DCLKQ outputs are LVDS. The electrical specifications of the LVDS

outputs are compatible with typical LVDS receivers available on ASIC and FPGA chips; but they are not

IEEE or ANSI communications standards compliant due to the low 1.9-V supply used on this chip. These

outputs should be terminated with a 100-Ωdifferential resistor placed as closely to the receiver as

possible. If the 100-Ωdifferential resistance is built in to the receiver, then an externally placed resistor is

not necessary. This section covers common-mode and differential voltage, and data rate.

6.1.3.1 Common-Mode and Differential Voltage

The LVDS outputs have selectable common-mode and differential voltage, VOS and VOD; see Electrical

Characteristics: Digital Control and Output Pin. See Output Control and Adjust for more information.

Selecting the higher VOS will also increase VOD slightly. The differential voltage, VOD, may be selected for

the higher or lower value. For short LVDS lines and low noise systems, satisfactory performance may be

realized with the lower VOD. This will also result in lower power consumption. If the LVDS lines are long

and/or the system in which the ADC12D1x00RF is used is noisy, it may be necessary to select the higher

VOD.

6.1.3.2 Output Data Rate

The data is produced at the output at the same rate it is sampled at the input. The minimum

recommended input clock rate for this device is fCLK(MIN); see Electrical Characteristics: AC. However, it is

possible to operate the device in 1:2 Demux Mode and capture data from just one 12-bit bus, for example,

just DI (or DId) although both DI and DId are fully operational. This will decimate the data by two and

effectively halve the data rate.

6.1.3.3 Terminating Unused LVDS Output Pins

If the ADC is used in Non-Demux Mode, then only the DI and DQ data outputs will have valid data present

on them. The DId and DQd data outputs may be left not connected; if unused, they are internally tri-

stated.

Similarly, if the Q-channel is powered-down (that is, PDQ is logic-high), the DQ data output pins, DCLKQ

and ORQ may be left not connected.

6.1.4 Synchronizing Multiple ADC12D1x00RFS in a System

The ADC12D1x00RF has two features to assist the user with synchronizing multiple ADCs in a system;

AutoSync and DCLK Reset. The AutoSync feature is new and designates one ADC12D1x00RF as the

Master ADC and other ADC12D1x00RFs in the system as Slave ADCs. The DCLK Reset feature

performs the same function as the AutoSync feature, but is the first generation solution to synchronizing

multiple ADCs in a system; it is disabled by default. For the application in which there are multiple Master

and Slave ADC12D1x00RFs in a system, AutoSync may be used to synchronize the Slave

ADC12D1x00RFs to each respective Master ADC12D1x00RF and the DCLK Reset may be used to

synchronize the Master ADC12D1x00RFs to each other.

If the AutoSync or DCLK Reset feature is not used, see Table 6-2 for recommendations about terminating

unused pins.

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CLK

Master

ADC12D1600/1000RF

Slave 1

ADC12D1600/1000RF

CLK

RCLK

RCOut1

RCOut2

DCLK

DCLK DCLK

RCLK

RCOut1

RCOut2

RCOut1

RCOut2

Slave 2

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Table 6-2. Unused AutoSync and DCLK Reset Pin

Recommendation

PINS UNUSED TERMINATION

RCLK+/- Do not connect.

RCOUT1+/- Do not connect.

RCOUT2+/- Do not connect.

DCLK_RST+ Connect to GND through 1-kΩresistor.

DCLK_RST- Connect to VAthrough 1-kΩresistor.

6.1.4.1 AutoSync Feature

AutoSync is a new feature which continuously synchronizes the outputs of multiple ADC12D1x00RFs in a

system. The feature may be used to synchronize the DCLK and data outputs of one or more Slave

ADC12D1x00RFs to one Master ADC12D1x00RF. Several advantages of this feature include: no special

synchronization pulse required, any upset in synchronization is recovered upon the next DCLK cycle, and

the Master/Slave ADC12D1x00RFs may be arranged as a binary tree so that any upset will quickly

propagate out of the system.

An example system is shown below in Figure 6-5 which consists of one Master ADC and two Slave ADCs.

For simplicity, only one DCLK is shown; in reality, there is DCLKI and DCLKQ, but they are always in

phase with one another.

Figure 6-5. AutoSync Example

To synchronize the DCLK (and Data) outputs of multiple ADCs, the DCLKs must transition at the same

time, as well as be in phase with one another. The DCLK at each ADC is generated from the CLK after

some latency, plus tOD minus tAD. Therefore, in order for the DCLKs to transition at the same time, the

CLK signal must reach each ADC at the same time. To tune out any differences in the CLK path to each

ADC, the tAD adjust feature may be used. However, using the tAD adjust feature will also affect when the

DCLK is produced at the output. If the device is in Demux Mode, then there are four possible phases

which each DCLK may be generated on because the typical CLK = 1GHz and DCLK = 250 MHz for this

case. The RCLK signal controls the phase of the DCLK, so that each Slave DCLK is on the same phase

as the Master DCLK.

The AutoSync feature may only be used through the Control Registers. For more information, see AN-

2132 Synchronizing Multiple GSPS ADCs in a System: The AutoSync Feature (SNAA073).

6.1.4.2 DCLK Reset Feature

The DCLK reset feature is available through ECM, but it is disabled by default. DCLKI and DCLKQ are

always synchronized, by design, and do not require a pulse from DCLK_RST to become synchronized.

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The DCLK_RST signal must observe certain timing requirements, which are shown in Figure 4-5 of the

Timing Diagrams. The DCLK_RST pulse must be of a minimum width and its deassertion edge must

observe setup and hold times with respect to the CLK input rising edge. These timing specifications are

listed as tPWR, tSR and tHR and may be found in Electrical Characteristics: AC.

The DCLK_RST signal can be asserted asynchronously to the input clock. If DCLK_RST is asserted, the

DCLK output is held in a designated state (logic-high) in Demux Mode; in Non-Demux Mode, the DCLK

continues to function normally. Depending upon when the DCLK_RST signal is asserted, there may be a

narrow pulse on the DCLK line during this reset event. When the DCLK_RST signal is deasserted, there

are tSYNC_DLY CLK cycles of systematic delay and the next CLK rising edge synchronizes the DCLK output

with those of other ADC12D1x00RFs in the system. For 90° Mode (DDRPh = logic-high), the

synchronizing edge occurs on the rising edge of CLK, 4 cycles after the first rising edge of CLK after

DCLK_RST is released. For 0° Mode (DDRPh = logic-low), this is 5 cycles instead. The DCLK output is

enabled again after a constant delay of tOD.

For both Demux and Non-Demux Modes, there is some uncertainty about how DCLK comes out of the

reset state for the first DCLK_RST pulse. For the second (and subsequent) DCLK_RST pulses, the DCLK

will come out of the reset state in a known way. Therefore, if using the DCLK Reset feature, TI

recommends applying one "dummy" DCLK_RST pulse before using the second DCLK_RST pulse to

synchronize the outputs. This recommendation applies each time the device or channel is powered-on.

When using DCLK_RST to synchronize multiple ADC12D1x00RFs, it is required that the Select Phase bits

in the Control Register (Addr: Eh, Bits 3,4) be the same for each Master ADC12D1x00RF.

6.1.5 Recommended System Chips

TI recommends these other chips including temperature sensors, clocking devices, and amplifiers to

support the ADC12D1x00RF in a system design.

6.1.5.1 Temperature Sensor

The ADC12D1x00RF has an on-die temperature diode connected to pins Tdiode+/- which may be used to

monitor the die temperature. TI also provides a family of temperature sensors for this application which

monitor different numbers of external devices, see Table 6-3.

Table 6-3. Temperature Sensor Recommendation

NUMBER OF EXTERNAL RECOMMENDED TEMPERATURE

DEVICES MONITORED SENSOR

1 LM95235

2 LM95213

4 LM95214

The temperature sensor (LM95235/13/14) is an 11-bit digital temperature sensor with a 2-wire System

Management Bus (SMBus) interface that can monitor the temperature of one, two, or four remote diodes

as well as its own temperature. It can be used to accurately monitor the temperature of up to one, two, or

four external devices such as the ADC12D1x00RF, a FPGA, other system components, and the ambient

temperature.

The temperature sensor reports temperature in two different formats for 127.875°C/–128°C range and

0°/255°C range. It has a Sigma-Delta ADC core which provides the first level of noise immunity. For

improved performance in a noisy environment, the temperature sensor includes programmable digital

filters for Remote Diode temperature readings. When the digital filters are invoked, the resolution for the

Remote Diode readings increases to 0.03125°C. For maximum flexibility and best accuracy, the

temperature sensor includes offset registers that allow calibration for other types of diodes.

Diode fault detection circuitry in the temperature sensor can detect the absence or fault state of a remote

diode: whether D+ is shorted to the power supply, D- or ground, or floating.

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100 pF

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IE = IF

100 pF

D1+

D2+

5D-

FPGA

IE = IF

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In the following typical application, the LM95213 is used to monitor the temperature of an ADC12D1x00RF

as well as an FPGA, see Figure 6-6. If this feature is unused, the Tdiode+/- pins may be left floating.

Figure 6-6. Typical Temperature Sensor Application

6.1.5.2 Clocking Device

The clock source can be a PLL/VCO device such as the LMX2531LQxxxx family of products. The specific

device should be selected according to the desired ADC sampling clock frequency. The

ADC12D1600RFRB uses the LMX2531LQ1570E, with the ADC clock source provided by the Aux PLL

output. Other devices which may be considered based on clock source, jitter cleaning, and distribution

purposes are the LMK01XXX, LMK02XXX, LMK03XXX, and LMK04XXX product families.

6.1.5.3 Amplifiers for the Analog Input

The following amplifiers can be used for ADC12D1x00RF applications which require DC coupled input or

signal gain, neither of which can be provided with a transformer coupled input circuit:

Table 6-4. Amplifier Recommendations

AMPLIFIER BANDWIDTH BRIEF FEATURES

LMH3401 7 GHz Fixed gain, single-ended to

differential conversion

LMH5401 8 GHz Configurable gain, single-ended to

differential conversion

LMH6401 4.5 GHz Digital variable controlled gain

LMH6554 2.8 GHz Configurable gain

LMH6555 1.2 GHz Fixed gain

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Clocking

Solution

1:2 Balun LVDS outputs

Power

Management

FPGA

Memory

USB

Port

GSPS ADC

10-MHz

Reference

I-Channel

Q-Channel

BPF

1:2 Balun

BPF

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6.1.5.4 Balun Recommendations for Analog Input

The following baluns are recommended for the ADC12D1x00RF for applications which require no gain.

When evaluating a balun for the application of driving an ADC, some important qualities to consider are

phase error and magnitude error.

Table 6-5. Balun Recommendations

BALUN BANDWIDTH

Mini Circuits TC1-1- 4.5 - 3000 MHz

13MA+

Anaren 400 - 3000 MHz

B0430J50100A00

Mini Circuits ADTL2- 30 - 1800 MHz

6.2 Typical Application

The ADC12D1600RF can be used to directly sample a signal in the RF frequency range for downstream

processing. The wide input bandwidth, buffered input, high sampling rate and make ADC12D1600RF ideal

for RF sampling applications.

Figure 6-7. Simplified Schematic

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6.2.1 Design Requirements

In this example ADC12D1600RF will be used to sample signals in DES mode and Non-Des mode. The

design parameters are listed Table 6-6.

Table 6-6. Design Parameters

PARAMETER EXAMPLE VALUE (Non-DESI mode) EXAMPLE VALUE (DESI mode)

Signal center frequency 1800 MHz 1000 MHz

Signal bandwidth 100 MHz 75 MHz

ADC sampling Rate 1600 MSPS 3200 MSPS

Signal nominal amplitude –7 dBm –7 dBm

Signal maximum amplitude 6 dBm 6 dBm

Minimum SNR (in BW of interest) 48 dBc 45 dBc

Minimum THD (in BW of interest) –54 dBc –58 dBc

Minimum SFDR (in BW of interest) 52 dBc 46 dBc

6.2.2 Detailed Design Procedure

Use the step described below to design the RF receiver:

• Select the appropriate mode of operation (DES mode or Non-DES mode).

• Use the input signal frequency to select an appropriate sampling rate.

• Select the sampling rate so that the input signal is within the Nyquist zone and away from any

harmonics and interleaving tones.

• Select the system components such as clocking device, amplifier for analog input and Balun according

to sampling frequency and input signal frequency.

• See Clocking Device for the recommended clock sources.

• See Amplifiers for the Analog Input for recommended analog amplifiers.

• See Balun Recommendations for Analog Input for recommended Balun components.

• Select the bandpass filters and limiter components based on the requirement to attenuate the

unwanted input signals.

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±110

±100

±90

±80

±70

±60

±50

±40

±30

±20

±10

0 100 200 300 400 500 600 700 800

Magnitude (dBFS)

Frequency (MHz)

C002

±110

±100

±90

±80

±70

±60

±50

±40

±30

±20

±10

0 200 400 600 800 1000 1200 1400 1600

Magnitude (dBFS)

Frequendy (MHz)

C001

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6.2.3 Application Curves

Figure 6-8 and Figure 6-9 show an RF signal at 1797.97 MHz captured at a sample rate of 1600 MSPS in

Non-DES mode and an RF signal at 997.97 MHz sample at an effective sample rate of 3200 MSPS in

DES mode.

NON - DES MODE DES MODE

Fin = 1797.97 MHz at -7 dBFS Fs = 1600 MHz Fin = 997.97 MHz at -7 dBFS Fs = 3200 MHz

Figure 6-8. Spectrum - Non-DES Mode Figure 6-9. Spectrum - DES Mode

Table 6-7. ADC12D1600RF Performance for Single

Tone Signal at 1797.97 MHz in Non-DES Mode

PARAMETER VALUE

SNR 49.7 dBc

SFDR 54 dBc

THD –65.5 dBc

SINAD 49.7 dBc

ENOB 7.9 bits

Table 6-8. ADC12D1600RF Performance for Single

Tone Signal at 997.97 MHz in DES Mode

PARAMETER VALUE

SNR 47.5 dBc

SFDR 50 dBc

THD –61.4 dBc

SINAD 47.3 dBc

ENOB 7.5 bits

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7 Power Supply Recommendations

7.1 System Power-on Considerations

Data-converter-based systems draw sufficient transient current to corrupt their own power supplies if not

adequately bypassed. A 10-μF capacitor must be placed within one inch (2.5 cm) of the device power pins

for each supply voltage. A 0.1-μF capacitor must be placed as close as possible to each supply pin,

preferably within 0.5 cm. Leadless chip capacitors are preferred due to their low-lead inductance.

As is the case with all high-speed converters, the ADC12D1600RF device must be assumed to have little

power supply noise-rejection. Any power supply used for digital circuitry in a system where a large amount

of digital power is consumed must not be used to supply power to the ADC12D1600RF device. If not a

dedicated supply, the ADC supplies must be the same supply used for other analog circuitry.

There are a couple important topics to consider associated with the system power-on event including

configuration and calibration, and the Data Clock.

7.1.1 Power-on, Configuration, and Calibration

Following the application of power to the ADC12D1x00RF, several events must take place before the

output from the ADC12D1x00RF is valid and at full performance; at least one full calibration must be

executed with the device configured in the desired mode.

Following the application of power to the ADC12D1x00RF, there is a delay of tCalDly and then the Power-

on Calibration is executed. This is why TI recommends setting the CalDly Pin through an external pullup

or pulldown resistor. This ensures that the state of that input will be properly set at the same time that

power is applied to the ADC and tCalDly will be a known quantity. For the purpose of this section, it is

assumed that CalDly is set as recommended.

The Control Bits or Pins must be set or written to configure the ADC12D1x00RF in the desired mode. This

must take place through either Extended Control Mode or Non-ECM (Pin Control Mode) before

subsequent calibrations will yield an output at full performance in that mode. Some examples of modes

include DES and Non-DES Mode, Demux and Non-demux Mode, and Full-Scale Range.

The simplest case is when device is in Non-ECM and the Control Pins are set by pullup and pulldown

resistors, see Figure 7-1. For this case, the settings to the Control Pins ramp concurrently to the ADC

voltage. Following the delay of tCalDly and the calibration execution time, tCAL, the output of the

ADC12D1x00RF is valid and at full performance. If it takes longer than tCalDly for the system to stabilize at

its operating temperature, TI recommends executing an on-command calibration at that time.

Another case is when the FPGA configures the Control Pins (Non-ECM) or writes to the SPI (ECM), see

Figure 7-2. It is always necessary to comply with the Operating Ratings and Absolute Maximum ratings,

that is, the Control Pins may not be driven below the ground or above the supply, regardless of what the

voltage currently applied to the supply is. Therefore, it is not recommended to write to the Control Pins or

SPI before power is applied to the ADC12D1x00RF. As long as the FPGA has completed writing to the

Control Pins or SPI, the Power-on Calibration will result in a valid output at full performance. Once again,

if it takes longer than tCalDly for the system to stabilize at its operating temperature, TI recommends

executing an on-command calibration at that time.

Due to system requirements, it may not be possible for the FPGA to write to the Control Pins or SPI

before the Power-on Calibration takes place, see Figure 7-3. It is not critical to configure the device before

the Power-on Calibration, but it is critical to realize that the output for such a case is not at its full

performance. Following an On-command Calibration, the device will be at its full performance.

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FPGA writes

Control Pins

Power-on

Calibration On-command

Calibration

Power to

ADC

Calibration

CalDly

FPGA writes

Control Pins

Power-on

Calibration On-command

Calibration

Power to

ADC

Calibration

CalDly ADC output

valid

Power-on

Calibration On-command

Calibration

Power to

ADC

Calibration

CalDly

Pull-up/down

resistors set

Control Pins

ADC output

valid

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Figure 7-1. Power-On With Control Pins Set by Pullup and Pulldown Resistors

Figure 7-2. Power-On With Control Pins Set by FPGA Pre-Power-On Cal

Figure 7-3. Power-On With Control Pins Set by FPGA Post-Power-On Cal

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DCLK

1900

1710

time

660

635

1490

520

300

1210

Slope = 1.22V/ms

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7.1.2 Power-on and Data Clock (DCLK)

Many applications use the DCLK output for a system clock. For the ADC12D1x00RF, each I- and Q-

channel has its own DCLKI and DCLKQ, respectively. The DCLK output is always active, unless that

channel is powered-down or the DCLK Reset feature is used while the device is in Demux Mode. As the

supply to the ADC12D1x00RF ramps, the DCLK also comes up, see this example from the

ADC12D1600RFRB: Figure 7-4. While the supply is too low, there is no output at DCLK. As the supply

continues to ramp, DCLK functions intermittently with irregular frequency, but the amplitude continues to

track with the supply. Much below the low end of operating supply range of the ADC12D1x00RF, the

DCLK is already fully operational.

Figure 7-4. Supply and DCLK Ramping

7.2 Supply Voltage

The ADC12D1600RF device is specified to operate with nominal supply voltages of 1.9 V (VA, VTC, VE

and VDR). For detailed information regarding the operating voltage minimums and maximums see

Section 4.3.

The voltage on a pin (except VinI+/- and VinQ+/-), including a transient basis, must not have a voltage that

is in excess of the supply voltage or below ground by more than 150 mV. A pin voltage that is higher than

the supply or that is below ground can be a problem during start-up and shutdown of power. Ensure that

the supplies to circuits driving any of the input pins, analog or digital, do not rise faster than the voltage at

the ADC12D1600RF power pins.

The values in Section 4.1 must be strictly observed including during power up and power down. A power

supply that produces a voltage spike at power turnon, turnoff, or both can destroy the ADC12D1600RF

device. Many linear regulators produce output spiking at power on unless there is a minimum load

provided. Active devices draw very little current until the supply voltages reach a few hundred millivolts.

The result can be a turnon spike that destroys the ADC12D1600RF device, unless a minimum load is

provided for the supply. A 100-Ωresistor at the regulator output provides a minimum output current during

power up to ensure that no turnon spiking occurs. Whether a linear or switching regulator is used, TI

recommends using a soft-start circuit to prevent overshoot of the supply.

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8 Layout

8.1 Layout Guidelines

8.1.1 Power Planes

All supply buses for the ADC should be sourced from a common linear voltage regulator. This ensures

that all power buses to the ADC are turned on and off simultaneously. This single source will be split into

individual sections of the power plane, with individual decoupling and connection to the different power

supply buses of the ADC. Due to the low voltage but relatively high supply current requirement, the

optimal solution may be to use a switching regulator to provide an intermediate low voltage, which is then

regulated down to the final ADC supply voltage by a linear regulator. See the documentation provided for

the ADC12D1600RFRB for additional details on specific regulators that are recommended for this

configuration.

Power for the ADC should be provided through a broad plane which is located on one layer adjacent to

the ground planes. Placing the power and ground planes on adjacent layers will provide low impedance

decoupling of the ADC supplies, especially at higher frequencies. The output of a linear regulator should

feed into the power plane through a low impedance multi-via connection. The power plane should be split

into individual power peninsulas near the ADC. Each peninsula should feed a particular power bus on the

ADC, with decoupling for that power bus connecting the peninsula to the ground plane near each

power/ground pin pair. Using this technique can be difficult on many printed circuit CAD tools. To work

around this, 0-Ωresistors can be used to connect the power source net to the individual nets for the

different ADC power buses. As a final step, the 0-Ωresistors can be removed and the plane and

peninsulas can be connected manually after all other error checking is completed.

8.1.2 Bypass Capacitors

The general recommendation is to have one 100-nF capacitor for each power/ground pin pair. The

capacitors should be surface mount multi-layer ceramic chip capacitors similar to Panasonic part number

ECJ-0EB1A104K.

8.1.3 Ground Planes

Grounding should be done using continuous full ground planes to minimize the impedance for all ground

return paths, and provide the shortest possible image/return path for all signal traces.

8.1.4 Power System Example

The ADC12D1600RFRB uses continuous ground planes (except where clear areas are needed to provide

appropriate impedance management for specific signals), see Figure 8-1. Power is provided on one plane,

with the 1.9-V ADC supply being split into multiple zones or peninsulas for the specific power buses of the

ADC. Decoupling capacitors are connected between these power bus peninsulas and the adjacent ground

planes using vias. The capacitors are located as close to the individual power/ground pin pairs of the ADC

as possible. In most cases, this means the capacitors are located on the opposite side of the PCB to the

ADC.

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1.9V ADC Main

Switching

Regulator

Linear

Regulator

VDR

VTC

HV or Unreg

Voltage

Intermediate

Voltage

ADC

Dielectric 1

Dielectric 2

Dielectric 3

Dielectric 4

Dielectric 5

Dielectric 6

Dielectric 7

Top Layer ± Signal 1

Ground 1

Signal 2

Ground 2

Power 1

Ground 3

Bottom Layer ± Signal X

Signal 3

Cross Section

Line

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Figure 8-1. Power and Grounding Example

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Analog input path with

minimal adjacent circuit

CLK path with minimal

adjacent circuit

Balun transformer to convert the

SE CLK signal to differential signal

High speed data paths and DCLK

signals should be of same length

To provide best grounding and thermal

performance all the ground pins on

internal pad should be connected to all the

ground layers with vias.

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8.2 Layout Example

Figure 8-2 and Figure 8-3 show layout example plots. Figure 8-4 show a typical stack up for a 10 layer

board.

Figure 8-2. ADC12D1600RF Layout Example 1 – Top Side and Inner Layers

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0.0036''

0.0030''

0.0060''

0.0036''

L1 – SIG

L2 – GND

L5 –GND

L10 – SIG

L7 – PWR

L6 – SIG 0.0580''

0.0070''

L4 – PWR

0.0060''

L3 – SIG

0.0060''

L9 – GND

L8 – SIG

0.0070''

1/2 oz. Copper on L1, L3, L6, L8, L10

1 oz. Copper on L2, L4, L5, L7, L9

100 , Differential Signaling and 50 Single ended on SIG LayersW W

Low loss dielectric adjacent very high speed trace layers

Finished thickness 0.0620" including plating and solder mask

Decoupling

capacitors near

the device

Decoupling

Capacitors near

VIN

The four holes highlighted with black squares were for the

socket version of the board and are not required for end

application.

All high speed signal routing should use impedance

controlled traces, either 50-Ω single ended or 100-Ω

differential

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Figure 8-3. ADC12D1600RF Layout Example 1 – Bottom Side and Inner Layers

Figure 8-4. ADC12D1600RF Typical Stackup – 10-Layer Board

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Cross Section Line IC Die Not to Scale

Mold Compound Copper Heat Slug

Substrate

4JC_2

4JC_1

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8.3 Thermal Management

The Heat Slug Ball Grid Array (HSBGA) package is a modified version of the industry standard plastic

BGA (Ball Grid Array) package. Inside the package, a copper heat spreader cap is attached to the

substrate top with exposed metal in the center top area of the package. This results in a 20%

improvement (typical) in thermal performance over the standard plastic BGA package.

Figure 8-5. HSBGA Conceptual Drawing

The center balls are connected to the bottom of the die by vias in the package substrate, Figure 8-5. This

gives a low thermal resistance between the die and these balls. Connecting these balls to the PCB ground

planes with a low thermal resistance path is the best way dissipate the heat from the ADC. These pins

should also be connected to the ground plane through a low impedance path for electrical purposes. The

direct connection to the ground planes is an easy method to spread heat away from the ADC. Along with

the ground plane, the parallel power planes will provide additional thermal dissipation.

The center ground balls should be soldered down to the recommended ball pads (see AN-1126

(SNOA021)). These balls will have wide traces which in turn have vias which connect to the internal

ground planes, and a bottom ground pad/pour if possible. This ensures a good ground is provided for

these balls, and that the optimal heat transfer will occur between these balls and the PCB ground planes.

In spite of these package enhancements, analysis using the standard JEDEC JESD51-7 four-layer PCB

thermal model shows that ambient temperatures must be limited to 70/77°C to ensure a safe operating

junction temperature for the ADC12D1x00RF. However, most applications using the ADC12D1x00RF will

have a printed-circuit-board (PCB) which is more complex than that used in JESD51-7. Typical circuit

boards will have more layers than the JESD51-7 (eight or more), several of which will be used for ground

and power planes. In those applications, the thermal resistance parameters of the ADC12D1x00RF and

the circuit board can be used to determine the actual safe ambient operating temperature up to a

maximum of 85°C.

Three key parameters are provided to allow for modeling and calculations. Because there are two main

thermal paths between the ADC die and external environment, the thermal resistance for each of these

paths is provided. θJC1 represents the thermal resistance between the die and the exposed metal area on

the top of the HSBGA package. θJC2 represents the thermal resistance between the die and the center

group of balls on the bottom of the HSBGA package. The final parameter is the allowed maximum junction

temperature, TJ.

In other applications, a heat sink or other thermally conductive path can be added to the top of the

HSBGA package to remove heat. In those cases, θJC1 can be used along with the thermal parameters for

the heat sink or other thermal coupling added. Representative heat sinks which might be used with the

ADC12D1x00RF include the Cool Innovations p/n 3-1212XXG and similar products from other vendors. In

many applications, the PCB will provide the primary thermal path conducting heat away from the ADC

package. In those cases, θJC2 can be used in conjunction with PCB thermal modeling software to

determine the allowed operating conditions that will maintain the die temperature below the maximum

allowable limit. Additional dissipation can be achieved by coupling a heat sink to the copper pour area on

the bottom side of the PCB.

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Typically, dissipation will occur through one predominant thermal path. In these cases, the following

calculations can be used to determine the maximum safe ambient operating temperature for the

ADC12D1000RF, for example:

TJ= TA+ PD× (θJC+θCA) (2)

TJ= TA+ PC(MAX) × (θJC+θCA) (3)

For θJC, the value for the primary thermal path in the given application environment should be used (θJC1

or θJC2). θCA is the thermal resistance from the case to ambient, which would typically be that of the heat

sink used. Using this relationship and the desired ambient temperature, the required heat sink thermal

resistance can be found. Alternately, the heat sink thermal resistance can be used to find the maximum

ambient temperature. For more complex systems, thermal modeling software can be used to evaluate the

PCB system and determine the expected junction temperature given the total system dissipation and

ambient temperature.

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9 Device and Documentation Support

9.1 Device Support

9.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES

NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR

SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR

SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

9.1.2 Device Nomenclature

9.1.2.1 Specification Definitions

APERTURE (SAMPLING) DELAY is the amount of delay, measured from the sampling edge of the CLK

input, after which the signal present at the input pin is sampled inside the device.

APERTURE JITTER (tAJ)is the variation in aperture delay from sample-to-sample. Aperture jitter can be

effectively considered as noise at the input.

CODE ERROR RATE (CER) is the probability of error and is defined as the probable number of word

errors on the ADC output per unit of time divided by the number of words seen in that amount of time. A

CER of 10-18 corresponds to a statistical error in one word about every 31.7 years for the

ADC12D1600RF.

CLOCK DUTY CYCLE is the ratio of the time that the clock waveform is at a logic high to the total time of

one clock period.

DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step

size of 1 LSB. It is measured at the relevant sample rate, fCLK, with fIN = 1MHz sine wave.

EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-

Noise and Distortion Ratio, or SINAD. ENOB is defined as (SINAD −1.76) / 6.02 and states that the

converter is equivalent to a perfect ADC of this many (ENOB) number of bits.

GAIN ERROR is the deviation from the ideal slope of the transfer function. It can be calculated from Offset

and Full-Scale Errors. The Positive Gain Error is the Offset Error minus the Positive Full-Scale Error. The

Negative Gain Error is the Negative Full-Scale Error minus the Offset Error. The Gain Error is the

Negative Full-Scale Error minus the Positive Full-Scale Error; it is also equal to the Positive Gain Error

plus the Negative Gain Error.

GAIN FLATNESS is the measure of the variation in gain over the specified bandwidth. For example, for

the ADC12D1600RF, from D.C. to Fs/2 is to 800 MHz for the Non- DES Mode and from D.C. to Fs/2 is

1600 MHz for the DES Mode.

INTEGRAL NON-LINEARITY (INL) is a measure of worst case deviation of the ADC transfer function

from an ideal straight line drawn through the ADC transfer function. The deviation of any given code from

this straight line is measured from the center of that code value step. The best fit method is used.

INSERTION LOSS is the loss in power of a signal due to the insertion of a device, for example, the

ADC12D1x00RF, expressed in dB.

INTERMODULATION DISTORTION (IMD) is a measure of the near-in 3rd order distortion products (2f2-

f1, 2f1- f2) which occur when two tones which are close in frequency (f1, f2) are applied to the ADC input. It

is measured from the input tone's level to the higher of the two distortion products (dBc) or simply the level

of the higher of the two distortion products (dBFS).

LSB (LEAST SIGNIFICANT BIT) is the bit that has the smallest value or weight of all bits. This value is

VFS / 2N(4)

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VD+

VD-

VOS

GND ½×VOD = | VD+ - VD- |

½×VOD

VD-

VD+

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where VFS is the differential full-scale amplitude VIN_FSR as set by the FSR input and "N" is the ADC

resolution in bits, which is 12 for the ADC12D1x00RF.

LOW VOLTAGE DIFFERENTIAL SIGNALING (LVDS) DIFFERENTIAL OUTPUT VOLTAGE (VID and

VOD)is two times the absolute value of the difference between the VD+ and VD- signals; each signal

measured with respect to Ground. VOD peak is VOD,P= (VD+-VD-) and VOD peak-to-peak is VOD,P-P=

2*(VD+-VD-); for this product, the VOD is measured peak-to-peak.

Figure 9-1. LVDS Output Signal Levels

LVDS OUTPUT OFFSET VOLTAGE (VOS)is the midpoint between the D+ and D- pins output voltage

with respect to ground; that is, [(VD+) +( VD-)]/2. See Figure 9-1.

MISSING CODES are those output codes that are skipped and will never appear at the ADC outputs.

These codes cannot be reached with any input value.

MSB (MOST SIGNIFICANT BIT) is the bit that has the largest value or weight. Its value is one half of full

scale.

NEGATIVE FULL-SCALE ERROR (NFSE) is a measure of how far the first code transition is from the

ideal 1/2 LSB above a differential −VIN/2 with the FSR pin low. For the ADC12D1x00RF the reference

voltage is assumed to be ideal, so this error is a combination of full-scale error and reference voltage

error.

NOISE FLOOR DENSITY is a measure of the power density of the noise floor, expressed in dBFS/Hz and

dBm/Hz. '0 dBFS' is defined as the power of a sinusoid which precisely uses the full-scale range of the

ADC.

NOISE POWER RATIO (NPR) is the ratio of the sum of the power inside the notched bins to the sum of

the power in an equal number of bins outside the notch, expressed in dB.

OFFSET ERROR (VOFF)is a measure of how far the mid-scale point is from the ideal zero voltage

differential input.

Offset Error = Actual Input causing average of 8k samples to result in an average code of 2047.5.

OUTPUT DELAY (tOD)is the time delay (in addition to Latency) after the rising edge of CLK+ before the

data update is present at the output pins.

OVER-RANGE RECOVERY TIME is the time required after the differential input voltages goes from ±1.2V

to 0V for the converter to recover and make a conversion with its rated accuracy.

PIPELINE DELAY (LATENCY) is the number of input clock cycles between initiation of conversion and

when that data is presented to the output driver stage. The data lags the conversion by the Latency plus

the tOD.

POSITIVE FULL-SCALE ERROR (PFSE) is a measure of how far the last code transition is from the ideal

1-1/2 LSB below a differential +VIN/2. For the ADC12D1x00RF the reference voltage is assumed to be

ideal, so this error is a combination of full-scale error and reference voltage error.

SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the fundamental for a

single-tone to the rms value of the sum of all other spectral components below one-half the sampling

frequency, not including harmonics or DC.

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THD = 20 x log + . . . + AAf22

f102

Af12

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SIGNAL TO NOISE PLUS DISTORTION (S/(N+D) or SINAD) is the ratio, expressed in dB, of the rms

value of the fundamental for a single-tone to the rms value of all of the other spectral components below

half the input clock frequency, including harmonics but excluding DC.

SPURIOUS-FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the rms values

of the input signal at the output and the peak spurious signal, where a spurious signal is any signal

present in the output spectrum that is not present at the input, excluding DC.

θJA is the thermal resistance between the junction to ambient.

θJC1 represents the thermal resistance between the die and the exposed metal area on the top of the

HSBGA package.

θJC2 represents the thermal resistance between the die and the center group of balls on the bottom of the

HSBGA package.

TOTAL HARMONIC DISTORTION (THD) is the ratio expressed in dB, of the rms total of the first nine

harmonic levels at the output to the level of the fundamental at the output. THD is calculated as

(5)

where Af1 is the RMS power of the fundamental (output) frequency and Af2 through Af10 are the RMS

power of the first 9 harmonic frequencies in the output spectrum.

– Second Harmonic Distortion (2nd Harm) is the difference, expressed in dB, between the RMS power

in the input frequency seen at the output and the power in its 2nd harmonic level at the output.

– Third Harmonic Distortion (3rd Harm) is the difference expressed in dB between the RMS power in

the input frequency seen at the output and the power in its 3rd harmonic level at the output.

9.2 Documentation Support

9.2.1 Related Documentation

For related documentation, see the following:

•AN-1126 BGA (Ball Grid Array),SNOA021

•AN-2132 Synchronizing Multiple GSPS ADCs in a System: The AutoSync Feature,SNAA073

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Product Folder Links: ADC12D1000RF ADC12D1600RF

ADC12D1000RF, ADC12D1600RF

SNAS519H –JULY 2011–REVISED AUGUST 2015

www.ti.com

9.3 Related Links

The table below lists quick access links. Categories include technical documents, support and community

resources, tools and software, and quick access to sample or buy.

Table 9-1. Related Links

TECHNICAL TOOLS & SUPPORT &

PARTS PRODUCT FOLDER SAMPLE & BUY DOCUMENTS SOFTWARE COMMUNITY

ADC12D1000RF Click here Click here Click here Click here Click here

ADC12D1600RF Click here Click here Click here Click here Click here

9.4 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the

respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;

see TI's Terms of Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster

collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge,

explore ideas and help solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools

and contact information for technical support.

9.5 Trademarks

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

9.6 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

9.7 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

10 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the

most current data available for the designated devices. This data is subject to change without notice and

revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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Product Folder Links: ADC12D1000RF ADC12D1600RF

PACKAGE OPTION ADDENDUM

www.ti.com 22-Sep-2018

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

ADC12D1000RFIUT/NOPB ACTIVE BGA NXA 292 40 Green (RoHS

& no Sb/Br) SNAG Level-3-250C-168 HR -40 to 85 ADC12D1000RFIUT

ADC12D1600RFIUT ACTIVE BGA NXA 292 40 TBD Call TI Call TI -40 to 85 ADC12D1600RFIUT

ADC12D1600RFIUT/NOPB ACTIVE BGA NXA 292 40 Green (RoHS

& no Sb/Br) SNAG Level-3-250C-168 HR -40 to 85 ADC12D1600RFIUT

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

PACKAGE OPTION ADDENDUM

www.ti.com 22-Sep-2018

Addendum-Page 2

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

MECHANICAL DATA

NXA0292A

www.ti.com

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