DS2164Q
G.726 ADPCM Processor
DS2164Q
022698 1/17
FEATURES
•Compresses/expands 64Kbps PCM voice to/from
either 32Kbps, 24Kbps, or 16Kbps as per the CCITT/
ITU G.726 specification
•Dual, fully independent channel architecture; device
can be programmed to perform either:
– two expansions
– two compressions
– one expansion and one compression
•Interconnects directly to combo-codec devices
•Input to output delay is less than 375 µs
•Simple serial port used to configure the device
•Onboard Time Slot Assigner Circuit (TSAC) function
allows data to be input/output at various time slots
•Supports Channel Associated Signaling
•Each channel can be independently idled or placed
into bypass
•Available hardware mode requires no host processor;
ideal for voice storage applications
•Backward-compatible with the DS2165 ADPCM
Processor Chip
•Single +5V supply; low-power CMOS technology
•Available in 28-pin PLCC
PIN ASSIGNMENT
27
28 26
432
5
6
7
8
9
12 1314 15 16 1718
25
24
23
22
21
20
19
10
11
FSY
YOUT
CS
SCLK
SDI
XOUT
NC
NC
A0
A1
A2
A3
A4
A5
1
TM1
RST
NC VDD
YINCLKX
XIN
FSX
SPS
MCLK
VSS TM0
NC
CLKY
28-Pin PLCC
DESCRIPTION
The DS2164Q ADPCM Processor Chip is a dedicated
Digital Signal Processing (DSP) chip that has been opti-
mized to perform Adaptive Differential Pulse Code Mod-
ulation (ADPCM) speech compression at three different
rates. The chip can be programmed to compress (ex-
pand) 64Kbps voice data down to (up from) either
32Kbps, 24Kbps, or 16Kbps. The compression follows
the algorithm specified by CCITT Recommendation
G.726. The DS2164Q can switch compression algo-
rithms on-the-fly. This allows the user to make maxi-
mum use of the available bandwidth on a dynamic ba-
sis.
OVERVIEW
The DS2164Q contains three major functional blocks: a
high performance (10 MIPS) DSP engine, two indepen-
dent PCM interfaces (X and Y) which connect directly to
serial Time Division Multiplexed (TDM) backplanes, and
a serial port that can configure the device on-the-fly via
an external controller. A 10 MHz master clock is re-
quired by the DSP engine. The DS2164Q can be confi-
gured to perform either two expansions, two compres-
sions, or one expansion and one compression. The
PCM/ADPCM data interfaces support data rates from
256 KHz to 4.096 MHz. Typically, the PCM data rates
DS2164Q
022698 2/17
will be 1.544 MHz for µ-law and 2.048 MHz for A-law.
Each channel on the device samples the serial input
PCM or ADPCM bit stream during a user-programmed
input time slot, processes the data and outputs the re-
sult during a user-programmed output time slot.
Each PCM interface has a control register which speci-
fies functional characteristics (compress, expand, by-
pass, and idle), data format (µ-law or A-law), and algo-
rithm reset control. With the SPS pin strapped high, the
software mode is enabled and the serial port can be
used to configure the device. In this mode, a novel ad-
dressing scheme allows multiple devices to share a
common 3-wire control bus, simplifying system-level in-
terconnect.
With SPS low, the hardware mode is enabled. This
mode disables the serial port and maps certain control
register bits to some of the address and serial port pins.
Under the hardware mode, no external host controller is
required and all PCM/ADPCM input and output time
slots default to time slot 0.
HARDWARE RESET
RST allows the user to reset both channel algorithms
and the contents of the internal registers. This pin must
be held low for at least 1 ms on system power-up after
the master clock is stable to ensure that that the device
has initialized properly. RST should also be asserted
when changing to or from the hardware mode. RST
clears all bits of the Control Register for both channels
except the IPD bits; the IPD bits for both channels are
set to 1.
SOFTWARE MODE
Tying SPS high enables the software mode. In this
mode, an external host controller writes configuration
data to the DS2164Q via the serial port through inputs
SCLK, SDI, and CS. (See Figure 2.) Each write to the
DS2164Q is either a 2-byte write or a 4-byte write. A 2-
byte write consists of the Address/Command Byte
(ACB), followed by a byte to configure the Control Reg-
ister (CR) for either the X or Y channel. The 4-byte write
consists of the ACB, followed by a byte to configure the
CR, and then one byte to set the input time slot and
another byte to set the output time slot.
ADDRESS/COMMAND BYTE
In the software mode, the address/command byte is the
first byte written to the serial port; it identifies which of
the 64 possible ADPCM processors sharing the port
wiring is to be updated. Address data must match that at
inputs A0 to A5. If no match occurs, the device ignores
the following configuration data. If an address match oc-
curs, the next three bytes written are accepted as con-
trol, input and output time slot data. Bit ACB.6 deter-
mines which side (X or Y) of the device is to be updated.
The PCM and ADPCM outputs are tristated during reg-
ister updates.
CONTROL REGISTER
The control register establishes idle, algorithm reset,
bypass, data format and channel coding for the selected
channel.
The X and Y side PCM interfaces can be independently
disabled (output 3-stated) via IPD. When IPD is set for
both channels, the device enters a low-power standby
mode. In this mode, the serial port must not be operated
faster than 39 KHz.
ALRST resets the algorithm coefficients for the selected
channel to their initial values. ALRST will be cleared by
the device when the algorithm reset is complete.
DS2164Q
022698 3/17
PIN DESCRIPTION Table 1
PIN SYMBOL TYPE DESCRIPTION
2 RST I Reset. A high-low-high transition resets the algorithm. The device should
be reset on power up and when changing to or from the hardware mode.
3
4TM0
TM1 ITest Modes 0 and 1. Tie to VSS for normal operation.
6
7
8
9
10
11
A0
A1
A2
A3
A4
A5
IAddress Select. A0 = LSB; A5 = MSB Must match address/command
word to enable the serial port.
12 SPS I Serial Port Select. T ie to VDD to select the serial port; tie to VSS to select
the hardware mode.
13 MCLK I Master Clock. 10 MHz clock for the ADPCM processing engine; may be
asynchronous to SCLK, CLKX, and CLKY.
14 VSS –SIgnal Ground. 0.0 volts.
16 XIN I X Data In. Sampled on falling edge of CLKX during selected time slots.
17 CLKX I X Data Clock. Data clock for the X side PCM interface; must be synchro-
nous with FSX.
18 FSX I X Frame Sync. 8 KHz frame sync for the X side PCM interface.
20 XOUT O X Data Output. Updated on rising edge of CLKX during selected time slots.
21 SCLK I Serial Data Clock. Used to write to the serial port registers.
22 SDI I Serial Data In. Data for onboard control registers; sampled on the rising
edge of SCLK. LSB sent first.
23 CS I Chip Select. Must be low to write to the serial port.
24 YOUT O Y Data Output. Updated on rising edge of CLKY during selected time slots.
25 FSY I Y Frame Sync. 8 KHz frame sync for the Y side PCM interface.
26 CLKY I Y Data Clock. Data clock for the Y side PCM interface; must be synchro-
nous with FSY.
27 YIN I Y Data In. Sampled on falling edge of CLKY during selected time slots.
28 VDD –Positive Supply. 5.0 volts.
DS2164Q
022698 4/17
DS2164Q BLOCK DIAGRAM Figure 1
X SIDE PCM/ADPCM
DATA INTERFACE
SERIAL PORT CONTROL/
HARDW ARE MODE LOGIC
Y SIDE PCM/ADPCM
DATA INTERFACE
RESET AND TEST LOGIC
ADPCM
PROCESSING
ENGINE
MCLK
VDD
VSS
FSX
CLKX
XIN
XOUT
SCLK
SPS
CS
SDI
A0 - A5
FSY
CLKY
YIN
YOUT
RST
TM0
TM1
SERIAL PORT WRITE Figure 2
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
A0 A1 A2 A3 A4 A5 X/Y 0 CR0 CR1 CR2 CR3 CR4 CR5 CR6 CR7
ADDRESS/COMMAND CONTROL
NOTE:
1. A 2-byte write is shown.
The bypass feature is enabled when BYP is set and IPD
is cleared. During bypass, no expansion or compres-
sion occurs. Bypass operates on bytewide (8 bits) slots
when CP/EX is set and on nibble-wide (4 bits) slots
when CP/EX is cleared.
A-law (U/A = 0) and µ-law (U/A = 1) PCM coding is inde-
pendently selected for the X and Y channels via CR.2. If
BYP and IPD are cleared, then CP/EX determines if the
input data is to be compressed or expanded.
DS2164Q
022698 5/17
ADDRESS/COMMAND BYTE Figure 3
(MSB) (LSB)
– X/Y A5 A4 A3 A2 A1 A0
SYMBOL POSITION NAME AND DESCRIPTION
– ACB.7 Reserved; must be 0 for proper operation
X/Y ACB.6X/Y Channel Select
0 = update channel Y characteristics
1 = update channel X characteristics
A5 ACB.5 MSB of Device Address
A4 ACB.4
A3 ACB.3
A2 ACB.2
A1 ACB.1
A0 ACB.0 LSB of Device Address
CONTROL REGISTER Figure 4
(MSB) (LSB)
AS0 AS1 IPD ALRST BYP U/A AS2 CP/EX
SYMBOL POSITION NAME AND DESCRIPTION
AS0 CR.7 Algorithm Select 0. See Table 2.
AS1 CR.6 Algorithm Select 1. See Table 2.
IPD CR.5 Idle and Power Down.
0 = channel enabled
1 = channel disabled (output 3-stated)
ALRST CR.4 Algorithm Reset.
0 = normal operation
1 = reset algorithm for selected channel
BYP CR.3 Bypass.
0 = normal operation
1 = bypass selected channel
U/A CR.2 Data Format.
0 = A-law
1 = µ-law
AS2 CR.1 Algorithm Select 2. See Table 2.
CP/EX CR.0 Channel Coding.
0 = expand (decode) selected channel
1 = compress (encode) selected channel
DS2164Q
022698 6/17
ALGORITHM SELECT BITS Table 2
ALGORITHM SELECTED AS2 AS1 AS0
64Kbps to/from 32Kbps 0 0 0
64Kbps to/from 24Kbps 1 1 1
64Kbps to/from 16Kbps 1 0 1
INPUT TIME SLOT REGISTER Figure 5
(MSB) (LSB)
–– D5 D4 D3 D2 D1 D0
SYMBOL POSITION NAME AND DESCRIPTION
- ITR.7 Reserved; must be 0 for proper operation.
- ITR.6 Reserved; must be 0 for proper operation.
D5 ITR.5 MSB of input time slot register .
D4 ITR.4
D3 ITR.3
D2 ITR.2
D1 ITR.1
D0 ITR.0 LSB of input time slot register .
OUTPUT TIME SLOT REGISTER Figure 6
(MSB) (LSB)
– – D5 D4 D3 D2 D1 D0
SYMBOL POSITION NAME AND DESCRIPTION
- OTR.7 Reserved; must be 0 for proper operation.
- OTR.6 Reserved; must be 0 for proper operation.
D5 OTR.5 MSB of output time slot register.
D4 OTR.4
D3 OTR.3
D2 OTR.2
D1 OTR.1
D0 OTR.0 LSB of output time slot register.
DS2164Q
022698 7/17
TIME SLOT ASSIGNMENT/ORGANIZATION
Onboard counters establish when PCM and ADPCM
I/O occurs. The counters are programmed via the time
slot registers. Time slot size (number of bits wide) is de-
termined by the state of CP/EX. The number of time
slots available is determined by both the state of CP/EX
and U/A. (See Figures 7 through 10.) For example, if the
X channel is set to compress (CP/EX = 1) and it is set to
expect µ-law data (U/A = 1), then the input port (XIN) is
set up for 32 8-bit time slots and the output port (XOUT)
is set up for 64 4-bit time slots. The time slot organiza-
tion is not dependent on which algorithm has been se-
lected. NOTE: Time slots are counted from the frame
sync signal starting at the first rising edge of either CLKX
or CLKY after the frame sync.
DS2164Q µ-LAW PCM INTERFACE Figure 7
TIME SLOT 0 TIME SLOT N TIME SLOT 0TIME SLOT 31
MSB LSB
MSB LSB
DON’T CARE
3-STATE
DON’T CARE
3-STATE
CLKX, CLKY
FSX, FSY
XIN, YIN
XOUT, YOUT
...
DS2164Q µ-LAW ADPCM INTERFACE Figure 8
TIME
SLOT 0 TIME
SLOT 1 TIME
SLOT N TIME
SLOT 62 TIME
SLOT 63 TIME
SLOT 0
CLKX, CLKY
FSX, FSY
XIN, YIN
XOUT, YOUT
MSB LSB
DON’T CARE
3-STATE
DON’T CARE
3-STATEMSB LSB
DS2164Q
022698 8/17
DS2164Q A-LAW PCM INTERFACE Figure 9
...
TIME SLOT 0 TIME SLOT N TIME SLOT 0TIME SLOT 31
MSB LSB
MSB LSB
DON’T CARE
3-STATE
DON’T CARE
3-STATE
CLKX, CLKY
FSX, FSY
XIN, YIN
XOUT, YOUT
DS2164Q A-LAW ADPCM INTERFACE Figure 10
TIME
SLOT 0 TIME
SLOT 1 TIME
SLOT N TIME
SLOT 62 TIME
SLOT 63 TIME
SLOT 0
CLKX, CLKY
FSX, FSY
XIN, YIN
XOUT, YOUT
MSB LSB
DON’T CARE
3-STATE
DON’T CARE
3-STATEMSB LSB
DS2164Q
022698 9/17
HARDWARE MODE
The hardware mode is intended for applications that do
not have an external controller available or do not re-
quire the extended features offered by the serial port.
T ying the SPS pin to VSS disables the serial port, clears
all internal register bits and maps the IPD, U/A, and
CP/EX bits for both channels to external bits. (See T able
3.) In the hardware mode, both the input and output time
slots default to time slot 0.
HARDWARE MODE Table 3
PIN # / NAME REG. LOCATION NAME AND DESCRIPTION
4 / A0 CP/EX
(Channel X) Channel X Coding Configuration
0 = Expand
1 = Compress
5 / A1 AS0/AS1/AS2
(Channel X & Y) Algorithm Select (see Table 5)
6 / A2 U/A
(Channel X) Channel X Data Format
0 = A-law
1 = µ-law
7 / A3 CP/EX
(Channel Y) Channel Y Coding Configuration
0 = Expand
1 = Compress
8 / A4 AS0/AS1/AS2
(Channel X & Y) Algorithm Select (see Table 5)
9 / A5 U/A
(Channel Y) Channel Y Data Format
0 = A-law
1 = µ-law
18 / SDI IPD
(Channel Y) Channel Y Idle Select
0 = Channel active
1 = Channel idle
19 / CS IPD
(Channel X) Channel X Idle Select
0 = Channel active
1 = Channel idle
NOTES:
1. SCLK must be tied to VSS when the hardware mode is selected.
2. When both channels are idled, power consumption is significantly reduced.
3. The DS2164Q will power-up within 800 ms after either channel is returned to active from an idle state.
DS2164Q
022698 10/17
ALGORITHM SELECT FOR HARDWARE MODE Table 4
ALGORITHM CONFIGURATION OF A1 AND A4
64Kbps to/from 32Kbps T ie both A1 and A4 to V SS.
64Kbps to/from 24Kbps Hold A1 and A4 low during a hardware reset; take both A1 and A4 high after
the RST pin has returned high (allow 3 µs after RST returns high before taking
A1 and A4 high).
64Kbps to/from 16Kbps T ie both A1 and A4 to V DD.
DS2164Q CONNECTION TO CODEC/FILTER Figure 11
CODEC/FILTER DS2164Q
ANALOG
INTERFACE
3-WIRE BUS FROM
EXTERNAL CONTROLLER
VFX-
VFX+
GSX
VFRO
DX
DR
MCLKR
BCLKX
BCLKR
FSR
FSX
MCLKX
XIN
YOUT
CLKX
CLKY
FSY
FSX
TM0
TM1
XOUT
YIN
MCLK
SPS
CS
SCLK
SDI
A0
A1
A2
A3
A4
A5
RST
TRANSMIT DAT A
RECEIVE DAT A
10 MHz CLOCK
ADDRESS SELECT
(ADDRESS=0 SHOWN)
TRANSMIT DAT A CLOCK
RECEIVE DAT A CLOCK
RECEIVE FRAME SYNC
TRANSMIT FRAME SYNC
RESET
CIRCUITRY
(DS1231)
NOTE:
Suggested Codec/Filters
TP305X National Semiconductor
ETC505X SGS–Thomson Microelectronics
MC1455XX Motorola
TCM29CXX Texas Instruments
HD44238C Hitachi
*other generic Codec/Filter devices can be substituted.
DS2164Q
022698 11/17
PCM AND ADPCM INPUT/OUTPUT
Since the organization of the input and output time slots
on the DS2164Q does not depend on the algorithm se-
lected, it always assumes that PCM input and output will
be in 8-bit bytes and that ADPCM input and output will
be in 4-bit bytes. Figure 12 demonstrates how the
DS2164Q handles the I/O for the three different algo-
rithms. In the figure, it is assumed that channel X is in the
compression mode (CP/EX = 1) and channel Y is in the
expansion mode (CP/EX = 0). Also, it is assumed that
both the input and output time slots for both channels
are set to 0.
PCM AND ADPCM I/O EXAMPLE Figure 12
CLKX
FSX
XOUT (32KBPS)
XOUT (24KBPS)
XOUT (16KBPS)
CLKY
FSY
YIN (32KBPS)
YIN (24KBPS)
YIN (16KBPS)
YOUT
3–STATE
MSB LSB
XIN
MSB LSB
MSB LSB
MSB LSB
3-STATE
3-STATE
SEE NOTE 1
00
MSB LSB
MSB LSB
MSB LSB
MSB LSB 3-STATE
NOTE:
1. The bit after the LSB in the 24Kbps ADPCM output will only be a 1 when the DS2164Q is operated in the
software mode and is programmed to perform 24Kbps compression; in all other configurations, it will be a 0.
DS2164Q
022698 12/17
TIME SLOT RESTRICTIONS
Under certain conditions, the DS2164Q does contain
some restrictions on the output time slots that are avail-
able. These restrictions are covered in detail in a sepa-
rate application note. No restrictions occur if the
DS2164Q is operated in the hardware mode.
INPUT TO OUTPUT DELAY
With all three compressions algorithms, the total delay,
from the time the PCM data sample is captured by the
DS2164Q to the time it is output, is always less than 375
µs. The exact delay is determined by the input and out-
put time slots selected for each channel.
CHANNEL ASSOCIATED SIGNALING
The DS2164Q supports Channel Associated Signaling
(CAS) via its ability to automatically change from the
32Kbps compression algorithm to the 24Kbps algo-
rithm. If the DS2164Q is configured to perform the
32Kbps algorithm, then in both the hardware and soft-
ware mode, it will sense the frame sync inputs (FSX and
FSY) for a double wide frame sync pulse. Whenever the
DS2164Q receives a double wide pulse, it will automati-
cally switch from the 32Kbps algorithm to the 24Kbps al-
gorithm. Switching to the 24Kbps algorithm allows the
user to insert signaling data into the LSB bit position of
the ADPCM output because this bit does not contain
any useful speech information.
ON-THE-FLY ALGORITHM SELECTION
In the software mode, the user can switch between the
three available algorithms on-the-fly. That is, the
DS2164Q does not need to be reset or stopped to make
the change from one algorithm to another. The
DS2164Q reads the Control Register before it starts to
process each PCM or ADPCM sample. If the user
wishes to switch algorithms, then the Control Register
must be updated via the serial port before the first input
sample to be processed with the new algorithm arrives
at either XIN or YIN. The PCM and ACPCM outputs will
tristate during register updates.
DS2164Q
022698 13/17
ABSOLUTE MAXIMUM RATINGS*
Voltage on any Pin Relative to Ground -1.0V to +7.0V
Operating Temperature 0°C to 70°C
Storage Temperature -55°C to +125°C
Soldering Temperature 260°C for 10 seconds
* This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operation sections of this specification is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS (0°C to 70°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Logic 1 VIH 2.0 Vcc+0.3 V
Logic 0 VIL -0.3 +0.8 V
Supply VDD 4.5 5.5 V
CAPACITANCE (tA=25°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Input Capacitance CIN 5pF
Output Capacitance COUT 10 pF
DC ELECTRICAL CHARACTERISTICS (0°C to 70°C; VDD=5V + 10%)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Active Supply Current IDDA 20 mA 1,2
Idle Supply Current IDDPD 1 mA 1,2,3
Input Leakage II-1.0 +1.0 µA
Output Leakage IO-1.0 +1.0 µA 4
Output Current (2.4V) IOH -1.0 mA
Output Current (0.4V) IOL +4.0 mA
NOTES:
1. CLKX = CLKY = 1.544 MHz; MCLK = 10 MHz.
2. Outputs open; inputs swinging full supply levels.
3. Both channels in idle mode.
4. XOUT and YOUT are 3-stated.
DS2164Q
022698 14/17
PCM INTERFACE
AC ELECTRICAL CHARACTERISTICS (0°C to 70°C; VDD=5V +10%)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
CLKX, CLKY Period tPXY 244 3906 ns 1
CLKX, CLKY Pulse Width tWXYL
tWXYH 100 ns
CLKX, CLKY Rise Fall T imes tRXY
tFXY 10 20 ns
Hold T ime from CLKX, CLKY
to FSX, FSY tHOLD 0ns 2
Setup T ime from FSX, FSY
high to CLKX, CLKY low tSF 50 ns 2
Hold T ime from CLKX, CLKY
low to FSX, FSY low tHF 100 ns 2
Setup Time for XIN, YIN to
CLKX, CLKY low tSD 50 ns 2
Hold T ime for XIN, YIN
to CLKX, CLKY low tHD 50 ns 2
Delay Time from CLKX,
CLKY to Valid XOUT, YOUT tDXYO 10 150 ns 3
Delay Time from CLKX,
CLKY to XOUT, YOUT 3-stated tDXYZ 20 150 ns 2,3,4
NOTES:
1. Maximum width of FSX and FSY is one CLKX or CLKY period (except for signaling frames).
2. Measured at VIH = 2.0V, VIL = 0.8V, and 10 ns maximum rise and fall times.
3. Load = 150 pF + 2 LSTTL loads.
4. For LSB of PCM or ADPCM byte.
MASTER CLOCK / RESET
AC ELECTRICAL CHARACTERISTICS (0°C to 70°C; VDD=5V + 10%)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
MCLK Period tPM 100 ns 1
MCLK Pulse Width tWMH,
tWML 45 50 55 ns
MCLK Rise/Fall T imes tRM, tFM 10 ns
RST Pulse Width tRST 1ms
NOTE:
1. MCLK = 10 MHz + 500 ppm
DS2164Q
022698 15/17
SERIAL PORT
AC ELECTRICAL CHARACTERISTICS (0°C to 70°C; VDD=5V + 10%)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
SDI to SCLK Set Up tDC 55 ns 1
SCLK to SDI Hold tCDH 55 ns 1
SCLK Low T ime tCL 250 ns 1
SCLK High T ime tCH 250 ns 1
SCLK Rise and Fall T ime tR, tF100 ns 1
CS to SCLK Setup tCC 50 ns 1
SCLK to CS Hold tCCH 250 ns 1
CS Inactive T ime tCWH 250 ns 1
SCLK Setup to CS Falling tSCC 50 ns 1
NOTE:
1. Measured at VIH = 2.0V, VIL = 0.8V, and 10ns maximum rise and fall times.
PCM INTERFACE AC TIMING DIAGRAM Figure 13
CLKX
CLKY
FSX
FSY
XIN
YIN
XOUT
YOUT (MSB)
tDXYZ
tDXYO
(MSB)
3-STATE
tSF tHD
tSD
tHF
tHOLD tRXY tWXYH tWXYL
tPXY
tFXY
tHF
FSX
FSY
DS2164Q
022698 16/17
MASTER CLOCK/RESET AC TIMING DIAGRAM Figure 14
MCLK
RST
tRM tFM
tRST
tPM
tWMH tWML
SERIAL PORT AC TIMING DIAGRAM Figure 15
SCLK
SDI
CS
tCC tCH tRtF
tCL
tDC
tCDH
tCWH tCCH
tSCC
tCWH
NOTE:
1. SCLK may be either high or low when CS is taken low.
DS2164Q
022698 17/17
DS2164Q G.726 ADPCM PROCESSOR 28-PIN PLCC
CH1
N
1
E
E1
D1 D D2
E2
e1
C
A1A2
A
B
L1
B1
INCHES
DIM MIN MAX
A 0.165 0.180
A1 0.090 0.120
A2 0.020 –
B 0.026 0.033
B1 0.013 0.021
C 0.009 0.012
D 0.485 0.495
D1 0.450 0.456
D2 0.390 0.430
E 0.485 0.495
E1 0.450 0.456
E2 0.390 0.430
L1 0.060 –
N 28 –
e1 0.050 BSC
CH1 0.042 0.048
