LTC3894
1
Rev. A
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TYPICAL APPLICATION
FEATURES DESCRIPTION
150V Low IQ Step-Down
DC/DC Controller with
100% Duty Cycle Capability
The LTC
®
3894 is a high voltage step-down DC/DC switch-
ing regulator controller. It drives a P-channel power
MOSFET switch allowing 100% duty cycle operation. It
enables a low part count, simple, and robust solution for
high reliability, high voltage applications.
The LTC3894 operates over a wide input voltage range
from 4.5V to 150V and can regulate output voltages
from 0.8V to 60V. It offers excellent light load efficiency,
drawing only 9μA quiescent current while regulating the
output voltage with no load. Its peak current mode, con-
stant frequency architecture provides for good control of
switching frequency and output current limit. The switch-
ing frequency can be programmed from 50kHz to 850kHz
with an external resistor and can be synchronized to an
external clock from 75kHz to 800kHz.
The LTC3894 offers programmable output voltage soft-
start or tracking. Safety features include overvoltage,
overcurrent and overtemperature protection with a power
good output monitor with adjustable threshold.
The LTC3894 is available in a thermally enhanced 20-Pin
TSSOP package with leads removed to accommodate
high voltage creepage and clearance requirements.
High Efficiency 150V to 5V Step-Down Regulator
APPLICATIONS
n Wide Operating VIN Range: 4.5V to 150V
n Wide VOUT Range: 0.8V to 60V
n 9μA IQ when Regulating 48VIN to 3.3VOUT
n 16μA IQ when Regulating 12VIN to 3.3VOUT
n Very Low Dropout Operation: 100% Duty Cycle
n Adjustable Input Overvoltage Lockout
n Programmable PGOOD Undervoltage Monitor
n RSENSE or Inductor DCR Current Sensing
n Selectable High Efficiency Burst Mode
®
Operation or
Pulse-Skipping Mode at Light Loads
n Programmable Fixed Frequency: 50kHz to 850kHz
n Phase-Lockable Frequency: 75kHz to 800kHz
n Internal Fixed Soft-Start and External Programmable
Soft-Start or Voltage Tracking
n Strong MOSFET Gate Driver with Selectable
Undervoltage Lockout Thresholds
n Optional External NMOS for Gate Driver Bias in High
Power Applications
n Automotive and Industrial Power Systems
n Telecommunication Power Systems
n Distributed Power Systems All registered trademarks and trademarks are the property of their respective owners.
Efficiency and Power Loss vs
Load Current
22µH
20mΩ
10µF
×2
330µF
0.47µF
0.1µF
36.5k
3.3nF
5.76k
422k
80.6k
100k
12µF
×2
PLLIN/MODE
FREQ
GND
TRACK/SS
VFB
ITH
SENSE–
RUN
CAP
SENSE+
VIN
GATE
DRVUV/EXTG
PGUV
3894 TA01a
PGOOD
OVLO
EXTS
LTC3894
1nF
VOUT
5V, 3A
VIN
6V to 150V
Burst Mode OPERATION
EFFICIENCY
POWER LOSS
LOAD CURRENT (A)
0.0001
0.001
0.01
0.1
1
3
0
10
20
30
40
50
60
70
80
90
100
0.1
1
10
100
1k
10k
EFFICIENCY (%)
POWER LOSS (mW)
3894 TA01b
VIN = 12V
VIN = 24V
LTC3894
2
Rev. A
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PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS
Input Supply Voltage (VIN), RUN .............. –0.3V to 150V
SENSE+, SENSE–, PGOOD Voltage ............. –0.3V to 65V
VIN-VCAP Voltage ........................................ –0.3V to 10V
VFB, PLLIN/MODE, PGUV, OVLO,
EXTS Voltages ............................................. –0.3V to 6V
TRACK/SS Voltage (Note 11) .................... –0.3V to 2.8V
ITH, FREQ Voltage........................................ –0.3V to 5V
DRVUV/EXTG Voltage .................................. –0.3V to 9V
Operating Junction Temperature Range (Notes 2, 3)
LTC3894E, LTC3894I ......................... –40°C to 125°C
LTC3894H .......................................... –55°C to 150°C
Storage Temperature Range .................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec) ...................300°C
(Note 1)
FE PACKAGE
20(16)-LEAD PLASTIC TSSOP
TJMAX = 150°C, θJA = 38°C/W
EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB FOR RATED
ELECTRICAL AND THERMAL CHARACTERISTICS
1
3
5
6
7
8
9
10
TOP VIEW
20
18
16
15
14
13
12
11
GATE
RUN
SENSE+
SENSE–
ITH
PGUV
VFB
TRACK/SS
VIN
CAP
DRVUV/EXTG
EXTS
OVLO
FREQ
PGOOD
PLLIN/MODE
21
GND
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC3894EFE#PBF LTC3894EFE#TRPBF LTC3894FE 20(16)-Lead Plastic TSSOP –40°C to 125°C
LTC3894IFE#PBF LTC3894IFE#TRPBF LTC3894FE 20(16)-Lead Plastic TSSOP –40°C to 125°C
LTC3894HFE#PBF LTC3894HFE#TRPBF LTC3894FE 20(16)-Lead Plastic TSSOP –40°C to 150°C
Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Input Supply
VIN Input Voltage Operating Range (Note 4) DRVUV = 0V 4.5 150 V
VOUT Regulated Output Voltage Set Point 0.8 60 V
IQNo Load DC Supply Current (Note 5)
Shutdown VIN Pin Current RUN = 0V 7 11 µA
Sleep Mode VIN Pin Current VSENSE– = 2.5V, VFB = 0.83V 27 40 µA
VSENSE– ≥ 3.2V, VFB = 0.83V 7 10 µA
Sleep Mode SENSE– Pin Current (Note 6) VSENSE– ≥ 3.2V, VFB = 0.83V 21 30 µA
Pulse-Skipping Mode VIN Pin Current VFB = 0.83V
VSENSE– = 0V
VSENSE– = 3.3V
VSENSE– = 5V
1.8
1.5
0.8
mA
mA
mA
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, unless otherwise noted. (Note 2)
ELECTRICAL CHARACTERISTICS
LTC3894
3
Rev. A
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ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, unless otherwise noted. (Note 2)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
IQ(VINR) Total Input Supply Current in Regulation at
No Load in Burst Mode (Note 7)
VIN = 12V
Figure14 Circuit, VOUT = 3.3V
Figure12 Circuit, VOUT = 5V
16
22
µA
µA
VIN = 48V
Figure14 Circuit, VOUT = 3.3V
Figure12 Circuit, VOUT = 5V
9
11
µA
µA
Output Sensing
VFB Regulated Feedback Voltage VITH = 1.2V (Note 8) l0.788 0.800 0.812 V
Feedback Voltage Line Regulation VIN = 4.5V to 150V (Note 8) ±0.002 0.015 %/V
Feedback Voltage Load Regulation VITH = 0.6V to 1.8V (Note 8) 0.03 0.15 %
gm(EA) Error Amplifier Transconductance VITH = 1.2V, ∆IITH = ±5µA (Note 8) 2 mS
IFB Feedback Input Bias Current –10 ±50 nA
Current Sensing
VSENSE(MAX) Maximum Current Sense Threshold
(VSENSE+ – VSENSE–)
VFB = 0.7V, VSENSE– = 3.3V l88 100 112 mV
ISENSE+SENSE+ Pin Input Current VSENSE+ = 3.3V 0.1 1 µA
ISENSE–SENSE– Pin Input Current in Non-Sleep
Mode (Note 6)
VSENSE– = 3.3V
VSENSE– = 5V
200
880
300
1260
µA
µA
Start-Up and Shutdown
VRUN RUN Pin Enable Threshold VRUN Rising l1.14 1.24 1.34 V
VRUNHYS RUN Pin Hysteresis 125 mV
ISS Soft-Start Pin Charging Current VSS = 0V or 0V to 0.8V 8 11 14 µA
VOVLO Overvoltage Lockout Threshold VOVLO Rising Up
Hysteresis
l0.77 0.8
30
0.82 V
mV
Gate Driver and VIN-Cap LDO
VUVLO Undervoltage Lockout DRVUV = 0
(VIN-VCAP) Ramping Up Threshold
(VIN-VCAP) Ramping Down Threshold
Hysteresis
l
l
3.4
3.25
3.75
3.50
0.25
4.3
3.75
V
V
V
DRVUV = Floating
(VIN-VCAP) Ramping Up Threshold
(VIN-VCAP) Ramping Down Threshold
Hysteresis
l
l
5.5
5.2
6.0
5.55
0.45
6.55
5.85
V
V
V
VCAP Gate Bias LDO Output Voltage (VIN-VCAP) ICAP = 0mA, 9V ≤ VIN ≤ 150V (Note 9) l7.5 8.0 8.5 V
VCAPDROP Gate Bias LDO Dropout Voltage (VIN-VCAP) VIN = 5V, ICAP = 15mA (Note 9) 4.1 4.4 V
∆VCAP(LOAD) Gate Bias LDO Load Regulation ICAP = 0mA to 20mA –2.8 –1.3 %
RUP Gate Pull-Up Resistance Gate High 2 Ω
RDN Gate Pull-Down Resistance Gate Low 0.9 Ω
tON(MIN) Gate Minimum On-Time (Note 10) 125 ns
Switching Frequency and Clock Synchronization
f Programmable Switching Frequency RFREQ = 25kΩ
RFREQ = 64.9kΩ
RFREQ = 105kΩ
375
100
440
810
505
kHz
kHz
kHz
LTC3894
4
Rev. A
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SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fLO Low Switching Frequency FREQ = 0V 320 350 380 kHz
fHI High Switching Frequency FREQ = Open 470 530 590 kHz
fSYNC Synchronization Frequency l75 800 kHz
VCLK(HI) Clock Input High Level into PLLIN/MODE l2 V
VCLK(LO) Clock Input Low Level into PLLIN/MODE l0.5 V
PGOOD Output
VPGL PGOOD Voltage Low IPGOOD = 2mA 0.2 0.35 V
IPG PGOOD Leakage Current VPGOOD = 65V 1 µA
VPGOV PGOOD Overvoltage Trip Threshold VFB Ramping Positive with Respect to Set
Regulated Voltage
Hysteresis
7 10
2.5
13 %
%
VPGUV PGOOD Undervoltage Trip Threshold VPGUV Ramping Negative
Hysteresis
700 720
2.5
740 mV
%
tPGDL PGOOD Delay PGOOD High to Low
PGOOD Low to High
100
100
µs
µs
VFBOV VFB Overvoltage Lockout Threshold VFB Ramping Positive with Respect to Set
Regulated Voltage
Hysteresis
10
2.5
%
%
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, unless otherwise noted. (Note 2)
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3894 is tested under pulsed load conditions such that
TJ≈TA. The LTC3894E is guaranteed to meet performance specifications
from 0°C to 85°C. Specifications over the –40°C to 125°C operating
junction temperature range are assured by design, characterization and
correlation with statistical process controls. The LTC3894I is guaranteed
over the –40°C to 125°C operating junction temperature range and the
LTC3894H is guaranteed over the –40°C to 150°C operating junction
temperature range. Note that the maximum ambient temperature
consistent with these specifications is determined by specific operating
conditions in conjunction with board layout, the rated package thermal
impedance and other environmental factors. High temperatures degrade
operating lifetimes; operating lifetime is derated for junction temperatures
greater than 125ºC. The junction temperature (TJ, in °C) is calculated from
the ambient temperature (TA, in °C) and power dissipation (PD, in Watts)
according to the formula:
TJ = TA + (PD • θJA)
where θJA = 38°C/W for the TSSOP package.
Note 3: This IC includes overtemperature protection that is intended to
protect the device during momentary overload conditions. The maximum
rated junction temperature will be exceeded when this protection is active.
Continuous operation above the specified absolute maximum operating
junction temperature may impair device reliability or permanently damage
the device.
Note 4: The minimum input supply operating range is dependent on the
UVLO thresholds as determined by the DRVUV/EXTG pin setting.
Note 5: The DC supply current is measured when the LTC3894 is not
switching. Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency.
Note 6: SENSE1– bias current is reflected to the input supply by the
formula
IVIN = ISENSE1– • VOUT/(VIN • η), where η is the efficiency.
Note 7: The total input supply current in Burst Mode is the total current
drawn from input supply as measured in the Typical Application circuit on
page 1 and Figure14 on page 32 with no load current. The specification
is not tested in production.
Note 8: The LTC3894 is tested in a feedback loop that servos the error
amplifier output voltage (on ITH pin) to a specified voltage and measures
the resultant VFB voltage.
Note 9: Positive ICAP current flows into the CAP pin and discharges the
capacitor between the VIN and CAP pins.
Note 10: The minimum on-time condition is specified for an inductor
peak-to-peak ripple current > 40% of IMAX.
Note 11: The absolute maximum rating for TRACK/SS pin is 2.8V when the
pin is driven externally. When the pin is not driven, it may be pulled higher
by the IC, typically to 4.7V.
LTC3894
5
Rev. A
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TYPICAL PERFORMANCE CHARACTERISTICS
Transient Response:
Burst Mode Operation
Dropout Behavior
(100% Duty Cycle) Low VIN Operation
Normal Soft Start-Up
Soft Start-Up into a Prebiased
Output Output Tracking
Pulse-Skipping Mode Operation
Waveforms
Burst Mode Operation
Waveforms
Transient Response:
Pulse-Skipping Mode Operation
TA = 25°C, unless otherwise noted.
1ms/DIV
V
IN
5V/DIV
TRACKSS
200mV/DIV
V
OUT
1V/DIV
3894 G07
VIN = 12V
VOUT = 5V
ILOAD = 100mA
FIGURE 11 CIRCUIT
V
OUT
PREBIASED
TO 2.6V
2ms/DIV
V
OUT
1V/DIV
RUN
5V/DIV
TRACK/SS
500mV/DIV
3894 G08
VIN = 12V
VOUT = 5V
ILOAD = 500mA
FIGURE 11 CIRCUIT
20ms/DIV
V
OUT
2V/DIV
TRACK/SS
200mV/DIV
3894 G09
VIN = 12V
VOUT = 5V
ILOAD = 500mA
FIGURE 11 CIRCUIT
V
OUT
= V
IN
DROPOUT
100ms/DIV
V
IN
2V/DIV
V
OUT
2V/DIV
GATE
10V/DIV
3894 G05
VIN TRANSIENT 12V TO 4V
AND BACK TO 12V
VOUT = 12V, ILOAD = 100mA
FIGURE 14 CIRCUIT
20ms/DIV
V
OUT
2V/DIV
V
IN
2V/DIV
SW
10V/DIV
3894 G06
VIN = 0V TO 7.8V
AND BACK TO 0V
VOUT = 5V, ILOAD = 100mA
FIGURE 11 CIRCUIT
20µs/DIV
V
OUT
50mV/DIV
V
SW
10V/DIV
IL
500mA/DIV
3894 G02
VIN = 12V
VOUT = 5V
ILOAD = 100mA
FIGURE 11 CIRCUIT
2µs/DIV
V
OUT
50mV/DIV
V
SW
10V/DIV
I
L
500mA/DIV
3894 G01
VIN = 12V
VOUT = 5V
ILOAD = 100mA
FIGURE 11 CIRCUIT
100µs/DIV
V
OUT
100mV/DIV
I
L
2A/DIV
I
LOAD
2A/DIV
3894 G03
VIN = 12V
VOUT = 5V
LOAD STEP = 100mA TO 2A
FIGURE 11 CIRCUIT
100µs/DIV
V
OUT
100mV/DIV
I
L
2A/DIV
I
LOAD
2A/DIV
3894 G04
VIN = 12V
VOUT = 5V
LOAD STEP = 100mA TO 2A
FIGURE 11 CIRCUIT
LTC3894
6
Rev. A
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TYPICAL PERFORMANCE CHARACTERISTICS
Burst Mode Input Current Over
Input Voltage (No Load)
Pulse-Skipping Mode Input
Current vs Input Voltage
Shutdown Input Current vs
Input Voltage
Free Running Frequency Over
Temperature
Output Regulation vs Load
Current
Output Regulation vs
Temperature
Overcurrent Protection Short-Circuit Protection VIN Line Transient Behavior
TA = 25°C, unless otherwise noted.
V
OUT
DROOPS IN CURRENT LIMIT
1A
1A
4A
10ms/DIV
V
OUT
2V/DIV
I
LOAD
2A/DIV
I
L
2A/DIV
3894 G16
VIN = 12V
VOUT = 5V
FIGURE 11 CIRCUIT
SHORT-CIRCUIT REGION
SOFT
RECOVERY
500µs/DIV
V
OUT
5V/DIV
TRIGGER
IL
2A/DIV
3894 G17
VIN = 12V
VOUT = 5V
ILOAD = 500mA
FIGURE 11 CIRCUIT
V
IN
(V)
0
25
50
75
100
125
150
0
5.0
10.0
15.0
20.0
25.0
30.0
3894 G10
VOUT = 5V
ILOAD = 0A
FIGURE 11 CIRCUIT
TOTAL INPUT SUPPLY CURRENT (µA)
V
IN
(V)
0
30
60
90
120
150
0.9
1.7
2.5
3.4
4.2
5.0
3894 G11
VOUT = 5V
ILOAD = 0A
FIGURE 11 CIRCUIT
TOTAL INPUT SUPPLY CURRENT (mA)
FIGURE 11 CIRCUIT
V
IN
(V)
0
25
50
75
100
125
150
4.0
5.0
6.0
7.0
8.0
TOTAL INPUT SUPPLY CURRENT (µA)
3894 G12
5ms/DIV
V
IN
20V/DIV
GATE
20V/DIV
V
OUT
20mV/DIV
3894 G18
VIN = 12V, SURGE TO 100V
VOUT = 5V
ILOAD = 2A
FIGURE 11 CIRCUIT
OPEN FREQ PIN
GND FREQ PIN
TEMPERATURE (°C)
–75
–50
–25
0
25
50
75
100
125
150
300
350
400
450
500
550
600
F (kHz)
3894 G13
Burst Mode OPERATION
PULSE–SKIPPING
I
LOAD
(A)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
–0.010
–0.006
–0.002
0.002
0.006
0.010
NORMALIZED ∆V
OUT
(%)
3894 G14
VIN = 12V
VOUT = 5V
ILOAD NORMALIZED AT ILOAD = 1A
FIGURE 11 CIRCUIT
Burst Mode OPERATION
PULSE-SKIPPING
TEMPERATURE (°C)
–75
–25
25
75
125
150
–1.0
–0.8
–0.6
–0.4
–0.2
0.0
0.2
0.4
0.6
0.8
1.0
NORMALIZED ∆V
OUT
(%)
3894 G15
VIN = 12V
VOUT = 5V
ILOAD = 200mA
VOUT NORMALIZED TO TA = 25°C
FIGURE 11 CIRCUIT
LTC3894
7
Rev. A
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TYPICAL PERFORMANCE CHARACTERISTICS
CLC vs VIN at 150°C
IVIN and ISENSE– vs VSENSE–
(Burst Mode Operation)
IVIN and ISENSE– vs VSENSE–
(Burst Mode Operation)
IVIN and ISENSE– vs VSENSE–
(Pulse-Skipping Mode)
IVIN and ISENSE– vs VSENSE–
(Pulse-Skipping Mode) ISENSE+ vs VSENSE+
Maximum Current Sense
Threshold vs ITH Voltage Buck Foldback Current Limit
Maximum Current Sense
Threshold vs Duty Cycle
TA = 25°C, unless otherwise noted.
MAXIMUM CURRENT SENSE/ITH = 90mV/V
PULSE SKIPPING MODE
Burst Mode OPERATION
ITH (V)
0
0.3
0.6
1.0
1.3
1.6
–20
0
20
40
60
80
100
CURRENT SENSE THRESHOLD (mV)
3894 G19
DUTY CYCLE (%)
0
15
30
45
60
75
90
0
20.0
40.0
60.0
80.0
100.0
120.0
3894 G21
MAXIMUM CURRENT SENSE THRESHOLD (mV)
VIN (V)
3.50
3.75
4
4.25
4.50
4.75
5
0
20
40
60
80
100
120
3894 G22
MAXIMUM CURRENT SENSE THRESHOLD (mV)
VOUT = 0V
VOUT = 0.5V
VOUT = 1.0V
VOUT = 2.0V
VSENSE– (V)
0
5
10
15
20
25
30
35
40
45
50
55
60
65
0
5.000
10.000
15.000
20.000
25.000
30.000
IVIN AND ISENSE+ (µA)
3894 G23
VSENSE– (V)
0
5
10
15
20
25
30
35
40
45
50
55
60
65
0
0.250
0.500
0.750
1.000
1.250
1.500
1.750
2.000
IVIN AND ISENSE– (mA)
3894 G25
VSENSE+ (V)
0
1
2
3
4
5
–500.000
–400.000
–300.000
–200.000
–100.000
0
100.000
ISENSE+ (nA)
3894 G27
PGUV
< 0.72V
FEEDBACK VOLTAGE (mV)
0
100
200
300
400
500
600
700
800
0
20.000
40.000
60.000
80.000
100.000
120.000
MAXIMUM CURRENT SENSE THRESHOLD (mV)
3894 G20
IVIN RISING
ISENSE– RISING
ISENSE– FALLING
IVIN FALLING
VSENSE– (V)
2.5
3
3.5
4
4.5
5
5.5
0
0.250
0.500
0.750
1.000
1.250
1.500
1.750
2.000
IVIN AND ISENSE– (mA)
3894 G26
(ZOOMED IN VSENSE–)
VIN RISING
SENSE– RISING
SENSE– FALLING
VIN FALLING
VSENSE– (V)
2.5
3
3.5
4
4.5
5
5.5
0
5.000
10.000
15.000
20.000
25.000
30.000
IVIN AND ISENSE+ (µA)
3894 G24
(ZOOMED IN VSENSE–)
LTC3894
8
Rev. A
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PIN FUNCTIONS
GATE (Pin 1): Gate Drive Output for External P-Channel
MOSFET. The voltage swing on this pin is between CAP
and VIN. The GATE driver output is held low at VCAP to
turn on the P-channel MOSFET and held high at VIN to
turn off the MOSFET. The gate driver output is held high
when (VIN-VCAP) is less than VUVLO.
RUN (Pin 3): Run Control High Impedance Input. A RUN
voltage above the 1.26V threshold enables normal opera-
tion, while forcing this pin below 1.12V shuts down the
controller. Forcing this pin below 0.7V shuts down the
entire LTC3894, reducing quiescent current to approxi-
mately 7µA. This pin can be tied to VIN directly or pulled
up by a resistor. Do not float this pin.
SENSE+ (Pin 5): Differential Current Sensing (+) Input.
For RSENSE current sensing, Kelvin (4-wire) connect
SENSE+ and SENSE– pins across the sense resistor. For
DCR sensing, Kelvin connect SENSE+ and SENSE– pins
across the sense filter capacitor.
SENSE– (Pin 6): Differential Current Sensing (–) Input. For
RSENSE current sensing, Kelvin (4-wire) connect SENSE+
and SENSE
–
pins across the sense resistor. For DCR sens-
ing, Kelvin connect SENSE+ and SENSE– pins across the
filter capacitor. When SENSE
–
is greater than 3.2V, the
SENSE
–
pin supplies power to internal circuitry. To reduce
sensing errors, minimize the impedance in series with the
SENSE– pin.
ITH (Pin 7): Error Amplifier Output and Switching
Regulator Compensation Point. The voltage on this pin
sets the current sense threshold.
PGUV (Pin 8): Pgood Undervoltage (UV) Comparator
High Impedance Input. Connect the PGUV pin to the out-
put through a resistor feedback divider or connect directly
to VFB pin to program the output PGOOD UV threshold.
When the P
GUV
pin voltage falls below 0.72V (0.8V – 10%)
or lower, the PGOOD pin is asserted low after a 100µs
blanking period.
VFB (Pin 9): Output Feedback Sense Input. A resistor
divider from the output to this pin sets the regulated out-
put voltage. The LTC3894 will nominally regulate VFB to
the internal reference value of 0.8V.
TYPICAL PERFORMANCE CHARACTERISTICS
Shutdown (RUN) Threshold vs
Temperature
GATE Bias LDO (VIN - VCAP) Load
Regulation
GATE Bias LDO (VIN - VCAP)
Dropout Regulation
TA = 25°C, unless otherwise noted.
RUN RISING
RUN FALLING
TEMPERATURE (°C)
–75
–50
–25
0
25
50
75
100
125
150
1.000
1.050
1.100
1.150
1.200
1.250
1.300
RUN PIN VOLTAGE (V)
3894 G28
V
IN
= 7V
IGATE (mA)
0
4
8
12
16
20
6.25
6.38
6.50
6.63
6.75
6.88
7.00
(V
IN
-V
CAP
) REGULATION (V)
3894 G30
125°C
25°C
–55°C
V
IN
= 12V
IGATE (mA)
0
4
8
12
16
20
–3.60
–3.00
–2.40
–1.80
–1.20
–0.60
0.00
(V
IN
–V
CAP
) REGULATION (%)
3894 G29
125°C
25°C
–55°C
LTC3894
9
Rev. A
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PIN FUNCTIONS
TRACK/SS (Pin 10): Soft-Start and External Tracking Input.
The LTC3894 regulates the VFB voltage to the smaller of
0.8V or the voltage on the SS pin. An internal 10μA pull-up
current source is connected to this pin. A capacitor to
ground at this pin sets the ramp time to the final regulated
output voltage. Alternatively, another voltage supply con-
nected through a resistor divider to this pin allows the
output to track the other supply during start-up.
PLLIN/MODE (Pin 11): External Reference Clock Input
and Burst Mode Enable/Disable. When an external clock
is applied to this pin, the internal phase-locked loop will
synchronize the turn-on edge of the gate drive signal with
the rising edge of the external clock. When no external
clock is applied, this input determines the mode of opera-
tion during light loading. Floating this pin selects low IQ
Burst Mode operation. Pulling to ground selects pulse-
skipping mode operation.
PGOOD (Pin 12): Power Good Monitor Output. This open
drain logic output is pulled to ground when the VFB pin is
10% above its regulation point (OV) or when the PGUV pin
voltage is below the PGOOD undervoltage (UV) threshold
V
PGUV
. There is a 100µs delay before PGOOD changes
state in response to either an OV or a UV event.
FREQ (Pin 13): Switching Frequency Setpoint Input. The
switching frequency is programmed between 75kHz and
850 kHz by an external setpoint resistor RFREQ connected
between the FREQ pin and SGND. An internal 20µA current
source creates a voltage across the external setpoint resis-
tor to set the internal oscillator frequency. Alternatively,
this pin can be driven directly by a DC voltage to set the
oscillator frequency. Grounding selects a fixed operating
frequency of 350kHz. Floating selects a fixed operating
frequency of535kHz.
OVLO (Pin 14): Overvoltage Lockout High Impedance
Input. For an adjustable VIN overvoltage protection, con-
nect this pin through a resistor divider to VIN. When
the voltage on this pin is greater than the 0.8V lockout
threshold, ,the external P-channel MOSFET is turned off
immediately and the TRACK/SS pin is discharged to GND
to ensure a graceful recovery. Connect this pin to GND
when the OVLO function is not used.
EXTS (Pin 15): Source Terminal Connection for the
Optional External N-Channel MOSFET. When an optional
external N-channel MOSFET is used to provide bias to
the gate driver, connect this pin to the MOSFET source
terminal and connect a 0.1µF bypass capacitor next to
the the pin to ensure stable operation (see Applications
Information section on page 21). When not in use, con-
nect this pin to ground. Do not float this pin.
DRVUV/EXTG (Pin 16): Driver Undervoltage Lockout
(UVLO) Select Pin and External N-Channel Gate
Connection. This is a dual function pin. Grounding this
pin selects a UVLO threshold of 3.75V between VIN and
CAP. Floating or connecting it to a voltage greater than
400mV selects a UVLO threshold of 6V. When an external
N-channel MOSFET is used for the gate driver bias, con-
nect its gate terminal to the pin through a 1k resistor. This
selects the 6V UVLO threshold by default.
CAP (Pin 18): Lower Supply Rail for Gate Driver Bias.
VIN is the higher supply rail. The gate driver bias supply
voltage (VIN-VCAP) is regulated to 8V when VIN is greater
than 8V. A low ESR ceramic bypass capacitor of at least
0.47μF is required from VIN to CAP pin to maintain stable
voltage regulation. The capacitor value needs to increase
to a minimum of 2.2µF if an external N-channel MOSFET
is used for gate driver bias. To ensure stable low noise
operation, the bypass capacitor should be placed adjacent
to the VIN and CAP pins and connected using the same
PCB metal layer.
VIN (Pin 20): Chip Power Supply. A minimum bypass
capacitor of 1µF is required from the VIN pin to GND.
For best performance use a low ESR ceramic capacitor
and place the capacitor near the VIN pin and GND pin to
minimize the size of the high current loop.
GND (Exposed Pad Pin 21): Chip Ground. The exposed
pad must be soldered to the circuit board for electrical
contact and for rated electrical and thermal performance
of the package.
LTC3894
10
Rev. A
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FUNCTIONAL DIAGRAM
–+
EA
(gm = 2mS)
0.8V
10µA
LOGIC
CONTROL
GATE
DRIVER
LDO
LDO
IN
OUT
PLL
SYSTEM
Q
S R
MODE/CLOCK
DETECT
DELAY
100µs
VCO
OV O.88V
SLOPE
COMPENSATION
O.72V
UV
CAP
DRUV
SHDN
0.8V8V
GATE
CAP
TRACK/SS
SHDN
VFB
VIN – 8V
SENSE+
VIN
1.26V
–
+
+
RPGD
PLLIN/MODE
CCAP
MP
D1
VOUT
UVLO
RFREQ
GND
FREQ
RUN
VIN
20µA
3894 FD
+
–
1.26V
DRVUV/EXTG
20µA
+
–
+
–
+
–
GATE
DRIVER
CLOCK
PGOOD
+
–
+
–
O.425V
Burst Mode
OPERATION
+
–
ITH
RITH
CITH1
CEXTS
PGUV
RPGUV1
RPGUV2
L
CSS
CIN
VIN
COUT
V
OUT
RFB2
RFB1
ICMP
+
+
–
SENSE–
R
OVLO1
R
OVLO2
CAP
EXTS
OVLO
+
–
CEXTG
REXTG
EXT
NMOS
OPTIONAL
LTC3894
11
Rev. A
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OPERATION
Main Control Loop (Refer to Functional Diagram)
The LTC3894 uses a constant frequency peak current-
mode control architecture to regulate the output voltage
in an nonsynchronous step-down DC/DC switching regu-
lator. The VFB input is compared to an internal reference
by a transconductance error amplifier (EA). The internal
reference can be either a fixed 0.8V reference VREF or
the voltage input on the TRACK/SS pin. In normal opera-
tion VFB regulates to the internal 0.8V reference voltage.
In soft-start or tracking mode, when the TRACK/SS pin
voltage is less than the internal 0.8V reference voltage,
VFB will regulate to the TRACK/SS pin voltage. The error
amplifier output connects to the ITH pin. The voltage level
on the ITH pin is then summed with a slope compensation
ramp to create the peak inductor current set point.
The peak inductor current is measured through a sense
resistor RSENSE placed across the SENSE+ and SENSE–
pins. The resultant differential voltage from SENSE
+
to
SENSE– is proportional to the inductor current and is
compared to the peak inductor current set point. During
normal operation the P-channel power MOSFET is turned
on when the clock leading edge sets the SR latch through
the S input. The P-channel MOSFET is turned off through
the SR latch R input when the differential voltage of
VSENSE+ – VSENSE– is greater than the peak inductor cur-
rent set point and the current comparator, ICMP, trips high.
After the MOSFET is turned off, an external Schottky diode
carries inductor current until it reaches zero or the begin-
ning of the next clock cycle.
Gate Driver Bias(VIN–CAP) and Undervoltage
Lockout (UVLO)
Power for the P-channel MOSFET gate driver is derived
from the VIN and CAP pins. The CAP pin is regulated
to 8V below VIN by an internal low dropout linear
regulator(LDO).A minimum capacitance of 0.47μF (low
ESR ceramic) is required between VIN and CAP to assure
stability. The internal VIN-CAP LDO can generate signifi-
cant on-chip heat when using a P-channel MOSFET with
large gate capacitance at high VIN and high switching
frequency. An external N-channel MOSFET bias path can
be used to move the heat off chip and its connections
are shown on page 10. When the external N-channel
MOSFET is used, a minimum capacitance of 2.2µF (low
ESR ceramic) is recommended between VIN and CAP.
For VIN ≤8V, the LDO will be in dropout and the CAP
voltage will be near ground (the VIN-CAP differential volt-
age will nearly equal VIN). If VIN-CAP is less than VUVLO,
the LTC3894 enters a UVLO state where the external
P-channel MOSFET is turned off and most internal cir-
cuitry is shut down. In order to exit UVLO, the VIN-CAP
voltage must exceed either 3.75V or 6V depending on
the DRVUV /EXTG voltage setting. When an external
N-channel MOSFET bias path is used, a UVLO threshold
of 6V is selected by default.
Shutdown and Soft-Start
When the RUN pin is below 0.7V, the controller and most
internal circuits are disabled. In this micropower shut-
down state, the LTC3894 draws only 7μA. The RUN pin
voltage must rise above 1.24V to enable the controller. The
RUN pin can be tied to or pulled up to an external supply
of up to 150V or it can be driven directly by a logic gate.
The start-up of the output voltage VOUT is controlled by
the voltage on the TRACK/SS pin. When the voltage on
the TRACK/SS pin is less than the 0.8V internal reference,
the VFB pin is regulated to the voltage on the TRACK/SS
pin. This allows the TRACK/SS pin to be used to program
a soft-start by connecting an external capacitor from the
TRACK/SS pin to signal ground. An internal 10μA pull-up
current charges this capacitor, creating a voltage ramp on
the TRACK/SS pin. As the TRACK/SS voltage rises from
0V to 0.8V, the output voltage VOUT rises smoothly from
zero to its final value.
Alternatively, the TRACK/SS pin can be used to cause the
startup of VOUT to track that of another supply. Typically,
this requires connecting the TRACK/SS pin to an external
resistor divider from the other supply to ground. (See
Applications Information section.) During a shutdown,
input overvoltage, and input undervoltage, or overtem-
perature event, the TRACK/SS pin is discharged to ground
to ensure smooth restart.
If the slew rate of the TRACK/SS pin is greater than
0.6V/ms, the output will track an internal soft-start ramp
instead of the TRACK/SS pin. The internal soft-start offers
LTC3894
12
Rev. A
For more information www.analog.com
OPERATION
a smooth start-up of the output in the case of a short-
circuit recovery where the output voltage will recover from
nearground.
Light Load Current Operation (Burst Mode Operation
or Pulse-Skipping Mode)
At light loads, the LTC3894 operates in either pulse-skip-
ping mode or high efficiency Burst mode. To select pulse-
skipping operation, tie the PLLIN/MODE pin to ground. To
select Burst Mode operation, float the PLLIN/MODE pin.
In Burst Mode operation, if the VFB is higher than the refer-
ence voltage, the error amplifier will decrease the voltage
on the ITH pin. When the ITH voltage drops below 0.425V,
the internal sleep signal goes high, enabling sleepmode.
In sleep mode, much of the internal circuitry is turned
off, reducing the quiescent current the LTC3894 draws to
30µA. When the SENSE– pin voltage is greater than 3.2V,
the majority of this current (25µA) is drawn by SENSE–
and only 6µA is drawn by the VIN pin. For output voltages
greater than 3.2V, this dramatically reduces the total qui-
escent current drawn from the input supply in sleep mode.
When referred back to the input supply, the quiescent
current is reduced by the DC/DC voltage conversion ratio
and the incremental efficiency from VOUT to VIN.
Therefore, for the typical application on the first page with
Burst Mode selected, the total input supply current at no
load in regulation can be estimated using:
IQ(VINR) =6µA +VOUT
0.9 • V
IN
=0.8V
R
FB1
+22µA
⎛
⎝
⎜⎞
⎠
⎟
where RFB1 is the lower feedback divider resistor.
As the output voltage and hence the feedback voltage
decreases, the error amplifier’s output will rise. When
the output voltage drops enough, the ITH pin is recon-
nected to the output of the error amplifier, and the con-
troller resumes normal operation by turning on the exter-
nal P-channel MOSFET on the next cycle of the internal
oscillator.
In Burst Mode operation, the peak inductor current has
to reach at least 25% of current limit for the current com-
parator, ICMP, to trip and turn the P-MOSFET back off,
even though the ITH voltage may indicate a lower current
setpoint value.
When the PLLIN/MODE pin is connected to ground for
pulse-skipping mode, the LTC3894 will skip pulses during
light loads. In this mode, ICMP may remain tripped for
several cycles and force the external P-channel MOSFET
to stay off, thereby skipping pulses. This mode offers the
benefits of smaller output ripple, lower audible noise, and
reduced RF interference, at the expense of lower efficiency
when compared to Burst Mode operation.
Frequency Selection and Clock Synchronization
The switching frequency of the LTC3894 can be selected
using the FREQ pin. If the PLLIN/MODE pin is not being
driven by an external clock source, the FREQ pin can be
tied to signal ground, floated, or programmed through
an external resistor. Tying the FREQ pin to signal ground
selects 350kHz, while floating selects 535kHz. Placing a
resistor between the FREQ pin and signal ground allows
the frequency to be programmed between 50kHz and
850kHz.
The phase-locked loop (PLL) on the LTC3894 will syn-
chronize the internal oscillator to an external clock source
when connected to the PLLIN/MODE pin. The PLL forces
the turn-on edge of the external P-channel MOSFET to be
aligned with the rising edge of the synchronizing signal.
The oscillator’s default frequency is based on the oper-
ating frequency set by the FREQ pin. If the oscillator’s
default frequency is near the external clock frequency,
only slight adjustments are needed for the PLL to syn-
chronize the external P-channel MOSFET’s turn-on edge
to the rising edge of the external clock. This allows the
PLL to lock rapidly without deviating far from the desired
frequency. The PLL is guaranteed from 75kHz to 750kHz.
The clock input levels should be greater than 2V for logic
high and less than 0.5V for logic low.
Power Good
The PGOOD pin connects to the open-drain output of an
internal N-channel MOSFET. The MOSFET pulls the PGOOD
pin low when either the VFB pin voltage is overvoltage
at 10% or more above or the PGUV pin is undervoltage
LTC3894
13
Rev. A
For more information www.analog.com
The LTC3894 is a current mode, constant frequency
nonsynchronous step-down DC/DC controller with a
P-channel power MOSFET acting as the main switch
and a Schottky power diode acting as the commutat-
ing (catch) diode. The input range extends from 4.5V to
150V. The output range can be programmed from 0.8V
to 60V. The LTC3894 can transition from regulation to
100% duty cycle when the input voltage drops below the
programmed output voltage. Additionally, the LTC3894
offers Burst Mode operation with a very low quiescent
current, delivering outstanding efficiency in light load
operation not typically found in a controller. The LTC3894
is a low pin-count, robust and easy to use solution in
applications which require high efficiency and operate
with widely varying high voltage inputs.
OPERATION
APPLICATIONS INFORMATION
at10% or more below the 0.8V internal voltage refer-
ence. The PGOOD pin is also pulled low during an over-
temperature, RUN pin shutdown, VIN overvoltage or VIN
undervoltage lockout event. When the VFB pin voltage is
less than 0.88V (0.8V + 10%) and PGUV is above 0.72V
(0.8V – 10%), the internal N-channel MOSFET is turned
off and the PGOOD pin is allowed to be pulled up by an
external resistor to VOUT or another source no greater than
60V. The PGOOD open-drain output has a 100μs delay
before it can transition states.
When the VFB voltage is higher than 0.88V (0.8V + 10%)
nominal, this is considered an overvoltage condition and
the external P-MOSFET is immediately turned off and
remains turned off until VFB falls below 0.88V with built-
in hysteresis of 20mV.
Current Limit Foldback
In the event of an output short-circuit or overcurrent con
-
dition that causes the output voltage to fall to less than
72% of its nominal regulated level and the PGUV pin volt-
age is less than 0.72V, current limit foldback is activated,
progressively lowering the peak current limit in propor-
tion to the drop of VOUT until reaching a minimum cur-
rent limit of about 36% of full current limit. Current limit
foldback reduces the power dissipation in the Schottky
diode and assures robust operation during a continu-
ous short-circuit fault. Current limit foldback is disabled
during soft-start (as long as the VFB voltage is keeping
up with the TRACK/SS voltage). Note that the LTC3894
continuously monitors the inductor current and prevents
current runaway under all conditions.
LTC3894 has an internal overtemperature protection cir-
cuit that shuts off the controller and the external P-channel
MOSFET when internal die temperature exceeds 180°C.
The circuit also discharges the TRACK/SS pin to GND to
ensure a smooth restart.
Input Supply Overvoltage Lockout (OVLO Pin)
The LTC3894 implements a protection feature that inhibits
switching when the input voltage rises above a program-
mable operating range. By using a resistor divider from
the input supply to ground, the OVLO pin serves as a
precise input supply voltage monitor. Switching is dis-
abled when the OVLO pin rises above 0.8V, which can be
configured to limit switching to a specific range of input
supply voltage. An input supply overvoltage event triggers
a TRACK/SS reset, which results in a graceful recovery
from an input supply transient.
The typical application on the front page is a basic
LTC3894 application circuit where the inductor current
is sensed using a low value sense resistor, R
SENSE
, placed
between the power inductor and VOUT. Once the required
output voltage and operating frequency have been deter-
mined, external component selection is driven by load
requirements, and begins with the selection of inductor
and RSENSE. Next, the power MOSFET and catch diode are
selected. Finally, input and output capacitors are selected.
Output Voltage Programming
The output voltage is programmed by connecting a feed-
back resistor divider from the output to the V
FB
pin as
shown in Figure1. The output voltage in steady state
LTC3894
14
Rev. A
For more information www.analog.com
APPLICATIONS INFORMATION
operation is set by the feedback resistors according to
the equation:
VOUT =0.8V • 1+RFB2
R
FB1
⎛
⎝
⎜⎞
⎠
⎟
To improve the transient response, a feedforward capaci-
tor CFF may be used. Great care should be taken to route
the V
FB
line away from noise sources, such as the inductor
or the GATE signal that drives the external P-MOSFET.
Switching Frequency and Clock Synchronization
The choice of operating frequency is a trade-off between
efficiency and component size. Lowering the operat-
ing frequency improves efficiency by reducing MOSFET
switching losses but requires larger inductance and/
or capacitance to maintain low output ripple voltage.
Conversely, raising the operating frequency degrades
efficiency but reduces component size.
The LTC3894 can free run at a user programmed switch-
ing frequency, or it can synchronize to an external clock.
When a clock signal is applied to the PLLIN/MODE pin,
the turn-on of the external P-channel MOSFET is coin-
cidental with the rising edge of the applied clock. The
switching frequency of the LTC3894 is programmed with
the FREQ pin, and the external clock is applied at the
PLLIN/MODE pin. Table1 highlights the different states
in which the FREQ pin can be used in conjunction with
the PLLIN/MODE pin.
Table1
FREQ PIN PLLIN/MODE PIN FREQUENCY
0V DC Voltage 350kHz
Floating DC Voltage 535kHz
Resistor to GND DC Voltage 50kHz to 850kHz
Any of the Above External Clock Phase Locked to External Clock
The free-running switching frequency can be programmed
from 50kHz to 850kHz by connecting a resistor from FREQ
pin to signal ground. The resulting switching frequency as
a function of resistance on FREQ pin is shown in Figure2.
Set the free-running frequency to the desired synchroni-
zation frequency using the FREQ pin so that the internal
oscillator is prebiased to approximately the synchroni-
zation frequency. While it is not required that the free-
running frequency be near the external clock frequency,
doing so will minimize synchronization time.
Inductor Selection
The operating frequency and inductor selection are inter-
related in that higher operating frequencies allow the
use of smaller inductor and capacitor values. A higher
frequency generally results in lower efficiency because
of MOSFET gate charge and transition losses. In addi-
tion to this basic trade-off, the effect of inductor value
on ripple current and low current operation must also be
considered.
The inductor value has a direct effect on ripple current. The
inductor ripple current, ∆IL, decreases with higher induc-
tance or higher frequency and increases with higherVIN.
Given the desired input and output voltages, the induc-
tor value and operation frequency determine the ripple
current:
ΔIL=
V
OUT
f •L
⎛
⎝
⎜
⎞
⎠
⎟1–
V
OUT
V
IN
⎛
⎝
⎜
⎞
⎠
⎟
LTC3894
VFB
V
OUT
RFB2 C
FF
RFB1
3894 F01
Figure1. Setting the Output Voltage
FREQ PIN RESISTOR (kΩ)
15
30
45
60
75
90
105
120
135
150
0
100.0
200.0
300.0
400.0
500.0
600.0
700.0
800.0
900.0
1000.0
FREQUENCY (kHz)
3894 F02
Figure2. Switching Frequency vs Resistor on FREQ Pin
LTC3894
15
Rev. A
For more information www.analog.com
Lower ripple current reduces core losses in the induc-
tor, ESR losses in the output capacitors and results in
lower output ripple. The highest efficiency operation can
be obtained at low frequency with small ripple current.
However, achieving this requires a large inductor. There
is a trade-off between component size, efficiency, and
operating frequency.
A reasonable starting point for ripple current is 40% of
I
OUT(MAX)
. The largest ripple current occurs at the highest
VIN. To guarantee that the ripple current does not exceed
a specified maximum, the inductance should be chosen
according to:
L=VOUT
f • ΔIL(MAX)
⎛
⎝
⎜⎞
⎠
⎟1– VOUT
VIN(MAX)
⎛
⎝
⎜⎞
⎠
⎟
The inductor value also has secondary effects. The tran-
sition to Burst Mode operation begins when the average
inductor current required results in a peak current below
25% of the current limit determined by RSENSE. Lower
inductor values (higher ∆IL) will cause this to occur at
lower load currents, which can cause a dip in efficiency in
the upper range of low current operation. In Burst Mode
operation, lower inductance values will cause the burst
frequency to decrease.
Inductor Core Selection
Once the inductance value has been determined, the type
of inductor must be selected. Core loss is independent of
core size for a given inductor value, but it is very depen-
dent on the inductance selected. As inductance increases,
core losses decrease. Unfortunately, increased inductance
requires more turns of wire and therefore copper losses
will increase.
Ferrite designs have very low core loss and are preferred
for high switching frequencies, so design goals can con-
centrate on copper loss and preventing saturation. Ferrite
core material saturates hard, which means that induc-
tance collapses abruptly when the peak design current is
exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
APPLICATIONS INFORMATION
Inductor Current Sensing
LTC3894 can be configured to use either low value series
resistor sensing (Figure3a) or DCR (inductor resistance)
sensing (Figure3b). The choice between the two current
sensing schemes is largely a design trade-off between
cost, power consumption and accuracy. DCR sensing is
becoming popular because it saves expensive current
sensing resistors and is more power efficient, especially
in high current applications. However, current sensing
resistors provide the most accurate current limits for the
controller.
SENSE+ and SENSE– Pins
The SENSE+ and SENSE– pins are the inputs to the dif-
ferential current comparator. The common mode voltage
range on these pins is 0V to 65V (absolute maximum),
enabling the LTC3894 to regulate an output voltage up
(3b) Using the Inductor DCR to Sense Current
Figure3. Current Sensing Methods
(3a) Using a Resistor to Sense Current
3894 F03a
LTC3894
SENSE+
SENSE–
GND
V
IN
V
OUT
RSENSE
C1*
VIN
GATE
CAP
3894 F03b
C1* R2
*PLACE C1 NEAR SENSE PINS
R
SENSE(EQ)
= DCR(R2/(R1+R2))
L DCR
INDUCTOR
R1
(R1||R2) • C1 = L/DCR
LTC3894
VIN
GATE
CAP
SENSE+
SENSE–
GND
V
IN
V
OUT
LTC3894
16
Rev. A
For more information www.analog.com
APPLICATIONS INFORMATION
to a nominal 60V (allowing margin for tolerances and
transients). The SENSE+ pin is high impedance. This high
impedance allows the current comparators to be used in
inductor DCR sensing.
The impedance of the SENSE– pin changes depending on
the common mode voltage. When SENSE– is less than
2.9V, it is high impedance, drawing less than 1µA. When
SENSE– is above 3.2V, pin current increases considerably
and can be as high as 1.2mA.
Any voltage drop caused by the current along the SENSE–
PCB board trace directly translates into errors in current
sensing. The impedance of the SENSE
–
board layout trace
need to be minimized to maintain high sensing accuracy.
Optional filter component C1, mutual to the sense lines,
should be placed close to the LTC3894, and the sense
lines should run close together to a 4-wire Kelvin con-
nection underneath the current sense element (shown in
Figure4). Sensing current elsewhere can effectively add
parasitic inductance and capacitance to the current sense
element, degrading the information at the sense terminals
and making the programmed current limit unpredictable.
If DCR sensing is used (Figure3b), R1 should be placed
close to the switching node, to prevent noise from cou-
pling into sensitive small-signal nodes.
peak-to-peak ripple current, ∆I
L
. To calculate the sense
resistor value, use the equation:
RSENSE =
V
SENSE(MAX)
IOUT(MAX) +ΔIL
2
Choose a sense resistor with low parasitic inductance to
improve sensing accuracy.
To ensure that the application will deliver full load cur-
rent over the full operating temperature range, choose the
minimum value (88mV) for the VSENSE(MAX) threshold in
the Electrical Characteristics table and take into account
inductance tolerance as listed in inductor manufacturer’s
data sheet (typically ±20%).
When using the controller in high duty cycle conditions,
the maximum output current level will be reduced due to
the internal compensation required to meet the stability
criterion for buck regulators operating at greater than 50%
duty factor. A curve is provided in the Typical Performance
Characteristics section to estimate this reduction in peak
inductor current depending upon the operating duty fac-
tor. (See Maximum Current Sense Threshold vs Duty
Cycle curve on page 7).
Inductor DCR Sensing
For applications requiring the highest possible efficiency
at high load currents, the LTC3894 is capable of sensing
the voltage drop across the inductor DCR, as shown in
Figure3b. The DCR of the inductor represents the small
amount of DC winding resistance of the copper, which
can be less than 1mΩ for today’s low value, high current
inductors. In a high current application requiring such
an inductor, power loss through a sense resistor would
cost several points of efficiency compared to inductor
DCR sensing.
If the external (R1||R2) • C1 time constant is chosen to
be exactly equal to the L/DCR time constant, the voltage
drop across the external capacitor is equal to the drop
across the inductor DCR multiplied by R2/(R1 + R2). R2
scales the voltage across the sense terminals for appli-
cations where the DCR is greater than the target sense
resistor value. To properly dimension the external filter
Low Value Resistor Current Sensing
A typical sensing circuit using a discrete resistor is shown
in Figure3a. RSENSE is chosen based on the required out-
put current. The voltage across the resistor, VSENSE, is
proportional to inductor current. The LTC3894 current
comparator has a fixed maximum current sense threshold
VSENSE(MAX) of 100mV (typical).
The current comparator threshold voltage sets the peak of
the inductor current, yielding a maximum average output
current, IOUT(MAX), equal to the peak value less half the
Figure4. Sense Lines Placement with Inductor or Sense Resistor
3894 F04
TO SENSE FILTER
NEXT TO THE CONTROLLER
INDUCTOR OR RSENSE
CURRENT FLOW
SWITCHING NODE
COUT
LTC3894
17
Rev. A
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APPLICATIONS INFORMATION
components, the DCR of the inductor must be known. It
can be measured using a good RLC meter, but the DCR
tolerance is not always the same and varies with tempera-
ture; consult the manufacturers’ data sheets for detailed
information.
Using the inductor ripple current value from the Inductor
Value Calculation section, the target sense resistor value
is:
RSENSE(EQUIV) =
V
SENSE(MAX)
IOUT(MAX) +ΔIL
2
To ensure that the application will deliver full load cur-
rent over the full operating temperature range, choose the
minimum value (88mV) for the VSENSE(MAX) threshold in
the Electrical Characteristics table.
Next, determine the DCR of the inductor. When provided,
use the manufacturer’s maximum value, usually given at
20°C. Increase this value to account for the temperature
coefficient of copper resistance, which is approximately
0.4%/°C. A conservative value for TL(MAX) is 100°C.
To scale the maximum inductor DCR to the desired sense
resistor value, use the divider ratio RD:
RD=RSENSE(EQUIV )
DCRMAX at TL(MAX)
C1 is usually selected to be in the range of 0.1μF to
0.47μF. This forces R1|| R2 to around 2k, reducing error
that might have been caused by the SENSE+ pin’s ±1μA
current.
The equivalent resistance R1||R2 is scaled to the room
temperature inductance and maximum DCR:
R1!R2 =
L
(DCR at 20°C)•C1
The sense resistor values are:
R1=
R1
!
R2
R
D
; R2 =
R1•R
D
1−R
D
=
R1
!
R2
1−R
D
The maximum power loss in R1 is related to duty cycle,
and will occur in continuous mode at the maximum input
voltage:
P
LOSS R1=
VIN(MAX) −VOUT
( )
• VOUT
R1
Ensure that R1 has a power rating higher than this value.
If high efficiency is necessary at light loads, consider this
power loss when deciding whether to use DCR sensing
or sense resistors. Light load power loss can be mod-
estly higher with a DCR network than with a sense resis-
tor, due to the extra switching losses incurred through
R1. However, DCR sensing eliminates a sense resistor,
reduces conduction losses and provides higher efficiency
at heavy loads. Peak efficiency is about the same with
either method.
Power MOSFET Selection
The LTC3894 drives a P-channel power MOSFET that
serves as the main switch for the asynchronous step-
down converter. Important P-channel power MOSFET
parameters include drain-to-source breakdown volt-
age V
BR(DSS)
, threshold voltage V
GS(TH)
, on-resistance
R
DS(ON)
, gate charge Q
G
, and the MOSFET’s thermal resis-
tance θJC(MOSFET) and θJA(MOSFET).
A partial list of P-channel MOSFET devices suitable
for a 150V high current LTC3894 application includes
FDMS86263P (Fairchild), SIR873DP (Vishay), IRF6218S
(Infineon), FDMC86259P (Fairchild), and Si7439DP
(Vishay).
The gate driver bias voltage VIN-VCAP is set by an internal
LDO regulator. In normal operation, the CAP pin will be
regulated to 8V below VIN. A minimum 0.47µF capacitor
is required between the VIN and CAP pins to ensure LDO
stability. If required, additional capacitance can be added
to accommodate higher gate currents. The capacitance
should be increased to a minimum of 2.2µF when the
external N-channel MOSFET is used. In shutdown and
Burst Mode operation, the CAP LDO is turned off. In the
event of CAP leakage to ground, the CAP voltage is lim-
ited to 9V by a weak internal clamp from VIN to CAP. As
a result, a minimum 10V VGS rated MOSFET is required.
LTC3894
18
Rev. A
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The power dissipated by the P-channel MOSFET when the
LTC3894 is in continuous conduction mode is given by:
P
MOSFET ≅D•IOUT
2
•ρτ•RDS ON
( )
+
VIN2•IOUT
2
⎛
⎝
⎜⎞
⎠
⎟• CMILLER
( )
•
RDN
VIN – VCAP
( )
– VMILLER
+RUP
VMILLER
⎡
⎣
⎢⎤
⎦
⎥• f
where D is duty factor, RDS(ON) is on-resistance of
P-MOSFET, ρt is temperature coefficient of on-resistance,
RDN is the pull-down driver resistance specified at 0.9Ω
typical and R
UP
is the pull-up driver resistance specified at
2Ω typical. VMILLER is the Miller effective VGS voltage and
is taken graphically from the power MOSFET data sheet.
The power MOSFET input capacitance CMILLER is
the most important selection criteria for determin-
ing the transition loss term in the P-channel MOSFET
but is not directly specified on MOSFET data sheets.
CMILLER is a combination of several components, but
it can be derived from the typical gate charge curve
included on most data sheets (Figure5). The curve is
generated by forcing a constant current out of the gate of a
common-source connected P-MOSFET that is loaded with
a resistor, and then plotting the gate voltage versus time.
The initial slope is the effect of the gate-to-source and
gate-to-drain capacitances. The flat portion of the curve
is the result of the Miller multiplication effect of the drain-
to-gate capacitance as the drain voltage rises across the
resistor load. The Miller charge (the increase in coulombs
on the horizontal axis from a to b while the curve is flat) is
specified for a given V
SD
test voltage, but can be adjusted
for different VSD voltages by multiplying by the ratio of
the adjusted VSD to the curve specified VSD value. A way
to estimate the CMILLER term is to take the change in gate
charge from points a and b (or the parameter QGD on a
manufacturer’s data sheet) and dividing it by the specified
VSD test voltage, VSD(TEST).
CMILLER ≅
Q
GD
VSD(TEST)
The term with CMILLER accounts for transition loss,
which is highest at high input voltages. For VIN < 20V,
the high-current efficiency generally improves with larger
MOSFETs, while for VIN > 20V, the transition losses rap-
idly increase to the point that the use of a higher RDS(ON)
device with lower CMILLER actually provides higher effi-
ciency. When an application is intended for use at low
VIN, care must be taken to select a P-channel MOSFET
with threshold voltage VGS(TH) low enough to operate at
low VIN.
Schottky Diode Selection
When the P-MOSFET is turned off, a power Schottky diode
is required to function as a commutating diode to carry the
inductor current. The average diode current is therefore
dependent on the P-MOSFET’s duty factor. The worst case
condition for diode conduction is a short-circuit condition
where the Schottky must handle the maximum current
as its duty factor approaches 100% (and the P-channel
MOSFET’s duty factor approaches 0%). The diode there-
fore must be chosen carefully to meet worst case voltage
and current requirements. The equation below describes
the continuous or average forward diode current rating
required, where D is the regulator duty factor.
I
F(AVG)
≅I
OUT(MAX)
• 1–D
( )
Once the average forward diode current is calculated,
the power dissipation can be determined. Refer to the
Schottky diode data sheet for the power dissipation
PDIODE as a function of average forward current IF(AVG).
PDIODE can also be iteratively determined by the two
equations below, where VF(IOUT,TJ) is a function of both
I
F(AVG)
and junction temperature T
J
. Note that the thermal
Figure5. (a) Typical P-MOSFET Gate Charge Characteristics
and (b) Test Set-Up to Generate Gate Charge Curve
S
D
G
V
SD(TEST)
RLOAD
IGATE
3894 F05
MILLER EFFECT
QIN
(a) (b)
a b
CMILLER = (QB – QA)/VSD(TEST)
V
SG
–
+
LTC3894
19
Rev. A
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resistance θJA(DIODE) given in the data sheet is typical and
can be highly layout dependent. It is therefore impor-
tant to make sure that the Schottky diode has adequate
heatsinking.
TJ≅PDIODE • TA
+θJ A(DIODE)
PDIODE ≅IF( AVG) • VF(IOUT,TJ )
The Schottky diode forward voltage is a function of both
IOUT and TJ, so several iterations may be required to
satisfy both equations. The Schottky forward voltage VF
should be taken from the Schottky diode data sheet curve
showing Instantaneous Forward Voltage. The forward
voltage will decrease as a function of TJ and increase as
a function of I
F
. The nominal forward voltage will also tend
to increase as the reverse breakdown voltage increases.
It is therefore advantageous to select a Schottky diode
appropriate to the input voltage requirements.
CIN and COUT Selection
The input capacitance CIN is required to filter the square
wave current through the P-channel MOSFET. Use a low
ESR capacitor sized to handle the maximum RMS current.
ICIN(RMS) ≅IOUT(MAX)•VOUT
V
IN
•VIN
V
OUT
–1
The formula has a maximum at VIN = 2VOUT, where
ICIN(RMS) = IOUT(MAX)/2. This simple worst-case condition
is commonly used for design because even significant
deviations do not offer much relief. Note that ripple cur-
rent ratings from capacitor manufacturers are often based
on only 2000 hours of life, which makes it advisable to
derate the capacitor.
The selection of COUT is primarily determined by the ESR
required to minimize voltage ripple and load step tran-
sients. The ∆VOUT is approximately bounded by:
ΔVOUT ≤ ΔILESR+1
8 • f •COUT
⎛
⎝
⎜
⎞
⎠
⎟
Since ∆IL increases with input voltage, the output ripple
is highest at maximum input voltage. Typically, once the
ESR requirement is satisfied, the capacitance is adequate
for filtering and has the necessary RMS current rating.
Multiple capacitors placed in parallel may be needed to
meet the ESR and RMS current handling requirements.
Dry tantalum, specialty polymer, aluminum electrolytic
and ceramic capacitors are all available in surface mount
packages. Specialty polymer capacitors offer very low
ESR but have lower specific capacitance than other types.
Tantalum capacitors have the highest specific capacitance,
but it is important to only use types that have been surge
tested for use in switching power supplies. Aluminum
electrolytic capacitors have significantly higher ESR, but
can be used in cost-sensitive applications provided that
consideration is given to ripple current ratings and long-
term reliability. Ceramic capacitors have excellent low ESR
characteristics but can have a high voltage coefficient and
audible piezoelectric effects.
The high Q of ceramic capacitors with trace inductance
can also lead to significant ringing. When used as input
capacitors, care must be taken to ensure that ringing from
inrush currents and switching does not pose an overvolt-
age hazard to the power switch and controller. To dampen
input voltage transients, add a small 5μF to 40μF alumi-
num electrolytic capacitor with an ESR in the range of
0.5Ω to 2Ω. High performance through-hole capacitors
may also be used, but an additional ceramic capacitor
in parallel is recommended to reduce the effect of lead
inductance.
Discontinuous and Continuous Operation
The LTC3894 operates in discontinuous conduction
(DCM) until the load current is high enough for the induc-
tor current to be positive at the end of the switching cycle.
The output load current at the continuous/discontinuous
boundary IOUT(CDB) is given by the following equation:
IOUT(CDB) ≅
(V
IN
– V
OUT
)( V
OUT
+V
F
)
2• L • f •(V
IN
+V
F
)
The continuous/discontinuous boundary is inversely
proportional to the inductor value. Therefore, if required,
I
OUT(CDB)
can be reduced by increasing the inductor value.
LTC3894
20
Rev. A
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RUN Pin and VIN Overvoltage/Undervoltage Lockout
The LTC3894 is enabled using the RUN pin. It has a rising
threshold of 1.24V with 100mV of hysteresis. Pulling the
RUN pin below 1.12V shuts down the main control loop.
Pulling it below 0.8V disables the controller and most
internal circuits. In this state the LTC3894 draws only 7μA
of quiescent current.
The RUN pin is high impedance and must be externally
pulled up/down or driven directly by logic. The RUN pin
can tolerate up to 150V (absolute maximum), so it can be
conveniently tied to VIN in always-on applications where
the controller is enabled continuously and never shut
down.
The RUN and OVLO pins can alternatively be configured as
adjustable undervoltage (UVLO) and overvoltage (OVLO)
lockouts on the V
IN
supply with a resistor divider from V
IN
to ground. A simple resistor divider can be used as shown
in Figure6 to meet specific VIN voltage requirements.
The current that flows through the R3-R4-R5 divider will
directly add to the shutdown, sleep, and active current
of the LTC3894, and care should be taken to minimize
the impact of this current on the overall efficiency of the
application circuit. Resistor values in the megaohm range
may be required to keep the impact on quiescent shut-
down and sleep currents low. To pick resistor values, the
sum total of R3 + R4 + R5 (RTOTAL) should be chosen
first based on the allowable DC current that can be drawn
from VIN.
The individual values of R3, R4 and R5 can be calculated
from the following equations:
R5 =RTOTAL •
0.8V
RISING VIN OVLO THRESHOLD
R4 =RTOTAL •1.24V
RISING VIN UVLO THRESHOLD –R5
R3 =RTOTAL –R5–R4
For applications that do not require an OVLO, the OVLO
pin can be tied directly to ground. The RUN pin in this type
of application can be used as an external UVLO using the
previous equations with R5 = 0Ω.
Similarly, for applications that do not require an adjustable
UVLO, the RUN pin can be tied to VIN. In this configura-
tion, the UVLO threshold is limited to the internal VIN-CAP
UVLO thresholds (VUVLO) as shown in the Electrical
Characteristics table. The resistor values for the OVLO can
be computed using the previous equations with R3 = 0Ω.
PGOOD Programming in Dropout Applications
(PGUV Pin)
The PGUV or Power Good Undervoltage pin is included
to give greater flexibility in defining a normal range of
operating V
OUT
for the LTC3894. In a conventional DC/DC
controller, the OV and UV comparators monitor the VFB pin
and define a fixed ± power good window about a regula-
tion point for VOUT. In the LTC3894, the OV comparator
monitors the VFB pin and the UV comparator monitors the
PGUV pin. For a typical application that does not operate
in dropout, the PGUV pin can be tied to the VFB pin to
establish a conventional ±10% PGOOD window around
the regulation point, outside of which VOUT enters UV
and OV condition respectively. Because the LTC3894 is a
100% duty cycle controller, it can be used in applications
where dropout or operating VOUT below regulation is part
of normal operation. For those applications, the PGUV
pin can be used to establish a lower limit for PGOOD
independent of the VFB pin.
A good example of defining power good in both regulation
and dropout is a 12V battery output preregulator with a
wide ranging VIN and VOUT regulation point set at 12V. If
the defined operating output range is 12V to 9V a conven-
tional power good cannot be used because 9V is under the
VFB UV threshold (12V – 10% or 10.8V). In this example,
the PGOOD window is defined between 10% above 12V
RUN
3894 F06
R3
V
IN
LTC3894
R4
R5
OVLO
Figure6. Adjustable UV and OV Lockout
LTC3894
21
Rev. A
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Figure7. Programmable Power Good UV
LTC3894
PGUV
V
OUT
RUV2
RUV1
3894 F07
APPLICATIONS INFORMATION
and 10% below 9V. The Output Voltage OV (VOUTOV) is
13.2V and Output Voltage UV (VOUTUV) is 8.1V.
To set PGUV to trigger at 9V minus 10% or 8.1V use a
resistor divider as seen in Figure7. The resistors RUV1
and RUV2 set the divided output to the PGUV pin. VOUTUV
is defined as the voltage where the divided output on the
PGUV pin is 0.72V (0.8V – 10%). The resistor divider may
be calculated as follows:
RUV(1,2) is chosen based on IQ current requirements.
RUV(1,2) =RUV1 +RUV2 =Assume 500k
RUV1 =RUV(1,2) •0.72V
VOUTUV
RUV1 =500k • 0.72V
8.1 =44k
RUV2 =RUV(1,2) – RUV1 =500k – 44k =456k
, use 453k
To reduce IQ and component counts, the above resistor
divider can be combined with the feedback resistors as
shown here and in Figure13.
Figure8.
PGUV
3894 F08
RFB3
LTC3894 RFB2
RFB1
VFB
VOUT
With the following design specifications:
VOUT(REGULATION) = 60V, VOUTUV = 42V and choose
RFB3=1MΩ,
RFB1 and RFB2 can be calculated as follows:
RFB1 =
0.8V • V
OUTUV
•R
FB3
V
OUT REGULATION
( )
• VOUTUV – 0.72V
( )
=13.6k
Select RFB1 to be the 1% standard value of 13.7k.
RFB2 =
0.72V •R
FB3
V
OUTUV
– 0.72V –RFB1 =3.8k, use 3.74k
The final selection of RFB3=1MΩ, RFB2=13.7k and
RFB1=3.74k results in VOUT(REGULATION)=59.4V and
VOUTUV=42V.
External N-Channel MOSFET Bias Path for the Gate
Driver (DRVUV/EXTG Pin and EXTS Pin)
The LTC3894 has an internal LDO to regulate the gate
driver bias voltage (V
IN
-CAP) to a nominal 8V and provide
the gate drive current. The amount of the gate current
depends on the external P-channel MOSFET gate capaci-
tance and switching frequency. Charging and discharging
the gate of the external P-channel MOSFET will result in an
effective gate drive current and power loss inside the chip.
For applications where a large gate drive current and
high VIN generate excessively high internal power dis-
sipation, the LTC3894 offers an option to bypass the
internal LDO with an external N-channel MOSFET. This
option will move the power dissipation off chip and lower
the internal chip temperature. To effectively keep the chip
and board temperature low, sufficient heat sink is required
for the N-channel MOSFET. The connections for the
N-channel MOSFET are shown in the Functional Diagram
on page 10. Connecting the N-channel MOSFET auto-
matically select the UVLO threshold of 6V. External buf-
fer resistor R
EXTG
(1k) and ceramic bypass capacitors
C
EXTS
and C
EXTG
(0.1µF each, 20V rated) are required and
need to be placed as close as practical to the N-channel
MOSFET source terminal and EXTG pin respectively to
ensure stable operation.
LTC3894
22
Rev. A
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External N-Channel MOSFET Selection
When selecting an external NMOS device for the external
gate driver charge path, threshold VGS(TH) ,maximum VDS
rating, and maximum power rating need to be considered
for the maximum V
IN
used in an application . A NMOS with
VGS(TH) less than 5V should be used. During operation,
the maximum continuous voltage drop across the external
N-channel MOSFET VDS can be calculated as:
VDS(EXT.NMOS) = VIN – 8V
The average current flowing through the NMOS can be
calculated as:
IAVG_NMOS = QG(ext. PFET) • f
where QG(ext. PFET) is the total Gate charge needed to turn
on the external PFET in a switching cycle, f is the switch-
ing frequency.
Total power dissipation in the N-channel MOSFET is:
P
NMOS
= V
DS(EXT.NMOS)
• I
AVG_NMOS
= (V
IN
– 8V) •
QG(ext. PFET) • f
As it can be seen, the maximum power dissipation occurs
at maximum VIN of 150V.
For example , in an application where VIN = 150V,
QG(ext. PFET) = 30nC, f = 350kHz, PNMOS = 142V • 30nC •
350kHz = 142V • 10.5mA = 1.49W
Sufficient heat sink is needed to remove the heat
generated.
External Soft-Start and Output Tracking
Start-up characteristics are controlled by the voltage on
the TRACK/SS pin. When the voltage on the TRACK/SS
pin is less than the internal 0.8V reference, the LTC3894
regulates the VFB pin voltage to the voltage on the TRACK/
SS pin. When the TRACK/SS pin is greater than the inter-
nal 0.8V reference, the VFB pin voltage regulates to the
0.8V internal reference. The TRACK/SS pin can be used to
program an external soft-start function or to allow VOUT
to track another supply during start-up.
Soft-start is enabled by connecting a capacitor from the
TRACK/SS pin to ground. An internal 10µA current source
charges the capacitor, providing a linear ramping voltage
at the TRACK/SS pin that causes VOUT to rise smoothly
from 0V to its final regulated value. The total soft-start
time will be approximately:
tSS =CSS •0.8V
10µA
When the LTC3894 is configured to track another supply, a
voltage divider can be used from the tracking supply to the
TRACK/SS pin to scale the ramp rate appropriately. Two
common implementations of tracking as shown in Figure9a
are coincident and ratiometric. For coincident tracking,
make the divider ratio from the external supply the same
as the divider ratio for the feedback voltage. Ratiometric
tracking could be achieved by using a different ratio than
the feedback (Figure9b).
Note that the constant TRACK/SS pin current produces a
small offset error to the resistive divider tracking. Account
for the error or minimize it by selecting small tracking
resistor values.
LTC3894
23
Rev. A
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Short-Circuit Faults: Current Limit and Foldback
In the LTC3894, the maximum inductor current is inher-
ently limited by the current mode controller by the maxi-
mum current sense threshold voltage VSENSE(MAX).
LTC3894 also includes current foldback to help limit load
current when the output is shorted to ground. When the
output feedback VFB voltage is less than 72% of the 0.8V
internal reference (560mV), and PGUV is less than 0.72V,
current limiting foldback is activated. The current limit will
continue to drop as VFB drops until reaching a minimum
foldback current of about 36% of the the full operational
current limit.
Figure9(a). Two Different Modes of Output Tracking
TIME
Coincident Tracking
EXTERNAL
SUPPLY
EXTERNAL
SUPPLY
VOUT
VOLTAGE
VOUT
TIME 3894 F08a
Ratiometric Tracking
VOLTAGE
Figure 9(b): Setup for Ratiometric and Coincident Tracking
RFB2
EXT. V
RFB1
Coincident Tracking Setup
TRACK/SS
RFB2
V
OUT
TO VFB
RFB1
R1
EXT. V
R2
R1+ R2 ≥
R2
TRACK/SS
RFB2
V
OUT
TO V
FB
RFB1
3894 F08b
Ratiometric Tracking Setup
0.8V
EXT. V
Under short-circuit conditions with very low duty cycles,
cycle skipping will begin in order to limit the short-circuit
current, thus preventing current limit runaway. In this
situation, the power Schottky diode will be dissipating
most of the power that is considerably reduced by the
current limit foldback. The short-circuit ripple current is
determined by the minimum on-time, tON(MIN), the input
voltage and inductor value:
ΔIL(SC)=tON(MIN)
V
IN
L
⎛
⎝
⎜⎞
⎠
⎟
The resulting average short-circuit current is:
ISC =45%•ILIM(MAX) –
1
2
ΔIL(SC)
LTC3894
24
Rev. A
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Short-Circuit Recovery and Internal Soft-Start
An internal soft-start feature guarantees a maximum posi-
tive output voltage slew rate in all operational cases. In a
short-circuit recovery condition for example, the output
recovery rate is limited by the internal soft-start so that
output voltage overshoot and excessive inductor current
buildup is prevented.
The internal soft-start voltage and the external TRACK/SS
pin operate independently. The output will track the lower
of the two voltages. The slew rate of the internal soft-start
voltage is roughly 0.6V/ms, which translates to a total
soft-start time of 1.3ms. If the slew rate of the TRACK/SS
pin is greater than 0.6V/ms the output will track the inter-
nal soft-start ramp. To assure robust fault recovery, the
internal soft-start feature is active in all operational cases.
If a short-circuit condition occurs which causes the output
to drop significantly, the internal soft-start will assure a
soft recovery when the fault condition is removed.
The internal soft-start assures a clean soft ramp-up from
any fault condition that causes the output to droop, guar-
anteeing a maximum ramp rate in soft-start, short-circuit
fault release, or output recovery from drop out. Figure10
illustrates how internal soft-start controls the output
ramp-up rate under varying scenarios.
Fault Conditions: Overtemperature Protection
At higher temperatures, or in cases where the internal
power dissipation causes excessive self heating on chip,
the overtemperature shutdown circuitry will shut down
the LTC3894. When the junction temperature exceeds
approximately 180°C, the overtemperature circuitry shuts
down most of the LTC3894 chip including the external
P-channel MOSFET and discharges TRACK/SS to ground.
Once the junction temperature drops back to the approxi
-
mately 165°C, the chip turns back on and restarts with a
soft-start ramp. Long term overstress (T
J
> 125°C) should
be avoided as it can degrade the performance or shorten
the life of the part.
UVLO Selection (DRVUV/EXTG Pin)
The DRVUV/EXTG pin can be used to select one of the
two Undervoltage Lockout thresholds (UVLO) for the Gate
drive bias voltage(VIN-CAP). When the pin is grounded,
the gate drive UVLO threshold is set to 3.75V. When
DRVUV/EXTG is floated, the UVLO is set to 6V.
Table2 summarizes the values of UVLO threshold selected
for different EXTG and EXTS pin configurations. Note that
when the external N-channel MOSFET is used, the 6V
UVLO is selected by default.
Table2
TYPICAL UVLO
RISING THRESHOLD
EXT
NMOS DRVUV/EXTG EXTS
3.75V No GND GND
6V No FLOAT GND
6V Yes* Connected to
External N-Channel
MOSFET GATE
Connected to
External N-Channel
MOSFET SOURCE
*(Connect the external N-channel MOSFET drain to the CAP pin.)
Figure10. Internal Soft-Start (a) Allows Soft Start-Up without
an External Soft-Start Capacitor and Allows Soft Recovery from
(b) a Short-Circuit or (c) a VIN Dropout
TIME~ 650µs
(a)
VOUT
VIN
VOLTAGE
3894 F09
INTERNAL SOFT-START INDUCED START-UP
(NO EXTERNAL SOFT-START CAPACITOR)
TIME
SHORT-CIRCUIT
(b)
VOUT
VOLTAGE
INTERNAL SOFT-START
INDUCED RECOVERY
INTERNAL SOFT-START
INDUCED RECOVERY
TIME
(c)
VOUT
VIN
VIN
DROPOUT
VIN
VOUT
VOLTAGE
LTC3894
25
Rev. A
For more information www.analog.com
APPLICATIONS INFORMATION
VIN Undervoltage Lockout (UVLO)
With the user selectable UVLO threshold, The LTC3894 is
designed to accommodate applications requiring widely
varying input voltages from 4.5V to 150V.
There is a built-in hysteresis between UVLO rising and
UVLO falling thresholds and its implication must be care-
fully considered in low VIN operation. When DRVUV/EXTG
pin is grounded, the nominal UVLO threshold with VIN ris-
ing is 3.75V and the nominal UVLO falling is 3.5V. For the
low UVLO threshold selection, the operating input voltage
range of the LTC3894 is guaranteed to be 3.75V to 150V
over temperature, but the initial VIN ramp must exceed
3.75V to guarantee a start-up. When the DRVUV/EXTG
pin is greater than 300mV, the nominal UVLO thresh-
old rising is 6V and nominal UVLO falling is 5.55V. For
this high UVLO threshold selection, the operating input
voltage range of the LTC3894 is guaranteed to be 5.55V
to 150V over temperature, but the initial VIN ramp must
exceed 6V to guarantee a start-up.
An automotive battery droops during a cold crank con-
dition. The typical automotive battery voltage is 12V to
14.4V, which has more than enough headroom for the
LTC3894 to start up. Onboard electronics which are pow-
ered by a DC/DC regulator require a minimum supply volt-
age for seamless operation during the cold crank condi-
tion, and the battery may droop close to these minimum
supply requirements during a cold crank. The DC/DC
regulator should not exacerbate the situation by having
excessive voltage drop between the already suppressed
battery voltage input and the output of the regulator
which powers these electronics. As seen in Figure11, the
LTC3894’s 100% duty cycle capability allows low dropout
from the battery to the output. The drop from VIN to VOUT
is determined by the output Load current multiplied by the
total series resistance in dropout mode. The guaranteed
UVLO falling thresholds of 3.5V and 5.55V assure suf-
ficient margin for continuous, uninterrupted operation in
extreme cold crank battery drooping conditions. However,
additional input capacitance or slower soft-start time may
be required at low VIN in order to limit VIN droop caused
by inrush currents, especially if the input source has a
sufficiently large output impedance.
Minimum On-Time Considerations
The minimum on-time, tON(MIN), is the smallest time
duration that the LTC3894 is capable of turning on an
external P-channel MOSFET, and is typically 125ns. It is
determined by internal timing delays and the gate charge
required to turn on the MOSFET. Low-duty-cycle applica-
tions may approach this minimum on-time limit, so care
should be taken to ensure that:
tON(MIN) <VOUT
VIN(MAX) • f
If the duty cycle falls below what can be accommodated
by the minimum on-time, the controller will skip cycles.
However, the output voltage will continue to regulate, but
the voltage and current ripple will increase.
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
the dominant contributors and therefore where efficiency
improvements can be made. Percent efficiency can be
expressed as:
% Efficiency = 100% – (L1+L2+L3+…)
where L1, L2, L3, etc., are the individual losses as a per-
centage of input power.
Figure11. Typical Automotive Cold Crank
3894 F10
TIME
VOUT
VBATTERY
12V
LTC3894’s 100% DUTY CYCLE CAPABILITY ALLOWS
VOUT TO RIDE VIN WITHOUT SIGNIFICANT DROP-OUT
5V
VOLTAGE
LTC3894
26
Rev. A
For more information www.analog.com
APPLICATIONS INFORMATION
Although all dissipative elements in the circuit produce
losses, four main sources account for most of the losses
in LTC3894 application circuits.
1. I2R Loss: I2R losses result from the P-channel MOSFET
resistance, inductor resistance, the current sense resis-
tor, and input and output capacitor ESR. In continu-
ous mode operation the average output current flows
through L but is chopped between the P-channel
MOSFET and the bottom side Schottky diode. The fol-
lowing equation may be used to determine the total I
2
R
loss:
P
L2R≈I2OUT +ΔI2L
12
⎛
⎝
⎜⎞
⎠
⎟•
RDCR
+
RSENSE
+
D•
RDS(ON) +RESR(CIN)
( )
⎡
⎣
⎢
⎢
⎤
⎦
⎥
⎥
+
ΔI2L
12
•RESR(COUT)
2. Transition Loss: Transition loss of the P-channel
MOSFET becomes significant only when operating
at high input voltages (typically 20V or greater.) The
P-channel transition losses (PPMOSTRL) can be deter-
mined from the following equation:
P
PMOSTRL =VIN2•IOUT
2
⎛
⎝
⎜⎞
⎠
⎟• CMILLER
( )
•
RDN
VIN −VCAP
( )
– VMILLER
+RUP
VMILLER
⎡
⎣
⎢⎤
⎦
⎥• f
3. Gate Charging Loss: Charging and discharging the gate
of the MOSFET will result in an effective gate charg-
ing current. Each time the P-channel MOSFET gate is
switched from low to high and low again, a packet of
charge dQ moves from the capacitor across VIN-VCAP
and is then replenished from VIN by the internal VCAP
regulator. The resulting dQ/dt current is a current out
of VIN flowing to ground. The total power loss in the
controller including gate charging loss is determined
by the following equation:
P
CNTRL
=V
IN
•(I
Q
+f •Q
G(PMOSFET)
)
4. Schottky Loss: The Schottky diode loss is most signifi-
cant at low duty factors (high step down ratios). The
critical component is the Schottky forward voltage as
a function of junction temperature and current. The
Schottky power loss is given by the following equation.
P
DIODE
≅(1–D)•I
OUT
• V
F(IOUT,TJ)
When making adjustments to improve efficiency, the input
current is the best indicator of changes in efficiency. If
changes cause the input current to decrease, then the
efficiency has increased. If there is no change in input
current, there is no change in efficiency.
OPTI-LOOP
®
Compensation
OPTI-LOOP compensation, through the availability of
the ITH pin, allows the transient response to be opti-
mized for a wide range of loads and output capacitors.
The ITH pin not only allows optimization of the control
loop behavior but also provides a test point for the step-
down regulator ’s DC-coupled and AC-filtered closed-loop
response. The DC step, rise time and settling at this test
point truly reflects the closed-loop response. Assuming a
predominantly second order system, phase margin and/
or damping factor can be estimated using the percentage
of overshoot seen at this pin. The bandwidth can also be
estimated by examining the rise time at this pin.
The ITH series RITH-CITH1 filter sets the dominant pole-
zero loop compensation. Additionally, a small capacitor
placed from the ITH pin to signal ground, CITH2, may be
required to attenuate high frequency noise. The values can
be modified to optimize transient response once the final
PCB layout is done and the particular output capacitor
type and value have been determined. The output capaci-
tors need to be selected because their various types and
values determine the loop feedback factor gain and phase.
An output current pulse of 20% to 100% of full load cur-
rent having a rise time of 1μs to 10μs will produce output
voltage and ITH pin waveforms that will give a sense of
the overall loop stability without breaking the feedback
loop. The general goal of OPTI-LOOP compensation is to
realize a fast but stable ITH response with minimal output
LTC3894
27
Rev. A
For more information www.analog.com
APPLICATIONS INFORMATION
droop due to the load step. For a detailed explanation of
OPTI-LOOP compensation, refer to Application Note 76.
Switching regulators take several cycles to respond to a
step in load current. When a load step occurs, V
OUT
imme-
diately shifts by an amount equal to ∆ILOAD • ESR, where
ESR is the effective series resistance of C
OUT
. ∆I
LOAD
also
begins to charge or discharge COUT
, generating a feed-
back error signal used by the regulator to return VOUT to
its steady-state value. During this recovery time, VOUT can
be monitored for overshoot or ringing that would indicate
a stability problem.
Connecting a resistive load in series with a power MOSFET,
then placing the two directly across the output capacitor
and driving the gate with an appropriate signal generator
is a practical way to produce a realistic load-step condi-
tion. The initial output voltage step resulting from the step
change in output current may not be within the bandwidth
of the feedback loop, so this signal cannot be used to
determine phase margin. This is why it is better to look
at the ITH pin signal which is in the feedback loop and
is the filtered and compensated feedback loop response.
The gain of the loop increases with RITH and the band-
width of the loop increases with decreasing CITH1. If RITH
is increased by the same factor that CITH1 is decreased,
the zero frequency will be kept the same, thereby keeping
the phase the same in the most critical frequency range
of the feedback loop. In addition, a feedforward capaci-
tor, CFF
, can be added to improve the high frequency
response, as shown in Figure1. Capacitor CFF provides
phase lead by creating a high frequency zero with RFB2
which improves the phase margin. The output voltage set-
tling behavior is related to the stability of the closed-loop
system and will demonstrate overall performance of the
step-down regulator.
In some applications, a more severe transient can be
caused by switching in loads with large (>10μF) input
capacitors. If the switch connecting the load has low
resistance and is driven quickly, then the discharged
input capacitors are effectively put in parallel with COUT
,
causing a rapid drop in VOUT
. No regulator can deliver
enough current to prevent this problem. The solution is
to limit the turn-on speed of the load switch driver. A hot
swap controller is designed specifically for this purpose
and usually incorporates current limiting, short-circuit
protection and soft starting.
Design Example
Consider a step-down regulator with the following speci-
fications (Figure12):
VIN=6V to 150V, VOUT=5V, IOUT(MAX)=3A, and
f=200kHz
The output voltage is programmed according to:
RFB2 =RFB1 •VOUT
0.8V • –1
⎛
⎝
⎜⎞
⎠
⎟
Select a 1% standard value resistor RFB1=80.6k, then
calculate and choose RFB2=422k.
A 36.5kΩ between the FREQ pin and signal ground pro-
grams the switching frequency to 200kHz. The smallest
on-time Ton occurs at 150V VIN and can be calculated as:
TON =
5V
200kHz •150V
≈182ns
This on-time TON is larger than LTC3894’s minimum
on-time of 125ns with sufficient margin to prevent cycle
skipping.
Next, set the inductor value to give 37% worst case ripple
at maximum VIN=150V:
L=5V
0.37 •3A • 200kHz 1– 5V
150V
⎛
⎝
⎜⎞
⎠
⎟≈21.7µH
Select a standard inductor of 22μH.
The resulting maximum inductor ripple current is:
∆IL=5V
22µH•200kHz 1– 5V
150V
⎛
⎝
⎜⎞
⎠
⎟≈1.1A
Next, set the R
SENSE
resistor value to ensure that the con-
verter can deliver the maximum load current of 3A with
sufficient margin to account for component variations and
worst-case operating conditions. Using a 20% margin
LTC3894
28
Rev. A
For more information www.analog.com
APPLICATIONS INFORMATION
factor and the minimum value for the maximum current
sense threshold (88mV), RSENSE can be calculated to be:
RSENSE =
88mV
1.2• 3A +1.1A
2
⎛
⎝⎞
⎠
=20.6mΩ
Select RSENSE to be the standard value of 20mΩ with
sufficient power rating.
The maximum value of the peak inductor current limit can
be calculated using the maximum value for the maximum
current sense threshold (112mV):
IL PEAK
( )
=
112mV
20mΩ
=5.6
A
Choose an inductor that has rated saturation current
higher than 5.6A with sufficient margin.
The nominal output current limit can be calculated as:
ILIMIT =
100mV
20mΩ
–
1.1A
2
=4.45A
Next choose a P-channel MOSFET with the appropriate
BVDSS and ID rating. In this example, a good choice is
the FAIRCHILD FDMS86263P (BV
DSS
=150V, I
D
=–4.4A,
RDS(ON)=45mΩ, θJA=50°C/W, ρT=1.4 at 75°C). The
power dissipation on the P-MOSFET can be estimated for
VIN of 150V with T (estimated)=75°C as follows:
PPMOS =
5V
150V • 3A
( )
2•1.4 • 4.5mΩ+150V
( )
2•
3A
2
•0.9Ω
8V – 3.9V +2Ω
3.9V
⎛
⎝
⎜⎞
⎠
⎟•90pF •200kHz
≈18.9mW +445mW
=464mW
Next choose an appropriate Schottky diode that will han-
dle the power requirements. The Diodes Inc. PDS4150
Schottky diode is selected (VF(4A,125°C)=0.57V,
VR=150V, θJA=90°C/W) for this application. The power
dissipation at full load=3A can be calculated as:
PDIODE =3A • 1– 5V
150V
⎛
⎝
⎜⎞
⎠
⎟•0.57V =1.65W
These power dissipation calculations show that careful
attention to heat sinking will be necessary.
An output short-circuit to ground will result in an output
current limit foldback of:
ISC =36mV
20mV –1
2
125ns –150V
22µH
⎛
⎝
⎜⎞
⎠
⎟=1.37A
The resulting power dissipated in the Schottky diode is:
PDIODE≈1.37A•0.57V=0.78W
The power dissipated in Schottky diode in short circuit
foldback is less than when under full-load conditions.
Choose low ESR ceramic capacitors as the input bypass
capacitors that can handle the maximum RMS current of
1.5A over temperature. C
OUT
is chosen with an ESR of
0.02Ω for low output ripple. The output ripple in continu-
ous mode will be highest at the maximum input voltage.
The output voltage ripple due to ESR is approximately:
VORIPPLE=RESR • ∆IL=0.02Ω•1.1A=22mVP-P
A soft-start time of 8ms can be programmed through a
0.1μF capacitor on the SS pin:
CSS =
8ms•10µA
0.8V
=0.1µF
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3894.
1. Multilayer boards with dedicated ground layers are
preferable for reduced noise and for heat sinking pur-
poses. Use wide rails and/or entire planes for VIN, VOUT
and GND for good filtering and minimal copper loss. If
a ground layer is used, then it should be immediately
below (and/or above) the routing layer for the power
train components which consist of C
IN
, sense resis-
tor, P-MOSFET, Schottky diode, inductor, and COUT.
Flood unused areas of all layers with copper for better
heatsinking.
LTC3894
29
Rev. A
For more information www.analog.com
APPLICATIONS INFORMATION
2. Keep signal and power grounds separate except at the
point where they are shorted together. Short signal and
power ground together only at a single point with a nar-
row PCB trace (or single via in a multilayer board). All
power train components should be referenced to power
ground and all small signal components (e.g., CITH1,
RFB1, RFB2, RFREQ, CSS etc.) should be referenced to
signal ground.
3. Place CIN, CCAP, the Schottky diode, the P-channel
MOSFET, inductor, and primary COUT capacitors close
together in one compact area. The junction connecting
the drain of P-MOSFET, cathode of Schottky, and (+)
terminal of inductor (this junction is commonly referred
to as the switch or phase node) should be compact but
large enough to handle the inductor currents without
large copper losses. Place the source of P-channel
MOSFET as close as possible to the (+) plate of CIN
capacitor(s) that provides the bulk of the AC current
(these are normally the ceramic capacitors), and connect
the anode of the Schottky diode as close as possible to
the (–) terminal of the same CIN capacitor(s). The high
dI/dt loop formed by CIN, the MOSFET, and the Schottky
diode should have short leads and PCB trace lengths to
minimize high frequency EMI and voltage stress from
inductive ringing. The (–) terminal of the primary COUT
capacitor(s) which filters the bulk of the inductor ripple
current (these are normally the ceramic capacitors)
should also be connected close to the (–) terminal of
CIN.
4. Keep high dV/dt signals on the GATE and the switch
nodes away from sensitive small signal traces and
components. All of these nodes have very large and
fast moving signals and therefore should be kept on
the output side of the LTC3894 and occupy minimum
PC trace area.
5. The SENSE– and SENSE+ leads should be routed
together as a differential pair with minimum PC trace
spacing. The optional filter capacitor between SENSE+
and SENSE– should be as close as possible to the IC.
Ensure accurate current sensing with Kelvin connec-
tions at the SENSE resistor. DCR sensing resistor R1
should be placed close to the switch node. Current
through the SENSE
–
trace can be 1mA or higher and IR
drop along the trace can adversely affect current sens-
ing accuracy. Care must be taken to reduce SENSE–
board trace impedance.
6. Place the resistive feedback divider RFB1/2 as close as
possible to the VFB pin and connect it between the (+)
terminal of COUT or the output regulation point and
signal ground. The divider shall not share a common
path with SENSE
–
connection and should be away from
any noisy power train path and components.
7. Place the ceramic CCAP capacitor as close as possible
to VIN and CAP pins. This capacitor provides the gate
charging current for the power P-channel MOSFET.
8. Place small signal components as close to their respec-
tive pins as possible. This minimizes the possibility of
PCB noise coupling into these pins. Give priority to
VFB, ITH, and FREQ pins. Use sufficient isolation when
routing a clock signal into PLLIN /MODE pin so that the
clock does not couple into sensitive small signal pins.
9. Minimize the length of board connection between the
Gate pin and gate terminal of the external P-channel
MOSFET and the connection between the CAP pin and
the drain terminal of the external N-channel MOSFET
when it is used.
LTC3894
30
Rev. A
For more information www.analog.com
TYPICAL APPLICATIONS
Efficiency vs Load Current Power Loss vs Load Current
V
IN
= 12V
V
IN
= 24V
V
IN
= 48V
V
IN
= 100V
V
IN
= 150V
LOAD CURRENT (A)
0.0001
0.001
0.01
0.1
1
3
0
10
20
30
40
50
60
70
80
90
100
EFFICIENCY (%)
3894 TA02b
Burst Mode OPERATION
V
IN
= 12V
V
IN
= 24V
V
IN
= 48V
V
IN
= 100V
V
IN
= 150V
LOAD CURRENT (A)
0.0001
0.001
0.01
0.1
1
3
0.1
1
10
100
1k
10k
POWER LOSS (mW)
3894 TA02c
Burst Mode OPERATION
GATE
LTC3894
PGOOD
CIN2
0.22µF
200V
×2
CIN1
12µF
160V
×2
VIN
6V TO 150V
VOUT
5V
3A
SENSE+
RSENSE
20mΩ
L1
22µH
D1
MP1
SENSE–
VIN
+
COUT1
10µF
50V
×2
COUT2
330µF
6.3V
RPG
100k
RFB2
422k
+
RFB1
80.6k
RFREQ
36.5k
PLLIN/MODE
CSS1
0.1µF
TRACK/SSGND FREQ
VFB
PGUV
RUN
EXTS
DRVUV/EXTG
ITH
OVLO
CAP
C
VIN1
0.1µF
200V
CITH1
3.3nF
CCAP
0.47µF
CITH2
47pF
RITH1
5.76k
3894 TA02a
CSNS
1nF
CVIN1: 0.1µF 200V MURATA GRM31CR72D104KW03L
CCAP: 0.47µF 16V MURATA GCM188R71C474KA55L
CIN1:12µF 160V ILLINOIS CAPACTOR 126AVG160MGBJ
CIN2: 0.22µF 200V MURATA GRM32DR72D224KW01
RSENSE : 20mΩ SUSUMU KRL3216E-M-R020-F-T1
L1: 22µH WURTH ELEKTRONIK 7447709220 OR 7447704220
MP1: FAIRCHILD FDMS86263P
D1: DIODES PDS4150
COUT2: 330µF 6.3V AVS TPSD337M006R0050
COUT1: 10µF 50V MURATA GRM31CR61H106MA12L
Figure12. High Efficiency 150V to 5V/3A, 200kHz Step-Down Regulator
LTC3894
31
Rev. A
For more information www.analog.com
Efficiency and Power Loss vs Load Current
PULSE–SKIPPING MODE
LOAD CURRENT (A)
0.0001
0.001
0.01
0.1
1
3
0
10
20
30
40
50
60
70
80
90
100
0.1
1
10
EFFICIENCY (%)
POWER LOSS (mW)
3894 TA03b
VIN = 75V
VOUT = 60V
EFFICIENCY
POWER LOSS
GATE
LTC3894
PGOOD
CIN2
1µF
250V
×3
CIN1
12µF
160V
×2
VIN
30V TO 120V*
VOUT
60V**
2A
SENSE+
RSENSE
33mΩ
L1
68µH
D1
MP1
SENSE–
VIN
+
COUT1
4.7µF
100V
×3
COUT2
100µF
63V
RPG
100k
RFB3
1M
+
RSP
10Ω
RFB1
13.7k
RFB2
3.74k
RFREQ
64.9k
ROV2
33.2k
ROV3
953k
ROV1
6.65k
PLLIN/MODE
CSS1
0.1µF
TRACK/SSGND FREQ
VFB
PGUV
RUN
EXTS
DRVUV/EXTG
ITH
OVLO
CAP
C
VIN1
0.1µF
CITH1
330pF
CCAP
0.47µF
CITH2
10pF
RITH1
48.7k
3894 TA03a
CSNS
1nF
CIN1: 12µF 160V ILLINOIS CAP 126AVG160MGBJ
CIN2: 1µF 250V TDK CGA8P3X7T2E105KS
COUT1: 4.7µF 100V TDK CGA6M3X7S2A475K
COUT2
: 100µF 63V UNITED CHEMI-CON EMVH630ARA101MKE0S
L1: 60µH WURTH ELEKTRONIK 7447709680
MP1: FAIRCHILD FDMC86259P
D1: ST MICRO STPS10150CG
450kHz
EXTERNAL CLOCK
* SURGES TO 150V, OVLO STOPS SWITCHING WHEN VIN > 120V.
REGULATOR SHUTS DOWN WHEN VIN < 30V.
** VOUT FOLLOWS VIN WHEN VIN < 60V.
PGOOD UNDERVOLTAGE = 42V
Figure13. High Efficiency 120V Input to 60V Step-Down Regulator with Surge Protection to 150V
TYPICAL APPLICATIONS
LTC3894
32
Rev. A
For more information www.analog.com
Efficiency and Power Loss vs Load Current
LOAD CURRENT (A)
0.0001
0.001
0.01
0.1
1
3
0
10
20
30
40
50
60
70
80
90
100
0.0001
0.001
0.01
0.1
1
10
EFFICIENCY (%)
POWER LOSS (mW)
3894 TA04b
VIN = 28V
VOUT = 3.3V
Burst Mode OPERATION
EFFICIENCY
POWER LOSS
Figure14. 6V to 150V Input, 3.3V/3A Output, 175kHz Step-Down Regulator
CIN1: 12µF 160V ILLINOIS CAP 126AVG160MGBJ
CIN2: 1µF 250V TDK CGA8P3X7T2E105KS
COUT1
: 10µF 50V MURATA GRM31CR61H106MA12L
COUT2: 220µF 6.3V KEMET T520B227M006ATE045
L1: 15µH WURTH ELEKTRONIK 744771115
MP1: FAIRCHILD FDMS86263P
D1: ST MICRO STPS10150CG
GATE
LTC3894
PGOOD
CIN2
1µF
250V
×3
CIN1
12µF
160V
×3
VIN
6V
TO 150V
VOUT
3.3V
3A
SENSE+
L1
15µH
D1
MP1
SENSE–
VIN
+
COUT1
10µF
50V
×2
COUT2
220µF
6.3V
RPG
100k
RFB3
1M
+
RFB1
316k
RFREQ
32.4k
PLLIN/MODE
CSS1
0.1µF
TRACK/SS
GND FREQ
VFB
PGUV
RUN
EXTS
DRVUV/EXTG
ITH
OVLO
CAP
CVIN1
0.1µF
200V
CITH1
4.7nF CITH2
47pF
CCAP
0.47µF
RITH1
7.5k
3894 TA04a
CDCR
47nF
RDCR2
63.4k
RDCR1
16.9k
TYPICAL APPLICATIONS
LTC3894
33
Rev. A
For more information www.analog.com
TYPICAL APPLICATIONS
Efficiency and Power Loss vs Load Current
LOAD CURRENT (A)
0.0001
0.001
0.01
0.1
1
2
0
10
20
30
40
50
60
70
80
90
100
1
10
100
1k
10k
100k
EFFICIENCY (%)
POWER LOSS (mW)
3894 TA05b
VIN = 48V
VOUT = 12V
Burst Mode OPERATION
EFFICIENCY
POWER LOSS
Figure15. 6V to 100V Input, 12V/2A Output, 350kHz Step-Down Regulator
GATE
LTC3894
PGOOD
CIN2
4.7µF
100V
CIN1
100µF
100V
VIN
6V
TO 100V
VOUT
12V**
2A
SENSE+
RSENSE
33mΩ
L1
39µH
D1
MP1
SENSE–
VIN
+
COUT2
22µF
16V
×2
COUT1
330µF
16V
RPG
100k
RFB3
1M
+
RFB1
71.5k
PLLIN/MODE
CSS1
0.1µF
TRACK/SS
GND FREQ
VFB
PGUV
RUN
EXTS
DRVUV/EXTG
ITH
OVLO
CAP
CVIN1
0.1µF
CITH1
150pF
CCAP
0.47µF
CITH2
47pF
CFB2
10pF
RITH1
280k
3894 TA05a
CSNS
1nF
CIN1
: 100µF 100V PANASONIC EEE-FK2A101AM
CIN2: 4.7µF 100V TDK CGA6M3X7S2A475K
COUT1: 330µF 16V AVX TCJE337M016R0050
COUT2: 22µF 16V TDK C3225X5R1C226MT
L1: 39µH WURTH ELEKTRONIK 7447709390
MP1: FAIRCHILD FDMS86163P
D1: VISHAY V12P10
** VOUT FOLLOWS VIN WHEN VIN < 12V
LTC3894
34
Rev. A
For more information www.analog.com
PACKAGE DESCRIPTION
FE20(16) (CB) TSSOP REV 0 0512
0.09 – 0.20
(.0035 – .0079)
0° – 8°
0.25
REF
RECOMMENDED SOLDER PAD LAYOUT
0.50 – 0.75
(.020 – .030)
4.30 – 4.50*
(.169 – .177)
1 3 5678 9 10
111214 13
6.40 – 6.60*
(.252 – .260)
3.86
(.152)
2.74
(.108)
20 18 16 15
1.20
(.047)
MAX
0.05 – 0.15
(.002 – .006)
0.65
(.0256)
BSC
0.195 – 0.30
(.0077 – .0118)
TYP
2.74
(.108)
0.45 ±0.05
0.65 BSC
4.50 ±0.10
6.60
±0.10
1.05 ±0.10
3.86
(.152)
MILLIMETERS
(INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
SEE NOTE 4
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
6.40
(.252)
BSC
FE Package
Variation: FE20(16)
20-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1924 Rev Ø)
Exposed Pad Variation CB
LTC3894
35
Rev. A
For more information www.analog.com
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
A 12/18 Added H-grade information 1–4
LTC3894
36
Rev. A
For more information www.analog.com
ANALOG DEVICES, INC. 2018-2019
D16856-0-07/19(A)
www.analog.com
RELATED PARTS
TYPICAL APPLICATION
Burst Mode OPERATION
EFFICIENCY
V
IN
= 12V
V
IN
= 24V
LOAD CURRENT (mA)
0.0001
0.001
0.01
0.1
1
5
0
10
20
30
40
50
60
70
80
90
100
0.1
1
10
100
1k
10k
EFFICIENCY (%)
POWER LOSS (mW)
3894 TA06b
POWER LOSS
High Efficiency 6V to 80V Input, 5V/3A Output, Step-Down Regulator
+
GATE
LTC3894
PGOOD
COUT2
22µF
CIN2
4.7µF
100V
VIN
6V TO 80V
V
OUT
5V
3A
SENSE+
R
SENSE
22mΩ
L1
15µH
D1
MP1
SENSE–
VIN
COUT1
10µF
50V
×2
+
COUT2
220µF
6.3V
RPG
100k
RFB3
1M
RFB1
187k
PLLIN/MODE
CSS1
0.1µF
TRACK/SSGND FREQ
VFB
PGUV
RUN
EXTS
DRVUV/EXTG
ITH
OVLO
CAP
C
VIN1
0.1µF
CITH1
3.3nF
CITH2
82pF
CCAP
0.47µF
RITH1
7.5k
3894 TA06a
CSNS
820pF
COUT2: 220µF 6.3V KEMET T520B227M006ATE045
L1: 15µH COILCRAFT SER1390-153MLB
MP1: FAIRCHILD FDMS86163P
D1: DIODES INC SBR3U100LP7
RFREQ
60.4k
PART NUMBER DESCRIPTION COMMENTS
LTC3895/
LTC7801
150V Low IQ, Synchronous Step-Down DC/DC Controller with
100% Duty Cycle
4V ≤ VIN ≤ 140V, 150V Abs Max, PLL Fixed Frequency 50kHz to900kHz,
0.8V ≤ VOUT ≤ 60V, Adjustable 5V to 10V Gate Drive, IQ = 40μA,
4mm×5mm QFN-24, TSSOP-24, TSSOP-38(31)
LTC3871 Bidirectional PolyPhase
®
Synchronous Buck or Boost
Controller
VHIGH Up to 100V, VLOW Up to 30V, High Power Buck or Boost on
Demand
LTC3639 High Efficiency, 150V 100mA Synchronous Step-Down
Regulator
Integrated Power MOSFETs, 4V ≤ VIN ≤ 150V, 0.8V ≤ VOUT ≤ VIN,
IQ = 12µA, MSOP-16(12)
LTC3638 High Efficiency, 140V 250mA Synchronous Step-Down
Regulator
Integrated Power MOSFETs, 4V ≤ VIN ≤ 140V, 0.8V ≤ VOUT ≤ VIN,
IQ = 12µA, MSOP-16(12)
LTC7138 High Efficiency, 140V 400mA Synchronous Step-Down
Regulator
Integrated Power MOSFETs, 4V ≤ VIN ≤ 140V, 0.8V ≤ VOUT ≤ VIN,
IQ = 12µA, MSOP-16(12)
LTC7860 High Efficiency Switching Surge Stopper 3.5V ≤ VIN ≤ 60V, Expandable to 200V+, Adjustable VOUT Clamp and
Current Limit, Power Inductor Improves EMI, MSOP-12
LT8631 100V, 1A Synchronous Micropower Step-Down Regulator Integrated Power MOSFETs, 3V ≤ VIN ≤ 100V, 0.8V ≤ VOUT ≤ 60V,
IQ = 7µA, TSSOP-20(16)
LTC3896 150V Low IQ, Synchronous Inverting DC/DC Controller 4V ≤ VIN ≤ 140V, 150VP-P, –60V ≤ VOUT ≤ –0.8V, Ground Reference
Interface Pins, Adjustable 5V to 10V Gate Drive, IQ = 40µA
LTC7103 105V, 2.3A Low EMI Synchronous Step-Down Regulator 4.4V ≤ VIN ≤ 105V, 1V ≤ VOUT ≤ VIN, IQ = 2μA Fixed Frequency 200kHz
to 2MHz, 5mm × 6mm QFN
LTC7810 150V, Low IQ, Dual, 2-Phase Synchronous Step-Down
DC/DC Controller
4.5V ≤ VIN ≤ 150V, 1V ≤ VOUT ≤ 60V, Low 16µA IQ, Adjustable Gate
Drive, Spread Spectrum, 7mm × 7mm EQFP
Efficiency and Power Loss vs Load Current