1. General description
The 74HC164-Q100; 74HCT164-Q100 is an 8-bit serial-in/parallel-out shift register. The
device featur es two ser ial da ta inputs (DSA and DSB), eight parallel data outputs (Q0 to
Q7). Data is entered serially through DSA or DSB and either input can be used as an
active HIGH enable for data entry through the other input. Data is shifted on the
LOW-to-HIGH transitions of the clock (CP) input. A LOW on the master reset input (MR)
clears the register and forces all outputs LOW, independently of other inputs. Inputs
include clamp diodes that enable the use of current limiting resistors to interface inputs to
voltages in excess of VCC.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from 40 C to +85 C and from 40 C to +125 C
Input levels:
For 74HC164-Q100: CMOS level
For 74HCT164-Q100: TTL level
Gated serial data inputs
Asynchronous master reset
Complies with JEDEC standard no. 7A
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
Multiple package options
74HC164-Q100; 74HCT164-Q100
8-bit serial-in, parallel-out shift register
Rev. 1 — 16 August 2013 Product data sheet
74HC_HCT164_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 16 Aug ust 2013 2 of 18
NXP Semiconductors 74HC164-Q100; 74HCT164-Q100
8-bit serial-in, parallel-out shift register
3. Ordering information
4. Functional diagram
Table 1. Ordering information
Type number Package
Temperatur e ra nge Name Description Version
74HC164D-Q100 40 C to +125 C SO14 plastic small outline package; 14 leads; body
width 3.9 mm SOT108-1
74HCT164D-Q100
74HC164PW-Q100 40 C to +125 C TSSOP14 plastic thin shrink small outline package;
14 leads; body width 4.4 mm SOT402-1
74HCT164PW-Q100
74HC164BQ-Q100 40 C to +125 C DHVQFN14 plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads; 14
terminals; body 2.5 30.85 mm
SOT762-1
74HCT164BQ-Q100
Fig 1. Logic symbol Fig 2. IEC logic symbol
001aac423
3
1
24
5
6
10
11
12
13
8
9
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
CP
DSB
DSA
MR
001aac424
9
8
&3
1
2
4
5
6
10
11
13
12
R
C1/
1D
SRG8
Fig 3. Logic diagra m
001aac425
1
2
310136412511
8
9
Q0 Q1 Q2
8-BIT SERIAL−IN/PARALLEL−OUT
SHIFT REGISTER
Q3 Q4 Q5 Q6 Q7
DSB
CP
MR
DSA
74HC_HCT164_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 16 Aug ust 2013 3 of 18
NXP Semiconductors 74HC164-Q100; 74HCT164-Q100
8-bit serial-in, parallel-out shift register
5. Pinning information
5.1 Pinning
Fig 4. Functional diagram
001aac616
Q0
D
FF1
Q
CP
RD
CP
DSB
DSA
MR
Q1
D
FF2
Q
CP
RD
Q2
D
FF3
Q
CP
RD
Q3
D
FF4
Q
CP
RD
Q4
D
FF5
Q
CP
RD
Q5
D
FF6
Q
CP
RD
Q6
D
FF7
Q
CP
RD
Q7
D
FF8
Q
CP
RD
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 5. Pin configuration SO14 and TSSOP14 Fig 6. Pin configuration DHVQFN14
+&4
+&74
'6$ 9
&&
'6% 4
4
4
4
4
4
4
4
05
*1' &3
DDD





DDD
+&4
+&74
*1'

7UDQVSDUHQWWRSYLHZ
4 05
4 4
4 4
4 4
'6% 4
*1'
&3
'6$
9
&&





WHUPLQDO
LQGH[DUHD
74HC_HCT164_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 16 Aug ust 2013 4 of 18
NXP Semiconductors 74HC164-Q100; 74HCT164-Q100
8-bit serial-in, parallel-out shift register
5.2 Pin description
6. Functional description
[1] H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition
L = LOW voltage level
I = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition
q = lower case letters indicate the state of the referenced input one set-up time prior to the LOW-to-HIGH clock transition
= LOW-to-HIGH clock transition
Table 2. Pin description
Symbol Pin Description
DSA 1 data input
DSB 2 data input
Q0 to Q7 3, 4, 5, 6, 10, 11, 12, 13 output
GND 7 ground (0 V)
CP 8 clock input (LOW-to-HIGH, edge-triggered)
MR 9 master reset input (active LOW)
VCC 14 positive supply voltage
Table 3. Function table[1]
Operating
modes Input Output
MR CP DSA DSB Q0 Q1 to Q7
Reset (clear)LXXXLLtoL
Shift H llLq0to q6
HlhLq0to q6
Hhl Lq0to q6
HhhHq0to q6
74HC_HCT164_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 16 Aug ust 2013 5 of 18
NXP Semiconductors 74HC164-Q100; 74HCT164-Q100
8-bit serial-in, parallel-out shift register
7. Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For SO14 package: Ptot derates linearly with 8 mW/K above 70 C.
For TSSOP14 packages: Ptot derates linearly with 5.5 mW/K above 60 C.
For DHVQFN14 packages: Ptot derates linearly with 4.5 mW/K above 60 C.
8. Recommended operating conditions
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage 0.5 +7 V
IIK input clamping current VI < 0.5 V or VI>V
CC +0.5 V [1] -20 mA
IOK output clamping current VO<0.5 V or VO>V
CC +0.5V [1] -20 mA
IOoutput curren t 0.5 V < VO < VCC +0.5V - 25 mA
ICC supply current - 50 mA
IGND ground current 50 - mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation [2] - 500 mW
Table 5. Recommended operating con ditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter Conditions 74HC164-Q100 74HCT164-Q100 Unit
Min Typ Max Min Typ Max
VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V
VIinput voltage 0 - VCC 0- V
CC V
VOoutput voltage 0 - VCC 0- V
CC V
Tamb ambient temperature 40 +25 +125 40 +25 +125 C
t/V input transition rise and fall rate VCC = 2.0 V - - 625 - - - ns/V
VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V
VCC = 6.0 V--83---ns/V
74HC_HCT164_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 16 Aug ust 2013 6 of 18
NXP Semiconductors 74HC164-Q100; 74HCT164-Q100
8-bit serial-in, parallel-out shift register
9. Static characteristics
Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ Max Min Max Min Max
74HC164-Q100
VIH HIGH-level
input voltage VCC = 2.0 V 1.5 1.2 - 1.5 - 1.5 - V
VCC = 4.5 V 3.15 2.4 - 3.15 - 3.15 - V
VCC = 6.0 V 4.2 3.2 - 4.2 - 4.2 - V
VIL LOW-level
input voltage VCC = 2.0 V - 0.8 0.5 - 0.5 - 0.5 V
VCC = 4.5 V - 2.1 1.35 - 1.35 - 1.35 V
VCC = 6.0 V - 2.8 1.8 - 1.8 - 1.8 V
VOH HIGH-level
output voltage VI = VIH or VIL
IO = 20 A; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V
IO = 20 A; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V
IO = 20 A; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V
IO = 4.0 mA; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V
IO = 5.2 mA; VCC = 6.0 V 5.48 5.81 - 5.34 - 5.2 - V
VOL LOW-level
output voltage VI = VIH or VIL
IO = 20 A; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V
IO = 20 A; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V
IO = 20 A; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V
IO = 4.0 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V
IO = 5.2 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V
IIinput leakage
current VI = VCC or GND;
VCC =6.0V --0.1 - 1-1A
ICC supply current VI = VCC or GND; IO=0A;
VCC =6.0V - - 8.0 - 80 - 160 A
CIinput
capacitance -3.5- - - - -pF
74HCT164-Q100
VIH HIGH-level
input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - 2.0 - V
VIL LOW-level
input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 - 0.8 V
VOH HIGH-level
output voltage VI = VIH or VIL; VCC = 4.5 V
IO = 20 A 4.4 4.5 - 4.4 - 4.4 - V
IO = 4.0 mA 3.98 4.32 - 3.84 - 3.7 - V
VOL LOW-level
output voltage VI = VIH or VIL; VCC = 4.5 V
IO = 20 A; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V
IO = 5.2 mA; VCC = 6.0 V - 0.15 0.26 - 0.33 - 0.4 V
IIinput leakage
current VI = VCC or GND;
VCC =6.0V --0.1 - 1-1A
74HC_HCT164_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 16 Aug ust 2013 7 of 18
NXP Semiconductors 74HC164-Q100; 74HCT164-Q100
8-bit serial-in, parallel-out shift register
10. Dynamic characteristics
ICC supply current VI = VCC or GND; IO=0A;
VCC =6.0V --8 - 80 - 160A
ICC additional
supply current per input pin;
VI=V
CC 2.1 V; IO=0A;
other inputs at VCC or GND;
VCC = 4.5 V to 5.5 V
- 100 360 - 450 - 490 A
CIinput
capacitance -3.5- - - - -pF
Table 6. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ Max Min Max Min Max
Table 7. Dynamic characteristics
GND = 0 V; tr= tf= 6 ns; CL= 50 pF; test circuit, see Figure 10; unless otherwise specified
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ Max Min Max Min Max
74HC164-Q100
tpd propagation
delay CP to Qn; see Figure 7 [1]
VCC = 2.0 V - 41 170 - 215 - 255 ns
VCC = 4.5 V - 15 34 - 43 - 51 ns
VCC = 5.0 V; CL=15pF - 12 - - - - - ns
VCC = 6.0 V - 12 29 - 37 - 43 ns
tPHL HIGH to LOW
propagation
delay
MR to Qn; see Figure 8
VCC = 2.0 V - 39 140 - 175 - 210 ns
VCC = 4.5 V - 14 28 - 35 - 42 ns
VCC = 5.0 V; CL=15pF - 11 - - - - - ns
VCC = 6.0 V - 11 24 - 30 - 36 ns
tttransition time see Figure 7 [2]
VCC = 2.0 V - 19 75 - 95 - 110 ns
VCC = 4.5 V - 7 15 - 19 - 22 ns
VCC = 6.0 V - 6 13 - 16 - 19 ns
tWpulse width CP HIGH or LOW;
see Figure 7
VCC = 2.0 V 80 14 - 100 - 120 - ns
VCC = 4.5 V 16 5 - 20 - 24 - ns
VCC = 6.0 V 14 4 - 17 - 20 - ns
MR LOW; see Figure 8
VCC = 2.0 V 60 17 - 75 - 90 - ns
VCC = 4.5 V 12 6 - 15 - 18 - ns
VCC = 6.0 V 10 5 - 13 - 15 - ns
74HC_HCT164_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 16 Aug ust 2013 8 of 18
NXP Semiconductors 74HC164-Q100; 74HCT164-Q100
8-bit serial-in, parallel-out shift register
trec recovery time MR to CP; see Figure 8
VCC = 2.0 V 60 17 - 75 - 90 - ns
VCC = 4.5 V 12 6 - 15 - 18 - ns
VCC = 6.0 V 10 5 - 13 - 15 - ns
tsu set-up time DSA, and DSB to CP;
see Figure 9
VCC = 2.0 V 60 8 - 75 - 90 - ns
VCC = 4.5 V 12 3 - 15 - 18 - ns
VCC = 6.0 V 10 2 - 13 - 15 - ns
thhold time DSA, and DSB to CP;
see Figure 9
VCC = 2.0 V +4 6- 4 - 4 - ns
VCC = 4.5 V +4 2- 4 - 4 - ns
VCC = 6.0 V +4 2- 4 - 4 - ns
fmax maximum
frequency for Cp, see Figure 7
VCC = 2.0 V 6 23 - 5 - 4 - MHz
VCC = 4.5 V 30 71 - 24 - 20 - MHz
VCC = 5.0 V; CL=15pF - 78 - - - - - MHz
VCC = 6.0 V 35 85 - 28 - 24 - MHz
CPD power
dissipation
capacitance
per package;
VI=GNDtoV
CC
[3] -40- - - - - pF
74HCT164-Q100
tpd propagation
delay CP to Qn; see Figure 7 [1]
VCC = 4.5 V - 17 36 - 45 - 54 ns
VCC = 5.0 V; CL=15pF - 14 - - - - - ns
tPHL HIGH to LOW
propagation
delay
MR to Qn; see Figure 8
VCC = 4.5 V - 19 38 - 48 - 57 ns
VCC = 5.0 V; CL=15pF - 16 - - - - - ns
tttransition time see Figure 7 [2]
VCC = 4.5 V - 7 15 - 19 - 22 ns
tWpulse width CP HIGH or LOW;
see Figure 7
VCC = 4.5 V 18 7 - 23 - 27 - ns
MR LOW; see Figure 8
VCC = 4.5 V 18 10 - 23 - 27 - ns
trec recovery time MR to CP; see Figure 8
VCC = 4.5 V 16 7 - 20 - 24 - ns
tsu set-up time DSA, and DSB to CP;
see Figure 9
VCC = 4.5 V 12 6 - 15 - 18 - ns
Table 7. Dynamic characteristics …continued
GND = 0 V; tr= tf= 6 ns; CL= 50 pF; test circuit, see Figure 10; unless otherwise specified
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ Max Min Max Min Max
74HC_HCT164_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 16 Aug ust 2013 9 of 18
NXP Semiconductors 74HC164-Q100; 74HCT164-Q100
8-bit serial-in, parallel-out shift register
[1] tpd is the same as tPHL and tPLH.
[2] tt is the same as tTHL and tTLH.
[3] CPD is used to determine the dynamic power dissipation (PD in W):
PD=C
PD VCC2fiN+ (CLVCC2fo) where:
fi= input frequency in MHz;
fo= output frequency in MHz;
CL= output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CLVCC2fo) = sum of outputs.
thhold time DSA, and DSB to CP;
see Figure 9
VCC = 4.5 V +4 2- 4 - 4 - ns
fmax maximum
frequency for Cp, see Figure 7
VCC = 4.5 V 27 55 - 22 - 18 - MHz
VCC = 5.0 V; CL=15pF - 61 - - - - - MHz
CPD power
dissipation
capacitance
per package;
VI=GNDtoV
CC 1.5 V [3] -40- - - - - pF
Table 7. Dynamic characteristics …continu ed
GND = 0 V; tr= tf= 6 ns; CL= 50 pF; test circuit, see Figure 10; unless otherwise specified
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ Max Min Max Min Max
(1) Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 7. Waveforms showing the clock (CP) to output (Qn) propagation delays, the clock pulse width, the output
transition times and the maximum clock frequency
001aal392
CP input
Qn output
tPHL tPLH
tTHL tTLH
tW
VOH
VI
GND
VOL
VM
VM
VX
VY
1/fmax
Table 8. Measurement points
Type Input Output
VMVMVXVY
74HC164-Q100 0.5VCC 0.5VCC 0.1VCC 0.9VCC
74HCT164-Q100 1.3 V 1.3 V 0.1VCC 0.9VCC
74HC_HCT164_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 16 Aug ust 2013 10 of 18
NXP Semiconductors 74HC164-Q100; 74HCT164-Q100
8-bit serial-in, parallel-out shift register
(1) Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 8. Waveforms showing the master re set (MR) pulse width, the master reset to output (Qn) propagation
delays and the master reset to clock (CP) re moval time
001aac427
MR input
CP input
Qn output
tPHL
tWfrec
VM
VI
GND
VI
VOH
VOL
GND
VM
VM
(1) Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
The shaded areas indicate when the input is permitted to change for predictable output performance.
Fig 9. Waveforms showing the data set-up and hold times for Dn inputs
74HC_HCT164_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 16 Aug ust 2013 11 of 18
NXP Semiconductors 74HC164-Q100; 74HCT164-Q100
8-bit serial-in, parallel-out shift register
Test data is given in Table 9.
Definitions test circuit:
RT = termination resistance should be equal to output impedance Zo of the pulse generator.
CL = load capacitance including jig and probe capacitance.
Fig 10. Test circuit for measuring switching times
001aah768
tW
tW
tr
tr
tf
VM
VI
negative
pulse
GND
VI
positive
pulse
GND
10 %
90 %
90 %
10 % VMVM
VM
tf
VCC
DUT
RT
VIVO
CL
G
Table 9. Test data
Type Input Load Test
VItr, tfCL
74HC164-Q100 VCC 6.0 ns 15 pF, 50 pF tPLH, tPHL
74HCT164-Q100 3.0 V 6.0 ns 15 pF, 50 pF tPLH, tPHL
74HC_HCT164_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 16 Aug ust 2013 12 of 18
NXP Semiconductors 74HC164-Q100; 74HCT164-Q100
8-bit serial-in, parallel-out shift register
11. Package outline
Fig 11. Package outline SOT108-1 (SO14)
UNIT A
max. A1A2A3bpcD
(1) E(1) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm
inches
1.75 0.25
0.10 1.45
1.25 0.25 0.49
0.36 0.25
0.19 8.75
8.55 4.0
3.8 1.27 6.2
5.8 0.7
0.6 0.7
0.3 8
0
o
o
0.25 0.1
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
1.0
0.4
SOT108-1
X
wM
θ
A
A1
A2
bp
D
HE
Lp
Q
detail X
E
Z
e
c
L
vMA
(A )
3
A
7
8
1
14
y
076E06 MS-012
pin 1 index
0.069 0.010
0.004 0.057
0.049 0.01 0.019
0.014 0.0100
0.0075 0.35
0.34 0.16
0.15 0.05
1.05
0.041
0.244
0.228 0.028
0.024 0.028
0.012
0.01
0.25
0.01 0.004
0.039
0.016
99-12-27
03-02-19
0 2.5 5 mm
scale
SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1
74HC_HCT164_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 16 Aug ust 2013 13 of 18
NXP Semiconductors 74HC164-Q100; 74HCT164-Q100
8-bit serial-in, parallel-out shift register
Fig 12. Package outline SOT402-1 (TSSOP14)
UNIT A1A2A3bpcD
(1) E(2) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
0.05 0.95
0.80 0.30
0.19 0.2
0.1 5.1
4.9 4.5
4.3 0.65 6.6
6.2 0.4
0.3 0.72
0.38 8
0
o
o
0.13 0.10.21
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
0.75
0.50
SOT402-1 MO-153 99-12-27
03-02-18
wM
bp
D
Z
e
0.25
17
14 8
θ
A
A1
A2
Lp
Q
detail X
L
(A )
3
HE
E
c
vMA
X
A
y
0 2.5 5 mm
scale
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1
A
max.
1.1
pin 1 index
74HC_HCT164_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 16 Aug ust 2013 14 of 18
NXP Semiconductors 74HC164-Q100; 74HCT164-Q100
8-bit serial-in, parallel-out shift register
Fig 13. Package outline SOT762-1 (DHVQFN14)
terminal 1
index area
0.51
A1Eh
b
UNIT ye
0.2
c
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 3.1
2.9
Dh
1.65
1.35
y1
2.6
2.4 1.15
0.85
e1
2
0.30
0.18
0.05
0.00 0.05 0.1
DIMENSIONS (mm are the original dimensions)
SOT762-1 MO-241 - - -- - -
0.5
0.3
L
0.1
v
0.05
w
0 2.5 5 mm
scale
SOT762-1
DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
14 terminals; body 2.5 x 3 x 0.85 mm
A(1)
max.
AA1c
detail X
y
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8
7
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02-10-17
03-01-27
terminal 1
index area
AC
CB
vM
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E(1)
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
D(1)
74HC_HCT164_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 16 Aug ust 2013 15 of 18
NXP Semiconductors 74HC164-Q100; 74HCT164-Q100
8-bit serial-in, parallel-out shift register
12. Abbreviations
13. Revision history
Table 10. Abbreviations
Acronym Description
CMOS Complementary Metal-Oxide Semiconductor
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model
MIL Military
MM Machine Model
TTL Transistor-Transistor Logic
Table 11. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74HC_HCT164_Q10 0 v.1 20130816 Product data sheet - -
74HC_HCT164_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 16 Aug ust 2013 16 of 18
NXP Semiconductors 74HC164-Q100; 74HCT164-Q100
8-bit serial-in, parallel-out shift register
14. Legal information
14.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device (s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
14.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall pre vail.
Product specificatio n — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to off er functions and qualities beyond tho se described in the
Product data sheet.
14.3 Disclaimers
Limited warr a nty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Se miconductors takes no
responsibility for the content in this document if provided by an inf ormation
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequ ential damages (including - wit hout limitatio n - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability t owards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. Unless ot herwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, lif e-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in perso nal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconducto rs products in such equipment or
applications an d ther efo re su ch inclusi on a nd/or use is at the cu stome r's own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty tha t such application s will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and ope ration of their applications
and products using NXP Semiconductors product s, and NXP Semiconductors
accepts no liability for any assistance with applicati ons or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suit able and fit for the custome r’s applications and
products planned, as well as fo r the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for th e customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanent ly and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individua l agreement. In case an individual
agreement is concluded only the ter ms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by cust omer.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.
Product [short] dat a sheet Production This document contains the product specification.
74HC_HCT164_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 16 Aug ust 2013 17 of 18
NXP Semiconductors 74HC164-Q100; 74HCT164-Q100
8-bit serial-in, parallel-out shift register
No offer to sell or license — Nothing in this document may be interpret ed or
construed as an of fer to sell product s that is op en for accept ance or the grant ,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Translations — A non-English (translated) version of a docume nt is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
14.4 Trademarks
Notice: All referenced b rands, produc t names, service names and trademarks
are the property of their respect i ve ow ners.
15. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors 74HC164-Q100; 74HCT164-Q100
8-bit serial-in, parallel-out shift register
© NXP B.V. 2013. All rights reserved.
For more information, please visit: http://www.nxp.co m
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 16 August 2013
Document identi fier: 74HC_HCT164_Q100
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
16. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
6 Functional description . . . . . . . . . . . . . . . . . . . 4
7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
8 Recommended operating conditions. . . . . . . . 5
9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7
11 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12
12 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 15
13 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 15
14 Legal information. . . . . . . . . . . . . . . . . . . . . . . 16
14.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16
14.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
14.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 16
14.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 17
15 Contact information. . . . . . . . . . . . . . . . . . . . . 17
16 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
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