PE44820
Document Category: Product Specification
UltraCMOS® RF Digital Phase Shifter 8-bit, 1.7–2.2 GHz
©2015–2016, Peregrine Semiconductor Corporation. All rights reserved. • Headquarters: 9380 Carroll Park Drive, San Diego, CA, 92121
Product Specification DOC-43214-6 – (07/2016)
www.psemi.com
Features
• 8-bit full-range phase shifter of 358.6°; 180°, 90°,
45°, 22.5°, 11.2°, 5.6°, 2.8° and 1.4° bits
• Low RMS phase and amplitude error
▪RMS phase error of 1.0°
▪RMS amplitude error of 0.1 dB
• High linearity of +60 dBm IIP3
• Extended narrow band frequency operation of
1.1–3.0 GHz
• +105 °C operating temperature
• Packaging – 32-lead 5 × 5 × 0.85 mm QFN
Applications
• Base station transceivers
• Weather and military radar
• Active antenna arrays
Product Description
The PE44820 is a HaRP™ technology-enhanced 8-bit digital phase shifter (DPS) designed for use in a broad
range of applications including: beamforming networks, distributed antenna systems, active antenna systems
and phased array applications. This DPS covers a phase range of 358.6 degrees in 1.4 degree steps,
maintaining excellent phase and amplitude accuracy across the nominal frequency band of 1.7–2.2 GHz. The
PE44820 is also capable of extended frequency operation from 1.1–3.0 GHz for narrow band applications, as
detailed in Application Note 45. An integrated digital control interface supports both serial and parallel
programming of the phase setting. The PE44820 also features an external negative supply option for a faster
switching frequency, and is offered in a 32-lead 5 × 5 × 0.85 mm QFN p ackage. In a ddition, no external blocking
capacitors are required if 0 VDC is present on the RF ports.
The PE44820 is manufactured on Peregrine’s UltraCMOS® process, a patented variation of silicon-on-insulator
(SOI) technology on a sapphire substrate.
Peregrine’ s HaRP technology enhancement s deliver h igh linearity and excelle nt harmonics per formance. It is an
innovative feature of the UltraCMOS process, offering the performance of GaAs with the economy and
integration of conventional CMOS.
Figure 1 • PE44820 Functional Diagram
RF1
90°
180°
45°
22.5°
11.2°
5.6°
2.8°
1.4°
RF2
VDD
VSS_EXT
GND
LEO
CLKO
SDO1
SDO2
S/P
S/P = SerialS/P = Parallel
OPT
P0... P7
Parallel
Interface
A0... A3
Serial
Address
Serial Interface
SI
CLK
LE
Digital Interface
8 4
PE44820
Digital Phase Shifter
Page 2 DOC-43214-6 – (07/2016)
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Optional External VSS
For proper operation, the VSS_EXT pin must be grounded or tied to the VSS voltage specified in Table 2. When the
VSS_EXT pin is grounded, FETs in the switch are biased with an internal negative voltage generator. For applica-
tions that require the lowest possible spur performance, VSS_EXT can be applied externally to bypass the internal
negative voltage generator.
Absolute Maximum Ratings
Exceeding absolute maximum ratings listed in Table 1 may cause permanent damage. Operation should be
restricted to the limits in Table 2. Operation between operating range maximum and absolute maximum for
extended periods may reduce reliability.
ESD Precautions
When handling this UltraCMOS device, observe the same precautions as with any other ESD-sensitive devices.
Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to
avoid exceeding the rating specified in Table 1.
Latch-up Immunity
Unlike conventional CMOS devices, UltraCMOS devices are immune to latch-up.
Table 1 • Absolute Maximum Ratings for PE44820
Parameter/Condition Min Max Unit
Supply voltage, VDD –0.3 5.5 V
Negative suppl y voltage, VSS_EXT –3.6 –2.4 V
Digital input voltage –0.3 3.6 V
Maximum input power 28 dBm
Storage temperature range –65 +150 °C
ESD voltage HBM, all pins(*) 500 V
Note: * Human body model (MIL-STD 883 Method 3015).
PE44820
Digital Phase Shifter
DOC-43214-6 – (07/2016) Page 3
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Recommended Operating Conditions
Table 2 lists the recommended operating conditions for the PE44820. Devices should not be operated outside
the recommended operating conditions listed below.
Table 2 • Recommended Operating Conditions for PE44820
Parameter Min Typ Max Unit
Normal mode, VSS_EXT = 0V(1)
Supply voltage, VDD 2.3 5.5 V
Supply current, IDD 130 200 µA
Bypass mode, VSS_EXT = –3.3V(2)
Supply voltage, VDD 3.3 5.5 V
Supply current, IDD 50 80 µA
Negative supply voltage, VSS_EXT –3.6 –3.2 V
Negative supply current, ISS –40 –16 µA
Normal or Bypass mode
Digital input high 1.17 3.6 V
Digital input low –0.3 0.6 V
Digital input current 15 µA
Digital input current, D4–D7(3) 200 µA
RF input power, CW 25 dBm
Operating temperature range –40 +25 +105 °C
Notes:
1) Normal mode: con nect V SS_EXT (pin 20) to GN D (V SS_EXT = 0V ) to en ab le in tern al n eg ative voltage gen er at or.
2) Bypass mode: use VSS_EXT (pin 20) to bypass and disable internal negative voltage generator.
3) Typical current draw 200 µA @ 3 .6 V. Recommended operat ion at 1. 8V redu ces inpu t curre nt dr a w to 0.6 µA .
PE44820
Digital Phase Shifter
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Electrical Specifications
Table 3 provides the PE44820 key electrical specifications at +25 °C (ZS = ZL = 50Ω), unless otherwise
specified. Normal mode(1) is at VDD = 3.3V a nd VSS_EXT = 0V. Bypass mode(2) is at VDD = 3.3V and VSS_EXT =
–3.3V.
Table 3 • PE44820 Electrical Specifications
Parameter Condition Min Typ Max Unit
Operating frequency 1.71.952.2GHz
Phase shift range LSB = 1.4° +0 358.6 deg
Number of bits 8bits
Insertion loss Across all states 6 7.1 dB
RMS phase error Over all 256 states 1.0 deg
RMS amplitude error Over all 256 states 0.1 dB
Phase accuracy Across all states ±3 deg
Attenuation variation Across all states ±0.50 dB
Phase accuracy relative
to reference phase @
1.95 GHz
1.4° bit –0.60 deg
2.8° bit –0.40 deg
5.6° bit +0.05 deg
11.2° bit +0.25 deg
22.5° bit +0.50 deg
45° bit +0.25 deg
90° bit +1.75 deg
180° bit –0.65 deg
Return loss 13 dB
Input 0.1dB compression
point(3) 28 dBm
Input IP3 60 dBm
Settling time(4) RF settled within 2 deg of final value 365 ns
Notes:
1) Normal mode: sing le e xte rn al p osit ive su pp ly use d.
2) Bypass mode: both external positive supp ly and externa l negative supp ly used.
3) The input P0.1dB compre ssion poin t is a linearit y figure of merit . Refer to Table 2 fo r th e operatin g RF in put pow er (50 Ω).
4) Use of VSS_EXT reduces the sett ling tim e.
PE44820
Digital Phase Shifter
DOC-43214-6 – (07/2016) Page 5
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Switching Frequency
The PE44820 has a maximum 25 kHz switching
frequency in normal mode (pin 20 tied to ground). A
faster switching frequency is available in bypass
mode (pin 20 tied to VSS_EXT).
Switching frequency describes the time duration
between switching events. Switching time is the time
between the point the control signal LE reaches 50%
of its final value and the point the RF output signal
reaches within 10% or 90% of its target value.
Control Logic
Table 4 and Table 5 provide the Serial/Parallel
selection truth table and the Serial and Parallel truth
table for the PE44820.
Table 4 • Serial/Parallel Selection Truth Table for
PE44820
P/S Pin Control Mode
L Parallel
HSerial
Table 5 • Serial and Parallel Truth Table(*)
Phase Control Setting Phase Shif t Setting
RF1–RF2
D0 D1 D2 D3 D4 D5 D6 D7 OPT
LLLLLLLLL Reference phase
HLLLLLLLL 1.4 deg
LHLLLLLLL 2.8 deg
LLHLLLLLL 5.6 deg
LLLHLLLLL 11.2 deg
LLLLHLLLL 22.5 deg
LLLLLHLLL 45 deg
LLLLLLHL H 90 deg
LLLLLLLHL 180 deg
HHHHHHHHH 358.6 deg
LLLLLLLL H 1.4 deg
Note: * Normal mode operation uses the OPT bit to synchronize the 90 degree bit optimizing the phase accuracy across all states. For additional infor-
mation on the OPT bit, reference Application Note 45.
PE44820
Digital Phase Shifter
Page 6 DOC-43214-6 – (07/2016)
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Figure 2 • Serial Control Register Map
Phase Setting Word
LSB (first in) MSB (last in)
SI
SDO2
SDO1
Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12
D6 D5 D4 D7 OPT A0 A1 A2 A3
Q0 Q1 Q2 Q3 Q4
D0 D1 D2 D3
Unit Address Word
205.3° × (256 states / 360°) = state 146
state 146 → 01001001
LSB→MSB (205.3 deg setting = 2.8° + 22.5° + 180°)
Program Word (LSB→MSB): 010010010 + 1100, OPT bit is synchronized to 90° bit
Phase Setting Word is derived directly from the Phase Setting. For example, to
program the 205.3 degree setting at unit address 3:
Unit Address Word: 1100 (Unit Address = 1 + 2)
Phase Setting Word: Multiply the degree desired by 256 states divided by 360° and convert to binary
PE44820
Digital Phase Shifter
DOC-43214-6 – (07/2016) Page 7
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Programming Options
Parallel/Serial Selection
Either a Parallel or Serial addressable interface can
be used to control the PE44820. The P/S bit provides
this selection, with P/S = LOW selecting the Parallel
interface and P/S = HIGH selecting the Serial-
addressable interface.
Parallel Mode Interface
The Parallel interface consists of nine CMOS-
compatible control lines that select the desired phase
state, as shown in Table 5.
The Parallel interface timing requirement s are defined
by Figure 5 (Latched Parallel/Direct Parallel Timing
Diagram) and Table 7 (Parallel and Direct Interface
AC Characteristics).
For Latched Parallel programming, the Latch Enable
(LE) should be held LOW while changing phase state
control values, then pulse LE HIGH to LOW (per
Figure 5) to latch new phase state into device.
For Direct Parallel programming, the LE line should
be pulled HIGH. Changing a phase st ate control value
will change the device state to a new phase. Direct
mode is ideal for manual control of the device (using
hardware, switches or jumpers).
Serial Interface
The Serial addressable interface is a 13-bit Serial-In,
Parallel-Out shift register buffered by a transparent
latch. The 13 bits make up two words comprising 9
data and 4 address bits. The first word is the Phase
Word, which controls the state of the DPS. The
second W ord is the Address W ord , which is compared
to the static (or programmed) logical states of the A0–
A3 digital state; othe rwise, it s current st ate will remain
unchanged. Figure 4 and Figure 6 illustrate
examples of timing diagrams for progr amming a state.
The Serial interface is controlled using three CMOS-
compatible signals: Serial In (SI), Clock (CLK) and
Latch Enable (LE). The SI and CLK inputs allow data
to be serially entered into the shift register. Serial data
is clocked in LSB first, beginning with the Phase
Word.
SDO1 is provided to connect several devices in
parallel to the serial bus. SDO1 is a non-inverting
buffered output of SI. SDO1 changes state with SI
without regard to CLK. This is useful to connect
multiple devices with different serial addresses to the
serial controller without the need for additional
external logic buffers.
SDO2 is the buffered output of the last bit of the
internal shift register and changes state on the rising
edge of the clock.
PE44820
Digital Phase Shifter
Page 8 DOC-43214-6 – (07/2016)
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Figure 3 • Buffered SDO1 Serial Interface(*)
Note: * SDO1 data buffered with respect to SI and valid on rising edge of CLK.
CLK
SI
SDO1
Register Data
LE
D0 D1 D2 D3
OPT
D5 D6 D7D4 A0 A1 A2 A3
D0 D1 D2 D3
OPT
D5 D6 D7D4 A0 A1 A2 A3
TCLK
TSU
THTCLKH
TLCLKH
TSettle
Default/Current Value New Value
TCLKL
TOVSDO1
Figure 4 • SDO2 (Last Bit of Shift Register)—Single Write with Readback(*)
Note: * SDO2 data changes on rising edge of CLK and is valid on falling edge of CLK.
CLK
SI
SDO2
Register Data
LE T
OVSDO2
T
CLK
T
SU
T
CLKH
T
Settle
T
OH
Default/Current Value New Value
T
CLKL
D0 D1 D2 D3
OPT
D5 D6D4 A0 A1 A2 A3
DON’T CARE
DON’T CARE
D1 D2 D3
OPT
D5 D6 D7D4 A0 A1 A2 A3D0
T
PD
T
H
D0
DON’T CARE
D7
PE44820
Digital Phase Shifter
DOC-43214-6 – (07/2016) Page 9
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Table 6 • Serial Interface AC Characteristics
Parameter Min Max Unit
Serial clock period, TCLK 100 ns
Serial clock HIGH time, TCLKH 30 ns
Serial clock LOW time, TCLKL 30 ns
Last serial clock rising edge setup
time to latch enable rising edge,
TSETTLE 10 ns
Latch enable min pulse width, TLEPW 30 ns
Serial data setup time, TSU 10 ns
Serial data hold time, TH10 ns
Digital register delay (internal), TPD 10 ns
SD01 and SD02 drive strength(*) 25 pF
Serial data output propagation delay
from SI to SDO1, TOVSD01 25 ns
Serial data output propagation delay
from CLK to SDO2, TOVSD02 25 ns
Serial data output hold time from
CLK rising edge, TOH 1ns
Note: * SD01/2 maximum capacitive load drive strength for clock
period of 100 ns.
Table 7 • Parallel and Direct Interface AC
Characteristics
Parameter Min Max Unit
Latch enable minimum pulse width,
TLEPW 30 ns
Parallel data setup time, TDISU 100 ns
Parallel data hold time, TDIH 100 ns
Parallel/Serial setup time, TPSSU 100 ns
Parallel/Serial hold time, TPSH 100 ns
Digital register delay (internal), TPD 10 ns
Digit al reg i ste r de l ay (i nt ernal, direct
mode only), TDIPD 5ns
Figure 5 • Latched Parallel/Direct Parallel Timing
Diagram
TLEPW
TDIH
TDISU
TDIPD
TPSH
TPD
Valid
Valid
DI[OPT, D7:0]
DO[OPT, D7:0]
LE
P/S
TPSSU
PE44820
Digital Phase Shifter
Page 10 DOC-43214-6 – (07/2016)
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Typical Performance Data
Figure 6–Figure 19 show the typical performance data at +25 °C, VDD = 3.3V and VSS_EXT = 0V, unless
otherwise specified.
Figure 6 • Relative Phase Error: OPT Bit
-5
-4
-3
-2
-1
0
1
2
3
4
5
[deg]
Phase Error: OPT Bit
1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200
Frequency [MHz]
PE44820
Digital Phase Shifter
DOC-43214-6 – (07/2016) Page 11
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Figure 7 • Relative Phase Error: 180 Deg Bit
Figure 8 • Relative Phase Error: 90 Deg Bit
-5
-4
-3
-2
-1
0
1
2
3
4
5
[deg]
Phase Error: 180°
1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200
Frequency [MHz]
-5
-4
-3
-2
-1
0
1
2
3
4
5
[deg]
Phase Error: 90°
1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200
Frequency [MHz]
PE44820
Digital Phase Shifter
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Figure 9 • Relative Phase Error: 45 Deg Bit
Figure 10 • Relative Phase Error: 22.5 Deg Bit
-5
-4
-3
-2
-1
0
1
2
3
4
5
[deg]
Phase Error: 45°
1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200
Frequency [MHz]
-5
-4
-3
-2
-1
0
1
2
3
4
5
[deg]
Phase Error: 22.5°
1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200
Frequency [MHz]
PE44820
Digital Phase Shifter
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Figure 11 • Relative Phase Error: 11.25 Deg Bit
Figure 12 • Relative Phase Error: 5.6 Deg Bit
-5
-4
-3
-2
-1
0
1
2
3
4
5
[deg]
Phase Error: 11.25°
1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200
Frequency [MHz]
-5
-4
-3
-2
-1
0
1
2
3
4
5
[deg]
Phase Error: 5.6°
1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200
Frequency [MHz]
PE44820
Digital Phase Shifter
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Figure 13 • Relative Phase Error: 2.8 Deg Bit
Figure 14 • Relative Phase Error: 1.4 Deg Bit
-5
-4
-3
-2
-1
0
1
2
3
4
5
[deg]
Phase Error: 2.8°
1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200
Frequency [MHz]
-5
-4
-3
-2
-1
0
1
2
3
4
5
[deg]
Phase Error: 1.4°
1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200
Frequency [MHz]
PE44820
Digital Phase Shifter
DOC-43214-6 – (07/2016) Page 15
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Figure 15 • RMS Amplitude Error
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
[dB]
-40 °C 25 °C 85 °C 105 °C
Frequency [MHz]
1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200
Figure 16 • RMS Phase Error
0
0.5
1
1.5
2
2.5
3
1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200
[deg]
Frequency [MHz]
-40°C 25°C 85°C 105°C
PE44820
Digital Phase Shifter
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Figure 17 • Maximum Return Loss S11 Over All Major States
Figure 18 • Maximum Return Loss S22 Over All Major States
-50
-45
-40
-35
-30
-25
-20
-15
-10
1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200
[dB]
Frequency [MHz]
-40 °C 25 °C 85 °C 105 °C
-50
-45
-40
-35
-30
-25
-20
-15
-10
1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200
[dB]
Frequency [MHz]
-40 °C 25 °C 85 °C 105 °C
PE44820
Digital Phase Shifter
DOC-43214-6 – (07/2016) Page 17
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Figure 19 • Insertion Loss—Reference States
-9
-8.5
-8
-7.5
-7
-6.5
-6
-5.5
-5
-4.5
-4
1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200
[dB]
Frequency [MHz]
-40 °C 25 °C 85 °C 105 °C
PE44820
Digital Phase Shifter
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Evaluation Kit
The PE44820 evaluation kit (EVK) includes hardware required to control and evaluate the functionality of the
DPS. The DPS evaluation software can be downloaded at www.psemi.com and requires a PC running
Windows® operating system to control the USB interface board. Refer to the PE44820 Evaluation Kit User ’s
Manual for more information.
Figure 20 • Evaluation Kit Layout for PE44820
PE44820
Digital Phase Shifter
DOC-43214-6 – (07/2016) Page 19
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Pin Information
This section provides pinout information for the
PE44820. Figure 21 shows the pin map of this device
for the available package. Table 8 provides a
description fo r each pin.
Figure 21 • Pin Configuration (Top View)
Table 8 • Pin Descriptions for PE44820
Pin No. Pin Name Description
1OPT(1) Parallel: phase accuracy optimi-
zation bit. Serial: not used—
must be tied low.
2VDD Supply voltage.
3S/P
Serial/parallel mode select.
4–6, 8–17,
19, 21 GND Ground.
7RF1(2) RF1 port.
18 RF2(2) RF2 port
20 VSS_EXT(3) External VSS negative supply
voltage.
22 LE Parallel: see table note(7). Serial:
serial interface latch enable
input.
23 CLK
Parallel: no t u sed , optional tie
high or low (internal pullup).
Serial: serial interface clock
input.
24 SI
Parallel: no t u sed , optional tie
high or low (internal pullup).
Serial: serial interface data
input.
25 D7/SDO2(4)(6)(8) Parallel—D7 180° bit/serial data
out 2.
26 D6/SDO1(4)(6)(8) Parallel—D6 90° bit/serial data
out 1.
27 D5/CLKO(6)(8) Parallel—D5 45° bit/serial-buff-
ered CLK out.
28 D4/LEO(6)(8) Parallel—D4 22.4° bit/serial buff-
ered LE out.
29 D3/A3 Parallel—D3 11.2° bit/serial A3
address bit.
30 D2/A2 Parallel—D2 5.6° bit/serial A2
address bit.
31 D1/A1 Parallel—D1 2.8° bit/serial A1
address bit.
32 D0/A0 Parallel—D0 1.4° bit/serial A0
address bit.
Pad GND Exposed pad: Ground for proper
operation.
Notes:
1) OPT bit is used to optimize the phase accuracy across all states.
OPT bit (pin 1) must be syn chron ized to th e 90 ° bit (p in 26) for
normal operation.
2) RF1 and RF2 (p ins 7 a nd 18 ) ar e bi-dir ect ion al.
3) Use VSS_EXT (pin 20) with negative supply (VSS_EXT = –3.4V) to
bypass and disable inter nal nega tive voltage gen erat or. Connect
VSS_EXT (pin 20) to GND (VSS_EXT = 0V) to enable internal neg-
ative voltage genera tor.
4) SDO2 is buffered output of the last bit of the internal shift register.
5) SDO1 is a buffered outp ut of the ser ial d ata inpu t.
6) D4–D7 (pins 25–28) ar e bi-directiona l pins.
7) LE operation in parallel mode: Holding LE HIGH while changin g
OPT, D7:D0 will immediately latch phase setting states into the
device. Holding LE low while chang ing OPT,D7:D0 r equir es a ris-
ing edge on LE to latch the phase setting states into the device.
8) If not using buffered output in serial mode, leave floating.
Table 8 • Pin Descriptions for PE44820 (Cont.)
Pin No. Pin Name Description
PE44820
Digital Phase Shifter
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Packaging Information
This section provides packaging data including the moisture sensitivity level, package drawing, package
marking and tape and reel information.
Moisture Sensitivity Level
The moisture sensitivity level rating for the PE44820 in the 32-lead 5 × 5 × 0.85 mm QFN package is MSL1.
Package Drawing
Top-Marking Specification
Figure 22 • Package Mechanical Drawing for 32-lead 5 × 5 × 0.85 mm QFN
Figure 23 • Package Marking Specifications for PE44820
TOP VIEW BOTTOM VIEW
SIDE VIEW
RECOMMENDED LAND PATTERN
A
0.10 C
(2X)
C
0.10 C
0.05 C
SEATING PLANE
B
0.10 C
(2X)
0.10 C AB
0.05 C
ALL FEATURES
PIN #1 CORNER
5.00
5.00
0.40±0.05
(x32)
3.60±0.05
0.25±0.05
(x32)
0.50
3.50
REF
3.60±0.05
0.85±0.05
0.05
REF
0.203
REF
(x28)
0.30
(x32)
0.60
(x32)
3.65
3.65
5.40
5.40
0.50
(x28)
18
932
17 24
25
16
=
YY =
WW =
ZZZZZZZ =
Pin 1 indicator
Last two digits of assembly year
Assembly work week
Assembly lot code (maximum seven characters)
44820
YYWW
ZZZZZZZ
PE44820
Digital Phase Shifter
DOC-43214-6 – (07/2016) Page 21
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Tape and Reel Specification
Figure 24 • Tape and Reel Specifications for 32-lead 5 × 5 × 0.85 mm QFN
Device Orientation in Tape
Pin 1
T
K0 A0
B0
P0
P1
D1
A
Section A-A
A
Direction of Feed
D0
E
W0
P2
see note 3
see
note 1
F
see note 3
A0
B0
K0
D0
D1
E
F
P0
P1
P2
T
W0
5.25
5.25
1.10
1.50 + 0.1/ -0.0
1.5 min
1.75 ± 0.10
5.50 ± 0.05
4.00
8.00
2.00 ± 0.05
0.30 ± 0.05
12.00 ± 0.30
Notes:
1. 10 Sprocket hole pitch cumulative tolerance ±0.2
2. Camber in compliance with EIA 481
3. Pocket position relative to sprocket hole measured
as true position of pocket, not pocket hole
Dimensions are in millimeters unless otherwise specified
PE44820 Digital Phase Shifter
Product Specification www.psemi.com DOC-43214-6 – (07/2016)
Document Categories
Advance Information
The product is in a formative or design stage. The datasheet contains
design target specifications for product development. Specifications
and features may change in any manner without notice.
Preliminary Specification
The datasheet contains prelimin ary data. Addition al data may be ad ded
at a later date. Peregrine reserves the right to change specifications at
any time withou t not ice in or der to supp ly th e b est po ssible pr oduct .
Product Specification
The datasheet contains final data. In the event Peregrine decides to
change the specifications, Peregrine will notify customers of the
intended changes by issuing a CNF (Customer Notification Form).
Product Brief
This document contains a shortened version of the datasheet. For the
full datasheet, contact sales@psemi.com.
Not Recommended for New Designs (NRND)
This product is in production but is not recommended for new designs.
End of Life (EOL)
This product is currently going through the EOL process. It has a
specific last-time buy date.
Obsolete
This product is discontinued. Orders are no longer accepted for this
product.
Sales Contact
For additional information, contact Sales at sales@psemi.com.
Disclaimers
The information in this document is believed to be reliable. However, Peregrine assumes no liability for the use of this information. Use shall be
entirely at the user’s own risk. No patent rights or licenses to any circuits described in this document are implied or granted to any third party.
Peregrine’s products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to
support or sustain life, or in any application in which the failure of the Peregrine product could create a situation in which personal injury or death
might occur. Peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in
such applications.
Patent Statement
Peregrine products are protected under one or more of the following U.S. patents: patents.psemi.com
Copyright and Trademark
©2015–2016, Peregrine Semiconductor Corporation. All rights reserved. The Peregrine name, logo, UTSi and UltraCMOS are registered trade-
marks and HaRP, MultiSwitch and DuNE are trademarks of Peregrine Semiconductor Corp.
Ordering Information
Table 9 lists the available ordering codes for the PE44820 as well as available shipping methods.
Table 9 • Order Codes for PE44820
Order Codes Description Packaging Shipping Method
PE44820A–X PE44820 Digital phase shifter Green 32-lead 5 × 5 mm QFN 500 units/T&R
EK44820–01 PE44820 Evaluation kit Evaluation kit 1/Box