NOTE: For detailed information on purchasing options, contact your
local Allegro field applications engineer or sales representative.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, revisions to the anticipated product life cycle plan
for a product to accommodate changes in production capabilities, alternative product availabilities, or market demand. The
information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no respon-
sibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use.
Recommended Substitutions:
10-Bit Serial Input Latched Source Driver
A6810
For existing customer transition, and for new customers or new appli-
cations, contact Allegro Sales.
Date of status change: November 1, 2010
This device is no longer in production. The device should not be
purchased for new design applications. Samples are no longer available.
Discontinued Product
Description
The A6810 combines 10-bit CMOS shift registers,
ac com pa ny ing data latches, and control cir cuit ry with bipolar
sourcing out puts and PNP active pull-downs. De signed
pri mar ily to drive vacuum-flu o res cent (VF) displays, the 60 V
and –40 mA output ratings also allow this device to be used in
many other peripheral power driver ap pli ca tions. The A6810
features an increased data input rate (com pared with the older
UCN/UCQ5810-F) and a con trolled output slew rate.
The CMOS shift register and latches allow direct interfacing
with microprocessor-based systems. With a 3.3 or 5 V logic
supply, serial data-input rates of at least 10 MHz can be
attained
A CMOS serial data output permits cascaded con nec tions in
ap pli ca tions re quir ing additional drive lines. Similar devices
are available as the A6812 (20-bit) and A6818 (32-bit).
The A6810 output source drivers are NPN Dar ling tons, capable
of sourcing up to 40 mA. The controlled output slew rate reduces
elec tro mag net ic noise, which is an important consideration in
systems that include telecommunications and microprocessors,
and to meet government emissions regulations. For inter-digit
26182.124I
Features and Benefits
▪ Controlled output slew rate
▪ High-speed data storage
▪ 60 V minimum output breakdown
▪ High data-input rate
▪ PNP active pull-downs
▪ Low output-saturation voltages
▪ Low-power CMOS logic and latches
▪ Improved replacements for TL4810x, UCN5810x, and
UCQ5810x
10-Bit Serial Input Latched Source Driver
Continued on the next page…
Packages:
Functional Block Diagram
Not to scale
A6810
18-pin DIP
(A package)
20-pin SOICW
(LW package)
10-Bit Serial Input Latched Source Driver
A6810
2
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Selection Guide
Part Number Pb-free Packing Ambient Temperature, TA (°C) Package
A6810EA-T Yes 21 pieces/tube –40 to 85 18-pin DIP
A6810SA-T Yes 21 pieces/tube –20 to 85
A6810ELWTR-T Yes 1000 pieces/13-in. reel –40 to 85
20-pin SOIC-WA6810KLWTR-T Yes 1000 pieces/13-in. reel –40 to 125
A6810SLWTR-T Yes 1000 pieces/13-in. reel –20 to 85
*Variant is in production but has been determined to be LAST TIME BUY. This classification indicates that the variant is obsolete and
notice has been given. Sale of the variant is currently restricted to existing customer applications. The variant should not be purchased
for new design applications because of obsolescence in the near future. Samples are no longer available. Status date change May 3,
2010. Deadline for receipt of LAST TIME BUY orders is October 29, 2010.
blanking, all output drivers can be dis abled and all sink drivers
turned on with a BLANK ING input high. The PNP active pull-
downs can sink at least 2.5 mA.
The A6810 is available in three temperature ranges for op ti mum
per for mance in commercial (S), industrial (E), and automotive (K)
ap pli ca tions. It is provided in two package styles, through-hole
DIP (package A) and surface-mount SOIC (package LW). Copper
leadframes, low logic-power dis si pa tion, and low output-saturation
voltages allow all devices to source 25 mA from all outputs
continuously over the full operating tem pera ture range.
The lead (Pb) free versions have 100% matte tin leadframe
plating.
Description (continued)
Absolute Maximum Ratings*
Characteristic Symbol Notes Rating Units
Logic Supply Voltage VDD 7.0 V
Driver Supply Voltage VBB 60 V
Input Voltage Range VIN –0.3 to VDD + 0.3 V
Continuous Output Current Range IOUT –40 to 15 mA
Operating Ambient Temperature TA
Range E –40 to 85 ºC
Range K –40 to 125 ºC
Range S –20 to 85 ºC
Maximum Junction Temperature TJ(max) 150 ºC
Storage Temperature Tstg –55 to 125 ºC
*Caution: These CMOS devices have input static protection (Class 2) but are still susceptible to damage if exposed to extremely high
static electrical charges.
10-Bit Serial Input Latched Source Driver
A6810
3
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Thermal Characteristics
Characteristic Symbol Test Conditions* Value Units
Package Thermal Resistance RθJA
Package A, 1-layer PCB with copper limited to solder pads 65 ºC/W
Package LW, 1-layer PCB with copper limited to solder pads 90 ºC/W
*Additional thermal information available on the Allegro website.
Pin-out Diagrams
10-Bit Serial Input Latched Source Driver
A6810
4
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Limits @ VDD = 3.3 V Limits @ VDD = 5 V
Characteristic Symbol Test Conditions Mln. Typ. Max. Min. Typ. Max. Units
Output Leakage Current ICEX V
OUT = 0 V — <-0.1 -15 — <-0.1 -15 μA
Output Voltage VOUT(1) I
OUT = -25 mA 57.5 58.3 — 57.5 58.3 — V
V
OUT(0) I
OUT = 1 mA — 1.0 1.5 — 1.0 1.5 V
Output Pull-Down Current IOUT(0) V
OUT = 5 V to VBB 2.5 5.0 — 2.5 5.0 — mA
Input Voltage VIN(1) 2.2 — — 3.3 — — V
V
IN(0) — — 1.1 — — 1.7 V
Input Current IIN(1) V
IN = VDD — <0.01 1.0 — <0.01 1.0 μA
I
IN(0) V
IN = 0 V — <-0.01 -1.0 — <-0.01 -1.0 μA
Input Clamp Voltage VIK I
IN = -200 μA — -0.8 -1.5 — -0.8 -1.5 V
Serial Data Output Volt age VOUT(1) I
OUT = -200 μA 2.8 3.05 — 4.5 4.75 — V
V
OUT(0) I
OUT = 200 μA — 0.15 0.3 — 0.15 0.3 V
Maximum Clock Frequency fc 10* — — 10* — — MHz
Logic Supply Current IDD(1) All Outputs High — 0.25 0.75 — 0.3 1.0 mA
I
DD(0) All Outputs Low — 0.25 0.75 — 0.3 1.0 mA
Load Supply Current IBB(1) All Outputs High, No Load — 1.5 3.0 — 1.5 3.0 mA
I
BB(0) All Outputs Low — 0.2 20 — 0.2 20 μA
Blanking
-to-
Output Delay tdis(BQ) C
L = 30 pF, 50% to 50% — 0.7 2.0 — 0.7 2.0 μs
t
en(BQ) CL = 30 pF, 50% to 50% — 1.8 3.0 — 1.8 3.0 μs
Strobe
-to-
Output Delay tp(STH-QL) R
L = 2.3 kΩ, CL ≤ 30 pF — 0.7 2.0 — 0.7 2.0 μs
t
p(STH-QH) R
L = 2.3 kΩ, CL ≤ 30 pF — 1.8 3.0 — 1.8 3.0 μs
Output Fall Time tf R
L = 2.3 kΩ, CL ≤ 30 pF 2.4 — 12 2.4 — 12 μs
Output Rise Time tr R
L = 2.3 kΩ, CL ≤ 30 pF 2.4 — 12 2.4 — 12 μs
Output Slew Rate dV/dt RL = 2.3 kΩ, CL ≤ 30 pF 4.0 — 20 4.0 — 20 V/μs
Clock
-to-
Serial Data Out Delay tp(CH-SQX) I
OUT = ±200 μA — 50 — — 50 — ns
Negative current is defi ned as coming out of (sourcing) the specifi ed device terminal.
Typical data is is for design information only and is at TA = +25°C.
*Operation at a clock frequency greater than the specifi ed minimum value is possible but not warranteed.
ELECTRICAL CHARACTERISTICS at TA = +25°C (A6810S-) or over op er at ing tem per a ture range (A6810E-),
VBB = 60 V, logic supply operating voltage VDD = 3.0 to 5.5 V; un less otherwise noted
10-Bit Serial Input Latched Source Driver
A6810
5
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
TIMING REQUIREMENTS and SPECIFICATIONS
(Logic Levels are VDD and Ground)
Serial Data present at the input is trans ferred to the shift
register on the logic “0” to logic “1” transition of the CLOCK
input pulse. On suc ceed ing CLOCK pulses, the registers shift
data information towards the SERIAL DATA OUTPUT. The
SERIAL DATA must appear at the input prior to the rising edge
of the CLOCK input waveform.
Information present at any register is transferred to the
respective latch when the STROBE is high (serial-to-par al lel
con ver sion). The latches will continue to accept new data as
long as the STROBE is held high. Ap pli ca tions where the
latches are bypassed (STROBE tied high) will require that the
BLANKING input be high during serial data entry.
When the BLANKING input is high, the output source
driv ers are disabled (OFF); the PNP active pull-down sink
drivers are ON. The in for ma tion stored in the latches is not
affected by the BLANKING input. With the BLANK ING input
low, the outputs are con trolled by the state of their re spec tive
latches.
BLANKING
OUT
N
Dwg. WP-030A
DATA
10%
50%
en(BQ)
t
dis(BQ)
t
HIGH = ALL OUTPUTS BLANKED (DISABLED)
r
t
f
t
50%
90%
A. Data Active Time Before Clock Pulse
(Data Set-Up Time), tsu(D) ........................................... 25 ns
B. Data Active Time After Clock Pulse
(Data Hold Time), th(D) ................................................ 25 ns
C. Clock Pulse Width, tw(CH) ................................................. 50 ns
D. Time Between Clock Ac ti va tion and Strobe, tsu(C) ......... 100 ns
E. Strobe Pulse Width, tw(STH) .............................................. 50 ns
NOTE – Timing is representative of a 10 MHz clock. Higher
speeds may be attainable; operation at high temperatures will
reduce the specifi ed maximum clock frequency.
CLOCK
SERIAL
DATA IN
STROBE
BLANKING
OUT
N
Dwg. WP-029
50%
SERIAL
DATA OUT
DATA
DATA
10%
90%
50%
50%
50%
C
A B
D E
LOW = ALL OUTPUTS ENABLED
p(STH-QL)
t
p(CH-SQX)
t
DATA
p(STH-QH)
t
10-Bit Serial Input Latched Source Driver
A6810
6
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
TRUTH TABLE
Serial Shift Register Contents Serial Latch Contents Output Con tents
Data Clock Data Strobe
Input Input I1 I
2 I
3 ... IN-1 I
N Output Input I1 I
2 I
3 ... IN-1 I
N Blanklng I1 I
2 I
3 ... IN-1 IN
H H R1 R2 ... RN-2 R
N-1 R
N-1
L L R1 R2 ... RN-2 R
N-1 RN-1
X R1 R2 R3 ... RN-1 RN RN
X X X ... X X X L R1 R2 R3 ... RN-1 RN
P
1 P2 P3 ... PN-1 PN P
N H P1 P2 P3 ... PN-1 PN L P1 P
2 P
3 ... PN-1 PN
X X X ... X X H L L L ... L L
L = Low Logic Level H = High Logic Level X = Irrelevant P = Present State R = Previous State
10-Bit Serial Input Latched Source Driver
A6810
7
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Package A 18-Pin DIP
5.33 MAX
0.46 ±0.12
22.86 ±0.51
6.35 +0.76
–0.25
3.30 +0.51
–0.38
10.92 +0.38
–0.25
1.52 +0.25
–0.38
7.62
2.54
0.25 +0.10
–0.05
C
SEATING
PLANE
21
18
A
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
ATerminal #1 mark area
All dimensions nominal, not for tooling use
(reference JEDEC MS-001 AC)
Dimensions in inches
Package LW 20-Pin SOICW
21
20
21
20
A
2.65 MAX
C
SEATING
PLANE
C0.10
20X
ATerminal #1 mark area
GAUGE PLANE
SEATING PLANE B
2.25
0.65
9.50
1.27
PCB Layout Reference View
For Reference Only
Dimensions in millimeters
(Reference JEDEC MS-013 AC)
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
BReference pad layout (reference IPC SOIC127P1030X265-20M)
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances
1.27
0.25
0.20 ±0.10
0.41 ±0.10
12.80±0.20
10.30±0.33
7.50±0.10
4° ±4
0.27 +0.07
–0.06
0.84 +0.44
–0.43
10-Bit Serial Input Latched Source Driver
A6810
8
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
For the latest version of this document, visit our website:
www.allegromicro.com
Copyright ©1998-2010, Allegro MicroSystems, Inc.
The products described here are manufactured under one or more U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per-
mit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, Inc. assumes no re spon si bil i ty for its use;
nor for any in fringe ment of patents or other rights of third parties which may result from its use.
