HIGH SPEED SYNCHRONOUS POWER MOSFET SMART DRIVER March 14, 2000 SC1405B TEL:805-498-2111 FAX:805-498-3804 WEB:http://www.semtech.com DESCRIPTION The SC1405B is a Dual-MOSFET Driver with an internal Overlap Protection Circuit to prevent shoot-through from VIN to GND in the main switching and synchronous MOSFET's. Each driver is capable of driving a 3000pF load in 15ns rise/fall time and has ULTRAFAST propagation delay from input transition to the gate of the power FET's. The Overlap Protection circuit ensures that the second FET does not turn on until the top FET source has reached a voltage low enough to prevent shoot-through. The delay between the bottom gate going low to the top gate transitioning to high is externally programmable via a capacitor for optimal reduction of switching losses at the operating frequency. The bottom FET may be disabled at light loads by keeping S_MOD low to trigger asynchronous operation, thus saving the bottom FET's gate drive current and inductor ripple current. An internal voltage reference allows threshold adjustment for an Output OverVoltage protection circuitry, independent of the PWM feedback loop. Under-Voltage-Lock-Out circuit is included to guarantee that both driver outputs are low when the 5V logic level is less than or equal to 4.4V (typ) at supply ramp up (4.35V at supply ramp down). A CMOS output provides status indication of the 5V supply. A low enable input places the IC in stand-by mode thereby reducing supply current to less than 10A. SC1405B is offered in a high pitch (.025" lead spacing) TSSOP package. PIN CONFIGURATION FEATURES * Fast rise and fall times (15ns with 3000pf load) * 14ns max. Propagation delay (BG going low) * Adaptive/programmable shoot-through protection * Wide input voltage range (4.5-25V) * Programmable delay between MOSFET's * Power saving asynchronous mode control * Output overvoltage protection/overtemp shutdown * Under-Voltage lock-out and power ready signal * Less than 10A stand-by current (EN=low) * Power ready output signal * Improved drive version of SC1405TS * High frequency (to 1.2MHz) operation allows use of small inductors and low cost caps in place of electrolytics APPLICATIONS * High Density/Fast transient power supplies * Motor Drives/Class-D amps * Portable computers ORDERING INFORMATION DEVICE (1) PACKAGE TEMP. RANGE (TJ) SC1405B TSSOP-14 0 - 125C Note: (1) Add suffix `TR' for tape and reel. BLOCK DIAGRAM Top View (14-Pin TSSOP) 1 (c) 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 HIGH SPEED SYNCHRONOUS POWER MOSFET SMART DRIVER SC1405B March 14, 2000 ABSOLUTE MAXIMUM RATINGS Parameter Symbol VCC Supply Voltage BST to PGND BST to DRN DRN to PGND OVP_S to PGND Input pin Continuous Power Dissipation VMAX5V VMAXBST-PGND VMAXBST-DRN VMAXDRN-PGN VMAXOVP_S-PGND CO Pd Conditions Maximum Units Tamb = 25C, TJ = 125C Tcase = 25C, TJ = 125C 7 30 7 25 10 -0.3 to 7.3 0.66 2.56 V V V V V V W Thermal Resistance Junction to Case JC 40 C/W Thermal Resistance Junction to Ambient JA 150 C/W TJ 0 to +125 C TSTG -65 to +150 C TLEAD 300 C Operating Temperature Range Storage Temperature Range Lead Temperature (Soldering) 10 sec NOTE: (1) Specification refers to application circuit in Figure 1. ELECTRICAL CHARACTERISTICS (DC OPERATING SPECIFICATIONS) Unless specified: -0 < J < 125C; VCC = 5V; 4V < VBST < 26V PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS VCC VCC 4.15 5 6.0 V Quiescent Current Iq_stby EN = 0V 10 A Quiescent Current, operating Iq_op VCC = 5V,CO=0V High Level Output Voltage VOH VCC = 4.6V, lload = 10mA Low Level Output Voltage VOL VCC < UVLO threshold, lload = 10A High Level Output Voltage VOH VCC = 4.6V, Cload = 100pF Low Level Output Voltage VOL VCC = 4.6V, Cload = 100pF POWER SUPPLY Supply Voltage 1 ma 4.55 V PRDY 4.5 0.1 0.2 V DSPS_DR 4.15 V 0.05 V 4.6 V UNDER-VOLTAGE LOCKOUT Start Threshold Hysteresis Logic Active Threshold 4.2 VSTART 0.05 VhysUVLO VACT 4.4 EN is low V 1.5 V 2 (c) 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 HIGH SPEED SYNCHRONOUS POWER MOSFET SMART DRIVER SC1405B March 14, 2000 ELECTRICAL CHARACTERISTICS (DC OPERATING SPECIFICATIONS) Cont. PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 1.145 1.2 1.255 OVERVOLTAGE PROTECTION Trip Threshold Hysteresis VTRIP 0.8 VhysOVP V V S_MOD High Level Input Voltage VIH Low Level Input Voltage VIL 2.0 V 0.8 V ENABLE High Level Input Voltage VIH Low Level Input Voltage VIL 2.0 V 0.8 V CO High Level Input Voltage VIH Low Level Input Voltage VIL 2.0 V 0.8 V THERMAL SHUTDOWN Over Temperature Trip Point TOTP 165 C Hysteresis THYST 10 C IPKH 2 A 1 .7 2 A 1.2 1.0 HIGH-SIDE DRIVER Peak Output Current Output Resistance RsrcTG RsinkTG duty cycle < 2%, tpw < 100s, TJ = 125C, VBST - VDRN = 4.5V, VTG = 4.0V (src)+VDRN or VTG = 0.5V (sink)+VDRN LOW-SIDE DRIVER Peak Output Current Output Resistance IPKL RsrcBG RsinkBG duty cycle < 2%, tpw < 100s, TJ = 125C VV_5 = 4.6V, VBG = 4V (src), or VLOWDR = 0.5V (sink) 3 (c) 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 HIGH SPEED SYNCHRONOUS POWER MOSFET SMART DRIVER SC1405B March 14, 2000 ELECTRICAL CHARACTERISTICS (DC OPERATING SPECIFICATIONS) Cont. PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS AC OPERATING SPECIFICATIONS HIGH-SIDE DRIVER rise time trTG, CI = 3nF, VBST - VDRN = 4.6V, 14 23 ns fall time tfTG CI = 3nF, VBST - VDRN = 4.6V, 12 19 ns propagation delay time, TG going high tpdhTG CI = 3nF, VBST - VDRN = 4.6V, C-delay=0 20 32 ns propagation delay time, TG going low tpdlTG CI = 3nF, VBST - VDRN = 4.6V, 15 24 ns rise time trBG CI = 3nF, VV_5 = 4.6V, 15 24 ns fall time trBG CI = 3nF, VV_5 = 4.6V, 13 21 ns propagation delay time BG going high tpdhBGHI CI = 3nF, VV_5 = 4.6V, DRN < 1V 12 19 ns progagation delay time BG going low tpdlBG CI = 3nF, VV_5 = 4.6V, 7 12 ns V_5 ramping up tpdhUVLO EN is High 10 us V_5 ramping down tpdlUVLO EN is High 10 us EN is transitioning from low to high tpdhPRDY V_5 > UVLO threshold, Delay measured from EN > 2.0V to PRDY > 3.5V 10 s EN is transitioning from high to low tpdhUVLO V_5 > UVLO threshold. Delay measured from EN < 0.8V tp PRDY < 10% of V_5 500 s CI = 100pf, V_5 = 4.6V, 20 ns LOW-SIDE DRIVER UNDER-VOLTAGE LOCKOUT PRDY DSPS_DR rise/fall time trDSPS_DR, tfDSPS_DR propagation delay, DSPS_DR going high tpdhDSPS_DR S_MOD goes high and BG goes high or S_MOD goes low 10 ns propagation delay DSPS_DR goes low tpdlDSPS_DR S_MOD goes high and BG goes low 10 ns tpdhOVP_S V_5 = 4.6V, TJ = 125C, OVP_S > 1.2V to BG > 90% of V_5 1 s OVERVOLTAGE PROTECTION propagation delay OVP_S going high 4 (c) 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 HIGH SPEED SYNCHRONOUS POWER MOSFET SMART DRIVER SC1405B March 14, 2000 PIN DESCRIPTION Pin # Pin Name Pin Function 1 OVP_S Overvoltage protection sense. External scaling resistors required to set protection threshold. 2 EN When high, this pin enables the internal circuitry of the device. When low, TG, BG and PRDY are forced low and the supply current (5V) is less than 10A. 3 GND Logic GND. 4 CO TTL-level input signal to the MOSFET drivers. 5 S_MOD When low, this signal forces BG to be low. When high, BG is not a function of this signal. 6 DELAY_C Sets the additional propagation delay for BG going low to TG going high. Total propagation delay= 20ns + 1ns/pF. 7 PRDY This pin indicates the status of 5V. When 5V is less than 4.4V(typ) this output is driven low. When 5V is greater than or equals to 4.4V(typ) this output is driven to 5V level. This output has a 10mA drive capability and 10A sink capability. 8 VCC +5V supply. A .22-1F ceramic capacitor should be connected from 5V to PGND very close to this pin. 9 BG Output drive for the synchronous MOSFET. 10 PGND Power ground. Connect to the synchronous FET power ground. 11 DSPS_DR Dynamic Set Point Switch Drive. TTL level output signal. When S_MOD is high, this pin follows the BG driver pin voltage. 12 DRN This pin connects to the junction of the switching and synchronous MOSFET's. This pin can be subjected to a -2V minimum relative to PGND without affecting operation. 13 TG Output gate drive for the switching (high-side) MOSFET. 14 BST Bootstrap pin. A capacitor is connected between BST and DRN pins to develop the floating bootstrap voltage for the high-side MOSFET. The capacitor value is typically between 0.1F and 1F (ceramic). NOTE: (1) All logic level inputs and outputs are open collector TTL compatible. PIN CONFIGURATION 5 (c) 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 HIGH SPEED SYNCHRONOUS POWER MOSFET SMART DRIVER SC1405B March 14, 2000 APPLICATION CIRCUIT Typical Distributed Power Supply INPUT POWER + + + MTB75N03 75A,30V D1 +5V 10uF,6.3V + 1N5819 .1uF .22uF 8 3 << P_READY >> PWM IN (20KHz-1MHz) 7 2 4 6 1 47pF 5 Vcc GND BST TG PRDY EN DRN CO DELAY_C BG OVP_S DSPS_DR S_MOD PGND 14 13 2.2 12 + + + MTB75N03 75A,30V 9 11 10 2.2 SC1405 << DSPS_DR Over-Voltage Sense <<< Output Feedback to PWM Controller Figure 1. TIMING DIAGRAM Figure 2. 6 (c) 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 (c) 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 7 Figure 3 B121 A121 VCC_L2 VID[4] 9 10 11 12 13 14 15 16 INPUT +5V 8 7 6 5 4 3 2 1 Vout/Clk switch S1 1 2 3 4 5 C5 C6 C7 6 1u,16V 1u,16V 1u,16V C8 1000uf,16V .01 C26 1.5k R6 100 R7 .1 C27 8 VID4 6 VID2 7 5 VID1 VID3 4 10k 20k R10 10 9 3 2 vcc5v 1 R38 10 R1 VID0 EN C12 C11 .1u C9 100UF 10uf U1 OC- OC+ Vid4 Vid3 Vid2 Vid1 Vid0 Rref NC Vcc5v 1000uf C10 SC1142CSW Comp FB Bgout FBG Enable GND Drv0 Vcc12v Drv1 Outv Long PCB Trace C23 .022 11 12 13 14 6k R8 VOUT 10 R43 10 R44 C55 300k .022 R11 C25 15 EN 16 17 18 19 20 .1 VIN VOUT * C33 C35 .1 10PF ovp_sens BST SC1405B U8 10PF TG PRDY DRN EN CO DELAY_C BG OVP_S DSPS_DR S_MOD PGND Vcc GND C34 SC1405B 11 10 9 12 13 14 5819 1K R16 11 10 9 12 13 5819 14 D10 R17 TBD 0 R42 0 R41 VIN 0 R13 * R12 51 * 51 FDB7030 Q4 IR7811 Q3 Q2 FDB7030 IR7811 Q1 R39 0 R40 C31 C4 22u,10V 1u,10V D11 BST TG PRDY DRN EN CO DELAY_C BG OVP_S DSPS_DR S_MOD PGND Vcc GND U7 C16 22u,10V R14 * 51 VOUT D2 R15 * 51 SS12 .6uh L2 .1 C58 D1 SS12 .6uh L1 .1 C56 22u,10V C32 22u,10V C29 22u,10V C24 22u,10V C22 22u,10V C21 22u,10V C20 22u,10V C19 22u,10V C18 22u,10V C14 22u,10V C13 1500uf C17 1500uf C30 Component not required when in synchronous mode SMOD=high 1u,10V C28 10 R9 5 7 2 4 6 1 8 3 .1 C57 5 7 2 4 6 1 8 3 C15 1u,10V VIN Date: B Size Title Sheet SC1142EVB-B Tuesday, June 08, 1999 Document Number PentiumII 1 SC1405B/SC1142 2-phase Synchronous Evaluation Board A120 A119 A118 A117 A116 A115 A114 A113 A112 A111 A110 A109 A108 A107 A106 A105 A104 A103 A102 A101 A100 A99 A98 A97 A96 A95 A94 A93 A92 A91 A90 A89 A88 A87 A86 A85 A84 A83 A82 A81 A80 A79 A78 A77 A76 A75 A74 A73 A72 A71 A70 A69 A68 A67 A66 A65 A64 A63 A62 A61 A60 A59 A58 A57 A56 A55 A54 A53 A52 A51 A50 A49 A48 A47 A46 A45 A44 A43 A42 A41 A40 A39 A38 A37 A36 A35 A34 A33 A32 A31 A30 A29 A28 A27 A26 A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 +12V VID[1] VID[2] GND $PIN116 $PIN115 $PIN114 GND $PIN112 $PIN111 $PIN110 GND $PIN108 $PIN107 $PIN106 GND $PIN104 $PIN103 $PIN102 GND $PIN100 $PIN99 $PIN98 GND $PIN96 $PIN95 $PIN94 GND $PIN92 $PIN91 $PIN90 GND $PIN88 $PIN87 $PIN86 GND $PIN84 $PIN83 $PIN82 GND $PIN80 $PIN79 $PIN78 GND $PIN76 $PIN75 $PIN74 GND $PIN72 $PIN71 $PIN70 GND $PIN68 $PIN67 $PIN66 GND $PIN64 $PIN63 $PIN62 GND $PIN60 $PIN59 $PIN58 GND $PIN56 $PIN55 $PIN54 GND $PIN52 $PIN51 $PIN50 GND $PIN48 $PIN47 $PIN46 GND $PIN44 $PIN43 $PIN42 GND $PIN40 $PIN39 $PIN38 GND $PIN36 $PIN35 $PIN34 GND $PIN32 $PIN31 $PIN30 GND $PIN28 $PIN27 $PIN26 GND $PIN24 $PIN23 $PIN22 GND $PIN20 $PIN19 $PIN18 GND $PIN16 Reserved THERMTRIP# GND TESTHI PWRGOOD TDO GND TDI IGNNE# FERR# GND A20M# IERR# VCC_VTT GND VCC_VTT J1 VID[0] VID[3] $PIN238 VCC_L2 $PIN236 $PIN235 $PIN234 VCC_L2 $PIN232 $PIN231 $PIN230 VCC5 $PIN228 $PIN227 $PIN226 VCC_CORE $PIN224 $PIN223 $PIN222 $PIN221 $PIN220 $PIN219 $PIN218 VCC_CORE $PIN216 $PIN215 $PIN214 VCC_CORE $PIN212 $PIN211 $PIN210 VCC_CORE $PIN208 $PIN207 $PIN206 VCC_CORE $PIN204 $PIN203 $PIN202 $PIN201 $PIN200 $PIN199 $PIN198 VCC_CORE $PIN196 $PIN195 $PIN194 VCC_CORE $PIN192 $PIN191 $PIN190 VCC_CORE $PIN188 $PIN187 $PIN186 VCC_CORE $PIN184 $PIN183 $PIN182 $PIN181 $PIN180 $PIN179 $PIN178 VCC_CORE $PIN176 $PIN175 $PIN174 VCC_CORE $PIN172 $PIN171 $PIN170 VCC_CORE $PIN168 $PIN167 $PIN166 VCC_CORE $PIN164 $PIN163 $PIN162 $PIN161 $PIN160 $PIN159 $PIN158 VCC_CORE $PIN156 $PIN155 $PIN154 VCC_CORE $PIN152 $PIN151 $PIN150 VCC_CORE $PIN148 $PIN147 $PIN146 VCC_CORE $PIN144 $PIN143 $PIN142 $PIN141 $PIN140 $PIN139 $PIN138 VCC_CORE $PIN136 $PIN135 $PIN134 VCC_CORE $PIN132 $PIN131 $PIN130 VCC_VTT $PIN128 $PIN127 $PIN126 VCC_VTT $PIN124 $PIN123 $PIN122 $PIN121 +5V B120 B119 B118 B117 B116 B115 B114 B113 B112 B111 B110 B109 B108 B107 B106 B105 B104 B103 B102 B101 B100 B99 B98 B97 B96 B95 B94 B93 B92 B91 B90 B89 B88 B87 B86 B85 B84 B83 B82 B81 B80 B79 B78 B77 B76 B75 B74 B73 B72 B71 B70 B69 B68 B67 B66 B65 B64 B63 B62 B61 B60 B59 B58 B57 B56 B55 B54 B53 B52 B51 B50 B49 B48 B47 B46 B45 B44 B43 B42 B41 B40 B39 B38 B37 B36 B35 B34 B33 B32 B31 B30 B29 B28 B27 B26 B25 B24 B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 Figure 3 - APPLICATION EVALUATION BOARD SCHEMATIC SC1405B/SC1142 Evaluation Board. 2-Phase synchronous, Freq.=1MHz Iout=30A max. (without external heatsink) SLOT1 connector included for operation with and simulating transient condition for the Pentium, Pentium IITM processors. of 1 Rev N/C March 14, 2000 HIGH SPEED SYNCHRONOUS POWER MOSFET SMART DRIVER SC1405B HIGH SPEED SYNCHRONOUS POWER MOSFET SMART DRIVER SC1405B March 14, 2000 BILL OF MATERIAL Item Qty Reference Value Manufacturer 1 3 C4,C15,C28 1u,10V, Cer. AVX, Murata 2 3 C5,C6,C7 1u,16V, Cer. AVX, Murata 3 1 C8 1000uF, 16V Nichicon, any 4 1 C9 100uF Nichicon, any 5 1 C10 1000uf Nichicon, any 7 1 C12 10uF Nichicon, any 8 12 C13,C14,C16,C18,C19,C20,C21,C22,C24,C29,C31,C32 9 2 C17,C30 1500uf 10 2 C23,C25 .022 Avx, any 11 1 C26 .01 Avx, any 12 7 C11,C27,C35,C55,C56,C57,C58 .1 Avx, any 13 2 C33,C34 10PF Avx, any 14 2 D1,D2 SS12 General Instruments, any 15 2 D10,D11 5819 General Instruments, any 16 1 J1 Input 17 2 L1,L2 .6uh 18 2 Q1,Q3 IR7811 Int. Rectifier (310) 252-7099 19 2 Q2,Q4 FDB7030 Fairchild Semi. (408) 822-2000 20 4 R1,R9,R43,R44 21 1 22 22u, 10V Murata (GRM235Y5V226Z010) Nichicon, Sanyo Falco, P/N: TO2508 (305) 662-9076 10 any R6 1.5k any 1 R7 100 any 23 1 R8 6k any 24 1 R10 20k any 25 1 R11 300k any 26 4 R12,R13,R14,R15 51 any, Required in asynch. operation 27 1 R16 1K any 28 1 R17 TBD any 29 1 R38 10k any 30 4 R39,R40,R41,R42 0 any 31 1 S1 Vout Selector switch 32 1 U2 Pentium IITM Slot 1 Connector 33 1 U1 SC1142CSW Semtech, (805) 499-2111 34 2 U7,U8 Digikey SC1405B 8 (c) 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 HIGH SPEED SYNCHRONOUS POWER MOSFET SMART DRIVER SC1405B March 14, 2000 APPLICATION INFORMATION: SC1405B is the newest and the higher speed version of the SC1405TS. It is designed to drive Low Rds_On power MOSFET's with ultra-low rise/fall times and propagation delays. As the switching frequencies of PWM controllers is increased to reduce power supply and Class-D amplifier volume and cost, fast rise and fall times are necessary to minimize switching losses (TOP MOSFET) and reduce Dead-time (BOTTOM MOSFET). While Low Rds_On MOSFET's present a 2 power saving in I R losses, the MOSFET's die area is larger and thus the effective input capacitance of the MOSFET is increased. Often a 50% decrease in Rds_On more than doubles the effective input gate charge, which must be supplied by the driver. The Rds_On power savings can be offset by the switching and dead-time losses with a sub-optimum driver. While discrete solution can achieve reasonable drive capability, implementing shoot-through, programmable delay and other housekeeping functions necessary for safe operation can become cumbersome and costly. The SC1405 family of parts presents a total solution for the high-speed, high power density applications. Wide input supply range of 4.5V-25V allows use in battery powered applications, new high voltage, distributed power servers as well as Class-D amplifiers. THEORY OF OPERATION The control input (CO) to the SC1405B is typically supplied by a PWM controller that regulates the power supply output. (See Application Evaluation Schematic, Figure 3). The timing diagram demonstrates the sequence of events by which the top and bottom drive signals are applied. The shoot-through protection is implemented by holding the bottom FET off until the voltage at the phase node (intersection of top FET source, the output inductor and the bottom FET drain) has dropped below 1V. This assures that the top FET has turned off and that a direct current path does not exist between the input supply and ground, a condition which both the top and bottom FET's are on momentarily. The top FET is also prevented from turning on until the bottom FET is off. This time is internally set to 20ns (typical) and may be increased by adding a capacitor to the C-Delay pin. The delay is approximately 1ns/pf in addition to the internal 20ns delay. The external capacitor may be needed if multiple High input capacitance MOSFET's are used in parallel and the fall time is substantially greater than 20ns. the parallel Shottkey or the bottom FET body diode will have to conduct during dead-time. LAYOUT GUIDELINES As with any high speed , high current circuit, proper layout is critical in achieving optimum performance of the SC1405B. The Evaluation board schematic (Refer to figure 3) shows a dual phase synchronous design with all surface mountable components. While components connecting to C-Delay, OVP_S, EN,S-MOD, DSPS_DR and PRDY are relatively noncritical, tight placement and short,wide traces must be used in layout of The Drives, DRN, and especially PGND pin. The top gate driver supply voltage is provided by bootstrapping the +5V supply and adding it the phase node voltage (DRN). Since the bootstrap capacitor supplies the charge to the TOP gate, it must be less than .5" away from the SC1405. Ceramic X7R capacitors are a good choice for supply bypassing near the chip. The Vcc pin capacitor must also be less than .5" away from the SC1405. The ground node of this capacitor, the SC1405 PGND pin and the Source of the bottom FET must be very close to each other, preferably with common PCB copper land and multiple vias to the ground plane (if used). The parallel Shottkey must be physically next to the Bottom FETS Drain and source. Any trace or lead inductance in these connections will drive current way from the Shottkey and allow it to flow through the FET's Body diode, thus reducing efficiency. PREVENTING INADVERTENT BOTTOM FET TURN-ON At high input voltages, (12V and greater) a fast turn-on of the top FET creates a positive going spike on the Bottom FET's gate through the Miller capacitance, Crss of the bottom FET. The voltage appearing on the gate due to this spike is: Vspike=Vin*crss/(Crass+ciss) Where Ciss is the input gate capacitance of the bottom FET. This is assuming that the impedance of the drive path is too high compared to the instantaneous impedance of the capacitors. (since dV/dT and thus the effective frequency is very high). If the BG pin of the SC1405B is very close to the bottom FET, Vspike will be reduced depending on trace inductance, rate if rise of current,etc. It must be noted that increasing the dead-time by high values of C-Delay capacitor will reduce efficiency since 9 (c) 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 HIGH SPEED SYNCHRONOUS POWER MOSFET SMART DRIVER SC1405B March 14, 2000 While not shown in Figure 3, a capacitor may be added from the gate of the Bottom FET to its source, preferably less than .1" away. This capacitor will be added to Ciss in the above equation to reduce the effective spike voltage, Vspike. The selection of the bottom MOSFET must be done with attention paid to the Crss/Ciss ratio. A low ratio reduces the Miller feedback and thus reduces Vspike. Also MOSFETs with higher Turn-on threshold voltages will conduct at a higher voltage and will not turn on during the spike. The MOSFET shown in the schematic (figure 3) has a 2 volt threshold and will require approximately 5 volts Vgs to be conducting, thus reducing the possibility of shoot-through. A zero ohm bottom FET gate resistor will obviously help keeping the gate voltage low. Ultimately, slowing down the top FET by adding gate resistance will reduce di/dt which will in turn make the effective impedance of the capacitors higher, thus allowing the BG driver to hold the bottom gate voltage low. RINGING ON THE PHASE NODE The top MOSFET source must be close to the bottom MOSFET drain to prevent ringing and the possibility of the phase node going negative. This frequency is determined by: Fring =1/(2 * Sqrt(Lst*Coss)) Where: Lst = The effective stray inductance of the top FET added to trace inductance of the connection between top FET's source and the bottom FET's drain added to the trace resistance of the bottom FET's ground connection. Coss=Drain to source capacitance of bottom FET. If there is a Shottkey used, the capacitance of the Shottkey is added to the value. Although this ringing does not pose any power losses due to a fairly high Q, it could cause the phase node to go too far negative, thus causing improper operation, double pulsing or at worst driver damage. This ringing is also an EMI nuisance due to its high resonant frequency. Adding a capacitor, typically 1000-2000pf, in parallel with Coss can often eliminate the EMI issue. If double pulsing is caused due to excessive ringing, placing 4.7-10 ohm resistor between the phase node and the DRN pin of the SC1405 should eliminate the double pulsing. Proper layout will guarantee minimum ringing and elimi- nate the need for external components. Use of SO8 or other surface mount MOSFETs will reduce lead inductance and their parasitic effects. ASYNCHRONOUS OPERATION The SC1405B can be configured to operate in Asynchronous mode by pulling S-MOD to logic LOW, thus disabling the bottom FET drive. This has the effect of saving power at light loads since the bottom FET's gate capacitance does not have to charged at the switching frequency. There can be a significant savings since the bottom driver can supply up to 2A pulses to the FET at the switching frequency. There is an additional efficiency benefit to operating in asynchronous mode. When operating in synchronous mode, the inductor current can go negative and flow in reverse direction when the bottom FET is on and the DC load is less than 1/2 inductor ripple current. At that point, the inductor core and wire losses, depending on the magnitude of the ripple current, can be quite significant. Operating in asynchronous mode at light loads effectively only charges the inductor by as much as needed to supply the load current, since the inductor never completely discharges at light loads. DC regulation can be an issue depending on the type of controller used and minimum load required to maintain regulation. If there are no Shottkeys used in parallel with bottom FET, the FET's body diode will need to conduct in asynchronous mode. The high voltage drop of this diode must be considered when determining the criteria for this mode of operation. DSPS DR This pin produces an output which is a logical duplicate of the bottom FET's gate drive, if S-MOD is held LOW. OVP_S/OVER TEMP SHUTDOWN Output over-voltage protection may be implemented on the SC1405 independent of the PWM controller . A voltage divider from the output is compared with the internal bandgap voltage of 1.2V (typical). Upon exceeding this voltage, the overvoltage comparator disables the top FET, while turning on the bottom FET to allow discharge of the output capacitors excessive voltage through the output inductor. There should be sufficient RC time constant as well as voltage headroom on the OVP_S pin to assure it does not enter overvoltage mode inadvertently. The SC1405 will shutdown if its Tj exceeds 165C. 10 (c) 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 HIGH SPEED SYNCHRONOUS POWER MOSFET SMART DRIVER SC1405B March 14, 2000 Performance diagrams, Application Evaluation Board. (Fig.3) Figure 4-Timing diagram: Ch1:CO input Ch2:TG drive Ch3:BG nonoverlap drive Ch4:phase node Iout=20A (10A/ phase) Refer to Eval. Schematic (fig.3) Figure 5-Timing diagram: Rise/Fall times Ch1:TG drive Ch2:BG drive Cursor:TpdhTG Iout=20A (10A/ phase) Refer to Eval. Schematic (fig.3) Vin = 12V,Vout = 1.6V Top FET=IR7811 FDB7030(BL) Qgd = 23nc 11 (c) 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 HIGH SPEED SYNCHRONOUS POWER MOSFET SMART DRIVER SC1405B March 14, 2000 OUTLINE DRAWING TSSOP-14 ECN00-924 12 (c) 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320