IDT85304-01PGGI8 - IDT, Integrated Device Technology Inc

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

IDT85304-01

LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL

FEBRUARY 2009

2006 Integrated Device Technology, Inc. DSC 6174/8c

IDT85304-01

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

LOW SKEW, 1-TO-5

DIFFERENTIAL-TO-3.3V

LVPECL FANOUT BUFFER

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

FEATURES:

• Five differential 3.3V LVPECL outputs

• Selectable differential CLK, xCLK, or LVPECL clock inputs

• CLK, xCLK pair can accept the following differential input levels:

LVDS, LVPECL, LVHSTL, SSTL, and HCSL

• PCLK, xPCLK supports the following input types: LVPECL, CML,

and SSTL

• Maximum output frequency: 650MHz

• Translates any single-ended input signal to 3.3V LVPECL levels

with resistor bias on xCLK input

• Output skew: 35ps (max.)

• Part-to-part skew: as low as 150ps

• Propagation delay: 2.1ns (max.)

• 3.3V operating supply

• Available in TSSOP package

DESCRIPTION:

The IDT85304-01 is a low skew, high performance 1-to-5 differential-to-

3.3V LVPECL clock generator-divider. It has two selectable clock inputs. The

CLK/ xCLK pair can accept most standard differential input levels. The PCLK/

xPCLK pair can accept LVPECL, CML, or SSTL input levels. The clock enable

is internally synchronized to eliminate runt pulses on the outputs during

asynchronous assertion/deassertion of the clock enable pin.

Guaranteed output and part-to-part skew characteristics make the IDT85304-

01 ideal for those applications that demand well-defined performance and

repeatability.

FUNCTIONAL BLOCK DIAGRAM

CLK_EN

CLK

xCLK

PCLK

xPCLK

CLK_SEL

xQ0

xQ1

xQ2

xQ3

xQ4

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

IDT85304-01

LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL

PIN CONFIGURATION

NOTE:

1. Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause

permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions above those indicated in the

operational sections of this specification is not implied. Exposure to absolute-

maximum-rated conditions for extended periods may affect device reliability.

ABSOLUTE MAXIMUM RATINGS(1)

Symbol Description Max Unit

VDD Power Supply Voltage 4.6 V

VIInput Voltage –0.5 to VDD+0.5 V

VOOutput Voltage –0.5 to VDD+0.5 V

θJA Package Thermal Impedance (0 lfpm) 92.6 °C/W

TSTG Storage Temperature –65 to +150 °C

CAPACITANCE(TA = +25°C, f = 1MHz, VIN = 0V)

Parameter Description Typ. Max. Unit

CIN Input Capacitance — 4 pF

RPULLUP Input Pullup Resistor 51 — KΩ

RPULLDOWN Input Pulldown Resistor 51 — KΩ

TSSOP

TOP VIEW

xQ0

xQ1

xQ2

xQ3

xQ4

VDD

CLK_EN

VDD

xPCLK

PCLK

VEE

xCLK

CLK

CLK_SEL

VDD

PIN DESCRIPTION(1)

Symbol Number Type Description

xQ0, Q0 1, 2 Output Differential Output Pair. LVPECL interface levels.

xQ1, Q1 3, 4 Output Differential Output Pair. LVPECL interface levels.

xQ2, Q2 5, 6 Output Differential Output Pair. LVPECL interface levels.

xQ3, Q3 7, 8 Output Differential Output Pair. LVPECL interface levels.

xQ4, Q4 9, 10 Output Differential Output Pair. LVPECL interface levels.

VDD 11, 18, 20 Power Positive Supply Pins

CLK_SEL 12 Input Pulldown Clock Select Input. When HIGH, selects PCLK / xPCLK inputs. When LOW, selects

CLK / xCLK inputs. LVTTL / LVCMOS interface levels.

CLK 13 Input Pulldown Non-Inverting Differential Clock Input

xCLK 14 Input Pullup Inverting Differential Clock Input

VEE 15 Power Negative Supply Pin

PCLK 16 Input Pulldown Non-Inverting Differential LVPECL Clock Input

xPCLK 17 Input Pullup Inverting Differential LVPECL Clock Input

CLK_EN 19 Input Pullup Synchronizing Clock Enable. When HIGH, clock outputs follow clock input. When

LOW, Q outputs are forced LOW, xQ outputs are forced HIGH. LVTTL / LVCMOS

interface levels.

NOTE:

1. Pullup and Pulldown refer to internal input resistors. See Capacitance table for typical values.

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

IDT85304-01

LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL

CONTROL INPUT FUNCTION TABLE(1,2)

Inputs Outputs

CLK_EN CLK_SEL Selected Source Q0:Q4 xQ0:xQ4

0 0 CLK, xCLK Disabled; LOW Disabled; HIGH

0 1 PCLK, xPCLK Disabled; LOW Disabled; HIGH

1 0 CLK, xCLK Enabled Enabled

1 1 PCLK, xPCLK Enabled Enabled

NOTES:

1. After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in the CLK_EN Timing Diagram below.

2. In active mode, the state of the outputs is a function of the CLK / xCLK and PCLK / xPCLK inputs as described in the Clock Input Function table.

CLOCK INPUT FUNCTION TABLE(1)

Inputs Outputs

CLK or PCLK xCLK or xPCLK Q0:Q4 xQ0:xQ4 Input to Output Mode Polarity

0 1 L H Differential to Differential Non-Inverting

1 0 H L Differential to Differential Non-Inverting

0 Biased(2) L H Single-Ended to Differential Non-Inverting

1 Biased(2) H L Single-Ended to Differential Non-Inverting

Biased(2) 0 H L Single-Ended to Differential Inverting

Biased(2) 1 L H Single-Ended to Differential Inverting

NOTES:

1. H = HIGH

L = LOW

2. See Single-Ended Signal diagram under Application Information at the end of this datasheet.

CLK_EN

xCLK, xPCLK

xQ0, xQ1, xQ2, xQ3, xQ4

≈

Disabled Enabled

≈

Q0, Q1, Q2, Q3, Q4

CLK, PCLK

CLK_EN Timing Diagram

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

IDT85304-01

LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL

NOTES:

1. For single-ended applications, the max. input voltage for PCLK / xPCLK is VDD + 0.3V.

2. Common mode voltage is defined as VIH.

3 . Outputs terminated with 50Ω to VDD - 2V.

DC ELECTRICAL CHARACTERISTICS, LVPECL

Symbol Parameter Test Conditions Min. Typ. Max. Unit

IIH Input Current HIGH PCLK VIN = VDD = 3.465V 150 μA

xPCLK VIN = VDD = 3.465V 5

IIL Input Current LOW PCLK VIN = 0V, VDD = 3.465V -5 μA

xPCLK VIN = 0V, VDD = 3.465V -150

VPP Peak-to-Peak Input Voltage 0.15 1.3 V

VCMR Common Mode Input Voltage(1,2) VEE + 1.5 VDD V

VOH Output Voltage HIGH(3) VDD - 1.4 VDD - 1 V

VOL Output Voltage LOW(3) VDD - 2 VDD - 1.7 V

VSWING Peak-to-Peak Output Voltage Swing 0.6 0.85 V

POWER SUPPLY CHARACTERISTICS

Symbol Parameter Test Conditions Min. Typ. Max. Unit

VDD Positive Supply Voltage 3.135 3.3 3.465 V

IEE Power Supply Current — — 5 5 mA

NOTES:

1. For single-ended applications, the max. input voltage for CLK / xCLK is VDD + 0.3V.

2. Common mode voltage is defined as VIH.

DC ELECTRICAL CHARACTERISTICS, DIFFERENTIAL

Symbol Parameter Test Conditions Min. Typ. Max. Unit

VPP Peak-to-Peak Input Voltage 0.15 1.3 V

VCMR Common Mode Input Voltage(1,2) 0.5 VDD - 0.85 V

IIH Input Current HIGH xCLK VIN = VDD = 3.465V 5 μA

CLK VIN = VDD = 3.465V 150

IIL Input Current LOW xCLK VIN = 0V, VDD = 3.465V -150 μA

CLK VIN = 0V, VDD = 3.465V -5

DC ELECTRICAL CHARACTERISTICS, LVCMOS / LVTTL

Symbol Parameter Test Conditions Min. Typ. Max. Unit

VIH Input Voltage, HIGH CLK_EN, 2 VDD + 0.3 V

CLK_SEL

VIL Input Voltage, LOW CLK_EN, -0.3 0.8 V

CLK_SEL

IIH Input Current HIGH CLK_EN VIN = VDD = 3.465V 5 μA

CLK_SEL VIN = VDD = 3.465V 150

IIL Input Current LOW CLK_EN VIN = 0V, VDD = 3.465V -150 μA

CLK_SEL VIN = 0V, VDD = 3.465V -5

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

IDT85304-01

LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL

NOTES:

1. Measured from the differential input crossingpoint to the differential output crossingpoint.

2. Defined as skew between outputs as the same supply voltage and with equal load conditions. Measured at the output differential crosspoints

3. Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each

device, the outputs are measured at the differential crosspoints.

4. This parameter is defined in accordance with JEDEC Standard 65.

AC ELECTRICAL CHARACTERISTICS

All parameters measured at 500MHz unless noted otherwise;

Cycle-to-cycle jitter = jitter on output; the part does not add jitter

Symbol Parameter Test Conditions Min. Typ. Max. Unit

FMAX Output Frequency 650 MHz

tPD Propagation Delay(1) f ≤ 650MHz 1 2.1 ns

tSK(O) Output Skew(2,4) 35 ps

tSK(PP) Part-to-Part Skew(3,4) 150 ps

tROutput Rise Time 20 - 80% @ 50MHz 300 700 ps

tFOutput Fall Time 20 - 80% @ 50MHz 300 700 ps

o d c Output Duty Cycle 48 50 52 %

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

IDT85304-01

LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL

VDD

VEE

xCLK, xPCLK

CLK, PCLK

VPP VCMR

Cross Points

LVPECL 50Ω

50Ω

Z = 50Ω

VDD

VEE = -1.3V ± 0.135V

VDD = 2V Z = 50Ω

xQx

Scope

xQx

xQy

tSK(0)

P ARAMETER MEASUREMENT INFORMATION

Output Skew

Output Load Test Circuit

Differential Input Level

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

IDT85304-01

LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL

VSWING

tRtF

20%

80% 80%

20%

Clock Outputs

xCLK, xPLK

CLK, PCLK

xQ0, xQ1, xQ2, xQ3, xQ4

Q0, Q1, Q2, Q3, Q4

tPD

xQ0, xQ1, xQ2, xQ3, xQ4

Q0, Q1, Q2, Q3, xQ4

odc =

tPERIOD

Pulse Width

tPERIOD

odc and tPERIOD

Propagation Delay

Input and Output Rise and Fall Time

P ARAMETER MEASUREMENT INFORMATION - CONTINUED

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

IDT85304-01

LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL

APPLICATION INFORMATION

WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE-ENDED LEVELS

The diagram below shows how the differential input can be wired to accept single-ended levels. The reference voltage VREF ∼ VDD/2 is generated by the

bias resistors R1, R2, and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to

position the VREF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, VREF should be 1.25V and R2/

R1 = 0.609.

Single-Ended Signal Driving Differential Input

VDD

VREF

0.1uF

CLK_IN

TERMINATION FOR LVPECL OUTPUTS

The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines.

FOUT and xFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to

ground) or current sources must be used for functionality. These outputs are designed to drive 50Ω transmission lines. Matched impedance techniques should

be used to maximize operating frequency and minimize signal distortion. The diagrams below show two different layouts which are recommended only as

guidelines. Other suitable clock layouts may exist. It is recommended that the board designers simulate to guarantee compatibility across all printed circuit and

clock component process variations.

LVPECL Output Termination, layout A LVPECL Output Termination, layout B

FOUT

50Ω50Ω

Zo = 50Ω

VDD - 2V

Zo = 50Ω

RTT

FIN

RTT =

(VOH + VOL / VDD - 2) - 2

FOUT

Zo = 50Ω

FIN

2Zo

3.3V

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

IDT85304-01

LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL

POWER CONSIDERATIONS

This section provides information on power dissipation and junction temperature for the IDT85304-01. Equations and example calculations are also provided.

POWER DISSIPATION:

The total power dissipation for the IDT85304-01is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation

for the VDD = 3.3V + 5% = 3.465V, which gives worst case results. Please refer to the following section, Calculations and Equations, for details on calculating

power dissipated in the load.

Power (core)MAX = VDD_MAX * IEE_MAX = 3.465 * 55mA = 190.57mW

Power (outputs)MAX = 30.2mW/Loaded Output Pair

If all outputs are loaded, the total power is 5 * 30.2mW = 151mW

Total Power_MAX (3.465V, with all outputs switching) = 190.57mW + 151mW = 341.57mW

JUNCTION TEMPERATURE:

Junction temperature (tJ) is the temperature at the junction of the bond wire and bond pad. It directly affects the reliability of the device. The maximum

recommended junction temperature for this device is 125°C.

The equation for is as follows: tJ = θJA * Pd_total + TA

tJ = Junction Temperature

θJA = Junction-to-Ambient Thermal Resistance

Pd_total = Total Device Power Dissipation (example calculation is in Power Dissipation, above)

TA = Ambient Temperature

In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance (θJA) must be used. Assuming a moderate air flow of 200

linear feet per minute and a multi-layer board, the appropriate value is 77.6°C/W per the following Thermal Resistance table. Therefore, tJ for an ambient

temperature of 85°C with all its outputs switching is:

85°C + 0.341W * 77.6°C/W = 111.5°C. This is well below the limit of 125°C.

This calculation is only an example. tJ will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single-

layer or multi-layer).

THERMAL RESISTANCE

θJA for 20-pin TSSOP, forced convection

θθ

θJA by Velocity (Linear Feet per mInute)

0 200 400 Unit

Multi-Layer PCB, JEDEC Standard Test boards 92.6 77.6 70.9 °C/W

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

IDT85304-01

LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL

CALCULATIONS AND EQUA TIONS

VDD

VOUT

VDD - 2V

LVPECL Output Driver Circuit and Termination

To calculate worst case power dissipation into the load, use the following equations, which assume a 50Ω load and a termination voltage of VDD – 2V.

For Logic HIGH: VOUT = VOH_MAX = VDD_MAX – 1V.

(VDD_MAX – VOH_MAX) = 1V

For Logic LOW: VOUT = VOL_MAX = VDD_MAX – 1.7V.

(VDD_MAX – VOL_MAX) = 1.7V

Pd_H is power dissipation when the output drives HIGH.

Pd_L is power dissipation when the output drives LOW.

Pd_H = {[ VOH_MAX – (VDD_MAX – 2V)] / RL} * (VDD_MAX – VOH_MAX) = {[ 2V – (VDD_MAX – VOH_MAX)] / RL} * (VDD_MAX – VOH_MAX) = [( 2V – 1V) / 50Ω] *

1V = 20mW.

Pd_L = {[ VOL_MAX – (VDD_MAX – 2V)] / RL} * (VDD_MAX – VOL_MAX) = {[ 2V – (VDD_MAX – VOL_MAX)] / RL} * (VDD_MAX – VOL_MAX) = [( 2V – 1.7V) / 50Ω] *

1.7V = 10.2mW.

Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

IDT85304-01

LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL

ORDERING INFORMATION

XXXXX XX X

Package Process

Device Type

Blank

85304-01 Low Skew, 1-to-5 Differential-to-3.3V LVPECL

Fanout Buffer

Thin Shrink Small Outline Package

TSSOP - Green

PGG

Commercial (0°C to +70°C)

Industrial (-40°C to +85°C)

CORPORATE HEADQUARTERS for SALES: for Tech Support:

6024 Silver Creek Valley Road 800-345-7015 or 408-284-8200 clockhelp@idt.com

San Jose, CA 95138 fax: 408-284-2775