®
Integrated Circuits Group
LH28F008SAT-85
Flash Memory
8M (1MB × 8)
(Model No.: LHF08S49)
Spec No.: EL105017A
Issue Date: October 5, 1999
PRODUCT SPECIFICATIONS
LHF08S49
●Handle this document carefully for it contains material protected by international
copyright law. Any reproduction, full or in part, of this material is prohibited
without the express written permission of the company.
●When using the products covered herein, please observe the conditions written herein
and the precautions outlined in the following paragraphs. In no event shall the
company be liable for any damages resulting from failure to strictly adhere to these
conditions and precautions.
(1) The products covered herein are designed and manufactured for the following
application areas. When using the products covered herein for the equipment
listed in Paragraph (2), even for the following application areas, be sure
to observe the precautions given in Paragraph (2). Never use the products
for the equipment listed in Paragraph (3).
･Office electronics
･Instrumentation and measuring equipment
･Machine tools
･Audiovisual equipment
･Home appliance
･Communication equipment other than for trunk lines
(2) Those contemplating using the products covered herein for the following
equipment which demands high reliability, should first contact a sales
representative of the company and then accept responsibility for incorporating
into the design fail-safe operation, redundancy, and other appropriate
measures for ensuring reliability and safety of the equipment and the overall system.
･Control and safety devices for airplanes, trains, automobiles, and other
transportation equipment
･Mainframe computers
･Traffic control systems
･Gas leak detectors and automatic cutoff devices
･Rescue and security equipment
･Other safety devices and safety equipment,etc.
(3) Do not use the products covered herein for the following equipment which
demands extremely high performance in terms of functionality, reliability, or accuracy.
･Aerospace equipment
･Communications equipment for trunk lines
･Control equipment for the nuclear power industry
･Medical equipment related to life support, etc.
(4) Please direct all queries and comments regarding the interpretation of the
above three Paragraphs to a sales representative of the company.
●Please direct all queries regarding the products covered herein to a sales
representative of the company.
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LHF08S49
CONTENTS
1 FEATURES ························ 2
2 PRODUCT OVERVIEW ························ 3
3 PRINCIPLES OF OPERATION ························ 8
4 BUS OPERATION ························ 9
5 COMMAND DEFINITIONS ························ 11
6 EXTENDED BLOCK ERASE/BYTE WRITE CYCLING ························ 13
7 AUTOMATED BYTE WRITE ························ 13
8 AUTOMATED BLOCK ERASE ························ 13
9 DESIGN CONSIDERATIONS ························ 13
10 ABSOLUTE MAXIMUM RATINGS ························ 18
11 OPERATING CONDITIONS ························ 18
12 DC CHARACTERISTICS ························ 18
13 CAPACITANCE ························ 19
14 AC CHARACTERISTICS ························ 20
15 BLOCK ERASE AND BYTE WRITE PERFORMANCE ························ 23
16 ALTERNATIVE CE#-CONTROLLED WRITES ························ 25
17 PACKAGING AND PACKING SPECIFICATION ························ 27
1
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LHF08S49
• Very High-Performance Read
- 85ns Maximum Access Time
• Operating Temperature
- 0˚C to +70˚C
• SRAM-Compatible Write Interface
• Hardware Data Protection Feature
- Erase/Write Lockout during Power Transi-
tions
• Industry Standard Packaging
- 40-Lead TSOP
• ETOX™* Nonvolatile Flash Technology
- 12V Byte Write/Block Erase
• CMOS Process (P-type silicon substrate)
• Not designed or rated as radiation hardened
1. FEATURES
•High-Density Symmetrically Blocked Architec-
ture
- Sixteen 64K-Byte Blocks
•Extended Cycling Capability
- 100,000 Block Erase Cycles
- 1.6 Million Block Erase Cycles per Chip
•Automated Byte Write and Block Erase
- Command User Interface
- Status Register
•System Performance Enhancements
- RY/BY# Status Output
- Erase Suspend Capability
•Deep-Powerdown Mode
- 10µA ICC Maximum
SHARP’s LH28F008SAT-85 8M-bit Flash Memory is the highest density nonvolatile read/write solution for solid state
storage. The LH28F008SA’s extended cycling, symmetrically blocked architecture, fast access time, write automation and
low power consumption provide a more reliable, lower power, lighter weight and higher performance alternative to tradi-
tional rotating disk technology. The LH28F008SAT-85 brings new capabilities to portable computing. Application and
operating system software stored in resident flash memory arrays provide instant-on rapid execute-in-place and protection
from obsolescence through in-system software updates. Resident software also extends system battery life and increases
reliability by reducing disk drive accesses.
For high density data acquisition applications, the LH28F008SAT-85 offers a more cost-effective and reliable alternative to
SRAM and battery. Traditional high density embedded applications, such as telecommunications, can take advantage of
the LH28F008SA’s nonvolatility, blocking and minimal system code requirements for flexible firmware and modular soft-
ware designs.
The LH28F008SAT-85 is offered in 40-lead TSOP (standard) package. Pin assignments simplify board layout when inte-
grating multiple devices in a flash memory array or subsystem. This device uses an integrated Command User Interface
and state machine for simplified block erasure and byte write. The LH28F008SAT-85 memory map consists of 16 sepa-
rately erasable 64K-byte blocks.
SHARP’s LH28F008SAT-85 employs advanced CMOS circuitry for systems requiring low power consumption and noise
immunity. Its 85ns access time provides superior performance when compared with magnetic storage media. A deep
powerdown mode lowers power consumption to 50µW maximum thru VCC, crucial in portable computing, handheld instru-
mentation and other low-power applications. The RP# power control input also provides absolute data protection during
system powerup/down.
* ETOX is a trademark of Intel Corporation.
LH28F008SAT-85
8M-BIT (1MBit x 8) FLASH MEMORY
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LHF08S49
2. PRODUCT OVERVIEW
The LH28F008SAT-85 is a high-performance 8M-bit
(8,388,608 bit) memory organized as 1M-byte (1,048,576
bytes) of 8 bits each. Sixteen 64K-Byte (65,536 byte)
blocks are included on the LH28F008SAT-85. A memory
map is shown in Figure 4 of this specification. A block erase
operation erases one of the sixteen blocks of memory in
typically 1.6s, independent of the remaining blocks. Each
block can be independently erased and written 100,000
cycles. Erase Suspend mode allows system software to
suspend block erase to read data or execute code from any
other block of the LH28F008SAT-85.
The LH28F008SAT-85 is available in the 40-lead TSOP
(Thin Small Outline Package, 1.2mm thick) package.
Pinouts are shown in Figure 2 of this specification.
The Command User Interface serves as the interface be-
tween the microprocessor or microcontroller and the inter-
nal operation of the LH28F008SAT-85.
Byte Write and Block Erase Automation allow byte write
and block erase operations to be executed using a two-
write command sequence to the Command User Interface.
The internal Write State Machine (WSM) automatically ex-
ecutes the algorithms and timings necessary for byte write
and block erase operations, including verifications, thereby
unburdening the microprocessor or microcontroller. Writing
of memory data is performed in byte increments typically
within 8µs.IPP byte write and block erase currents are
10mA typical, 30mA maximum. VPP byte write and
block erase voltage is 11.4V to 12.6V.
The Status Register indicates the status of the WSM and
when the WSM successfully completes the desired byte
write or block erase operation.
The RY/BY# output gives an additional indicator of WSM
activity, providing capability for both hardware signal of sta-
tus (versus software polling) and status masking (interrupt
masking for background erase, for example). Status polling
using RY/BY# minimizes both CPU overhead and system
power consumption. When low, RY/BY# indicates that the
WSM is performing a block erase or byte write operation.
RY/BY# high indicates that the WSM is ready for new com-
mands, block erase is suspended or the device is in deep
powerdown mode.
Maximum access time is 85ns (tACC) over the commercial
temperature range (0˚C to +70˚C) and over VCC supply volt-
age range (4.5V to 5.5V and 4.75V to 5.25V). ICC active
current (CMOS Read) is 20mA typical, 35mA maximum
at 8MHz.
When the CE# and RP# pins are at VCC, the ICC CMOS
Standby mode is enabled.
ADeep Powerdown mode is enabled when the RP# pin is
at GND, minimizing power consumption and providing write
protection. ICC current in deep powerdown is 10µA
maximum. Reset time of 400ns is required from RP#
switching high until outputs are valid to read attempts.
Equivalently, the device has a wake time of 1µs from RP#
high until writes to the Command User Interface are
recognized by the LH28F008SAT-85. With RP# at GND,
the WSM is reset and the Status Register is cleared.
Please do not execute reprogramming "0" for the bit which
has already been programed "0". Overwrite operation may
generate unerasable bit. In case of reprogramming "0" to
the data which has been programed "1".
•Program "0" for the bit in which you want to change data
from "1" to "0".
•Program "1" for the bit which has already been
programmed "0".
For example, changing data from "10111101" to
"10111100" requires "11111110" programming.
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LHF08S49
INPUT
BUFFER
ADDRESS
LATCH
ADDRESS
COUNTER
Y-DECODER
X-DECODER
Y-GATING WRITE STATE
MACHINE PROGRAM/ERASE
VOLTAGE SWITCH
COMMAND
USER
INTERFACE
OUTPUT
BUFFER INPUT
BUFFER
IDENTIFIER
REGISTER
STATUS
REGISTER
DATA
COMPARATOR
16
64K-BYTE
BLOCKS
I/O LOGIC
CE#
WE#
OE#
RP#
RY/BY#
V
PP
V
CC
GND
OUTPUT
MULTIPLEXER
DATA
REGISTER
DQ0-DQ7
A0-A19
Figure 1. Block Diagram
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LHF08S49
Table 1. Pin Description
Name and Function
GROUND
GND
DEVICE POWER SUPPLY (5V±0.5V, 5V±0.25V)
VCC
BLOCK ERASE/BYTE WRITE POWER SUPPLY: for erasing blocks of
the array or writing bytes of each block.
With VPP<VPPLMAX, memory contents cannot be altered.
READY/BUSY#: Indicates the status of the internal Write State Machine.
When low, it indicates that the WSM is performing a block erase or byte
write operation. RY/BY# high indicates that the WSM is ready for new
commands, block erase is suspended or the device is in deep
powerdown mode. RY/BY# is always active and does NOT float to tri-state
off when the chip is deselected or data outputs are disabled.
OUTPUTRY/BY#
WRITE ENABLE: Controls writes to the Command User Interface and
array blocks. WE# is active low. Addresses and data are latched on the
rising edge of the WE# pulse.
INPUTWE#
OUTPUT ENABLE: Gates the device's outputs through the data buffers
during a read cycle. OE# is active low.
INPUTOE#
RESET/POWERDOWN: Puts the device in deep powerdown mode and
resets internal automation. RP# is active low; RP# high gates normal
operation. RP# also locks out block erase or byte write operations when
active low, providing data protection during power transitions.
INPUTRP#
CHIP ENABLE: Activates the device's control logic input buffers
decoders, and sense amplifiers. CE# is active low; CE# high deselects the
memory device and reduces power consumption to standby levels.
INPUT
CE#
DATA INPUT/OUTPUTS: Inputs data and commands during Command
User Interface write cycles; outputs data during memory array, Status
Register and Identifier read cycles. The data pins are active high and float
to tri-state off when the chip is deselected or the outputs are disabled.
Data is internally latched during a write cycle.
INPUT/OUTPUTDQ0-DQ7
ADDRESS INPUTS: for memory addresses. Addresses are internally
latched during a write cycle.
INPUT
A0-A19
Symbol Type
VPP NOTE:
SUPPLY
SUPPLY
SUPPLY
NC NO CONNECT: Lead is not internal connected; recommend to be floated.
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LHF08S49
Figure 2. TSOP Lead Configuration
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
A
5
RP#
CE#
WE#
NC
NC
OE#
RY/BY#
DQ
7
GND
GND
40 LEAD TSOP
STANDARD PINOUT
10mm x 20mm
TOP VIEW
A
2
A
3
A
7
A
0
A
19
A
17
A
12
A
14
A
16
A
18
A
10
A
6
A
1
A
9
A
15
A
13
A
11
A
8
A
4
V
CC
V
CC
V
PP
DQ
0
DQ
2
DQ
4
DQ
1
DQ
6
DQ
3
DQ
5
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LHF08S49
FLSHDCS#
PSTART#
80386SL
82360SL
Controller
LATCH
XCVR
LH28F008SA
SA0-16,
LA17-20
SBHE#
PM/IO#
PW/R#
SD0-15
CS#
TO OTHER
LH28F008SA's
RD#
CS1#
CS2#
CS3#
RP#
RP#
TO OTHER
LH28F008SA's
PAIRS
A0-19
SA1-16,
LA17-20
A0-19
VPP
WE#
PCMD#
PRDY#
VGACS#
RESET#
POWERGOOD
RY/BY1#
RY/BY2#
RY/BY#
FROM OTHER
LH28F008SA's
RY/BY# RP# RY/BY# RP#
VPP
VPP
RESET#
GPIO
Switch
12V
OE#
WR# WE#
OE#
CE#
CE#
CSL1#
CSH1#
FD0-7
INT
EPLD(s)
SA0,
LA21-22
RD#
WR#
FD8-15
SBHE#
DQ0-7
DQ0-7
CTRL
RY/BY#
LH28F008SA
80386SL µPLD
Figure 3. LH28F008SA Array Interface to 386SL Microprocessor Superset through PI Bus (Including RY/BY#
Masking and Selective Powerdown), for DRAM Backup during System SUSPEND, Resident O/S and Applications
and Motherboard Solid-State Disk.
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8LHF08S49
Figure 4. Memory Map
3. PRINCIPLES OF OPERATION
The LH28F008SAT-85 includes on-chip write automation to
manage write and erase functions. The Write State Ma-
chine allows for: 100% TTL-level control inputs; fixed power
supplies during block erasure and byte write; and minimal
processor overhead with SRAM-like interface timings.
After initial device powerup, or after return from deep
powerdown mode (see Bus Operations), the
LH28F008SAT-85 functions as a read-only memory. Ma-
nipulation of external memory-control pins allow array read,
standby and output disable operations. Both Status Regis-
ter and intelligent identifiers can also be accessed through
the Command User Interface when VPP=VPPL.
This same subset of operations is also available when high
voltage is applied to the VPP pin. In addition, high voltage on
VPP enables successful block erasure and byte writing of
the device. All functions associated with altering memory
contents — byte write, block erase, status and intelligent
identifier — are accessed via the Command User Interface
and verified thru the Status Register.
Commands are written using standard microprocessor write
timings. Command User Interface contents serve as input
to the WSM, which controls the block erase and byte write
circuitry. Write cycles also internally latch addresses and
data needed for byte write or block erase operations. With
the appropriate command written to the register, standard
microprocessor read timings output array data, access the
intelligent identifier codes, or output byte write and block
erase status for verification.
Interface software to initiate and poll progress of internal
byte write and block erase can be stored in any of the
LH28F008SAT-85 blocks. This code is copied to, and ex-
ecuted from, system RAM during actual flash memory up-
date. After successful completion of byte write and/or block
erase, code/data reads from the LH28F008SAT-85 are
again possible via the Read Array command. Erase sus-
pend/resume capability allows system software to suspend
block erase to read data and execute code from any other
block.
64K-byte Block
64K-byte Block
64K-byte Block
64K-byte Block
64K-byte Block
64K-byte Block
64K-byte Block
64K-byte Block
64K-byte Block
64K-byte Block
64K-byte Block
64K-byte Block
64K-byte Block
64K-byte Block
64K-byte Block
64K-byte Block
FFFFF
F0000
EFFFF
E0000
DFFFF
CFFFF
D0000
C0000
BFFFF
B0000
AFFFF
A0000
9FFFF
90000
8FFFF
80000
7FFFF
70000
6FFFF
60000
5FFFF
50000
4FFFF
40000
3FFFF
30000
2FFFF
20000
1FFFF
10000
0FFFF
00000
Command User Interface and Write Automation
An on-chip state machine controls block erase and byte
write, freeing the system processor for other tasks. After re-
ceiving the Erase Setup and Erase Confirm commands, the
state machine controls block pre-conditioning and erase,
returning progress via the Status Register and RY/BY#
output. Byte write is similarly controlled, after destination
address and expected data are supplied. The program and
erase algorithms of past standard Flash memories are now
regulated by the state machine, including pulse repetition
where required and internal verification and margining of
data.
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9LHF08S49
The first task is to write the appropriate read mode com-
mand to the Command User Interface (array, intelligent
identifier, or Status Register). The LH28F008SAT-85 auto-
matically resets to Read Array mode upon initial device
powerup or after exit from deep powerdown. The
LH28F008SAT-85 has four control pins, two of which must
be logically active to obtain data at the outputs. Chip Enable
(CE#) is the device selection control, and when active en-
ables the selected memory device. Output Enable (OE#) is
the data input/output (DQ0-DQ7) direction control, and
when active drives data from the selected memory onto the
I/O bus. RP# and WE# must also be at VIH. Figure 8 illus-
trates read bus cycle waveforms.
Output Disable
With OE# at a logic-high level (VIH), the device outputs are
disabled. Output pins (DQ0-DQ7) are placed in a high-im-
pedance state.
Standby
CE# at a logic-high level (VIH) places the LH28F008SAT-85
in standby mode. Standby operation disables much of the
LH28F008SA’s circuitry and substantially reduces device
power consumption. The outputs (DQ0-DQ7) are placed in a
high-impedence state independent of the status of OE#. If
the LH28F008SAT-85 is deselected during block erase or
byte write, the device will continue functioning and consum-
ing normal active power until the operation completes.
Data Protection
Depending on the application, the system designer may
choose to make the VPP power supply switchable (available
only when memory byte writes/block erases are required) or
hardwired to VPPH. When VPP=VPPL, memory contents
cannot be altered. The LH28F008SAT-85 Command User
Interface architecture provides protection from unwanted
byte write or block erase operations even when high voltage
is applied to VPP. Additionally, all functions are disabled
whenever VCC is below the write lockout voltage VLKO, or
when RP# is at VIL. The LH28F008SAT-85 accommodates
either design practice and encourages optimization of the
processor-memory interface.
The two-step byte write/block erase Command User Inter-
face write sequence provides additional software write pro-
tection.
4. BUS OPERATION
Flash memory reads, erases and writes in-system via the
local CPU. All bus cycles to or from the flash memory con-
form to standard microprocessor bus cycles.
Read
The LH28F008SAT-85 has three read modes. The memory
can be read from any of its blocks, and information can be
read from the intelligent identifier or Status Register. VPP
can be at either VPPL or VPPH.
Table 2. Bus Operations(1,2)
NOTES:
1. Refer to DC Characteristics. When VPP=VPPL, memory contents can be read but not written or erased.
2. X can be VIL or VIH for control pins and addresses, and VPPL or VPPH for VPP. See DC Characteristics for VPPL and VPPH voltages.
3. RY/BY# is VOL when the Write State Machine is executing internal block erase or byte write algorithms. It is VOH when the WSM is
not busy, in Erase Suspend mode or deep powerdown mode.
4. Command writes involving block erase or byte write are only successfully executed when VPP=VPPH.
5. Refer to Table 3 for valid DIN during a write operation.
6. Don't use the timing both OE# and WE# are VIL.
X
D
IN
X
X
4,5,6Write
V
OH
A2H
X
Intelligent Identifier (Device)
89H
X
V
IL
V
IH
Intelligent Identifier (Mfr)
High Z
X
X
XX
X
V
IL
V
IL
V
IL
V
IL
V
IL
V
IL
V
IH
V
IH
V
IH
V
IH
V
IH
V
OH
V
OH
X
X
XX
High Z
High Z
V
IL
V
IL
V
IL
Deep PowerDown
Standby
Output Disable
Read
Mode Notes CE# A
0
V
PP
DQ
0-7
6D
OUT
V
IH
V
IH
V
IH
V
IH
V
IH
V
IH
V
IH
XX
X
X
X
X
X
RP# OE# WE# RY/BY#
(3)
V
IH
V
IL
6
6
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10LHF08S49
Deep Power-Down
The LH28F008SAT-85 offers a deep powerdown feature,
entered when RP# is at VIL. Current draw thru VCC is 10µA
maximum in deep powerdown mode, with current draw
through VPP maximal 5µA. During read modes, RP#-low
deselects the memory, places output drivers in a high-
impedence state and turns off all internal circuits. The
LH28F008SAT-85 requires time tPHQV (see AC Character-
istics-Read-Only Operations) after return from powerdown
until initial memory access outputs are valid. After this
wakeup interval, normal operation is restored. The
Command User Interface is reset to Read Array, and the
upper 5bits of the Status Register are cleared to value
10000, upon return to normal operation.
During block erase or byte write modes, RP# low will abort
either operation. Memory contents of the block being al-
tered are no longer valid as the data will be partially written
or erased. Time tPHWL after RP# goes to logic-high (VIH) is
required before another command can be written.
Intelligent Identifier Operation
The intelligent identifier operation outputs the manufacturer
code, 89H; and the device code, A2H for the
LH28F008SAT-85. The system CPU can then automatically
match the device with its proper block erase and byte write
algorithms.
The manufacturer- and device-codes are read via the Com-
mand User Interface. Following a write of 90H to the Com-
mand User Interface, a read from address location 00000H
outputs the manufacturer code (89H). A read from address
00001H outputs the device code (A2H). It is not necessary
to have high voltage applied to VPP to read the intelligent
identifiers from the Command User Interface.
Write
Writes to the Command User Interface enable reading of
device data and intelligent identifiers. They also control in-
spection and clearing of the Status Register. Additionally,
when VPP=VPPH, the Command User Interface controls
block erasure and byte write. The contents of the interface
register serve as input to the internal state machine.
Table 3. Command Definitions(6)
NOTES:
1. Bus operations are defined in Table 2.
2. IA=Identifier Address: 00H for manufacturer code, 01H for device code.
BA=Address within the block being erased.
WA=Address of memory location to be written.
3. SRD=Data read from Status Register. See Table 4 for a description of the Status Register bits.
WD=Data to be written at location WA. Data is latched on the rising edge of WE#.
IID=Data read from intelligent identifiers.
4. Following the intelligent identifier command, two read operations access manufacture and device codes.
5. Either 40H or 10H are recognized by the WSM as the Byte Write Setup command.
6. Commands other than those shown above are reserved by SHARP for future device implementations and should not be used.
Operation(1)
WD
WA
Write
10H
WAWrite
5
2
Alternate Byte Write Setup/Write
WDWA
Write40HWAWrite
5
2
Byte Write Setup/Write
D0H
X
Write
Write
B0HX
Write
Write
Write
Write
Write
Write
X
X
X
X
X
2
2
Erase Suspend/Erase Resume
Erase Setup/Erase Confirm D0HBA
20HBA
50H
70H
90H
FFH
Read
Read IA
SRD
IID
4
2
3
1
1
Clear Status Register
Read Status Register
Intelligent Identifier
Read Array/Reset
Command
Bus
Cycles
Req'd
Notes First Bus Cycle Second Bus Cycle
Address(2)Data(3) Operation(1) Address(2) Data(3)
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11LHF08S49
The Command User Interface itself does not occupy an ad-
dressable memory location. The interface register is a latch
used to store the command and address and data informa-
tion needed to execute the command. Erase Setup and
Erase Confirm commands require both appropriate com-
mand data and an address within the block to be erased.
The Byte Write Setup command requires both appropriate
command data and the address of the location to be written,
while the Byte Write command consists of the data to be
written and the address of the location to be written.
The Command User Interface is written by bringing WE# to
a logic-low level (VIL) while CE# is low. Addresses and data
are latched on the rising edge of WE#. Standard micropro-
cessor write timings are used.
Refer to AC Write Characteristics and the AC Waveforms
for Write Operations, Figure 9, for specific timing param-
eters.
5. COMMAND DEFINITIONS
When VPPL is applied to the VPP pin, read operations from
the Status Register, intelligent identifiers, or array blocks
are enabled. Placing VPPH on VPP enables successful byte
write and block erase operations as well.
Device operations are selected by writing specific com-
mands into the Command User Interface. Table 3 defines
the LH28F008SAT-85 commands.
Read Array Command
Upon initial device powerup and after exit from deep
powerdown mode, the LH28F008SAT-85 defaults to Read
Array mode. This operation is also initiated by writing FFH
into the Command User Interface. Microprocessor read
cycles retrieve array data. The device remains enabled for
reads until the Command User Interface contents are al-
tered. Once the internal Write State Machine has started a
block erase or byte write operation, the device will not rec-
ognize the Read Array command, until the WSM has com-
pleted its operation. The Read Array command is functional
when VPP=VPPL or VPPH.
Intelligent Identifier Command
The LH28F008SAT-85 contains an intelligent identifier op-
eration, initiated by writing 90H into the Command User In-
terface. Following the command write, a read cycle from ad-
dress 00000H retrieves the manufacturer code of 89H. A
read cycle from address 00001H returns the device code of
A2H. To terminate the operation, it is necessary to write
another valid command into the register. Like the Read Ar-
ray command, the intelligent identifier command is func-
tional when VPP=VPPL or VPPH.
Table 4. Status Register Definitions
SR. 7=WRITE STATE MACHINE STATUS (WSMS)
1=Ready
0=Busy
SR. 6=ERASE SUSPEND STATUS (ESS)
1=Erase Suspended
0=Erase in Progress/Completed
SR. 5=ERASE STATUS (ES)
1=Error in Block Erasure
0=Successful Block Erase
SR. 4=BYTE WRITE STATUS (BWS)
1=Error in Byte Write
0=Successful Byte Write
SR. 3=VPP STATUS (VPPS)
1=VPP Low Detect; Operation Abort
0=VPP OK
SR. 2-0=RESERVED FOR FUTURE ENHANCEMENTS (R)
These bits are reserved for future use and should be masked
out when polling the Status Register.
NOTES:
RY/BY# or the Write State Machine Status bit must first be
checked to determine byte write or block erase completion, be-
fore the Byte Write or Erase Status bit are checked for success.
If the Byte Write AND Erase Status bits are set to "1"s during a
block erase attempt, an improper command sequence was en-
tered. Attempt the operation again.
If VPP low status is detected, the Status Register must be cleared
before another byte write or block erase operation is attempted.
The VPP Status bit, unlike an A/D converter, does not provide
continuous indication of VPP level. The WSM interrogates the
VPP level only after the byte write or block erase command se-
quences have been entered and informs the system if VPP has
not been switched on. The VPP Status bit is not guaranteed to
report accurate feedback between VPPL and VPPH.
WSMS
01234567
RRRVPPSBWSESESS
sharp
12LHF08S49
Read Status Register Command
The LH28F008SAT-85 contains a Status Register which
may be read to determine when a byte write or block erase
operation is complete, and whether that operation com-
pleted successfully. The Status Register may be read at
any time by writing the Read Status Register command
(70H) to the Command User Interface. After writing this
command, all subsequent read operations output data from
the Status Register, until another valid command is written
to the Command User Interface. The contents of the Status
Register are latched on the falling edge of OE# or CE#,
whichever occurs last in the read cycle. OE# or CE# must
be toggled to VIH before further reads to update the Status
Register latch. The Read Status Register command func-
tions when VPP=VPPL or VPPH.
Clear Status Register Command
The Erase Status and Byte Write Status bits are set to "1"s
by the Write State Machine and can only be reset by the
Clear Status Register Command. These bits indicate vari-
ous failure conditions (see Table 4). By allowing system
software to control the resetting of these bits, several opera-
tions may be performed (such as cumulatively writing sev-
eral bytes or erasing multiple blocks in sequence). The Sta-
tus Register may then be polled to determine if an error oc-
curred during that sequence. This adds flexibility to the way
the device may be used.
Additionally, the VPP Status bit (SR.3) MUST be reset by
system software before further byte writes or block erases
are attempted. To clear the Status Register, the Clear Sta-
tus Register command (50H) is written to the Command
User Interface. The Clear Status Register command is func-
tional when VPP=VPPL or VPPH.
Erase Setup/Erase Confirm Commands
Erase is executed one block at a time, initiated by a two-
cycle command sequence. An Erase Setup command
(20H) is first written to the Command User Interface, fol-
lowed by the Erase Confirm command (D0H). These com-
mands require both appropriate sequencing and an ad-
dress within the block to be erased to FFH. Block precondi-
tioning, erase and verify are all handled internally by the
Write State Machine, invisible to the system. After the two-
command erase sequence is written to it, the
LH28F008SAT-85 automatically outputs Status Register
data when read (see Figure 6; Block Erase Flowchart). The
CPU can detect the completion of the erase event by ana-
lyzing the output of the RY/BY# pin, or the WSM Status bit
of the Status Register.
When erase is completed, the Erase Status bit should be
checked. If erase error is detected, the Status Register
should be cleared. The Command User Interface remains in
Read Status Register mode until further commands are is-
sued to it.
This two-step sequence of set-up followed by execution en-
sures that memory contents are not accidentally erased.
Also, reliable block erasure can only occur when
VPP=VPPH. In the absence of this high voltage, memory
contents are protected against erasure. If block erase is
attempted while VPP=VPPL, the VPP Status bit will be set to
"1". Erase attempts while VPPL<VPP<VPPH produce
spurious results and should not be attempted.
Erase Suspend/Erase Resume Commands
The Erase Suspend command allows block erase interrup-
tion in order to read data from another block of memory.
Once the erase process starts, writing the Erase Suspend
command (B0H) to the Command User Interface requests
that the WSM suspend the erase sequence at a predeter-
mined point in the erase algorithm. The LH28F008SAT-85
continues to output Status Register data when read, after
the Erase Suspend command is written to it. Polling the
WSM Status and Erase Suspend Status bits will determine
when the erase operation has been suspended (both will be
set to "1"). RY/BY# will also transition to VOH.
At this point, a Read Array command can be written to the
Command User Interface to read data from blocks other
than that which is suspended. The only other valid com-
mands at this time are Read Status Register (70H) and
Erase Resume (D0H), at which time the WSM will continue
with the erase process. The Erase Suspend Status and
WSM Status bits of the Status Register will be automatically
cleared and RY/BY# will return to VOL. After the Erase Re-
sume command is written to it, the LH28F008SAT-85 auto-
matically outputs Status Register data when read (see Fig-
ure 7; Erase Suspend/Resume Flowchart). VPP must re-
main at VPPH while the LH28F008SAT-85 is in Erase Sus-
pend.
sharp
13LHF08S49
Byte Write Setup/Write Commands
Byte write is executed by a two-command sequence. The
Byte Write Setup command (40H or 10H) is written to the
Command User Interface, followed by a second write
specifying the address and data (latched on the rising edge
of WE#) to be written. The WSM then takes over, controlling
the byte write and write verify algorithms internally. After the
two-command byte write sequence is written to it, the
LH28F008SAT-85 automatically outputs Status Register
data when read (see Figure 5; Byte Write Flowchart). The
CPU can detect the completion of the byte write event by
analyzing the output of the RY/BY# pin, or the WSM Status
bit of the Status Register. Only the Read Status Register
command is valid while byte write is active.
When byte write is complete, the Byte Write Status bit
should be checked. If byte write error is detected, the Status
Register should be cleared. The internal WSM verify only
detects errors for "1"s that do not successfully write to "0"s.
The Command User Interface remains in Read Status Reg-
ister mode until further commands are issued to it. If byte
write is attempted while VPP=VPPL, the VPP Status bit will be
set to "1". Byte write attempts while VPPL<VPP<VPPH
produce spurious results and should not be attempted.
6. EXTENDED BLOCK ERASE/BYTE WRITE
CYCLING
The LH28F008SAT-85 is designed for 100,000 byte write/
block erase cycles on each of the sixteen 64K-byte blocks.
Low electric fields, advanced oxides and minimal oxide
area per cell subjected to the tunneling electric field com-
bine to greatly reduce oxide stress and the probability of
failure. A 20M-byte solid-state drive using an array of
LH28F008SA’s has a MTBF (Mean Time Between Failure)
of 33.3 million hours(1), over 600 times more reliable than
equivalent rotating disk technology.
7. AUTOMATED BYTE WRITE
The LH28F008SAT-85 integrates the Quick-Pulse pro-
gramming algorithm using the Command User Interface,
Status Register and Write State Machine (WSM). On-chip
integration dramatically simplifies system software and pro-
vides processor interface timings to the Command User In-
terface and Status Register. WSM operation, internal verify
and VPP high voltage presence are monitored and reported
via the RY/BY# output and appropriate Status Register bits.
Figure 5 shows a system software flowchart for device byte
write. The entire sequence is performed with VPP at VPPH.
(1) Assumptions: 10K-byte file written every 10 minutes. (20M-byte array)/(10K-byte file) = 2,000 file writes before erase required.
(2000 files writes/erase) x (100,000 cycles per LH28F008SA block) = 200 million file writes.
(200 x 106 file writes) x (10 min/write) x (1 hr/60 min) = 33.3 x 106 MTBF.
Byte write abort occurs when RP# transitions to VIL, or VPP
drops to VPPL. Although the WSM is halted, byte data is
partially written at the location where byte write was
aborted. Block erasure, or a repeat of byte write, is required
to initialize this data to a known value.
8. AUTOMATED BLOCK ERASE
As above, the Quick-Erase algorithm is now implemented
internally, including all preconditioning of block data. WSM
operation, erase success and VPP high voltage presence
are monitored and reported through RY/BY# and the Status
Register. Additionally, if a command other than Erase Con-
firm is written to the device following Erase Setup, both the
Erase Status and Byte Write Status bits will be set to "1"s.
When issuing the Erase Setup and Erase Confirm com-
mands, they should be written to an address within the ad-
dress range of the block to be erased. Figure 6 shows a
system software flowchart for block erase.
Erase typically takes 1.6s per block. The Erase Suspend/
Erase Resume command sequence allows suspension of
this erase operation to read data from a block other than
that in which erase is being performed. A system software
flowchart is shown in Figure 7.
The entire sequence is performed with VPP at VPPH. Abort
occurs when RP# transitions to VILor VPP falls to VPPL,
while erase is in progress. Block data is partially erased by
this operation, and a repeat of erase is required to obtain a
fully erased block.
9. DESIGN CONSIDERATIONS
Three-Line Output Control
The LH28F008SAT-85 will often be used in large memory
arrays. SHARP provides three control inputs to
accommodate multiple memory connections. Three-line
control provides for:
a) lowest possible memory power dissipation
b) complete assurance that data bus contention will not oc-
cur
To efficiently use these control inputs, an address decoder
should enable CE#, while OE# should be connected to all
memory devices and the system’s READ# control line. This
assures that only selected memory devices have active out-
puts while deselected memory devices are in Standby
Mode. Finally, RP# should either be tied to the system
RESET#, or connected to VCC if unused.
sharp
14LHF08S49
RY/BY# and Byte Write/Block Erase Polling
RY/BY# is a full CMOS output that provides a hardware
method of detecting byte write and block erase completion.
It transitions low time tWHRL after a write or erase command
sequence is written to the LH28F008SAT-85, and returns to
VOH when the WSM has finished executing the internal al-
gorithm.
RY/BY# can be connected to the interrupt input of the sys-
tem CPU or controller. It is active at all times, not tristated if
the LH28F008SAT-85 CE# or OE# inputs are brought to
VIH. RY/BY# is also VOH when the device is in Erase Sus-
pend or deep powerdown modes.
Start
Write 40H (10H),
Byte Address
Write Byte
Address/Data
NO
YES
Full Status
Check if Desired
Byte Write
Completed
Status Register Data
Read (See Above)
Byte Write
Successful
VPP Range
Error
Byte Write
Error
FULL STATUS CHECK PROCEDURE
WSM
Ready?
SR.3=0
?
SR.4=0
?
YES
YES
NO
NO
Bus
Operation Command Comments
Write
Write
Standby/Read
Byte Write
Setup
Byte Write
Data=40H(10H)
Address=Byte to be written
Data to be written
Address=Byte to be written
Check RY/BY#
VOH=Ready, VOL=Busy
or
Read Status Register
Check SR.7
1=Ready, 0=Busy
Toggle OE# or CE# to
update Status Register
Repeat for subsequent bytes
Full status check can be done after each byte or after a
sequence of bytes
Write FFH after the last byte write operation to reset the
device to Read Array Mode
Bus
Operation Command Comments
Optional
Read
Standby
Standby
CPU may already have read
Status Register data in WSM
Ready polling above
Check SR.3
1=VPP Low Detect
SR.3 MUST be cleared, if set during a byte write attempt,
before further attempts are allowed by the Write State
Machine.
SR.4 is only cleared by the Clear Status Register Command,
in cases where multiple bytes are written before full status is
checked.
If error is detected, clear the Status Register before
attempting retry or other error recovery.
Check SR.4
1=Byte Write Error
Figure 5. Automated Byte Write Flowchart
sharp
15
LHF08S49
Start
Write 20H,
Block Address
Write D0H
Block Address
NO
YES
Full Status
Check if Desired
Block Erase
Completed
Suspend
Erase?
Erase Suspend
Loop
Status Register Data
Read (See Above)
Block Erase
Successful
VPP Range
Error
Command Sequence
Error
FULL STATUS CHECK PROCEDURE
Block Erase
Error
YES
YES
NO
NO
YES
NO
WSM
Ready?
NO
SR.3=0
?
SR.4,5=1
?
SR.5=0
?
YES
Bus
Operation Command Comments
Write
Write
Standby/Read
Erase
Setup
Erase
Data=20H
Address=Within block to be
erased
Data=D0H
Address=Within block to be
erased
Check RY/BY#
VOH=Ready, VOL=Busy
or
Read Status Register
Check SR.7
1=Ready, 0=Busy
Toggle OE# or CE# to
update Status Register
Repeat for subsequent bytes
Full status check can be done after each block or after a
sequence of blocks
Write FFH after the last block erase operation to reset the
device to Read Array Mode
Bus
Operation Command Comments
Optional
Read
Standby
Standby
CPU may already have read
Status Register data in WSM
Ready polling above
Check SR.3
1=VPP Low Detect
SR.3 MUST be cleared, if set during a block erase attempt,
before further attempts are allowed by the Write State
Machine.
SR.5 is only cleared by the Clear Status Register Command,
in cases where multiple blocks are erased before full status is
checked.
If error is detected, clear the Status Register before
attempting retry or other error recovery.
Check SR.4,5
Both 1=Command Sequence
Error
Standby Check SR.5
1=Block Erase Error
Figure 6. Automated Block Erase Flowchart
sharp
16LHF08S49
Figure 7. Erase Suspend/Resume Flowchart
Write B0H
Write 70H
YES
YES
Read Status
Register
NO
NO
YES
SR.7=1
?
Done
Reading?
Write D0H
Write FFH
Continue Erase
Erase Has
Completed
NO
Start
SR.6=1
?
Bus
Operation Command Comments
Write
Standby
Read
Check RY/BY#
VOH=Ready, VOL=Busy
or Read Status Register
Standby/
Read
Check SR.7
1=Ready, 0=Busy
Toggle OE# or CE# to
Update Status Register
Write
Write
Write
Erase
Suspend
Read
Status Register
Read Array
Erase Resume
Data=B0H
Data=70H
Check SR.6
1=Suspended
Data=FFH
Read array data from block
other than that being
erased.
Data=D0H
Power Supply Decoupling
Flash memory power switching characteristics require care-
ful device decoupling. System designers are interested in 3
supply current issues; standby current levels (ISB), active
current levels (ICC) and transient peaks produced by falling
and rising edges of CE#. Transient current magnitudes de-
pend on the device outputs’ capacitive and inductive load-
ing. Two-line control and proper decoupling capacitor selec-
tion will suppress transient voltage peaks. Each device
should have a 0.1µF ceramic capacitor connected between
each VCC and GND, and between its VPP and GND. These
high frequency, low inherent-inductance capacitors should
be placed as close as possible to package leads. Addition-
ally, for every 8 devices, a 4.7µF electrolytic capacitor
should be placed at the array’s power supply connection
between VCC and GND. The bulk capacitor will overcome
voltage slumps caused by PC board trace inductances.
VPP Trace on Printed Circuit Boards
Writing flash memories, while they reside in the target sys-
tem, requires that the printed circuit board designer pay at-
tention to the VPP power supply trace. The VPP pin supplies
the memory cell current for writing and erasing. Use similar
trace widths and layout considerations given to the VCC
power bus. Adequate VPP Supply traces and decoupling will
decrease VPP voltage spikes and overshoots.
sharp
17
LHF08S49
A system designer must guard against spurious writes for
VCC voltages above VLKO when VPP is active. Since both
WE# and CE# must be low for a command write, driving
either to VIH will inhibit writes. The Command User Interface
architecture provides an added level of protection since al-
teration of memory contents only occurs after successful
completion of the two-step command sequences.
Finally, the device is disabled until RP# is brought to VIH,
regardless of the state of its control inputs. This provides an
additional level of memory protection.
Power Dissipation
When designing portable systems, designers must consider
battery power consumption not only during device opera-
tion, but also for data retention during system idle time.
Flash nonvolatility increases usable battery life, because
the LH28F008SAT-85 does not consume any power to re-
tain code or data when the system is off.
In addition, the LH28F008SA’s deep powerdown mode en-
sures extremely low power dissipation even when system
power is applied. For example, portable PCs and other
power sensitive applications, using an array of
LH28F008SA’s for solid-state storage, can lower RP# to VIL
in standby or sleep modes, producing negligible power con-
sumption. If access to the LH28F008SAT-85 is again
needed, the part can again be read, following the tPHQV and
tPHWL wakeup cycles required after RP# is first raised back
to VIH. See AC Characteristics —
Read-Only and Write Operations and Figures 8 and 9 for
more information.
VCC, VPP, RP# Transitions and the Command/
Status Registers
Byte write and block erase completion are not guaranteed if
VPP drops below VPPH. If the VPP Status bit of the Status
Register (SR.3) is set to "1", a Clear Status Register com-
mand MUST be issued before further byte write/block erase
attempts are allowed by the WSM. Otherwise, the Byte
Write (SR.4) or Erase (SR.5) Status bits of the Status Reg-
ister will be set to "1"s if error is detected. RP# transitions to
VIL during byte write and block erase also abort the opera-
tions. Data is partially altered in either case, and the com-
mand sequence must be repeated after normal operation is
restored. Device poweroff, or RP# transitions to VIL, clear
the Status Register to initial value 10000 for the upper 5
bits.
The Command User Interface latches commands as issued
by system software and is not altered by VPP or CE#
transitions or WSM actions. Its state upon powerup, after
exit from deep powerdown or after VCC transitions below
VLKO, is Read Array Mode.
After byte write or block erase is complete, even after VPP
transitions down to VPPL, the Command User Interface
must be reset to Read Array mode via the Read Array com-
mand if access to the memory array is desired.
Power Up/Down Protection
The LH28F008SAT-85 is designed to offer protection
against accidental block erasure or byte writing during
power transitions. Upon power-up, the LH28F008SAT-85 is
indifferent as to which power supply, VPP or VCC, powers up
first. Power supply sequencing is not required. Internal cir-
cuitry in the LH28F008SAT-85 ensures that the Command
User Interface is reset to the Read Array mode on power up.
sharp
18LHF08S49
10. ABSOLUTE MAXIMUM RATINGS*
Operating Temperature
During Read .........................................0˚C to +70˚C(1)
During Block Erase/Byte Write ................0˚C to +70˚C
Temperature Under Bias .....................-10˚C to +80˚C
Storage Temperature ........................-65˚C to +125˚C
Voltage on Any Pin
(except VCC and VPP)
with Respect to GND .........................-2.0V to +7.0V(2)
VPP Program Voltage with
Respect to GND during
Block Erase/Byte Write .................-2.0V to +14.0V(2,3)
VCC Supply Voltage
with Respect to GND ..........................-2.0V to +7.0V(2)
Output Short Circuit Current ...........................100mA(4)
NOTES:
1. Operating temperature is for commercial product defined by
this specification.
2. All specified voltages are with respect to GND. Minimum DC
voltage is -0.5V on input/output pins and -0.2V on VCC and
VPP pins. During transitions, this level may undershoot to
-2.0V for periods <20ns. Maximum DC voltage on input/output
pins, VCC and RP# pin is VCC+0.5V which, during transitions,
may overshoot to VCC+2.0V for periods <20ns.
3. Maximum DC voltage on VPP may overshoot to +14.0V for
periods <20ns.
4. Output shorted for no more than one second. No more than
one output shorted at a time.
* WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and
extended exposure beyond the "Operating Conditions"
may affect device reliability.
TA=0 to +70
11. OPERATING CONDITIONS
NOTE:
1. ±0.25V VCC specifications reference the LH28F008SA-85 in its High Speed configuration. ±0.5V VCC specifications reference the
LH28F008SA-85 in its Standard configuration.
12. DC CHARACTERISTICS
V
V
5.254.751
V
CC
Supply Voltage (5V±0.25V)
V
CC
5.504.501
V
CC
Supply Voltage (5V±0.5V)V
CC
T
A
Operating Temperature 0 +70 °C
Symbol Parameter Notes Min. Max. Unit
V
CC
=V
CC
Max., CE#=V
IL
f=8MHz, I
OUT
=0mA
TTL Inputs
mA50
V
CC
=V
CC
Max., CE#=GND
f=8MHz, I
OUT
=0mA
CMOS Inputs
mA35
1
V
CC
Read CurrentI
CCR
RP#=GND±0.2V
I
OUT
(RY/BY#)=0mA
101
V
CC
Deep PowerDown
Current
I
CCD
V
CC
=V
CC
Max.
CE#=RP#=V
CC
±0.2V
100
V
CC
=V
CC
Max.
CE#=RP#=V
IH
mA2.0
1, 3
V
CC
Standby CurrentI
CCS
V
CC
=V
CC
Max.
V
OUT
=V
CC
or GND
±101
1
Output Leakage CurrentI
LO
I
LI
Input Load Current V
CC
=V
CC
Max.
V
IN
=V
CC
or GND
Symbol Parameter Notes Min. Typ. Max. Unit Test Condition
±1.0
µA
µA
µA
µA
1.0
30
20
25
0.2
sharp
19
LHF08S49
DC CHARACTERISTICS (Continued)
Symbol
VOUT=0V
pF128
Output Capacitance
COUT
CIN Input Capacitance 6 8 pF VIN=0V
Condition
UnitMax.
Typ.
Parameter
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at VCC=5.0V, VPP=12.0V, TA=+25˚C.
2. ICCES is specified with the device deselected. If read while in Erase Suspend Mode, current draw is the sum of ICCES and ICCR.
3. Includes RY/BY#.
4. Block Erases/Byte Writes are inhibited when VPP=VPPL and not guaranteed in the range between VPPH and VPPL.
13. CAPACITANCE(1)
TA=+25˚C, f=1MHz
NOTE:
1. Sampled, not 100% tested.
V
2.0
VCC Erase/Write Lock
Voltage
VLKO
V12.612.011.4
VPP during Erase/Write
Operations
VPPH
V
V
V
V
V
6.5
4
VPPL
VOH1
VPP during Normal
Operations
Output High Voltage (TTL)
VOL Output Low Voltage
VIH Input High Voltage
VIL Input Low Voltage
IPPES VPP Erase Suspend Current
IPPE VPP Block Erase Current
IPPW VPP Byte Write Current
IPPD VPP Deep PowerDown
Current
VPP Standby Current
ICCES VCC Erase Suspend Current
ICCE VCC Block Erase Current
ICCW VCC Byte Write Current
Symbol Parameter Notes Min. Typ. Max. Unit Test Condition
VCC=VCC Min.
IOH=-2.5mA
VCC=VCC Min.
IOL=5.8mA
VPP=VPPH
Block Erase Suspended
VPP=VPPH
Block Erase in Progress
VPP=VPPH
Byte Write in Progress
RP#=GND±0.2V
VPP>VCC
VPP=GND
Block Erase Suspended
CE#=VIH
Block Erase In Progress
Byte Write In Progress
mA130
30
10
+15/
-300
200
5.0
200
0.8
VCC+0.5
0.45
2.43
3
1
1
1
1
1
1
-0.5
2.0
mA
mA
µA
µA
µA
µA
mA
mA30
30
1,2
IPPR
IPPS
VPP Read Current 1
5
0.1
90
0.0
10
10
10
10
VOH2 Output High Voltage
(CMOS) 0.85VCC
VCC-0.4
V
IOH=-2.0mA
VCC=VCC Min.
IOH=-100µA
VCC=VCC Min.
sharp
20LHF08S49
DEVICE
UNDER
TEST
1.3V
1N914
OUT
RL
CL
RL=3.3kΩ
CL=30pF
(CL Includes Jig Capacitance)
DEVICE
UNDER
TEST
1N914
OUT
R
L
C
L
R
L
=3.3kΩ
C
L
=100pF
(C
L
Includes Jig Capacitance)
1.3V
TEST POINTS
1.5
INPUT
3.0
0.0
1.5 OUTPUT
TEST POINTS
2.0
0.8
INPUT
2.4
0.45
2.0
0.8
OUTPUT
AC INPUT/OUTPUT REFERENCE WAVEFORM(1)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
00
0
00
0
3
Output Hold from
Addresses, CE# or OE#
Change,Whichever is First
t
OH
3030OE# High to Output High Zt
DF
t
GHQZ
t
GLQX
t
OLZ
OE# to Output Low Z
t
EHQZ
t
HZ
CE# High to Output High Z
t
ELQX
t
LZ
t
GLQV
CE# to Output Low Z
t
OE
OE# to Output Delay
t
PHQV
t
PWH
RP# High to Output Delay
t
ELQV
t
CE
CE# to Output Delay
t
AVQV
t
ACC
Address to Output Delay
t
AVAV
t
RC
Read Cycle Time
Versions V
CC
=5V±0.25V
(4)
V
CC
=5V±0.5V
(5)
Unit
Symbol Parameter Notes Min. Max. Min. Max.
85
85
85
400
40
55
90
90
90
400
45
55
3
3
3
3
2
2
AC TESTING LOAD CIRCUIT(1)
AC test inputs are driven at VOH (2.4VTTL) for a Logic "1" and VOL
(0.45VTTL) for a Logic "0". Input timing begins at VIH (2.0VTTL) and VIL
(0.8VTTL). Output timing ends at VIH and VIL. Input rise and fall times (10%
to 90%) <10ns.
HIGH SPEED
AC INPUT/OUTPUT REFERENCE WAVEFORM(2) HIGH SPEED
AC TESTING LOAD CIRCUIT(2)
AC test inputs are driven at 3.0V for a Logic "1" and 0.0V for a Logic "0".
Input timing begins, and output timing ends, at 1.5V. Input rise and fall
times (10% to 90%) <10ns.
NOTES:
1. Testing characteristics for LH28F008SA-85 in Standard configuration.
2. Testing characteristics for LH28F008SA-85 in High Speed configuration.
14. AC CHARACTERISTICS — Read-Only Operations(1)
NOTES:
1. See AC Input/Output Reference Waveform for timing measurements.
2. OE# may be delayed up to tCE-tOE after the falling edge of CE# without impact on tCE.
3. Sampled, not 100% tested.
4. See High Speed AC Input/Output Reference Waveforms and High Speed AC Testing Load circuits for testing characteristics.
5. See AC Input/Output Reference Waveforms and AC Testing Load Circuits for testing characteristics.
sharp
LHF08S49 21
VOL
VOH
VCC POWER-UP STANDBY
DEVICE AND
ADDRESS SELECTION OUTPUTS ENABLED DATA VALID
ADDRESSES STABLE
VCC POWER-DOWN
STANDBY
ADDRESSES (A)
VIH
VIL
VIL
VIL
GND
VIH
VIH
VIH
5.0V
VIH
VIL
VIL
CE# (E)
OE# (G)
WE# (W)
DATA (D/Q)
RP# (P)
VCC
HIGH Z HIGH Z
tAVAV
tEHQZ
tGHQZ
tOH
tGLQV
tELQV
tGLQX
tELQX
tAVQV
tPHQV
VALID OUTPUT
Figure 8. AC Waveform for Read Operations
sharp
22
LHF08S49
AC CHARACTERISTICS - Write Operations(1)
ns
ns
ns
ns
ns
ns
ns
ns
ns
Versions V
CC
=5V±0.25V
(7)
V
CC
=5V±0.5V
(8)
Unit
Symbol Parameter Notes Min. Max. Min. Max.
t
QVVL
002,6
V
PP
Hold from Valid SRD,
RY/BY# High
t
VPH
t
WHGL
Write Recovery before
Read 00
t
WHQV2
Duration of Block Erase
Operation 5,6 0.3 0.3
ns
s
t
WHQV1
Duration of Byte Write
Operation 5,6 6 6 µs
ns
ns
ns
100100
t
WHRL
WE# High to RY/BY# Going
Low
WE# Pulse Width High
t
WHWL
t
WPH
9085
t
AVAV
t
WC
Write Cycle Time
t
PHWL
t
PS
RP# High Recovery to
WE# Going Low 21 1
t
ELWL
t
CS
CE# Setup to WE# Going
Low 00
50
t
WLWH
t
WP
WE# Pulse Width 50
V
PP
Setup to WE# Going
High
t
VPWH
t
VPS
Address Setup to WE#
Going High
t
AVWH
t
AS
Data Setup to WE# Going
High
t
DVWH
t
DS
Data Hold from WE# High
t
WHDX
t
DH
t
WHAX
Address Hold from WE#
High
t
AH
t
WHEH
CE# Hold from WE# High
t
CH
2
3
4
100
40
40
5
5
0
25
100
40
40
5
5
0
25
µs
NOTES:
1. Read timing characteristics during erase and byte write operations are the same as during read-only operations. Refer to AC
Characteristics for Read-Only Operations.
2. Sampled, not 100% tested.
3. Refer to Table 3 for valid AIN for byte write or block erasure.
4. Refer to Table 3 for valid DIN for byte write or block erasure.
5. The on-chip Write State Machine incorporates all byte write and block erase system functions and overhead of standard SHARP
flash memory, including byte program and verify (byte write) and block precondition, precondition verify, erase and erase verify
(block erase).
6. Byte write and block erase durations are measure to completion (SR.7=1, RY/ BY#=VOH). VPP should be held at VPPH until determi-
nation of byte write/block erase success (SR.3/4/5=0).
7. See High Speed AC Input/Output Reference Waveforms and High Speed AC Testing Load Circuits for testing characteristics.
8. See AC Input/Output Reference Waveforms and AC Testing Load Circuits for testing characteristics.
sharp
LHF08S49 23
15. BLOCK ERASE AND BYTE WRITE PERFORMANCE
s
s
Parameter Notes UnitMin. Typ.(1) Max.
Block Erase Time
Block Write Time
2
2
1.6
0.6
10
2.1
Byte Write Time 8 µs
NOTES:
1. TA=+25˚C, 12.0V VPP.
2. Excludes System-Level Overhead.
t
PLRH
RY/BY#(R)
RP#(P) V
IH
V
OH
V
IL
V
OL
t
PLPH
t
PLPLC
RY/BY#(R)
RP#(P) V
IH
V
OH
V
IL
V
OL
t
PLPH
(A) Reset During Read Array Mode
(B) Reset During Block Erase or Byte Write
Sym. Parameter Notes Min. Max. Unit
t
PLPH
t
PLRH
RP# Pulse Low Time
(If RP# is tied to V
CC
, this specification is not applicable)
RP# Low to Reset during Block Erase or Byte Write
(If RP# is tied to V
CC
, this specification is not applicable)
100
12
ns
µs1,2
t
PLPLC
Reset Cycle Time (During Read Array Mode) 4 µs
NOTES:
1. If RP# is asserted when the WSM is not busy (RY/BY#="1"), the reset will complete within 100ns.
2. A reset time, tPHQV, is required from the latter of RY/BY# or RP# going high until outputs are valid.
RESET AC Specifications
AC Waveform for Reset Operation
AC CHARACTERISTICS - Reset Operation
sharp
24
LHF08S49
VCC POWER-UP
& STANDBY
WRITE BYTE WRITE OR
ERASE SETUP COMMAND
ADDRESSES (A)
VIH
VIL
CE# (E)
tAVAV tAVWH
AIN AIN
tWHAX
tELWL tWHEH
tWHWL
tWHGL
tWHQV1, 2
tWHDX
tWLWH
tDVWH
HIGH Z
tPHWL
DIN DIN DIN
VALID
SRD
tWHRL
tVPWH tQVVL
WRITE
VALID ADDRESS & DATA (BYTE WRITE)
OR ERASE CONFIRM COMMAND
AUTOMATED BYTE WRITE
OR ERASE DELAY
READ STATUS
REGISTER DATA
WRITE READ ARRAY
COMMAND
VIH
VIL
VIH
VIL
VIH
VIL
DATA (D/Q)
VIH
VIL
RY/BY# (R)
VOH
VOL
VPPH
VPPL
VIH
VIL
OE# (G)
WE# (W)
RP# (P)
VIH
VIL
VPP (V)
Figure 9. AC Waveform for Write Operations
sharp
LHF08S49 25
NOTES:
1. Chip-Enable Controlled Writes: Write operations are driven by the valid combination of CE# and WE#. In systems where CE#
defines the write pulsewidth (within a longer WE# timing waveform), all setup, hold and inactive WE# times should be measured
relative to the CE# waveform.
2. Sampled, not 100% tested.
3. Refer to Table 3 for valid A
IN
for byte write or block erasure.
4. Refer to Table 3 for valid D
IN
for byte write or block erasure.
5. Byte write and block erase durations are measured to completion (SR.7=1, RY/BY#=VOH). VPP should be held at VPPH until determi-
nation of byte write/block erase success (SR.3/4/5=0).
6. See High Speed AC Input/Output Reference Waveforms and High Speed AC Testing Load Circuits for testing characteristics.
7. See AC Input/Output Reference Waveforms and AC Testing Load Circuits for testing characteristics.
16. ALTERNATIVE CE#-CONTROLLED WRITES(1)
ns
ns
ns
ns
ns
ns
ns
ns
ns
Versions V
CC
=5V±0.25V
(7)
V
CC
=5V±0.5V
(8)
Unit
Symbol Parameter Notes Min. Max. Min. Max.
t
QVVL
002,5
V
PP
Hold from Valid SRD,
RY/BY# High
t
VPH
t
EHGL
Write Recovery before
Read 00
t
EHQV2
Duration of Block Erase
Operation 5 0.3 0.3
ns
s
t
EHQV1
Duration of Byte Write
Operation 56 6 µs
ns
ns
ns
100100
t
EHRL
CE# High to RY/BY# Going
Low
CE# Pulse Width High
t
EHEL
t
EPH
9085
t
AVAV
t
WC
Write Cycle Time
t
PHEL
t
PS
RP# High Recovery to
CE# Going Low 21 1
t
WLEL
t
WS
WE# Setup to CE# Going
Low 00
50
t
ELEH
t
CP
CE# Pulse Width 50
V
PP
Setup to CE# Going
High
t
VPEH
t
VPS
Address Setup to CE#
Going High
t
AVEH
t
AS
Data Setup to CE# Going
High
t
DVEH
t
DS
Data Hold from CE# High
t
EHDX
t
DH
t
EHAX
Address Hold from CE# High
t
AH
t
EHWH
WE# Hold from CE# High
t
WH
2
3
4
100
40
40
5
5
0
25
100
40
40
5
5
0
25
µs
sharp
26
LHF08S49
VCC POWER-UP
& STANDBY
WRITE BYTE WRITE OR
ERASE SETUP COMMAND
ADDRESSES (A)
VIH
VIL
WE# (W)
tAVAV tAVEH
AIN AIN
tEHAX
tWLEL tEHWH
tEHEL
tEHGL
tEHQV1, 2
tEHDX
tELEH
tDVEH
HIGH Z
tPHEL
DIN DIN DIN
VALID
SRD
tEHRL
tVPEH tQVVL
WRITE
VALID ADDRESS & DATA (BYTE WRITE)
OR ERASE CONFIRM COMMAND
AUTOMATED BYTE WRITE
OR ERASE DELAY
READ STATUS
REGISTER DATA
WRITE READ ARRAY
COMMAND
VIH
VIL
VIH
VIL
VIH
VIL
DATA (D/Q)
VIH
VIL
RY/BY# (R)
VOH
VOL
VPPH
VPPL
VIH
VIL
OE# (G)
CE# (E)
RP# (P)
VIH
VIL
VPP (V)
Figure 10. AC Waveform for Write Operations
sharp
Rev. 1.10
i
A-1 RECOMMENDED OPERATING CONDITIONS
A-1.1 At Device Power-Up
AC timing illustrated in Figure A-1 is recommended for the supply voltages and the control signals at device power-up.
If the timing in the figure is ignored, the device may not operate correctly.
Figure A-1. AC Timing at Device Power-Up
For the AC specifications tVR, tR, tF in the figure, refer to the next page. See the “ELECTRICAL SPECIFICATIONS“
described in specifications for the supply voltage range, the operating temperature and the AC specifications not shown in
the next page.
t2VPH *1
VCC
GND
VCC(min)
RP#
VIL
VIH
(P)
tPHQV
VCCW *2
GND
VCCWH1/2
(V)
CE#
VIL
VIH
(E)
WE#
VIL
VIH
(W)
OE#
VIL
VIH
(G)
WP#
VIL
VIH
(S)
VOH
VOL
(D/Q)
DATA High Z Valid
Output
tVR
tF
tR
tELQV
tFtGLQV
(A)ADDRESS Valid
(RST#)
(VPP)
tRor tF
Address
VIL
VIH
tAVQV
*1 t5VPH for the device in 5V operations.
tRor tF
tR
tR
*2 To prevent the unwanted writes, system designers should consider the VCCW (VPP) switch, which connects VCCW (VPP)
to GND during read operations and VCCWH1/2 (VPPH1/2) during write or erase operations.
(VPPH1/2)
See the application note AP-007-SW-E for details.
sharp
Rev. 1.10
ii
A-1.1.1 Rise a nd Fall Ti me
NOTES:
1. Sampled, not 100% tested.
2. This specification is applied for not only the device power-up but also the normal operations.
tR(Max.) and tF(Max.) for RP# (RST#) are 100µs/V.
Symbol Parameter Notes Min. Max. Unit
tVR VCC Rise Time 1 0.5 30000 µs/V
tRInput Signal Ri se Time 1, 2 1 µs/V
tFInput Si gnal Fall Time 1, 2 1 µs/V
sharp
Rev. 1.10
iii
A-1.2 Glitch Noises
Do n ot in put the gli tch noises which are bel ow VIH (Min .) o r a bove VIL (Max.) on address, dat a, res et , and control s ign al s,
as shown in Figure A-2 (b). The acceptable glitch noises are illustrated in Figure A-2 (a).
Figure A-2. Waveform for Glitch Noises
See the “DC CHARACTERISTICS“ described in specifications for VIH (Min.) and VIL (Max.).
(a) Acceptable Glitch Noises
Input Signal
VIH (Min.)
Input Signal
VIH (Min.)
Input Signal
VIL (Max.)
Input Signal
VIL (Max.)
(b)
NOT
Acceptable Glitch Noises
sharp
Rev. 1.10
iv
A-2 RELATED DOCUMENT INFORMATION(1)
NOTE:
1. International customers should contact their local SHARP or distribution sales office.
Document No. Document Name
AP-001-SD-E Flash Memory Family Software Drivers
AP-006-PT-E Data Protection M ethod of SHARP Flash Memory
AP-007-SW-E RP#, VPP Electric Potential S witching Circuit
sharp
SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE.
Suggested applications (if any) are for standard use; See Important Restrictions for limitations on special applications. See Limited
Warranty for SHARP’s product warranty. The Limited Warranty is in lieu, and exclusive of, all other warranties, express or implied.
ALL EXPRESS AND IMPLIED WARRANTIES, INCLUDING THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR USE AND
FITNESS FOR A PARTICULAR PURPOSE, ARE SPECIFICALLY EXCLUDED. In no event will SHARP be liable, or in any way responsible,
for any incidental or consequential economic or property damage.
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