NEC NEC Electronics Inc. pHPD42270 NTSC Field Buffer June 1990 Description The pPD42270 is a field buffer designed for NTSC TV applications and for other applications where serial data is needed. Equipped with four planes of 263-line by 910-bit storage, the uPD42270 can execute serial write and read cycles on any of the 263 lines. Within a line, four planes of 910 bits each may be written or read at the NTSC sampling rate of 4fg. Each of the four planes in the uPD42270 is equipped with two ports, one each for the write and read data registers. Each of the registers is split into two 455-bit segments but functions as if it were organized as one scan line of 910 bits. Independent control of write and read operation makes it possible for the device to operate synchronously or asynchronously at a clock frequency of 14.3 MHz or higher. The synchronous option simplifies interframe Jumi- nance () and chrominance (C) separation and inter- field noise reduction and makes it easy to obtain a one-field delay line for digital TY and VCR applications requiring NTSC 4fgc sampling. To obtain a very long delay, field length can be configured from 260 to 263 lines and line length of the fast line from 896 to 910 bits. The asynchronous option is useful in applications such as frame synchronization and time base correction, where line jump, line hold, line reset and pointer clear functions are required to support special effects in TV field processing. Regular refreshing of the device's dynamic storage cells is performed automatically by an internal circuit. All inputs and outputs, including clocks, are TTL- compatible. The uPD42270 is packaged in a 400-mil, 28-pin plastic DIP and is guaranteed for operation at -20 to +70C, Ordering Information Access Time Cycle Time Part Number (max) (min) Package uPD42270C-60 40ns 60 ns 28-pin plastic DIP 60101 Pin Configuration 28-Pin Plastic DIP a8 5 = ESS 2 x poopog arn finan = _ Qn = 96 O71 GND Test O oF O DOUT, DOUT; DOUTs DOUT; Cf o 10 1 13 14 uPD42270 27 25 24 22 21 19 18 17 16 15 UUUUUUUUUOUUOo ALRAST WLRAST ALJ WLJ BSg/ALH BS2/WLH Voc BS1/RCO BSg/WCO DINg DIN; DINo DIN B3IH-7086.4 Features 0 0 ag 00 Q@Q@ Q O Three functional blocks Four 263-line x 910-bit storage planes Four 910-bit write registers, one for each plane Four 910-bit read registers, one for each plane Two data ports: serial write and serial read Asynchronous operation - Dual-port accessibility ~~ Carry-out feature to indicate position of scan line Line jump, line hold, tine reset, and pointer clear functions Synchronous operation Variable field length: from 260 to 263 lines Variable last line length: from 896 to 910 bits Automatic refreshing CMOS technology Fully TTL-compatible inputs, outputs, and clocks Three-state outputs Single + 5-volt power supply On-chip substrate bias generator Standard 400-mil, 28-pin plastic DIP packaging 18c-1pPD42270 NEC Pin Identification Symbol Function Dino - Dina. Write data inputs Douto - Pouts Read data outputs Ww Write enable OE Output enable weckK Write clock input RCK Read clock input WCLA Write pointer clear RCLR Read pointer clear WLRST Write line reset RLRST Read line reset WLJ Write line jump RU Read line jump WLH Write line hold RLH Read line hold wco Write data register carry output RCO Read data register carry output LSo - LS; Line select inputs BSo - BS4 Bit select inputs MODE Synchronous/asynchronous control GND Ground Voc +5-volt power supply TEST Test pin (connect to GND in system) Pin Functions Dino - Ding. These pins function as write data inputs, e.g., for 4fgg composite color or brightness signals. Douto - Douts- These pins are three-state read data outputs. W. A low level on W enables write operation. W must be kept low throughout the entire scan line to ensure that data is stored serially; if W goes high any time during the WCK clock sequencing for a line, write operation will be disabled for the half of the line (455 bits) being written. The write address pointer increments in syn- chronization with WCK, regardless of W. OE. This signal controls read data output. When OE is low, read data is output on Douto-Dout3. When OE is high, Douro - Douts are in a state of high impedance. The read address pointer is incremented by RCK, re- gardiess of the signal level of OE. WCK The rising edge of WCK latches write data from Dino - Ding. Each time this signal is activated, the write bit pointer increments sequentially and 4 bits of data 18C-2 are sampled and loaded into the write register. Although the register functions as one scan line of 910 bits, data is moved into and out of it in blocks of 455 x 4 bits. While 455 serial write cycles are being executed in one-half of the register, the 455 addresses previously written to the other half are simultaneously transferred to storage. Writing continues in this manner, alternating between the two halves of the register. Automatic refreshing and data transfer timing decisions are made by the internal arbitration circuit after each block of 455 addresses has been written. RCK, The rising edge of RCK initiates read operation. Each time this signal is activated, the bit pointer incre- ments by 1 and serial read cycles are executed in the read register. Although the register functions as one scan line of 910 bits, data is moved into and out of it in blocks of 455 x 4 bits. While 455 serial read cycles are being executed in one-half of the register, the 455 addresses previously read out of the other half are replaced by data from the storage array. Reading con- tinues in this manner, alternating between the two halves of the register Automatic refreshing and data transfer timing decisions are made by the arbitration circuit after each block of 455 addresses has been read. In synchronous operation, WCK controls read cycles and RCK is not used. WCLR. When WLRST is high, WCLR can be brought low to clear the write pointers to address O of the data register and scan line 0 of the storage array. At least one rising edge of WCK must occur while WCLR is held jow for a minimum of 3 ys to ensure clearing of both pointers. The clear function ends when WCLR goes high. If WLRST is still high, the next rising edge of WCK writes the data on Djno - Ding into address 0 of the write register. RCLR. When RLRST is high, RCLR can be brought low to clear the read pointers to address 0 of the data register and scan line 0 of the storage array (asynchro- nous operation only). At least one rising edge of RCK must occur while RCLR is held low for a minimum of 3s to ensure clearing of both pointers. The clear function ends when RCLR goes high. If RLRST is still high, the data from address 0 is read out on Douto - Dour3 and the next rising edge of RCK initiates data access from address 1. WLRST. This pin is used in synchronous or asynchro- nous operation to reset the bit pointer to address 0 of the line following the one to which the signal is applied. In standard write operation, the scan line pointer incre- ments by 1 whenever the bit pointer reaches the last address of a line. If WGLR is high, WLRST can be brought low for a minimum of 3 us to force an end-of-NEC pPD42270 line condition, whereby write cycles begin executing from address 0 of the next sequential scan line. When used in conjunction with WLH, WLRST resets the cur- rent scan line; when combined with WLJ, WLRST begins writing from address 0 of the line to which the scan line pointer is jumped. RLRST. This pin is valid in asynchronous operation and can be used to reset the bit pointer to address 0 of the read line following the one to which the signal is applied. In standard read operation, the scan line pointer increments by 1 whenever the bit pointer reaches the last address of a line. If RCLR is high, RLRST can be brought low for a minimum of 3ys to force an end-of-line condition, whereby read cycles begin executing from address 0 of the next sequential scan line. When used in conjunction with RLH, RLRST resets the current scan line; when combined with RLJ, RLRST begins reading from address 0 of the line to which the scan line pointer is jumped. WLJ. Each positive pulse of this signal increments the write scan line pointer by one line (asynchronous operation only). WLU is sampled at the rising edge of WCK. If WLd is high, a single jump is executed. If WLJ remains high, no further jumps occur. To jump again, WLJ must go low for at least one rising edge of WCK before going high again. It takes a minimum of two WCK cycles to complete a line jump. The first cycle senses the high level of WLJ and increments the sean line pointer. An additional WCK cycle with WLJ low is re- quired to complete the function. If more than one line jump is needed, then the sequence must be repeated. A line jump occurs either when the current line has been completely filled or after WLRST has reset the write address. The new scan line can be calculated by n+11+1x (where n is the current line and ''x equals the number of positive WLJ pulses). Changes in the level of WLJ must be made when the bit pointer is between locations 229 and 909 of the current line and when WCLR and WLRST are high and WLH is low. RLJ. Each positive pulse of this signal increments the read scan line pointer by one line (asynchronous oper- ation only). RLJ is sampled at the rising edge of RCK. If RLJ remains high, a single line jump is executed. To jump again, RLJ must go low for at least one rising edge of RCK before going high again. It takes a minimum of two RCK cycles to complete a line jump. The first cycle senses the high level of RLJ and increments the scan line pointer. An additional RCK cycle with RLU low is required to complete the function.|f more than one line jump is needed, then this sequence must be repeated. Aline jump occurs either when the current line has been completely read or after RLRST has reset the read address. The new scan line can be calculated by n+1+x (where "n" is the current line and x equals the number of positive RLJ pulses). Changes in the level of RLJ must be made when the bit pointer is between locations 682 and 909 of the previ- ous line, or between 0 and 452 of the current line, and when RCLR and RLRST are high and RLH is low. WLH. Once this input is applied, the write scan line pointer will hold its position even if successive write clocks are applied. The level of WLH is sampled at the rising edge of WCK and must be applied between locations 229 and 909 of the line to be held. The held line is released after 910 addresses have been rewritten or after WLRST resets the write line address. WLH is multiplexed with BSo and is valid in asynchronous operation only. WLH (high) must be input only when WCLR and WLRST are high and WLd is low. RLH. Once this input is applied, the read scan line pointer will hold its position even if successive read clocks are applied. The level of RL.H is sampled at the rising edge of RCK and must be clocked between locations 682 and 909 of the line preceding the line to hold, or between locations 0 and 452 of the line to hold. The held line is released after 910 addresses have been read or after RLRST resets the read line address. RLH (high) must be input only when RCLR and RLAST are high and RLJ is low. RLH is multiplexed with BS3 and is valid in asynchronous operation only. WCO. When the bit pointer reaches address 909 of the write data register, this signal goes high for one WCK cycle. WCO is multiplexed with BS, and is valid in asynchronous operation only. RCO. When the bit pointer reaches address 909 of the read data register, this signal goes high for one RCK cycle, RCO is multiplexed with BS, and is valid in asynchronous operation only. BSp - BS3. These pins control the number of bits in the last line of the field. The combined signals of BSo-BS, set the line length from 896 to 910 bits in one-bit steps (table 1). The length of the last line can change for each field, but all four pins should not be set low. BSo, BS, BS, and BS3 are multiplexed with WCO, RCO, WLH and RLH, respectively, and are valid in synchronous oper- ation only. In asynchronous operation, the line length is fixed at 910 bits. LS - LS;. These pins contro! the number of lines for one field in either synchronous or asynchronous oper- ation. The combined signals of LSg and LS, set the number of lines to 260, 261, 262, or 263 (table 2). The number of lines can be changed for each field. 18c-3pPD42270 NEC MODE. This pin selects the operating mode. A low signal selects synchronous operation and a high signal selects asynchronous operation. If MODE is changed after power has been applied to the uPD42270, it is necessary to clear the address pointers by bringing WCLR and RCLR low. MODE can be changed at any time; however, data input in one mode may be unreli- able in the other (see table 3 for valid pin functions). Table 1. Line Length Adjustment Number of Bits BSo in the Last Line Prohibited 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 BS, a & TJS CPCI LPT l( UTTER ler yer yryryryrys rycpaeloiyri[erie fer | cy cy zy cy ry rye le xl[xzl[rojer (cy cir ltr} cyclo pr yey ecierie xielxf{ref} cle yp Cyr] cir [| cy eo]y cyer | cie Notes: (1) LSg- LS, and BSg - BS3 must be held at a stable high or low level to maintain the number of bits per scan line and the number of scan lines per field while the line pointer indicates the position between lines 258 and 262, Capacitance Ta = 25C; Voo = +5,.0V 10%; GND = OV; f = 1 MHz Table 2. Line Number Adjustment LS, LSq Number of Lines L L 260 L H 261 H L 262 H H 263 Notes: (1) LSg- LS and BS - BS3 must be held at a stable high or low level to maintain the number of bits per scan line and the number of scan lines per field while the line pointer indicates a position between lines 258 and 262. Table 3. Valid Pin Functions According to Mode Synchronous Mode Asynchronous Mode Pin Name (Note 4) (Note 2) MODE 0 1 BSpWCO BSo wco BS,/RCO BS, RCO BSo/WLH BSo WLH BS3/RLH BS3 RLH RCLR invalid _ Valid RCK Invalid Valid RLRST Invalid Valid WCLR Valid Valid WCK Valid Valid WLRST Valid Valid WL invalid Valid RU Invalid Valid Notes: (1) Write and read cycles are controlled by WCLA, WCK, and WLRST in synchronous operation. (2) In asynchronous operation, write and read cycles are controlled independently. Parameter Symbol Min Typ Max Unit Pins Under Test Input capacitance Cc 5 pF Dino - Dina: W, OE, WCK, ACK, WCLR, ACLA, WLAST, RLRST, WLJ, RLJ, LSp - LSy, BSo/WLH, BS3/RLH, MODE /O capacitance Cyo 8 pF BS,)/WCO, BS,/RCO Output capacitance Co 7 pF Dour - DoutNEC pPD42270 DEVICE OPERATION The pPD42270 supports two operating modes to ac- commodate various NTSC TV applications. Depending on the logic level of the MODE pin, the device will execute either synchronous or asynchronous write and read cycles on the addresses specified by the internal address pointers. When selecting the mode after power- on, it is necessary to reset these pointers to starting address 0 using WCLR and RCLR. The level of MODE may be changed at any time. Synchronous Mode In synchronous mode, write and read cycles are exe- cuted simultaneously by WCLR, WLRST, WCK, W and OE to create a delay line, which means that write and read addresses always coincide. After all lines within a field have been written, they then are read out as the device begins overwriting new data to the same ad- dresses again. Field length may be configured from 260 to 263 lines and last line length from 896 to 910 bits by means of the LS and BS pins, respectively. Synchro- nous operation is useful in applications where a very long delay line is required and may be selected by setting MODE low. Asynchronous Mode In asynchronous mode, WCLR, WLRST, WCK and W control write cycles, while read cycles are controlled independently by RCLR, RLRST, RCK and OE. Field length may be configured from 260 to 263 lines using LSo - LS;. Line length remains fixed at 910 bits and BSo-BS3 are disabled to provide for the register carry out, line hold, and line jump functions. Asynchronous operation is useful for frame synchronization or time base correction and may be selected by setting MODE high. Address Clear. Setting WCLR and RCLR low for a minimum of 3ys during successive WCK and RCK cycles initializes the internal pointers to starting ad- dress 0 of the first scan line (RCLR is disabled in synchronous mode). Although address clear signals must meet the specifications for setup and hold times as measured from the rising edges of WCK and ACK, they are not dependent on the status of W or OE. An address clear cycle cannot occur in conjunction with WLRST or RLRST line reset cycles. Write Operation. Write cycles are executed in synchro- nization with WCK as W is held low. Bits are input sequentially into one of the two halves of the data register before being transferred to the storage array. Since data is transferred into the array in blocks of 455 x 4 bits, no data transfer occurs if W goes high to disable write operation before all 455 bits are written. Despite write operation being disabled, the internal bit pointer continues to increment with each successive write clock. Read Operation. Read cycles are executed in synchro- nization with RCK (asynchronous operation only) or WCK (synchronous operation only) as OE is held low. If OE goes high any time during a cycle, the outputs are in a state of high impedance until OE returns low. Since the internal bit pointer increments by 1 in spite of read operation being disabled, it is always important to reset the write and read pointers using WCLR and RCLR prior to beginning or resuming operation at the first address location in the array. Special Functions Line Reset. A line reset is similar to an address clear cycle, except that it only affects the bit pointers within a tine. While WCLR and RCLRA are held high, WLRST or RLRST can be brought low for a minimum of 3 ys during successive WCK or RCK cycles to reset the bit pointer to address 0 of the scan line. At the completion of the reset cycle, the next sequential scan line will be selected unless line hold (WLH or RLH) or line jump (WLJ or RLJ) are also used. See WLRST and RLRST for more detail. A combination of line reset and an address clear cycle must be separated by at least one serial clock cycle. The timing relationship of WCLR, WLRST and WCK (or RCLR, RLRST and RCK) is shown in figure 1. In asynchronous operation, WLRST and RLRST inde- pendently reset the write and read bit pointers. During synchronous operation, WLRST resets both pointers. Line Jump. With the line jump function, it is possible to advance the current write or read line position accord ing to the number of positive WLJ or RLJ pulses applied (see descriptions for the WLJ and RLJ pins). In this cycle, which is valid in asynchronous mode only, the scan line pointer resets to address 0 if the number of positive pulses causes the resulting line number (n+11+1x, where n is the current line number and x is the number of positive WLJ or RLJ pulses) to exceed the maximum line number (number of lines minus 1) specified by the LSg and LS, pins (table 2). 418c-5yPD42270 NEC Line Hold. The line hold feature is available in asyn- chronous mode only and can be used to prevent the internal scan line pointers from incrementing to the next sequential address. The read and write line pointers Block Diagram may be held independently; however, restrictions per- taining to when this function can be initiated, detailed in the descriptions for the WLH and RLH pins, should be carefully followed. . Refresh Timer LSo ~LSy J BSg woo J BS4/ACO BS WLH BSq /ALH MODE WCK 1 Wo WCLR WLRST _J WLJ "74 ROK -~J _ OF RCLR "4 RLRST RLJ + Timing Generator Write Scan Line Pointer | Write Bit Pointer Write Bit Pointer > J | 1 Write Data Register Write Data Register i y rl Y Read Scan Line Pointer Refresh Counter Scan Line Selector 263 Lines Per Plane 910 Bits Per Line ->} Storage Cel! Array | Read Data Register | Read Data Register | Read Bit Pointer Read Bit Pointer | 1 Dino - Ding Data Input Buffer Data Output Buffer U Douto~Poutsa 83B-7087B 18C-6N: KE C pPD42270 Figure 1. Separation of Clear and Reset Signals Absolute Maximum Ratings Supply voltage on any pin except Voc relative -1.5to +7.0V t2 tWCK Of tRCK to GND, Vay Supply voltage on Vog relative to GND, Vp -1.5 to +7.0V WCK/RCK J LI | | | | | | | | Operating temperature, Topr -20 to +70C Storage temperature, Tstg -55 to +125C WCLRVRCLE Short-circuit output current, los 50 mA Power dissipation, Pp 15 W Exposure to Absolute Maximum Ratings for extended periods may WORS/ALRST \ J affect device reliability, exceeding the ratings could cause perma- 1 Ss To nent damage. The device should be operated within the limits 6VB.70688 specified under DC and AC Characteristics. Recommended Operating Conditions Parameter Symbot Min Typ Max = Unit Supply voltage Vee 45 5.0 5.5 Vv Input voltage, high Vin 24 Veco v Input voltage, low Vit -1.5 0.8 v Ambient temperature Ta -20 70 C DC Characteristics Ta = -20 to +70C; Veg = +5.0V +10%; GND = OV Parameter Symbol Min Typ Max Unit Test Conditions Input leakage current Ie -10 10 HA Vin = OV to Voc; all other pins not under test = 0 V Output leakage current lo -10 10 HA Dout disabled; Voyt = OV to Voo Output voltage, high Vou 2.4 v Jon = -1 mA Output voltage, low Vout 0.4 Vv lop = 2mA Standby current loot 6 20 mA WCK, RCK = Vit Operating current leee2 40 30 mA twek = twek (min); tack = track (min) AC Characteristics Ta = -20 to +70C; Voc = +5.0V 10%; GND = OV Parameter Symbol Min Max Unit Test Conditions Access time from RCK tac 40 ns Write clock cycle time twok 60 ns (Note 5) Write clock active pulse width twow 20 ns Write clock precharge time twep 20 ns Read clock cycle time tack 60 ns (Note 5) Read clock active pulse width trow 20 ns Read clock precharge time trop 20 ns Output hold time tou 5 ns Output low impedance delay tiz 5 40 ns {Note 6) Data output buffer high impedance delay tuz 5 40 ns (Note 7) Input data setup time tos 15 ns 18C-7pPD42270 NEC AC Characteristics (cont) Parameter Symbol Min Max Unit Test Conditions Input data hold time tox 3 ns WCGLR (RCLR) setup time before the rising edge of WCK (RCK) tes 20 ns (Note 8) WGLR (RCLRA) hold time after the rising edge of WCK (RCK) tc ns (Note 8) WCLR (RCLR) invalid hold time after the rising edge of WCK (RCK) tond ns (Note 8) WCGLR (RCLR) invalid setup time before the rising edge of WCK (RCK) tone 20 ns (Note 8) WCLR (RCLR) low level valid time toLr 3 us WLRST (RLRST) setup time before the rising edge of WCK (RCK) tis 20 ns (Note 8) WLRST (RLRST) hold time after the rising edge of WCK (ROK) tiRH 3 ns (Note 8) WLRST (RERST) invalid hold time after the rising edge of WCK (RCK) tLRN 5 ns (Note 8) WLRST (RLRST) invalid setup time before the rising edge of WCK tLAN 20 ns (Note 8) (ACK) WLRST (RLRS7) !ow level valid time tLRST 3 Us W setup time before the rising edge of WCK tws 20 ns (Note 9) W hold time after the rising edge of WCK tWH ns (Note 9) W valid hold time after subline (1/2) switch twni 5 ns (Note 9) W valid setup time before subline (1/2) switch twn2 20 ns {Note 9) WLH (RLH) setup time before the rising edge of WCK (RCK) tLus 20 ns WLH (RLH) hold time after the rising edge of WCK (RCK) tLHH 3 ns WLH invalid hold time measured from the end of write cycle 227 tWHN1 5 ns WLH invalid setup time measured before write cycle 0 tWHN2 20 ns RLH invalid hold time measured from the end of read cycle 681 tRHN4 5 ns RLH invalid setup time measured before read cycle 453 tRHN2 20 ns WLJ (RLU) setup time before the rising edge of WCK (RCK) {lus 20 ns WLJ (RLU) hold time after the rising edge of WCK (RCK) tLaH 3 ns WLJ hold time measured from the end of write cycle 227 tWUNd 5 ns WLJ setup time measured before write cycle 0 twuN2 20 ns RLJ hold time measured from the end of read cycle 681 trun 5 ns RLJ setup time measured before read cycle 453 teauN2 20 ns OE setup time before the rising edge of RCK (WCK) toes 20 ns {Note 9) OE hold time after the rising edge of RCK (WCK) toEH 3 ns (Note 9) OE valid hold time after the rising edge of RCK (WCK) toENt 5 ns (Note 9) OE valid setup time before the rising edge of RCK (WCK) toEN2 20 ns (Note 9) LS, BS setup time before WCK (RCK), line 258 tess 0 ns LS, BS hold time after WCK (RCK), line 0 tesH 3 ES Write carry output high level delay tWoLH 40 ns 16C-8NEC pPD42270 AC Characteristics (cont) Parameter Symbol Min Max Unit Test Conditions Write carry output low level delay tWCHL 40 ns Read carry output high level delay tacLH 40 ns Read carry output low level delay tRcHL 40 ns Transition time tr 3 35 ns (Note 4) Notes: (1) All voltages are referenced to GND (8) For proper execution of the pointer clear and line reset functions, _ specifications for tos, tow, ton: tone, tLas: ttRH: tLAN. and (2} Ac measurements assume ty = 5 ns. tLAN2 must be met; otherwise, these functions may not affect the (3) Input timing reference levels = 1.5 V; input levels are measured desired cycles or may affect adjacent cycles erroneously. between GND and 3.0 V; output levels are measured between 0.8 (0) Ha Ww (or OE) pulse does not satisfy the specifications tor tws, (4) () ) and 2.0 V. See figures 2 and 3. Vin (min) and Vi, (max) are reference levels for measuring the timing of input signals. Transition times are measured between Vin and VIL: The minimum specifications are used only to indicate the cycle time at which proper operation over the full temperature range (Ta = -20 to 70C) is assured. This delay is measured at -200 mV from the steady-state voltage with the load specified in figure 5. This delay is measured at the maximum steady-state output high voltage 200 mV or the minimum steady-state output low voltage +200 mV with the load specified in figure 5. (19) tw twa and twa (oF togs, togH: toEN1 and toga), the write disable function (output high impedance) being executed may not affect the desired cycles or may affect adjacent cycles erroneously. For the pPD42270 to read new data, read operation must be delayed from write operation by at least 920 cycles. in those cases where the delay is less than 920 cycles, read data will vary as shown below: Delay Between Write Source of Read Data and Read Operation Old data 0 to 450 cycles Indeterminate (either old or new data) 451 to 919 cycles New data 920 or more cycles 18C-9 -pPD42270 NEC Figure 2. Input Timing 0.0V 5ns 5ns A3IH-67018 Figure 3. Output Timing 83IH-6658B Figure 4. Output Loading for tac, ton, twecn, twont, tacin, tRcHL 45V 1.9k0 DouT P | = 1.0K0 T pF = = S31H-6702B Figure 5. Output Loading for t, z and tyz DouT +5V = 1.9k0 s 3 1.0kQ 5 pF | 831H-6706B 18 C10NEC pPD42270 Timing Waveforms Synchronous Write/Read Cycle WCK =| R| Couto Pouts n-2 twow PNK NS n | +1 - n+ n+2 toes tOEH Notes: [1] In synchronous mode, output data is delayed by one field from the input data. [2] WLRST = WCLR = Vjyq. MODE = Vj_. LSgand LS , = Vy or Vqp. RLAST, RCLR, and RCK are don't care inputs. [3} BSg- BS3 = Vin OF VIL. [4] Data is transferred inio and out of the data registers In blocks of 455 x 4 bits. When W goes high before all 455 words are input, write operation !s disabled and none of the words are transferred to the storage array. let HZ tLz hn High Impedance n+3 83VB-7089B 16C-11..pPD42270 NEC Timing Waveforms (cont) Asynchronous Write and Read Cycies WCK =| Dino -Oina RCK fl n-2 n-1 m+ Douto-PouTs Notes: {1} WCLR = RCER = Vj. WLAST = ALRST = Vj. MODE = Vix. {2] RLJ, WLJ, WLH, and RLH = Vy or Vy. LSg and LS, = Vyy or Vic. [3] Data is transferred into and out of the data registers In blocks of 455 x 4 bits. When W goes high before all 455 words are input, write operation is disabled and none of the words are transferred to the storage array. High Impedance 83VB-7090B {8C-12N: KE C pPD42270 Timing Waveforms (cont) Synchronous Pointer Clear Cycle <Clear >)<__________L ine 0 ARR R AR <_'tcH* tCN2 WCLR Dino-D ins fv Pouro:Pours OX a Notes: [1] Wa OE = Vi_. MODE = Vi. [2] LSo and LS4 = Vjy or Vy_. BSg, BS 4, BSp and BSg = Viy or V 1. [3] RLRST, ACLA, and RCK = don't care. [4] WLRST = Vin during the clear cycle. 83VB-70918 18(-13pPD42270 Timing Waveforms (cont) Asynchronous Pointer Clear Cycle Clear WCK WCLR Dino-O Ins RCLR H#f AC tOH Notes: [1] W = OE = Vy. MODE = Vy. WLAST and RLAST = V4 during clear pulse. [2] LSg and LSy = Vjy OF VIL. {3] WLH, RLH, WLJ and RLJ = Vi, during clear pulse. 83VB-7092B IBC-14NEC pPD42270 Timing Waveforms (cont) Synchronous Line Reset Cycie WCK __/ 'LRNI WLRST Notes: [1] WCLR = Vy. W, OF and MODE = Vy. [2] LSg and LSy = Vy or Vi_. BSg BSg= Vip or VIL. 'LRS [3] RCLR, RLRST, ROK, WLJ, RLJ = don't care. > tLAN2 83VB-7093B 418C-15.pPD42270 NV. KE C Timing Waveforms (cont) Asynchronous Line Reset Cycle WCK TLRNI WLRST Dino-Dins RCK _ f TAC X Doute-Pouts m2 m-1 my Notes: [1} WCCR, RCLA and MODE = Vy. WLH, RLH, WLJ, and RLJ = Vy during a reset cycle. [2] LSg and LSy = Vy. (3] W=OE=V IL: 83VB-7094B ige-i6N: KE Cc pPD42270 Timing Waveforms (cont) Write Line Jump Cycle Line n ne 228 909 ue NY TWJN1 twJN2-} WLJ WLH VIL Wwco $5 VIH MODE Notes: [1] RCLR, RLRST, ROK, RLH, RLJ, W, and O = don't care. (2) K and K' = 229 to 909 of line n. [3] WLRST and WCLR = Vijy [4] LSg and LS; = Vip Or VIL. 89VB-70958 Read Line Jump Cycle Linen-1 Sf Linen une 681 0 RCK TRING RLJ RLH VIL RCO / \ / \ a fd a of VIH MODE Notes: [1] WCLR, WLRST, WCK, WLH, WLJ, W, and O = don't care. [2] J and J' = 0 to 452 of line n or 682 to 909 of linen - 1. [3] RLAST and RCLR = Vip. [4] LSq and LS4 = Vir ViL. 83VB-70968 18C17pPD42270 NV: KE Cc Timing Waveforms (cont) Write Line Hold Cycle Line n 227 228 229 908 909 0 WCK TWHN1 + TWHN2 it Li oF fa mu LLk \\ fe. \. Cl ae VIH 55 $$ WCLR tWCLH TWCHL WCO Lt K af ae VIH Lt Lt oe ae MODE Notes: [1] RLRST, RLJ, W, RLH, OE, RCLA, and RCK = don't care. [2] K = 229 to 909, [3] WLRST = Vy. WL = Vic. [4] LSq and LS; =Viqor VIL. 83VB-7097B Read Line Hold Cycle Linen 1 55- 45 Line n xl<-Linen 680 681 682 J 451 452 908 909 0 ne NY tRHNi tLHH TRHN2 'LHS RLH F Lt, ie oF oF wid 45 $5 4$ RCLR tROLH 'RCHL RCO ___ $55 Ss iH 45 $5 45 MODE Notes: [1] WLRST, WLJ, W, WLH, OE, WCLR, and WCK = don't care. [2] J = 682 to 909 In (n 1)" or 0 to 452 inn line. [3] RLAST = Vy. RL = Vy. [4] LSg and LS; = Vipyor Vy. 83VB-7098B 48C-18NV: KE Cc pPD42270 Timing Waveforms (cont) Synchronous Field Buffer Size Adjustment Lines 258-262 WCK BSg- BS3 LSq-LS 4 Notes: [1] WLRST and WCLR = Viy. [2] MODE = Vj, . [3] RLRST, W, RCK, RCLR, and OE = don't care. 83VB-70998 Asynchronous Field Buffer Size Adjustment Line 257 3-&L ines 258-262 Line 0 909 6 CFSH Lt Sy | Pee 45 LSo- LS, Stable Stable Lt = A AAA A A A it $5 $F Notes: {T] WCLR, RCLR, WLRST, and RLAST = V IH. (2] MODE = Vjq. WLJ and ALJ = Vj. {3] W, OE, WLH, and RLH = don't care. 83VB-71008 18C-19pPD42270 NV: KE Cc Timing Waveforms (cont) Write Register Carry Out Line n la Line n+ 4 0 WCK WwCcO Notes: [1] MODE, WCLR, ACLA, WLRST, ALAST = Vj [2] LSg and LSy = Viyor Va [3] OE, W, WLH, RLH, WLJ, RLJ = don't care. 83vB8-7101B Read Regisiter Carry Out Line m ple Line m+ 1 RCK RCO Notes: [1] MODE, WCLR, RCLA, WLRST, RLRST = V jy, [2] LSg and LS4 = Viyor Vit [3] OF, W, WLH, RLH, WLU, RLJ = don't care. 83V8-71028 18G20NEC pPD42270 APPLICATION EXAMPLES Delay Line The synchronous mode may be used to create a full- field delay line with a fixed length (figures 6 and 7). Useful video applications inctude field interpolation, interframe noise reduction, and separation of lumi- nance (Y) and chrominance (C) signals. in these appli- cations, field buffer size is determined by the logic levels applied to pins LS - LS, and BSpo - BS3. The former allows variation of the number of lines from 260 to 263, while the latter controls the actual line length at 896 to 910 bits for the last line. The actual! delay between data being written into Diy and read on Doyy is con- trolled by the WCK clock period and the con figured size of the buffer. Frame Synchronization or Time Base Correction The yPD42270 has the capability of executing asyn chronous write and read cycles by independently clacking WCK and RCK, respectively. The feature is useful in applications requiring frame synchronization, time base correction or buffering, where WCK, RCK, WCLR and RCLR may all have variable time periods. In addition, the write carry out (WCO) and read carry out (RCO) options give a positive indication when the bit pointer reaches the end of the line. Vertical or Horizontal Image Compression and Expansion Vertical compression and expansion of the video im- age may be accomplished by means of the line jump or line hold functions. Compression occurs when WLJ or RLU are used to jump over lines that are not to be displayed. Expansion occurs when the WLH or RLH line hold signals are used to display a line multiple times. Horizontal compression and expansion can be achieved by modifying the cycle time of the WCK and RCK clocks, and by using the WLRST and RLRST line reset signals. Figure 6. Example of Delay Line GND Wii, 47753 L_ Move GND RCK RLAST WOK 2 27 Voc Clock Rt 4 25 GND WCLR Is 24 |__ WL LSo _ BS3 /RLH is |, 9 I BS5AWn Voc 7 R22 GND GND ja = ar, Voce Test [9 % 29] _8S1/RCO OE 10 19 BSg /(WCO < DouTo_ 414 18 1, Dino Data DouT1 | 12 17 |, DiNt Data Output Dout2__] 13 16], DIN2 Input DouT3__|14 15 |. Ding Notes: (1) W, OE, MODE, WLJ, and RLH = VIL, (2) BSo- BS3,LS 9 -LS1, WCLR, and WLRST = Vip. (3) RCK, RCLA, and RLAST = don't care. 83VB-7103B. 48C-21NEC pPD42270 gros BAce 1 9729 LUOP = YTOH pue MOH 1SHT1Y [Z] Wa sol, = +g] - 05) pue Egg Ogg [9] "HIA = HIOM pue 1SHM Is] Wa = 30 pue'm 'aqow [rl 016 01 968 = w [e] e9z 40 192 092 ese =U [2] w+uol6=e [1] SOION ENI q- ONIg Le af i- 7 \ HIOM WU Suruns aur] Aejaq +2 asnbig A 18c-N: KE C uPD42270 Figure 8 Example of Frame Synchronization/Time Base Correction GND Wt, 4 2g} MODE Voc Read Clock RCK Ia 297 |_RLRST Write Clock __WCK_J.3 26 |_WLRST Read Clear -_-__RGLR_, I 4 25 |_ RLY GND Write Clear ____WELR._ I 5 24] WJ Vee LSo |g 94 |_BS3/RLH So is; _|5 2 BS>/WLH oe TEST <a BA RCO Vec >jP 20 waa Read Carry Out Of 0 ape SW Write Carry Out DouTo_ J 11 18 |. Dino Data <__ Pours _| 12 17 le DIN1 Data Output <___Pout2 _}13 16 |. DIN2 Input Dours | 14 15 |, DIN3 Notes: (1) W, OF, WLJ, RLJ, WLH, and RLH = Vi, (2) LSq-LS1, MODE, WLAST, and RLRST = Vin. @3VB-7105B Figure 9. Asynchronous Read/Write Timing for Frame Synchronization or Time Base Correction WCK Lt oF WCLR Dino-P ns tes 'CH ACLAR Couto Pout3 Notes: {1] MODE, WLRST, and RLRST = Vy. [2] Wand OE = Vit- [3] LSg and LSy =Vjyq or Viz. [4] WLH, RLH, RLJ, and WLJ = VyL. 83VB-7106B 18C-23