ALLEGRO MICROSYSTEMS INC K {1} OUT3 OUT2 OUT4 Out, OUTPUT ENABLE GROUND GROUND GROUND GROUND SUPPLY STROBE INy IN4 IN2 IN3 Ovwg. PP-025-1 ABSOLUTE MAXIMUM RATINGS at T, < +150C Output Voltage, Veg .. 0-2 eee eee 50 V Output Voltage, Vce(eus) Sec e eee es 45 V* Output Current, Io; (peak) ......... 12A (continuous) ................. 10A Logic Supply Voltage, Vj,.-.-...-.. 7.0V CMOS Input Voltage Range, Ving cote eens 0.3 VtoV,,+0.3V Package Power Dissipation, Pore cece eee e eee ees See Graph Operating Temperature Range, Ty cece cece eee e eas -20C to +85C Storage Temperature Range, Ty eee eee eee -55C to +150C For inductive load applications: The sum of the load supply voltage and the clamping voltage. Output current may be limited by duty cycle, number of drivers operating, ambient temperature, and heat sinking. Under any set of conditions, do not exceed the specified maximum current rating or a junction temperature of 150C. Caution: CMOS devices have input static protec- tion but are susceptible to damage when exposed to extremely high static electrical charges. 3-198 33E D M@ 0504338 0005275 & MMALGR 2A3-25 BiMOS If 4-BIT LATCHED DRIVER The UCN5830B latched driver is a high-current integrated circuit comprised of CMOS data latches, a bipolar Darlington transistor driver for each latch, and CMOS control circuitry for the common STROBE and OUTPUT ENABLE functions. Although primarily designed for use with 2-phase unipolar stepper motors, this device can also be used to drive relays, solenoids, or incandescent lamps within its 1.2 A peak output current rating. The bipolar/CMOS combination provides an extremely low-power latch with maximum interface flexibility. TS The CMOS inputs cause minimum loading and are compatible with most microprocessor/LSI-based systems. TTL or DTL circuits may require the use of appropriate pull-up resistors to ensure an input logic high. The latches will typically accept data at better than a 4.4 MHz rate. The bipolar power outputs are open-collector 50 V Darlington drivers with a sustaining voltage of 45 V and integral clamp diodes for inductive load transient suppression. Under normal operating condi- tions, the four outputs can simultaneously sink load currents in excess of 500 mA continuously and without additional heat sinking. A similar device, featuring saturated (non-Darlington) outputs, is the UCN5831B. The UCN5830B is furnished in a 16-pin plastic dual in-line batwing package with a copper lead frame and heat-sinkable tabs that maximize the devices power-handling capabilities. FEATURES 50 V Minimum Output Breakdown, 45 V Minimum Sustaining Voltage 1.2 A Peak Output Current Reduced Supply Current Requirements Internal Transient Suppression Low-Power CMOS Latches Output Enable and Strobe Functions Always order by complete part number: |UCN5830B1 . FUNCTIONAL BLOCK DIAGRAM ! STROBE OUTPUT ENABLE \ ! GROUND (ACTIVE LOW) \ ! ttt a J COMMON MOS CONTROL ! TYPICAL MOS LATCH ' TYPICAL BIPOLAR DRIVE ova. FP-016 TRUTH TABLE OUTPUT IN, STROBE ENABLE OUT, xX 0 0 Prior State 0 1 0 Off 1 1 0 On xX x 1 Off X = Irrelevant KA TYPICAL INPUT CIRCUIT 8 NS oe 435 6 N 4 IN O een | x re | 28 0 75 100 125 150 ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS TEMPERATURE IN C Dwg. GP-004-1 Dwg. EP-010-1 3-199 ALLEGRO MICROSYSTEMS INC 33E D MM 0504336 0005277 T MBALGR POLS CSTR AVC DN Agar) ELECTRICAL CHARACTERISTICS at T A= +25C, Ty < +150C, Vop =5V (unless otherwise noted). ; Limits Characteristic Symbol Test Conditions Min. Typ. _Max, Units Output Leakage Current loex Vo =50V - 1.0 100 HA Output Saturation Voltage Vegisany |, = 800 mA - 1.0 1.2 Vv Output Sustaining Voltage Veetsus) |, = 800 mA, L = 400 mH 45 - - v Clamp Diode Leakage Current I, V_, = 50 V - 1.0 100 LA Clamp Diode Forward Voltage Ve |, = 800 mA - 14 1.2 Vv Logic Input Voltage Vinny 3.5 - 5.3 Vv Vino) -0.3 - 0.8 Vv Logic Input Current lacey Vin = Yoo - 50 500 nA lingo) Vin = 0.8 V - -50 -600 ; nA Logic Supply Current Ibo All Outputs OFF - - 100 HA One Output ON ~ 1.0 2.0 mA TYPICAL APPLICATION UNIPOLAR STEPPER-MOTOR DRIVE TT Yoo + z+e +5 O+24V Vee r CTT TT TTT tet Veo + Ve OUT 4 5 g IN 4 BV 53 iN 1 QUT 1 vy CEIsSAT) Lot den co trol | fea 7 5 lour eZ ZENER CLAMP "re % at Ee Sy DIODE CLAMP HP Z ( a teex = 4 om a or is it oF lel je, fe Dwg. WP-001 IN 3 Our 3 IN 2 OUT 2 A typical application is shown driving a unipolar stepper- STROBE - , motor. A Zener diode is used to increase the flyback OUTPUT ENABLE (Active Low) voltage. This gives a much faster inductive load tum-OFF current decay. The maximum Zener voltage plus the load supply voltage plus the internal diode forward voltage Dwg. EP-018-t must not exceed the device's rated sustaining voltage. 3-200 OUTPUT ENABLE STROBE Ay C t- B _ rd > ht-B INN Pl e-D Di Mic OUTN Dwg. WP-009-1 TIMING CONDITIONS Logic Levels are V,,,, and Ground A. Minimum Data Active Time Before Strobe Enabled (Data Set-Up Time)... 0... cece cece cece enue 50 ns B. Minimum Data Active Time After Strobe Enabled (Data Hold Time)... i ccc seen c eens 50 ns C. Minimum Strobe Pulse Width .......... ccc ce cece eeees 125 ns D. Typical Time Between Strobe Activation and Output Turn-OFF Transition (Resistive Load) .........ccc ceca ee uaee 500 ns E. Typical Time Between Strobe Activation and Output Turn-ON Transition (Resistive Load) .......c. cscs ees euees 100 ns F. Minimum Data Pulse Width .................. beeen 225 ns Data present at an input is transferred to its respective latch when STROBE is high. The latches will continue to accept new data as long as STROBE is held high. In applications where the latches are by- passed (STROBE tied high), the outputs will follow the data unless the OUTPUT ENABLE is high during data entry. When OUTPUT ENABLE is high, all of the output buffers are disabled (OFF) without affecting the information stored in the latches. With OUTPUT ENABLE low, the outputs are controlled by the state of the latches.