3-Axis, ±1.5 g/±3 g/±6 g/±12 g
Digital Accelerometer
Data Sheet ADXL312
Rev. A Document Feedback
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FEATURES
Ultralow power: as low as 57 μA in measurement mode and
0.1 μA in standby mode at VS = 3.3 V (typical)
Power consumption scales automatically with bandwidth
User-selectable resolution
Fixed 10-bit resolution
Full resolution, where resolution increases with g range,
up to 13-bit resolution at ±12 g (maintaining 2.9 mg/LSB
scale factor in all g ranges)
Embedded FIFO technology minimizes host processor load
Built-in motion detection functions for activity/inactivity
monitoring
Supply and I/O voltage range: 2.0 V to 3.6 V
SPI (3- and 4-wire) and I2C digital interfaces
Flexible interrupt modes mappable to either interrupt pin
Measurement ranges selectable via serial command
Bandwidth selectable via serial command
Wide temperature range (−40 to +105°C)
10,000 g shock survival
Pb free/RoHS compliant
Small and thin: 5 mm × 5 mm × 1.45 mm LFCSP package
Qualified for automotive applications
APPLICATIONS
Car alarm
Hill start aid (HSA)
Electronic parking brake
Data recorder (black box)
GENERAL DESCRIPTION
The ADXL3121 is a small, thin, low power, 3-axis accelerometer
with high resolution (13-bit) measurement up to ±12 g. Digital
output data is formatted as 16-bit twos complement and is
accessible through either a serial port interface (SPI) (3- or 4-wire)
or I2C digital interface.
The ADXL312 is well suited for car alarm or black box applica-
tions. It measures the static acceleration of gravity in tilt-sensing
applications, as well as dynamic acceleration resulting from motion
or shock. Its high resolution (2.9 mg/LSB) enables resolution of
inclination changes of as little as 0.25°. A built-in FIFO facili-
tates using oversampling techniques to improve resolution to as
little as 0.05° of inclination.
Several special sensing functions are provided. Activity and
inactivity sensing detects the presence or absence of motion and
whether the acceleration on any axis exceeds a user-set level.
These functions can be mapped to interrupt output pins. An
integrated 32 level FIFO can be used to store data to minimize
host processor intervention.
Low power modes enable intelligent motion-based power
management with threshold sensing and active acceleration
measurement at extremely low power dissipation.
The ADXL312 is supplied in a small, thin 5 mm × 5 mm ×
1.45 mm, 32-lead, LFCSP package.
FUNCTIONAL BLOCK DIAGRAM
3-AXIS
SENSOR
SENSE
ELECTRONICS DIGITAL
FILTER
ADXL312 POWER
MANAGEMENT
CONTROL
AND
INTERRUPT
LOGIC
SERIAL I/O
INT1
V
S
V
DD I/O
INT2
SDA/SDI/SDIO
SDO/ALT
ADDRESS
SCL/SCLK
GND
ADC
32 LEVEL
FIFO
CS
08791-001
Figure 1. ADXL312 Simplified Block Diagram
1 Protected by U.S. Patent 8,156,264B2.
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DOCUMENTATION
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•ADXL312: 3-Axis, ±1.5
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/±3
g
/±6
g
/±12
g
Digital
Accelerometer Data Sheet
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ADXL312 Data Sheet
Rev. A | Page 2 of 32
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution .................................................................................. 5
Pin Configuration and Function Descriptions ............................. 6
Typical Performance Characteristics ............................................. 7
Theory of Operation ...................................................................... 10
Power Sequencing ...................................................................... 10
Power Savings.............................................................................. 10
Serial Communications ................................................................. 12
SPI ................................................................................................. 12
I2C ................................................................................................. 15
Interrupts ..................................................................................... 17
FIFO ............................................................................................. 18
Self-Test ....................................................................................... 19
Register Map ................................................................................... 20
Register Definitions ................................................................... 21
Applications Information .............................................................. 25
Power Supply Decoupling ......................................................... 25
Mechanical Considerations for Mounting .............................. 25
Threshold .................................................................................... 25
Link Mode ................................................................................... 25
Sleep Mode vs. Low Power Mode............................................. 25
Using Self-Test ............................................................................ 26
Data Formatting of Upper Data Rates ..................................... 27
Noise Performance ..................................................................... 28
Axes of Acceleration Sensitivity ............................................... 29
Solder Profile ................................................................................... 30
Outline Dimensions ....................................................................... 31
Ordering Guide .......................................................................... 32
Automotive Products ................................................................. 32
REVISION HISTORY
7/15—Rev. 0 to Rev. A
Changes to Features Section............................................................ 1
Changes to Pin 22 Description, Table 4 ......................................... 6
Changes to Serial Communications Section, SPI Section,
Figure 21, and Figure 22 ................................................................ 12
Added Serial Port I/O Default States Section ............................. 12
Added Preventing Bus Traffic Errors Section and Figure 23;
Renumbered Sequentially ............................................................. 13
Changes to FIFO Section ............................................................... 18
Changes to Figure 41 ...................................................................... 31
12/10—Revision 0: Initial Version
Data Sheet ADXL312
Rev. A | Page 3 of 32
SPECIFICATIONS
TA = −40°C to +105°C, VS = VDD I/O = 3.3 V, acceleration = 0 g, unless otherwise noted.
Table 1. Specifications1
Parameter Test Conditions/Comments Min Typ Max Unit
SENSOR INPUT Each axis
Measurement Range User selectable ±1.5, 3, 6, 12 g
Nonlinearity Percentage of full scale ±0.5 %
Inter-Axis Alignment Error ±0.1 Degrees
Cross-Axis Sensitivity2 ±1 %
OUTPUT RESOLUTION Each axis
All g Ranges Default resolution 10 Bits
±1.5 g Range Full resolution enabled 10 Bits
±3 g Range Full resolution enabled 11 Bits
±6 g Range Full resolution enabled 12 Bits
±12 g Range Full resolution enabled 13 Bits
SENSITIVITY Each axis
Scale Factor at X
OUT
, Y
OUT
, Z
OUT
±1.5 g, 10-bit or full resolution 2.6 2.9 3.2 mg/LSB
Scale Factor at X
OUT
, Y
OUT
, Z
OUT
±3 g, 10-bit resolution 5.2 5.8 6.4 mg/LSB
Scale Factor at X
OUT
, Y
OUT
, Z
OUT
±6 g, 10-bit resolution 10.4 11.6 12.8 mg/LSB
Scale Factor at X
OUT
, Y
OUT
, Z
OUT
±12 g, 10-bit resolution 20.9 23.2 25.5 mg/LSB
Sensitivity at XOUT, YOUT, ZOUT
±1.5
g
, 10-bit or full resolution
312
345
385
LSB/
g
Sensitivity at X
OUT
, Y
OUT
, Z
OUT
±3 g, 10-bit resolution 156 172 192 LSB/g
Sensitivity at X
OUT
, Y
OUT
, Z
OUT
±6 g, 10-bit resolution 78 86 96 LSB/g
Sensitivity at X
OUT
, Y
OUT
, Z
OUT
±12 g, 10-bit resolution 39 43 48 LSB/g
Sensitivity Change Due to Temperature ±0.01 %/°C
0 g BIAS LEVEL Each axis
Initial 0 g Output T = 25°C, X
OUT
, Y
OUT
−150 +150 mg
Initial 0 g Output T = 25°C, Z
OUT
−250 +250 mg
0 g Output over Temperature −40°C < T < 105°C, X
OUT
, Y
OUT
, Z
OUT
−250 +250 mg
0 g Offset Tempco X
OUT
, Y
OUT
±0.8 mg/°C
0 g Offset Tempco Z
OUT
±1.5 mg/°C
NOISE PERFORMANCE
Noise Density (X-, Y-axes) 200 340 440 µg/√Hz
Noise Density (Z-axis) 200 470 595 µg/√Hz
OUTPUT DATA RATE/BANDWIDTH User selectable
Measurement Rate3 6.25 3200 Hz
SELF-TEST4 Data rate ≥ 100 Hz, 2.0 ≤ V
S
≤ 3.6
Output Change in X-Axis
0.20
2.10
g
Output Change in Y-Axis −2.10 −0.20 g
Output Change in Z-Axis 0.30 3.40 g
POWER SUPPLY
Operating Voltage Range (V
S
) 2.0 3.6 V
Interface Voltage Range (V
DD I/O
) 1.7 V
S
V
Supply Current Data rate > 100 Hz 100 170 300 µA
Data rate < 10 Hz 30 55 110 µA
Standby Mode Leakage Current 0.1 2 µA
Turn-On (Wale-Up) Time5 1.4 ms
TEMPERATURE
Operating Temperature Range
−40
+105
°C
ADXL312 Data Sheet
Rev. A | Page 4 of 32
1 All minimum and maximum specifications are guaranteed. Typical specifications are not guaranteed.
2 Cross-axis sensitivity is defined as coupling between any two axes.
3 Bandwidth is half the output data rate.
4 Self-test change is defined as the output (g) when the SELF_TEST bit = 1 (in the DATA_FORMAT register) minus the output (g) when the SELF_TEST bit = 0 (in the
DATA_FORMAT register). Due to device filtering, the output reaches its final value after 4 × τ when enabling or disabling self-test, where τ = 1/(data rate).
5 Turn-on and wake-up times are determined by the user-defined bandwidth. At a 100 Hz data rate, the turn-on and wake-up times are each approximately 11.1 ms. For
other data rates, the turn-on and wake-up times are each approximately τ + 1.1 in milliseconds, where τ = 1/(data rate).
Data Sheet ADXL312
Rev. A | Page 5 of 32
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
Acceleration
Any Axis, Unpowered 10,000 g
Any Axis, Powered 10,000 g
V
S
−0.3 V to 3.9 V
V
DD I/O
−0.3 V to 3.9 V
All Other Pins −0.3 V to VDD I/O + 0.3 V or
3.9 V, whichever is less
Output Short-Circuit Duration
(Any Pin to Ground)
Indefinite
Temperature Range
Powered −40°C to +125°C
Storage −40°C to +125°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 3. Thermal Resistance
Package Type θ
JA
θ
JC
Unit
32-Lead LFCSP Package 27.27 30 °C/W
ESD CAUTION
ADXL312 Data Sheet
Rev. A | Page 6 of 32
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
NOTES
1. NC = NO CO NNE C T. DO NOT CONNECT TO THIS PIN.
2. THE EXPOSED PAD MUST BE SOL DE RE D TO THE GROUND P LANE.
24 SDA/SDI/SDIO
23 SDO/ALTADDRESS
22 RESERVED
21 INT2
20 INT1
19 NC
18 NC
17 NC
1
2
3
4
5
6
7
8
GND
RESERVED
GND
GND
VS
CS
RESERVED
NC
9
10
11
12
13
14
15
16
NC
NC
NC
NC
NC
NC
NC
NC
32
31
30
29
28
27
26
25
NC
VDD I/O
NC
NC
NC
NC
SCL/SCLK
NC
TOP VIEW
(No t t o Scal e)
ADXL312
08791-002
Figure 2. Pin Configuration (Top View)
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1 GND This pin must be connected to ground.
2 Reserved Reserved. This pin must be connected to V
S
or left open.
3
GND
This pin must be connected to ground.
4 GND This pin must be connected to ground.
5 V
S
Supply Voltage.
6 CS Chip Select.
7 Reserved Reserved. This pin must be left open.
8 to19 NC No Connect. Do not connect to this pin.
20 INT1 Interrupt 1 Output.
21 INT2 Interrupt 2 Output.
22 Reserved Reserved. This pin must be connected to GND.
23 SDO/ALT ADDRESS Serial Data Out, Alternate I2C Address Select.
24 SDA/SDI/SDIO Serial Data (I2C), Serial Data In (SPI 4-Wire), Serial Data In/Out (SPI 3-Wire).
25 NC No Connect. Do not connect to this pin.
26 SCL/SCLK Serial Communications Clock.
27 to 30 NC No Connect. Do not connect to this pin.
31 V
DD I/O
Digital Interface Supply Voltage.
32 NC No Connect.
EP
The exposed pad must be soldered to the ground plane.
Data Sheet ADXL312
Rev. A | Page 7 of 32
TYPICAL PERFORMANCE CHARACTERISTICS
N > 1000, unless otherwise noted.
0
5
10
15
20
25
30
35
40
–150 –120 –60 –30–90 06030 90 120 150
ZERO g OFFSET (mg)
PERCENT OF POPULATION (%)
08791-003
Figure 3. X-Axis Zero-g Bias. 25°C, VS = VDD I/O = 3.3 V
0
5
10
15
20
25
30
35
–150 –120 –60 –30–90 06030 90 120 150
ZERO g OFFSET (mg)
PERCENT OF POPULATION (%)
08791-004
Figure 4. Y Axis Zero-g Bias, 25°C, VS = VDD I/O = 3.3 V
0
5
10
15
20
25
30
35
40
45
50
–250 –200 –100 –50–150 010050 150 200 250
ZERO g OFFSET (mg)
PERCENT OF POPULATION (%)
08791-005
Figure 5. Z Axis Zero-g Bias, 25°C, VS = VDD I/O = 3.3 V
0
5
10
15
20
25
30
35
40
–3.0
–2.5
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
2.0
3.0
1.5
2.5
ZERO g T EMPERATURE COEFFICIENT (mg/°C)
PERCENT OF POPULATION (%)
08791-006
Figure 6. X-Axis Zero-g Bias Drift, VS = VDD I/O = 3.3 V
0
5
10
15
20
25
30
35
40
–3.0
–2.5
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
2.0
3.0
1.5
2.5
ZERO g T EMPERATURE COEFFICIENT (mg/°C)
PERCENT OF POPULATION (%)
08791-007
Figure 7. Y-Axis Zero-g Bias Drift, VS = VDD I/O = 3.3 V
0
5
10
15
20
25
–3.0
–2.5
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
2.0
3.0
1.5
2.5
ZERO g T EMPERATURE COEFFICIENT (mg/°C)
PERCENT OF POPULATION (%)
08791-008
Figure 8. Z-Axis Zero-g Bias Drift, VS = VDD I/O = 3.3 V
ADXL312 Data Sheet
Rev. A | Page 8 of 32
0
10
20
40
60
30
50
70
312
318
324
330
336
342
348
354
360
372
384
366
378
SENSITIVITY (LSB/g)
PERCENT OF POPULATION (%)
08791-009
Figure 9. X-Axis Sensitivity, VS = VDD I/O = 3.3 V, 25°C
0
10
20
40
60
30
50
70
312
318
324
330
336
342
348
354
360
372
384
366
378
SENSITIVITY (LSB/g)
PERCENT OF POPULATION (%)
08791-010
Figure 10. Y-Axis Sensitivity, VS = VDD I/O = 3.3 V, 25°C
0
10
20
40
60
30
50
70
312
318
324
330
336
342
348
354
360
372
384
366
378
SENSITIVITY (LSB/g)
PERCENT OF POPULATION (%)
08791-011
Figure 11. Z-Axis Sensitivity, VS = VDD I/O = 3.3 V, 25°C
0
5
10
20
15
25
30
–0.030
–0.025
–0.020
–0.015
–0.010
–0.005
0
0.005
0.010
0.020
0.030
0.015
0.025
SENSITIVITY TEMPERATURE COEFFICIENT (%/°C)
PERCENT OF POPULATION (%)
08791-012
Figure 12. X-Axis Sensitivity Temperature Coefficient, VS = VDD I/O = 3.3 V
0
5
10
20
15
25
35
30
–0.030
–0.025
–0.020
–0.015
–0.010
–0.005
0
0.005
0.010
0.020
0.030
0.015
0.025
SENSITIVITY TEMPERATURE COEFFICIENT (%/°C)
PERCENT OF POPULATION (%)
08791-013
Figure 13. Y-Axis Sensitivity Temperature Coefficient, VS = VDD I/O = 3.3 V
0
5
10
20
15
25
35
30
–0.030
–0.025
–0.020
–0.015
–0.010
–0.005
0
0.005
0.010
0.020
0.030
0.015
0.025
SENSITIVITY TEMPERATURE COEFFICIENT (%/°C)
PERCENT OF POPULATION (%)
08791-014
Figure 14. Z-Axis Sensitivity Temperature Coefficient, VS = VDD I/O = 3.3 V
Data Sheet ADXL312
Rev. A | Page 9 of 32
0
10
20
40
30
50
80
70
60
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
SELF-T EST RESPONSE (g)
PERCENT OF POPULATION (%)
08791-015
Figure 15. X-Axis Self-Test Delta, VS = VDD I/O = 3.3 V, 25°C
0
10
20
40
30
50
70
60
–2.1
–1.9
–1.7
–1.5
–1.3
–1.1
–0.9
–0.7
–0.5
–0.3
SELF-T EST RESPONSE (g)
PERCENT OF POPULATION (%)
08791-016
Figure 16. Y-Axis Self-Test Delta, VS = VDD I/O = 3.3 V, 25°C
0
10
20
40
30
50
80
70
60
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.33.0
SELF-T EST RESPONSE (g)
PERCENT OF POPULATION (%)
08791-017
Figure 17. Z-Axis Self-Test Delta, VS = VDD I/O = 3.3 V, 25°C
0
10
20
40
30
50
80
70
60
30
50
70
90
110
130
150
170
190
210
230
250
270
290
310
CURRENT (nA)
PERCENT OF POPULATION (%)
08791-018
Figure 18. Standby Mode Current Consumption, VS = VDD I/O = 3.3 V, 25°C
0
5
10
20
15
25
35
30
100
120
140
160
180
200
220
240
260
280
300
CURRENT CONSUM P TION (µA)
PERCENT OF POPULATION (%)
08791-019
Figure 19. Current Consumption, Measurement Mode, Data Rate = 100 Hz,
VS = VDD I/O = 3.3 V, 25°C
0
50
100
150
200
2.0 2.4 2.8 3.2 3.6
SUPPLY
VOLTAGE (V)
SUPPLY CURRENT ( µA)
08791-233
Figure 20. Supply Current vs. Supply Voltage, VS at 25°C
ADXL312 Data Sheet
Rev. A | Page 10 of 32
THEORY OF OPERATION
The ADXL312 is a complete 3-axis acceleration measurement
system with a selectable measurement range of ±1.5 g, ±3 g, ±6
g, or ±12 g. It measures both dynamic acceleration resulting
from motion or shock and static acceleration, such as gravity,
which allows it to be used as a tilt sensor.
The sensor is a polysilicon surface-micromachined structure
built on top of a silicon wafer. Polysilicon springs suspend the
structure over the surface of the wafer and provide a resistance
against acceleration forces.
Deflection of the structure is measured using differential
capacitors that consist of independent fixed plates and plates
attached to the moving mass. Acceleration deflects the beam
and unbalances the differential capacitor, resulting in a sensor
output whose amplitude is proportional to acceleration. Phase-
sensitive demodulation is used to determine the magnitude and
polarity of the acceleration.
POWER SEQUENCING
Power can be applied to VS or VDD I/O in any sequence without
damaging the ADXL312. All possible power-on modes are
summarized in Table 5. The interface voltage level is set with
the interface supply voltage, VDD I/O, which must be present to
ensure that the ADXL312 does not create a conflict on the
communication bus. For single-supply operation, VDD I/O can be
the same as the main supply, VS. In a dual-supply application,
however, VDD I/O can differ from VS to accommodate the desired
interface voltage, as long as VS is greater than or equal to VDD I/O.
After VS is applied, the device enters standby mode, where power
consumption is minimized and the device waits for VDD I/O to be
applied and for the command to enter measurement mode to be
received. (This command can be initiated by setting the measure
bit in the POWER_CTL register (Address 0x2D).) In addition, any
register can be written to or read from to configure the part while
the device is in standby mode. It is recommended to configure the
device in standby mode and then to enable measurement mode.
Clearing the measure bit returns the device to the standby mode.
Table 5. Power Sequencing
Condition V
S
V
DD I/O
Description
Power Off Off Off The device is completely off, but
there is a potential for a
communication bus conflict.
Bus Disabled On Off The device is on in standby mode,
but communication is unavailable
and creates a conflict on the
communication bus. The duration
of this state should be minimized
during power-up to prevent a
conflict.
Bus Enabled Off On No functions are available, but
the device will not create a conflict
on the communication bus.
Standby or
Measurement
On On The device is in standby mode,
awaiting a command to enter
measurement mode, and all sensor
functions are off. After the device is
instructed to enter measurement
mode, all sensor functions are
available.
POWER SAVINGS
Power Modes
The ADXL312 automatically modulates its power consumption
in proportion to its output data rate, as outlined in Table 6. If
additional power savings is desired, a lower power mode is
available. In this mode, the internal sampling rate is reduced,
allowing for power savings in the 12.5 Hz to 400 Hz data rate
range at the expense of slightly greater noise. To enter low
power mode, set the LOW_POWER bit (Bit 4) in the BW_RATE
register (Address 0x2C). The current consumption in low power
mode is shown in Table 7 for cases where there is an advantage
to using low power mode. Use of low power mode for a data
rate not shown in Table 7 does not provide any advantage over
the same data rate in normal power mode. Therefore, it is
recommended that only data rates shown in Table 7 be used in
low power mode. The current consumption values shown in
Table 6 and Table 7 are for a VS of 3.3 V.
Data Sheet ADXL312
Rev. A | Page 11 of 32
Table 6. Current Consumption vs. Data Rate
(TA = 25°C, VS = VDD I/O = 3.3 V)
Output Data
Rate (Hz) Bandwidth (Hz) Rate Code I
DD
(µA)
3200 1600 1111 170
1600
800
1110
115
800 400 1101 170
400 200 1100 170
200 100 1011 170
100 50 1010 170
50 25 1001 115
25 12.5 1000 82
12.5 6.25 0111 65
6.25 3.125 0110 57
Table 7. Current Draw vs. Data Rate, Low Power Mode
(TA = 25°C, VS = VDD I/O = 3.3 V)
Output Data
Rate (Hz) Bandwidth (Hz) Rate Code I
DD
(µA)
400 200 1100 115
200 100 1011 82
100 50 1010 65
50 25 1001 57
25 12.5 1000 50
12.5 6.25 0111 43
Autosleep Mode
Additional power savings can be had by having the ADXL312
automatically switch to sleep mode during periods of inactivity.
To enable this feature, set the THRESH_INACT register
(Address 0x25) to an acceleration threshold value. Levels of
acceleration below this threshold are regarded as no activity
levels. Set TIME_INACT (Address 0x26) to an appropriate
inactivity time period. Then set the AUTO_SLEEP bit and the
link bit in the POWER_CTL register (Address 0x2D). If the
device does not detect a level of acceleration in excess of
THRES_INACT for TIME_INACT seconds, then the device is
transitioned to sleep mode automatically. Current consumption
at the sub-8 Hz data rates used in this mode is typically 30 µA
for a VS of 3.3 V.
Standby Mode
For even lower power operation, standby mode can be used. In
standby mode, current consumption is reduced to 0.1µA
(typical). In this mode, no measurements are made. Standby
mode is entered by clearing the measure bit (Bit 3) in the
POWER_CTL register (Address 0x2D). Placing the device into
standby mode preserves the contents of the FIFO.
ADXL312 Data Sheet
Rev. A | Page 12 of 32
SERIAL COMMUNICATIONS
The ADXL312 can communicate via I2C and SPI digital
communications interfaces. In both cases, the ADXL312 operates
as a slave. If I2C is the desired interface for the application, tie
the CS pin directly to VDD I/O as shown in Figure 27. If SPI is the
desired interface for the application, drive the CS pin with an
external controller, as demonstrated in Figure 21 and Figure 22.
Because the I2C interface is enabled any time the CS pin is brought
up to VDD I/O, there is a potential for bus conflicts to occur when the
ADXL312 is implemented into a SPI network. Refer to the
Preventing Bus Traffic Errors section for information on how to
avoid such conditions. In both SPI and I2C modes of operation,
ignore data transmitted from the ADXL312 to the master device
during writes to the ADXL312.
Note that throughout this section, multifunction pins, such as
SDA/SDI/SDIO, are referred to either by the entire pin name or
by a single function of the pin, for example, SDA, when only
that function is relevant.
SERIAL PORT I/O DEFAULT STATES
Ensure that all serial port I/Os are in a defined state and that no
pin is allowed to float when not in use. This is applicable to all
serial port I/Os, regardless of SPI or I2C operation.
For I2C applications, always tie the CS pin high to VDD I/O.
Connect the SCL and SDA pins to an external controller, with
pull-up resistors implemented according to the UM10204 I2C-
Bus Specification and User Manual, Rev. 03—19 June 2007,
available from NXP Semiconductor. The ALT ADDRESS pin
must be tied to either VDD I/O or ground, thereby selecting the
desired I2C address for the ADXL312.
If SPI is the intended communications interface, drive the CS
pin with an external controller, as shown in Figure 21 and
Figure 22. When communications with the ADXL312 are
suspended (CS = VDD I/O), ensure that the SCLK, SDI/SDIO, and
SDO pins are not floating.
For either SPI or I2C operation, not taking these precautions may
result in an inability to communicate with the device or excessive
current consumption.
SPI
For the SPI, either 3- or 4-wire configuration is possible, as shown
in the connection diagrams in Figure 21 and Figure 22. Clearing
the SPI bit in the DATA_FORMAT register (Address 0x31)
selects 4-wire mode, whereas setting the SPI bit selects 3-wire
mode. The maximum SPI clock speed is 5 MHz with 100 pF
maximum loading, and the timing scheme follows clock polarity
(CPOL) = 1 and clock phase (CPHA) = 1. If power is applied to
the ADXL312 before the clock polarity and phase of the host
processor are configured, bring the CS pin high before changing
the clock polarity and phase. When using 3-wire SPI, pull the
SDO pin up to VDD I/O or down to ground via a 10 kΩ resistor, as
shown in Figure 21.
CS is the serial port enable line and is controlled by the SPI master.
This line must go low at the start of a transmission and high at
the end of a transmission, as shown in Figure 24. SCLK is the
serial port clock and is supplied by the SPI master. SDI and
SDO are the serial data input and output, respectively.
08791-044
ADXL312
PROCESSOR
CS
SDIO
SDO
SCLK
D_OUT
D_IN/OUT
D_OUT
R
PD
Figure 21. 3-Wire SPI Connection Diagram
08791-045
ADXL312
PROCESSOR
CS
SDI
SDO
SCLK
D_OUT
D_OUT
D_IN
D_OUT
Figure 22. 4-Wire SPI Connection Diagram
To read or write multiple bytes in a single transmission, the
multiple-byte bit, located after the R/W bit in the first byte transfer
(MB in Figure 24 to Figure 26), must be set. After the register
addressing and the first byte of data, each subsequent set of
clock pulses (eight clock pulses) causes the ADXL312 to point
to the next register for a read or write. This shifting continues
until the clock pulses cease and CS is deasserted. To perform reads
or writes on different nonsequential registers, CS must be
deasserted between transmissions, and the new register must be
addressed separately.
The timing diagram for 3-wire SPI reads or writes is shown in
Figure 26. The 4-wire equivalents for SPI writes and reads are
shown in Figure 24 and Figure 25, respectively. For correct opera-
tion of the device, the logic thresholds and timing parameters in
Table 8 and Table 9 must be met at all times.
Use of the 3200 Hz and 1600 Hz output data rates is only
recommended with SPI communication rates greater than or
equal to 2 MHz. The 800 Hz output data rate is recommended
only for communication speeds greater than or equal to 400 kHz,
and the remaining data rates scale proportionally. For example,
the minimum recommended communication speed for a 200 Hz
output data rate is 100 kHz. Operation at an output data rate
below the recommended minimum may result in undesirable
effects on the acceleration data, including missing samples or
additional noise.
Data Sheet ADXL312
Rev. A | Page 13 of 32
Preventing Bus Traffic Errors
The ADXL312 CS pin initiates SPI transactions and enables I2C
mode. When the ADXL312 is used on a SPI bus with multiple
devices, its CS pin is held high while the master communicates
with the other devices. There may be conditions where a SPI
command transmitted to another device looks like a valid I2C
command. In this case, the ADXL312 interprets this as an
attempt to communicate in I2C mode and may interfere with
other bus traffic. Unless bus traffic can be adequately controlled
to ensure such a condition never occurs, it is recommended to
add a logic gate in front of the SDI pin, as shown in Figure 23.
This OR gate holds the SDA line high when CS is high to
prevent bus traffic at the ADXL312 from appearing as an I2C
start command.
08791-046
ADXL312
PROCESSOR
CS
SDI
SDO
SCLK
D_OUT
D_OUT
D_IN
D_OUT
Figure 23. Recommended SPI Connection Diagram when Using Multiple SPI
Devices on a Single Bus
Table 8. SPI Digital Input/Output
Limit1
Parameter Test Conditions Min Max Unit
Digital Input
Low Level Input Voltage (V
IL
) 0.3 × V
DD I/O
V
High Level Input Voltage (V
IH
) 0.7 × V
DD I/O
V
Low Level Input Current (I
IL
) V
IN
= V
DD I/O
0.1 µA
High Level Input Current (I
IH
) V
IN
= 0 V −0.1 µA
Digital Output
Low Level Output Voltage (V
OL
) I
OL
= 10 mA 0.2 × V
DD I/O
V
High Level Output Voltage (V
OH
) I
OH
= −4 mA 0.8 × V
DD I/O
V
Low Level Output Current (I
OL
) V
OL
= V
OL, max
10 mA
High Level Output Current (I
OH
) V
OH
= V
OH, min
−4 mA
Pin Capacitance f
IN
= 1 MHz, V
IN
= 2.5 V 8 pF
1 Limits based on characterization results, not production tested.
Table 9. SPI Timing (TA = 25°C, VS = VDD I/O = 3.3 V)1
Limit2, 3
Parameter
Min
Max
Unit
Description
f
SCLK
5 MHz SPI clock frequency.
tSCLK
200
ns
1/(SPI clock frequency) mark-space ratio for the SCLK input is 40/60 to 60/40.
tDELAY 5 ns CS falling edge to SCLK falling edge .
tQUIET 5 ns SCLK rising edge to CS rising edge.
tDIS 10 ns CS rising edge to SDO disabled.
t
CS,DIS
150 ns CS deassertion between SPI communications.
t
S
0.3 × t
SCLK
ns SCLK low pulse width (space).
t
M
0.3 × t
SCLK
ns SCLK high pulse width (mark).
t
SETUP
5 ns SDI valid before SCLK rising edge.
t
HOLD
5 ns SDI valid after SCLK rising edge.
t
SDO
40 ns SCLK falling edge to SDO/SDIO output transition.
t
R
4 20 ns SDO/SDIO output high to output low transition.
tF4
20
ns
SDO/SDIO output low to output high transition.
1 The CS, SCLK, SDI, and SDO pins are not internally pulled up or down; they must be driven for proper operation.
2 Limits based on characterization results, characterized with fSCLK = 5 MHz and bus load capacitance of 100 pF; not production tested.
3 The timing values are measured corresponding to the input thresholds (VIL and VIH) given in Table 8.
4 Output rise and fall times measured with capacitive load of 150 pF.
ADXL312 Data Sheet
Rev. A | Page 14 of 32
t
DELAY
t
SETUP
t
HOLD
t
SDO
t
R
,
t
F
XXX
WMB A5 A0 D7 D0
XX X
ADDRESS BITS DATA BITS
t
SCLK
t
M
t
S
t
QUIET
t
DIS
t
CS,DIS
S
CL
K
SDI
SDO
CS
08791-129
Figure 24. SPI 4-Wire Write
CS
XXX
RMBA5 A0
D7 D0X
XX
ADDRESS BITS
DATA BITS
t
DIS
SCL
K
SDI
SDO
t
QUIET
t
SDO
t
SETUP
t
DELAY
t
SCLK
t
M
t
S
t
R
,
t
F
t
HOLD
t
CS,DIS
08791-130
Figure 25. SPI 4-Wire Read
CS
t
DELAY
t
SETUP
t
HOLD
t
SDO
R/W MB A5 A0 D7 D0
ADDRESS BITS DATA BITS
t
SCLK
t
M
t
S
t
QUIET
SCLK
SDIO
SDO
NOTES
1. t
SDO
IS ONLY PRESENT DURING READS.
t
R
,t
F
t
CS,DIS
08791-131
Figure 26. SPI 3-Wire Read/Write
Data Sheet ADXL312
Rev. A | Page 15 of 32
I2C
With CS tied high to VDD I/O, the ADXL312 is in I2C mode,
requiring a simple 2-wire connection as shown in Figure 27.
The ADXL312 conforms to the UM10204 I2C-Bus Specification
and User Manual, Rev. 03—19 June 2007, available from NXP
Semiconductor. It supports standard (100 kHz) and fast (400 kHz)
data transfer modes if the bus parameters given in Table 10 and
Table 11 are met. Single- or multiple-byte reads/writes are
supported, as shown in Figure 28. With the ALT ADDRESS pin
high, the 7-bit I2C address for the device is 0x1D, followed by the
R/W bit. This translates to 0x3A for a write and 0x3B for a read. An
alternate I2C address of 0x53 (followed by the R/W bit) can be
chosen by grounding the ALT ADDRESS pin (Pin 7). This
translates to 0xA6 for a write and 0xA7 for a read.
PROCESSOR
D IN/ OUT
D OUT
RP
VDD I/O
RP
ADXL312
CS
SDA
ALT ADDRESS
SCL
08791-032
Figure 27. I2C Connection Diagram (Address 0x53)
If other devices are connected to the same I2C bus, the nominal
operating voltage level of these other devices cannot exceed VDD I/O
by more than 0.3 V. External pull-up resistors, RP, are necessary
for proper I2C operation. Refer to the UM10204 I2C-Bus
Specification and User Manual, Rev. 03—19 June 2007, when
selecting pull-up resistor values to ensure proper operation.
Table 10. I2C Digital Input/Output
Limit1
Parameter Test Conditions Min Max Unit
Digital Input
Low Level Input Voltage (V
IL
) 0.3 × V
DD I/O
V
High Level Input Voltage (V
IH
) 0.7 × V
DD I/O
V
Low Level Input Current (I
IL
) V
IN
= V
DD I/O
0.1 µA
High Level Input Current (I
IH
) V
IN
= 0 V −0.1 µA
Digital Output
Low Level Output Voltage (V
OL
) V
DD I/O
< 2 V, I
OL
= 3 mA 0.2 × V
DD I/O
V
V
DD I/O
≥ 2 V, I
OL
= 3 mA 400 mV
Low Level Output Current (I
OL
) V
OL
= V
OL, max
3 mA
Pin Capacitance f
IN
= 1 MHz, V
IN
= 2.5 V 8 pF
1 Limits based on characterization results; not production tested.
NOTES
1. THIS START IS EITHER A RESTART OR A STOP FOLLOWED BY A START.
2. T HE S HADE D ARE AS RE P RE S E NT W HE N THE DEV ICE IS L ISTENI NG.
08791-033
MASTER START SLAVE ADDRESS + WRIT E REGIS TER ADDRE SS
SLAVE ACK ACK ACK
MASTER START SLAVE ADDRESS + WRIT E REGIS TER ADDRE SS
SLAVE ACK ACK ACK ACK
MASTER START SLAVE ADDRESS + WRIT E REGIS TER ADDRE SS STOP
SLAVE ACK ACK
MASTER START
START
1
START
1
SLAVE ADDRESS + WRI T E REGIS TE R ADDRESS NACK STOP
SLAVE ACK ACK DATA
STOP
ACK
SINGLE-BYTE W RI T E
MULTIPLE- BYTE WRI TE
DATA
DATA
MULTIPLE-BYTE READ
SLAVE ADDRESS + READ
SLAVE ADDRESS + READ
ACK
DATA
DATA
DATA
STOP
NACK
ACK
SINGLE-BYTE READ
Figure 28. I2C Device Addressing
ADXL312 Data Sheet
Rev. A | Page 16 of 32
Table 11. I2C Timing (TA = 25°C, VS = VDD I/O = 3.3 V)
Limit1, 2
Parameter Min Max Unit Description
f
SCL
400 kHz SCL clock frequency
t
1
2.5 µs SCL cycle time
t
2
0.6 µs t
HIGH
, SCL high time
t
3
1.3 µs t
LOW
, SCL low time
t
4
0.6 µs t
HD, STA
, start/repeated start condition hold time
t
5
100 ns t
SU, DAT
, data setup time
t
6
3, 4, 5, 6 0 0.9 µs t
HD, DAT
, data hold time
t
7
0.6 µs t
SU, STA
, setup time for repeated start
t
8
0.6 µs t
SU, STO
, stop condition setup time
t
9
1.3 µs t
BUF
, bus-free time between a stop condition and a start condition
t
10
300 ns t
R
, rise time of both SCL and SDA when receiving
0 ns t
R
, rise time of both SCL and SDA when receiving or transmitting
t11
250
ns
tF, fall time of SDA when receiving
300
ns
tF, fall time of both SCL and SDA when transmitting
20 + 0.1 C
b7
ns t
F
, fall time of both SCL and SDA when transmitting or receiving
C
b
400 pF Capacitive load for each bus line
1 Limits based on characterization results, with fSCL = 400 kHz and a 3 mA sink current; not production tested.
2 All values referred to the VIH and the VIL levels given in Table 10.
3 t6 is the data hold time that is measured from the falling edge of SCL. It applies to data in transmission and acknowledge.
4 A transmitting device must internally provide an output hold time of at least 300 ns for the SDA signal (with respect to VIH(min) of the SCL signal) to bridge the
undefined region of the falling edge of SCL.
5 The maximum t6 value must be met only if the device does not stretch the low period (t3) of the SCL signal.
6 The maximum value for t6 is a function of the clock low time (t3), the clock rise time (t10), and the minimum data setup time (t5(min)). This value is calculated as
t6(max) = t3 − t10 − t5(min).
7 Cb is the total capacitance of one bus line in picofarads.
SDA
t9
SCL
t3t10 t11 t4
t4t6t2t5t7t1t8
START
CONDITION REPEATED
START
CONDITION
STOP
CONDITION
08791-034
Figure 29. I2C Timing Diagram
Data Sheet ADXL312
Rev. A | Page 17 of 32
INTERRUPTS
The ADXL312 provides two output pins for driving interrupts:
INT1 and INT2. Both interrupt pins are push-pull, low impedance
pins with output specifications shown in Table 12. The default
configuration of the interrupt pins is active high. This can be