Direct Modulation/Fast Waveform Generating,
13 GHz, Fractional-N Frequency Synthesizer
Data Sheet
ADF4159
Rev. E Document Feedback
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FEATURES
RF bandwidth to 13 GHz
High and low speed FMCW ramp generation
25-bit fixed modulus allows subhertz frequency resolution
PFD frequencies up to 110 MHz
Normalized phase noise floor of −224 dBc/Hz
FSK and PSK functions
Sawtooth, triangular, and parabolic waveform generation
Ramp superimposed with FSK
Ramp with 2 different sweep rates
Ramp delay, frequency readback, and interrupt functions
Programmable phase control
2.7 V to 3.45 V analog power supply
1.8 V digital power supply
Programmable charge pump currents
3-wire serial interface
Digital lock detect
ESD performance: 3000 V HBM, 1000 V CDM
Qualified for automotive applications
APPLICATIONS
FMCW radars
Communications test equipment
Communications infrastructure
GENERAL DESCRIPTION
The ADF4159 is a 13 GHz, fractional-N frequency synthesizer
with modulation and both fast and slow waveform generation
capability. The part uses a 25-bit fixed modulus, allowing subhertz
frequency resolution.
The ADF4159 consists of a low noise digital phase frequency
detector (PFD), a precision charge pump, and a programmable
reference divider. The Σ-Δ-based fractional interpolator allows
programmable fractional-N division. The INT and FRAC registers
define an overall N divider as N = INT + (FRAC/225).
The ADF4159 can be used to implement frequency shift keying
(FSK) and phase shift keying (PSK) modulation. Frequency sweep
modes are also available to generate various waveforms in the
frequency domain, for example, sawtooth and triangular wave-
forms. Sweeps can be set to run automatically or with each step
manually triggered by an external pulse. The ADF4159 features
cycle slip reduction circuitry, which enables faster lock times
without the need for modifications to the loop filter.
Control of all on-chip registers is via a simple 3-wire interface. The
ADF4159 operates with an analog power supply in the range of
2.7 V to 3.45 V and a digital power supply in the range of 1.62 V
to 1.98 V. The device can be powered down when not in use.
FUNCTIONAL BLOCK DIAGRAM
LOCK
DETECT
CP
DATA
LE
32-BIT
DATA
REGISTER
CLK
AGND
DV
DD
DGND
R
DIV
SD
OUT
N
DIV
DGND CPGND
SDV
DD
DV
DD
AV
DD
V
P
CE
RF
IN
A
RF
IN
B
OUTPUT
MUX
MUXOUT
+
HIGH-Z
PHASE
FREQUENCY
DETECTOR
ADF4159
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
FRACTION
VALUE INTEGER
VALUE
CHARGE
PUMP
TX
DATA
REFERENCE
R
SET
REF
IN
×2
DOUBLER 5-BIT
R COUNT E R ÷2
DIVIDER
MODULUS
2
25
VALUE
N COUNT E R +
SW2
SW1
SDGND
10849-001
FAST LOCK
SWITCH
CSR
Figure 1.
ADF4159 Data Sheet
Rev. E | Page 2 of 36
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 3
Specifications ..................................................................................... 4
Timing Specifications .................................................................. 5
Absolute Maximum Ratings ............................................................ 7
Thermal Resistance ...................................................................... 7
ESD Caution .................................................................................. 7
Pin Configuration and Function Descriptions ............................. 8
Typical Performance Characteristics ............................................. 9
Theory of Operation ...................................................................... 11
Reference Input Section ............................................................. 11
RF Input Stage ............................................................................. 11
RF INT Divider ........................................................................... 11
25-Bit Fixed Modulus ................................................................ 11
INT, FRAC, and R Counter Relationship ................................ 11
R Counter .................................................................................... 11
Phase Frequency Detector (PFD) and Charge Pump ............ 12
MUXOUT and Lock Detect ...................................................... 12
Input Shift Register..................................................................... 12
Program Modes .......................................................................... 12
Register Maps .................................................................................. 13
FRAC/INT Register (R0) Map .................................................. 15
LSB FRAC Register (R1) Map ................................................... 16
R Divider Register (R2) Map .................................................... 17
Function Register (R3) Map ...................................................... 19
Clock Register (R4) Map ........................................................... 21
Deviation Register (R5) Map .................................................... 22
Step Register (R6) Map .............................................................. 23
Delay Register (R7) Map ........................................................... 24
Applications Information .............................................................. 25
Initialization Sequence .............................................................. 25
RF Synthesizer Worked Example ............................................. 25
Reference Doubler ...................................................................... 25
Cycle Slip Reduction for Faster Lock Times ........................... 25
Modulation .................................................................................. 26
Waveform Generation ............................................................... 26
Waveform Deviations and Timing ........................................... 27
Single Ramp Burst ...................................................................... 27
Single Triangular Burst .............................................................. 27
Single Sawtooth Burst ................................................................ 27
Sawtooth Ramp........................................................................... 27
Triangular Ramp ........................................................................ 27
FMCW Radar Ramp Settings Worked Example ...................... 27
Activating the Ramp .................................................................. 28
Other Waveforms ....................................................................... 28
Ramp Complete Signal to MUXOUT ..................................... 31
External Control of Ramp Steps ............................................... 31
Interrupt Modes and Frequency Readback ............................ 32
Fast Lock Mode .......................................................................... 33
Spur Mechanisms ....................................................................... 34
Filter Design Using ADIsimPLL .............................................. 34
PCB Design Guidelines for the Chip Scale Package .............. 34
Application of the ADF4159 in FMCW Radar........................... 35
Outline Dimensions ....................................................................... 36
Ordering Guide .......................................................................... 36
Automotive Products ................................................................. 36
Data Sheet ADF4159
Rev. E | Page 3 of 36
REVISION HISTORY
7/14—Rev. D to Rev. E
Changed θJA from 30.4°C/W to 56°C/W ........................................ 7
Changes to Single Full Triangle Section ....................................... 24
Changes to Timeout Interval Section ........................................... 27
11/13—Rev. C to Rev. D
Change to General Description Section ......................................... 1
Moved Revision History Section ..................................................... 3
Changes to Table 1 ............................................................................ 4
Change to 25-Bit Fixed Modulus Section .................................... 11
Changes to Loss of Lock (LOL) Section and Lock Detect
Precision (LDP) Section ................................................................. 19
Changes to Σ-Δ Modulator Mode Section, Clock Divider Select
Section, and Clock Divider Mode Section ................................... 21
Added External Control of Ramp Steps Section and Figure 49;
Renumbered Sequentially .............................................................. 31
Changes to Fast Lock Timer and Register Sequences Section,
Fast Lock Example Section, and Fast Lock Loop Filter Topology
Section .............................................................................................. 33
Changes to Ordering Guide ........................................................... 36
9/13—Rev. B to Rev. C
Change to Features Section .............................................................. 1
Change to Figure 2 ............................................................................ 4
Changes to Figure 24 ...................................................................... 13
Added Σ-Δ Modulator Mode Section ........................................... 20
Changes to Figure 29 ...................................................................... 20
Change to Interrupt Modes and Frequency Readback Section ...... 31
Change to Fast Lock Timer and Register Sequences Section .... 32
Changes to Ordering Guide ........................................................... 35
Added Automotive Products Section ........................................... 35
6/13—Rev. A to Rev. B
Changed PFD Antibacklash Pulse from 3 ns to 1 ns in Phase
Frequency Detector (PFD) and Charge Pump Section .............. 11
Changes to Charge Pump Current Setting Section and
Reference Doubler Section ............................................................ 16
Changes to Negative Bleed Current Enable Section and Loss of
Lock (LOL) Section ......................................................................... 18
5/13—Revision A: Initial Version
ADF4159 Data Sheet
Rev. E | Page 4 of 36
SPECIFICATIONS
AVDD = VP = 2.7 V to 3.45 V, DVDD = SDVDD = 1.8 V, AGND = DGND = SDGND = CPGND = 0 V, fPFD = 110 MHz, TA = TMIN to TMAX,
dBm referred to 50 Ω, unless otherwise noted.
Table 1.
Parameter1 Min Typ Max Unit Test Conditions/Comments
RF CHARACTERISTICS
RF Input Frequency (RFIN) 0.5 13 GHz 10 dBm min to 0 dBm max; for lower
frequencies, ensure a slew rate ≥ 400 V/µs
Prescaler Output Frequency 2 GHz For higher frequencies, use 8/9 prescaler
REFERENCE CHARACTERISTICS
REFIN Input Frequency 10 260 MHz 5 dBm min to +9 dBm max biased at
1.8/2 (ac coupling ensures 1.8/2 bias); for
frequencies < 10 MHz, use a dc-coupled,
CMOS-compatible square wave with a
slew rate > 25 V/µs
Reference Doubler Enabled 10 50 MHz Bit DB20 in Register R2 set to 1
REFIN Input Capacitance 1.2 pF
REFIN Input Current ±100 µA
PHASE FREQUENCY DETECTOR (PFD)
Phase Detector Frequency2 110 MHz
CHARGE PUMP
ICP Sink/Source Current Programmable
High Value 4.8 mA RSET = 5.1 k
Low Value 300 µA
Absolute Accuracy 2.5 % RSET = 5.1 kΩ
RSET Range 4.59 5.1 5.61 kΩ
ICP Three-State Leakage Current 1 nA Sink and source current
Sink and Source Matching 2 % 0.5 V < VCP < VP − 0.5 V
ICP vs. VCP 2 % 0.5 V < VCP < VP − 0.5 V
ICP vs. Temperature 2 % VCP = VP/2
LOGIC INPUTS
Input High Voltage, VINH 1.17 V
Input Low Voltage, VINL 0.4 V
Input Current, IINH/IINL ±1 µA
Input Capacitance, CIN 10 pF
LOGIC OUTPUTS
Output High Voltage, VOH DVDD − 0.4 V CMOS output selected
Output Low Voltage, VOL 0.3 V IOL = 500 µA
Output High Current, IOH 100 µA
POWER SUPPLIES
AVDD 2.7 3.45 V
DVDD, SDVDD 1.62 1.8 1.98 V
VP 2.7 3.45 V
AIDD 26 40 mA Supply current drawn by AVDD;
fPFD = 110 MHz
DIDD 7.5 10 mA Supply current drawn by DVDD;
fPFD = 110 MHz
IP 5.5 7 mA Supply current drawn by VP; fPFD = 110 MHz
Power-Down Mode 2 µA
Data Sheet ADF4159
Rev. E | Page 5 of 36
Parameter1 Min Typ Max Unit Test Conditions/Comments
NOISE CHARACTERISTICS
Normalized Phase Noise Floor3 PLL loop BW = 1 MHz
Integer-N Mode −224 dBc/Hz FRAC = 0; see Σ-Δ Modulator Mode section
Fractional-N Mode −217 dBc/Hz
Normalized 1/f Noise (PN1_f)4 −120 dBc/Hz
Measured at 10 kHz offset, normalized
to 1 GHz
Phase Noise Performance5 At VCO output
12,002 MHz Output6 −96 dBc/Hz At 50 kHz offset, 100 MHz PFD frequency
1 Operating temperature: −40°C to +125°C.
2 Guaranteed by design. Sample tested to ensure compliance.
3 This specification can be used to calculate phase noise for any application. Use the formula ((Normalized Phase Noise Floor) + 10 log(fPFD) + 20 logN) to calculate
in-band phase noise performance as seen at the VCO output.
4 The PLL phase noise is composed of flicker (1/f) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency (fRF)
and at an offset frequency (f) is given by PN = PN1_f + 10 log(10 kHz/f) + 20 log(fRF/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in ADIsimPLL.
5 The phase noise is measured with the EV-ADF4159EB3Z and the Rohde & Schwarz FSUP signal source analyzer.
6 fREFIN = 100 MHz; fPFD = 100 MHz; offset frequency = 50 kHz; RFOUT = 12,002 MHz; N = 120.02; loop bandwidth = 250 kHz.
TIMING SPECIFICATIONS
AVDD = VP = 2.7 V to 3.45 V, DVDD = SDVDD = 1.8 V, AGND = DGND = SDGND = CPGND = 0 V, TA = TMIN to TMAX, dBm referred to 50 Ω,
unless otherwise noted.
Table 2. Write Timing
Parameter Limit at TMIN to TMAX Unit Description
t1 20 ns min LE setup time
t2 10 ns min DATA to CLK setup time
t3 10 ns min DATA to CLK hold time
t4 25 ns min CLK high duration
t5 25 ns min CLK low duration
t6 10 ns min CLK to LE setup time
t7 20 ns min LE pulse width
Write Timing Diagram
CLK
DATA
LE
DB30 DB1
(CONTROL BIT C2)
DB2
(CONTROL BIT C3) DB0 (LS B)
(CONTRO
L
BIT C1)
t
1
t
2
t
3
t
4
t
5
t
7
t
6
10849-002
DB31 (MS B)
Figure 2. Write Timing Diagram
ADF4159 Data Sheet
Rev. E | Page 6 of 36
Table 3. Read Timing
Parameter Limit at TMIN to TMAX Unit Description
t11 t
PFD + 20 ns min TXDATA setup time
t2 20 ns min CLK setup time to data (on MUXOUT)
t3 25 ns min CLK high duration
t4 25 ns min CLK low duration
t5 10 ns min CLK to LE setup time
1 tPFD is the period of the PFD frequency; for example, if the PFD frequency is 50 MHz, tPFD = 20 ns.
Read Timing Diagram
CLK
t
4
t
3
MUXOUT DB36 DB35 DB1DB2 DB0
TX
DATA
t
1
t
2
LE
t
5
NOTES
1. LE SHOULD BE KEPT HIGH DURING RE ADBACK.
10849-003
Figure 3. Read Timing Diagram
TO MUXOUT
PIN C
L
10pF
500µA I
OL
100µA I
OH
0.9V
10849-004
Figure 4. Load Circuit for MUXOUT Timing, CL = 10 pF
Data Sheet ADF4159
Rev. E | Page 7 of 36
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, GND = AGND = DGND = SDGND = CPGND =
0 V, unless otherwise noted.
Table 4.
Parameter Rating
AVDD to GND 0.3 V to +3.9 V
DVDD to GND 0.3 V to +2.4 V
VP to GND 0.3 V to +3.9 V
VP to AVDD 0.3 V to +0.3 V
Digital I/O Voltage to GND 0.3 V to DVDD + 0.3 V
Analog I/O Voltage to GND 0.3 V to AVDD + 0.3 V
REFIN to GND 0.3 V to DVDD + 0.3 V
RFIN to GND 0.3 V to AVDD + 0.3 V
Operating Temperature Range,
Industrial
40°C to +125°C
Storage Temperature Range 65°C to +125°C
Maximum Junction Temperature 150°C
Reflow Soldering
Peak Temperature 260°C
Time at Peak Temperature 40 sec
ESD
Charged Device Model 1000 V
Human Body Model 3000 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
Thermal impedance (θJA) is specified for a device with the
exposed pad soldered to AGND.
Table 5. Thermal Resistance
Package Type θJA Unit
24-Lead LFCSP_WQ 56 °C/W
ESD CAUTION
ADF4159 Data Sheet
Rev. E | Page 8 of 36
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
CPGND
NOTES
1. THE LFCSP HAS AN EXPOSED PAD
T HAT MUST BE CONNECT E D TO A GND.
2
1
3
4
5
6
18
17
16
15
14
13
8
9
10
11
7
12
20
19
21
22
23
24
ADF4159
TOP VIEW
(Not to Scal e)
AGND
AGND
RF
IN
B
RF
IN
A
AV
DD
AV
DD
AV
DD
REF
IN
DGND
SDGND
TX
DATA
SDV
DD
MUXOUT
LE
DATA
CLK
CE
CP
R
SET
V
P
SW2
SW1
DV
DD
10849-005
Figure 5. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic Description
1 CPGND Charge Pump Ground. This pin is the ground return path for the charge pump.
2, 3 AGND Analog Ground.
4 RFINB Complementary Input to the RF Prescaler. Decouple this pin to the ground plane with a small bypass capacitor,
typically 100 pF.
5 RFINA Input to the RF Prescaler. This small signal input is normally ac-coupled from the VCO.
6, 7, 8 AVDD Positive Power Supply for the RF Section. Place decoupling capacitors to the ground plane as close as possible
to these pins.
9 REFIN Reference Input. This CMOS input has a nominal threshold of DVDD/2 and an equivalent input resistance of 100 kΩ.
It can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled.
10 DGND Digital Ground.
11 SDGND Digital Σ-Δ Modulator Ground. This pin is the ground return path for the Σ-Δ modulator.
12 TXDATA Transmit Data Pin. This pin provides the data to be transmitted in FSK or PSK mode and also controls some
ramping functionality.
13 CE Chip Enable (1.8 V Logic). A logic low on this pin powers down the device and places the charge pump output
into three-state mode.
14 CLK Serial Clock Input. This input is used to clock in the serial data to the registers. The data is latched into the input
shift register on the CLK rising edge. This input is a high impedance CMOS input.
15 DATA
Serial Data Input. The serial data is loaded MSB first; the three LSBs are the control bits. This input is a high
impedance CMOS input.
16 LE Load Enable Input. When LE is high, the data stored in the input shift register is loaded into one of the eight
latches; the latch is selected using the control bits. This input is a high impedance CMOS input.
17 MUXOUT Multiplexer Output. This pin allows various internal signals to be accessed externally.
18 SDVDD Power Supply for the Digital Σ-Δ Modulator. Place decoupling capacitors to the ground plane as close as
possible to this pin.
19 DVDD Positive Power Supply for the Digital Section. Place decoupling capacitors to the digital ground plane as close
as possible to this pin.
20, 21 SW1, SW2 Switches for Fast Lock.
22 VP Charge Pump Power Supply. The voltage on this pin must be greater than or equal to AVDD.
23 RSET Connecting a resistor between this pin and ground sets the maximum charge pump output current. The
relationship between ICP and RSET is as follows:
ICP_MAX = 24.48/RSET
where:
ICP_MAX = 4.8 mA.
RSET = 5.1 kΩ.
24 CP Charge Pump Output. When the charge pump is enabled, this output provides ±ICP to the external loop filter,
which, in turn, drives the external VCO.
25 EPAD Exposed Pad. The LFCSP has an exposed pad that must be connected to AGND.
Data Sheet ADF4159
Rev. E | Page 9 of 36
TYPICAL PERFORMANCE CHARACTERISTICS
–180
–160
–140
–120
–100
–80
–60
–40
100 1k 10k 100k 1M 10M 100M
PHASE NOISE (d Bc/Hz)
FREQUENCY OFFSET (Hz)
10849-106
Figure 6. Phase Noise at 12.002 GHz, fPFD = 100 MHz, ICP = 2.5 mA,
Loop Bandwidth = 250 kHz, Bleed Current = 11.03 µA
11.98
11.99
12.00
12.01
12.02
12.03
12.04
12.05
12.06
050 100 150 200
FREQUENCY (GHz)
TIME (µs)
10849-107
Figure 7. Sawtooth Ramp, fPFD = 100 MHz, ICP = 2.5 mA,
Loop Bandwidth = 250 kHz, CLK1 = 3, CLK2 = 26, DEV = 1024,
DEV_OFFSET = 8, Number of Steps = 64
Figure 8. Sawtooth Ramp with Delay, fPFD = 100 MHz, ICP = 2.5 mA,
Loop Bandwidth = 250 kHz, CLK1 = 3, CLK2 = 26, DEV = 1024,
DEV_OFFSET = 8, Number of Steps = 64, Delay Word = 1000
11.98
11.99
12.00
12.01
12.02
12.03
12.04
12.05
12.06
020 40 60 80 100
FREQUENCY (GHz)
TIME (µs)
10849-109
Figure 9. Sawtooth Burst, fPFD = 100 MHz, ICP = 2.5 mA,
Loop Bandwidth = 250 kHz, CLK1 = 3, CLK2 = 26, DEV = 1024,
DEV_OFFSET = 8, Number of Steps = 64
Figure 10. Dual Sawtooth Ramp, fPFD = 100 MHz, ICP = 2.5 mA,
Loop Bandwidth = 250 kHz, CLK1 = 3; First Ramp: CLK2 = 26, DEV = 1024,
DEV_OFFSET = 8, Number of Steps = 64; Second Ramp: CLK2 = 52,
DEV = 1024, DEV_OFFSET = 7, Number of Steps = 64
11.99
12.00
12.01
12.02
12.03
12.04
12.05
12.06
0100 200 300 400 500
FREQUENCY (GHz)
TIME (µs)
10849-111
Figure 11. Triangle Ramp, fPFD = 100 MHz, ICP = 2.5 mA,
Loop Bandwidth = 250 kHz, CLK1 = 3, CLK2 = 26, DEV = 1024,
DEV_OFFSET = 8, Number of Steps = 64
ADF4159 Data Sheet
Rev. E | Page 10 of 36
11.99
12.00
12.01
12.02
12.03
12.04
12.05
12.06
050 100 150 200
FREQUENCY (GHz)
TIME (µs)
10849-112
Figure 12. Fast Ramp (Triangle Ramp with Different Slopes), fPFD = 100 MHz,
ICP = 2.5 mA, Loop Bandwidth = 250 kHz, CLK1 = 3; Up Ramp: CLK2 = 26,
DEV = 1024, DEV_OFFSET = 8, Number of Steps = 64; Down Ramp: CLK2 = 70,
DEV = 16,384, DEV_OFFSET = 8, Number of Steps = 4
–200
–150
–100
–50
0
50
100
150
200
050 100 150 200
PHASE ( Degrees)
TIME (µs)
10849-113
Figure 13. Phase Shift Keying (PSK), Loop Bandwidth = 250 kHz,
Phase Value = 1024, Data Rate = 20 kHz
11.996
11.997
11.998
11.999
12.000
12.001
12.002
12.003
12.004
050 100 150 200
FREQUENCY (GHz)
TIME (µs)
10849-114
Figure 14. Frequency Shift Keying (FSK), Loop Bandwidth = 250 kHz,
DEV = 1049, DEV_OFFSET = 9, Data Rate = 20 kHz
11.994
11.996
11.998
12.000
12.002
12.004
12.006
12.008
12.010
12.012
12.014
0100 200 300 400 500
FREQUENCY (GHz)
TIME (µs)
10849-115
Figure 15. FSK Ramp, fPFD = 100 MHz, ICP = 2.5 mA, Loop Bandwidth = 250 kHz,
CLK1 = 3, CLK2 = 26, DEV = 1024, DEV_OFFSET = 8, Number of Steps = 64;
FSK: DEV = 512, DEV_OFFSET = 8
–40
–35
–30
–25
–20
–15
–10
–5
0
0 5 10 15 20
RF SENSITIVITY (dBm)
FREQUENCY (GHz)
PRES CALER 8/9
PRES CALER 4/5
10849-116
Figure 16. RFIN Sensitivity at Nominal Temperature
–6
–4
–2
0
2
4
6
00.5 1.0 1.5 2.0 2.5 3.0
I
CP
(mA)
V
CP
(V)
10849-117
Figure 17. Charge Pump Output Characteristics
Data Sheet ADF4159
Rev. E | Page 11 of 36
THEORY OF OPERATION
REFERENCE INPUT SECTION
Figure 18 shows the reference input stage. The SW1 and SW2
switches are normally closed (NC in Figure 18). The SW3 switch
is normally open (NO in Figure 18). When power-down is
initiated, SW3 is closed, and SW1 and SW2 are opened. In this
way, no loading of the REFIN pin occurs during power-down.
BUFFER TO R COUNTER
REF
IN
100k
NC
SW2
SW3
NO
NC
SW1
POWER-DOWN
CONTROL
10849-013
Figure 18. Reference Input Stage
RF INPUT STAGE
Figure 19 shows the RF input stage. The input stage is followed
by a two-stage limiting amplifier to generate the current-mode
logic (CML) clock levels required for the prescaler.
BIAS
GENERATOR 1.6V
AGND
AV
DD
2k2k
RF
IN
B
RF
IN
A
10849-014
Figure 19. RF Input Stage
RF INT DIVIDER
The RF INT CMOS divider allows a division ratio in the PLL
feedback counter. Division ratios from 23 to 4095 are allowed.
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
FRAC
VALUE
MOD
VALUE
INT
VALUE
RF INT DIVIDER
N = INT + FRAC/MOD
FROM RF
INPUT STAGE TO PFD
N COUNTER
10849-015
Figure 20. RF INT Divider
25-BIT FIXED MODULUS
The ADF4159 has a 25-bit fixed modulus. This modulus allows
output frequencies to be spaced with a resolution of
fRES = fPFD/225 (1)
where fPFD is the frequency of the phase frequency detector
(PFD). For example, with a PFD frequency of 100 MHz,
frequency steps of 2.98 Hz are possible. Due to the architecture
of the Σ-Δ modulator, there is a fixed +(fPFD/226) offset on the
VCO output. To remove this offset, see the Σ-Δ Modulator
Mode section.
INT, FRAC, AND R COUNTER RELATIONSHIP
The INT and FRAC values, in conjunction with the R counter,
make it possible to generate output frequencies that are spaced
by fractions of the PFD frequency.
The RF VCO frequency (RFOUT) equation is
RFOUT = (INT + (FRAC/225)) × fPFD (2)
where:
RFOUT is the output frequency of the external voltage
controlled oscillator (VCO).
INT is the preset divide ratio of the binary 12-bit counter
(23 to 4095).
FRAC is the numerator of the fractional division (0 to (225 − 1)).
The PFD frequency (fPFD) equation is
fPFD = REFIN × [(1 + D)/(R × (1 + T))] (3)
where:
REFIN is the reference input frequency.
D is the REFIN doubler bit (0 or 1).
R is the preset divide ratio of the binary 5-bit programmable
reference (R) counter (1 to 32).
T is the REFIN divide-by-2 bit (0 or 1).
R COUNTER
The 5-bit R counter allows the input reference frequency (REFIN)
to be divided down to supply the reference clock to the PFD.
Division ratios from 1 to 32 are allowed.
ADF4159 Data Sheet
Rev. E | Page 12 of 36
PHASE FREQUENCY DETECTOR (PFD) AND
CHARGE PUMP
The PFD takes inputs from the R counter and N counter and
produces an output proportional to the phase and frequency
difference between them. Figure 21 shows a simplified sche-
matic of the PFD.
U3
CLR2
Q2
D2 U2
DOWN
UP
HIGH
HIGH
CP
–IN
+IN
CHARGE
PUMP
DELAY
CLR1
Q1D1
U1
10849-016
Figure 21. PFD Simplified Schematic
The PFD includes a fixed delay element that sets the width of the
antibacklash pulse, which is typically 1 ns. This pulse ensures that
there is no dead zone in the PFD transfer function and gives a
consistent reference spur level.
MUXOUT AND LOCK DETECT
The multiplexer output on the ADF4159 allows the user
to access various internal points on the chip. The state of
MUXOUT is controlled by the M4, M3, M2, and M1 bits in
Register R0 (see Figure 25). Figure 22 shows the MUXOUT
section in block diagram form.
MUXOUT
THREE-STATE OUTPUT
N DIV IDER OUTPUT
DGND
DGND
R DIV IDER OUTPUT
DIGITAL LO CK DE TECT
READBACK TO MUX OUT
CLK DIVIDE R OUTP UT
SERIAL DATA OUT P UT
R DIV IDER/2
N DIV IDER/2
CONTROL
MUX
10849-017
DVDD
DVDD
Figure 22. MUXOUT Schematic
INPUT SHIFT REGISTER
The ADF4159 digital section includes a 5-bit R counter, a 12-bit
INT counter, and a 25-bit FRAC counter. Data is clocked into the
32-bit input shift register on each rising edge of CLK. The data
is clocked in MSB first. Data is transferred from the input shift
register to one of eight latches on the rising edge of LE.
The destination latch is determined by the state of the three
control bits (C3, C2, and C1) in the input shift register. As shown
in Figure 2, the control bits are the three LSBs (DB2, DB1, and
DB0, respectively). Table 7 shows the truth table for these bits.
Figure 23 and Figure 24 provide a summary of how the latches
are programmed.
Table 7. Truth Table for the C3, C2, and C1 Control Bits
Control Bits
Register
C3 C2 C1
0 0 0 R0
0 0 1 R1
0 1 0 R2
0 1 1 R3
1 0 0 R4
1 0 1 R5
1 1 0 R6
1 1 1 R7
PROGRAM MODES
Table 7 and Figure 25 through Figure 32 show how the program
modes are set up in the ADF4159.
The following settings in the ADF4159 are double buffered:
LSB fractional value, phase value, charge pump current setting,
reference divide-by-2, reference doubler, R counter value, and
CLK1 divider value. Before the part uses a new value for any
double-buffered setting, the following two events must occur:
1. The new value is latched into the device by writing to the
appropriate register.
2. A new write is performed to Register 0 (R0).
For example, updating the fractional value involves a write to
the 13 LSB bits in R1 and the 12 MSB bits in R0. R1 must be
written to first, followed by the write to R0. The frequency change
begins after the write to R0. Double-buffering ensures that the
bits written to R1 do not take effect until after the write to R0.
Data Sheet ADF4159
Rev. E | Page 13 of 36
REGISTER MAPS
DB31
CONTROL
BITS
12-BI T MSB F RACTIONAL V ALUE
(FRAC)
13-BI T LSB FRACTIONAL VALUE
(FRAC)
12-BI T INT E GER VALUE (INT)
MUXOUT
CONTROL
DB30 D D
B29 B28DB27 DB26DB25 DB24 DB23 DB22 DB21 DB20 DB19DB18 DB17DB16DB15DB14DB13DB12DB11DB10DB9 DB8DB7 DB6 DB5 DB4 DB3DB2DB1 DB0
R1 M4M3 M2 M1 N12 N11 N10 N9 N8 N7 N6N5 N4 N3N2N1F25F24F23F22F21 F20 F19 F18F17 F16 F15 F14 C3(0) C2(0) C1(0)
RAMP ON
FRAC/INT REGISTER (R0)
DB31
12-BI T PHASE V ALUE
RESERVED
DB30DB29DB28DB27DB26DB25 DB24 DB23DB22 DB21DB20 DB19 DB18 DB17 DB16 DB15 DB14DB13 DB12DB11 DB10 DB9 DB8 DB7 DB6DB5DB4DB3DB2DB1 DB0
00 0 P1 F13 F12 F11 F10 F9 F8 F7 F6F5 F4 F3 F2F1 P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 C3(0) C2(0) C1(1)
LSB FRAC REGISTER (R1)
DB31
RESERVED NEG BLEED
CURRENT
POWER-DOWN
PD
POLARITY
LDP
PSK
COUNTER
RESET
CP
THREE-STATE
DB30 DB29 DB28DB27DB26DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15DB14DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4DB3 DB2DB1 DB0
00 0 00 0 0 NB3 NB2 NB1 00001 L1NS1 U12 0 0 0 0RM2 RM1 U11 U10U9 U8U7 C3(0) C2(1) C1(1)
FUNCT ION REGISTER (R3)
DB31
5-BI T R COUNT E R
RESERVED
RESERVED
PHASE
ADJUST
PRESCALER
CSR
RDIV 2 DBB
DB30 DB29 DB28 DB27 DB26 DB25 DB24DB23DB22DB21DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13DB12DB11DB10 DB9DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0CR1 CPI4 CPI3CPI2 CPI10P1 U2 U1 R5 R4 R3 R2 R1 D12 D11D10D9 D8D7 D6 D5 D4 D3 D2 D1 C3(0) C2(1)C1(0)
R DIVIDER REGISTER (R2)
DBB DBB DBB
DBB DBB
SD
RESET
RAMP M ODE
RESERVED
RESERVED
RESERVED
NEG BLEED
ENABLE
FSK
N SEL
LOL
NOTES
1. DBB = DOUBLE - BUFFE RE D BITS .
CONTROL
BITS
CONTROL
BITS
CONTROL
BITS
12-BI T CLK
1
DIV IDER VAL UE
CP
CURRENT
SETTING
REFERENCE
DOUBLER DBB
10849-018
Figure 23. Register Summary 1
ADF4159 Data Sheet
Rev. E | Page 14 of 36
RESERVED
DB31
20-BI T STE P WORD
DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 0 0 0 0 SSE1 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 C3(1) C2(1) C1(0)
STEP R EGISTER (R6)
DB31
12-BI T DELAY S TART WORD
RAMP DE LAY FL
DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 0 0 0 0 0 0TD1 ST1 TR1 FR1 RD1 DC1 DSE1 DS12 DS11 DS10 DS9 DS8 DS7 DS6 DS5 DS4 DS3 DS2 DS1 C3(1) C2(1) C1(1)
DEL AY REGISTER (R7)
RESERVED
DEL S TART EN
DEL CLK SEL
RAMP DE LAY
FAS T RAMP
TX
DATA
TRIGGER
TX
DATA
TRIGGER DELAY
SING FULL TRI
TRI DELAY
Σ-Δ
MO DULATO R M ODE RESERVED
RESERVED
DB31
12-BI T CLK
2
DIV IDER VAL UE
DB30DB29 DB28 DB27 DB26 DB25 DB24 DB23DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5DB4 DB3 DB2 DB1 DB0
LS1 S5 S4 S3 S2 S1 R5 R4 R3 R2 R1 C2 C1 D12D11 D10 D9D8 D7 D6 D5 D4D3 D2 D1 C3(1) C2(0) C1(0)
CLOCK REGISTER (R4)
CLK
DIV
MODE
CS100 0
DB31
16-BI T DEVI ATION WORD
DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 0
TR1 I2 I1 DS1 DO4 DO3 DO2 DO1 D16 D15 D14 D13 D12 D11D10 D9D8 D7 D6 D5 C3(1) C2(0) C1(1)
DEVIATION REGIST ER (R5)
D4D3 D2 D1
4-BIT DEVIATION
OFFSET WORD
DEV SEL
STEP SEL
INTERRUPT
TX RAM P CLK
TX
DATA
INVERT
PARABOLIC
RAMP
DUAL RAM P
FS K RAM P
LE SEL
CLK DIV SEL
CONTROL
BITS
CONTROL
BITS
CONTROL
BITS
CONTROL
BITS
CONTROL
BITS
NOTES
1. DBB = DOUBLE - BUFFE RE D BITS .
10849-019
RAMP
STATUS
Figure 24. Register Summary 2
Data Sheet ADF4159
Rev. E | Page 15 of 36
FRAC/INT REGISTER (R0) MAP
When Bits DB[2:0] are set to 000, the on-chip FRAC/INT
register (Register R0) is programmed (see Figure 25).
Ramp On
When Bit DB31 is set to 1, the ramp function is enabled. When
Bit DB31 is set to 0, the ramp function is disabled.
MUXOUT Control
The on-chip multiplexer of the ADF4159 is controlled by
Bits DB[30:27]. See Figure 25 for the truth table.
12-Bit Integer Value (INT)
Bits DB[26:15] set the INT value, which forms part of the overall
feedback division factor. For more information, see the INT,
FRAC, and R Counter Relationship section.
12-Bit MSB Fractional Value (FRAC)
Bits DB[14:3], along with Bits DB[27:15] in the LSB FRAC register
(Register R1), set the FRAC value that is loaded into the fractional
interpolator. The FRAC value forms part of the overall feedback
division factor. These 12 bits are the most significant bits (MSBs)
of the 25-bit FRAC value; Bits DB[27:15] in the LSB FRAC register
(Register R1) are the least significant bits (LSBs). For more infor-
mation, see the RF Synthesizer Worked Example section.
DB31
CONTROL
BITS
12-BI T MSB F RACTIONAL V ALUE
(FRAC)
12-BI T INT E GER VALUE (INT)
MUXOUT
CONTROL
DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
R1 M4 M3 M2 M1 N12 N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 C3(0) C2(0) C1(0)
RAMP ON
M4 M3 M2 M1 OUTPUT
0 0 0 0 THREE-STATE OUTPUT
0 0 0 1 DVDD
0 0 1 0 DGND
0 0 1 1 R DIVIDER OUTPUT
0 1 0 0 N DIVIDER OUTPUT
0 1 0 1 RESERVED
0 1 1 0 DIGITAL LOCK DETECT
0 1 1 1 SERIAL DATA OUTPUT
1 0 0 0 RESERVED
1 0 0 1 RESERVED
1 0 1 0 CLK DIVIDER OUTPUT
1 0 1 1 RESERVED
1 1 0 0 RESERVED
1 1 0 1 R DIVIDER/2
1 1 1 0 N DIVIDER/2
1 1 1 1 READBACK TO MUXOUT
R1 RAMP ON
0RAMP DISABLE D
RAMP E NABLED
1
F25 F24 ... F15 F14 MSB FRACTIONAL V ALUE
(FRAC)*
0
1
2
3
.
.
.
4092
4093
4094
4095
0
0
0
0
.
.
.
1
1
1
1
0
0
0
0
.
.
.
1
1
1
1
...
...
...
...
...
...
...
...
...
...
...
0
0
1
1
.
.
.
0
0
1
1
0
1
0
1
.
.
.
0
1
0
1
N12 N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1 INTEGER VALUE (INT)
0 0 0 0 0 0 0 1 0 1 1 1 23
0 0 0 0 0 0 0 1 1 0 0 0 24
0 0 0 0 0 0 0 1 1 0 0 1 25
0 0 0 0 0 0 0 1 1 0 1 0 26
. . . . . . . . . . . . .
. . . . . . . . . . . . .
. . . . . . . . . . . . .
1 1 1 1 1 1 1 1 1 1 0 1 4093
1 1 1 1 1 1 1 1 1 1 1 0 4094
1 1 1 1 1 1 1 1 1 1 1 1 4095
*THE FRAC VALUE IS MADE UP OF THE 12-BI T MSB S TORE D IN
REG ISTE R R0 AND THE 13-BIT LSB ST ORED I N RE GIS TER R1.
FRAC V ALUE = 13-BIT LSB + 12-BIT M S B × 213.
10849-020
Figure 25. FRAC/INT Register (R0) Map
ADF4159 Data Sheet
Rev. E | Page 16 of 36
LSB FRAC REGISTER (R1) MAP
When Bits DB[2:0] are set to 001, the on-chip LSB FRAC
register (Register R1) is programmed (see Figure 26).
Reserved Bits
All reserved bits must be set to 0 for normal operation.
Phase Adjustment
Bit DB28 enables and disables phase adjustment. The phase
shift is generated by the value programmed in Bits DB[14:3].
13-Bit LSB Fractional Value (FRAC)
Bits DB[27:15], along with Bits DB[14:3] in the FRAC/INT
register (Register R0), set the FRAC value that is loaded into
the fractional interpolator. The FRAC value forms part of the
overall feedback division factor.
These 13 bits are the least significant bits (LSBs) of the 25-bit
FRAC value; Bits DB[14:3] in the FRAC/INT register are the
most significant bits (MSBs). For more information, see the
RF Synthesizer Worked Example section.
12-Bit Phase Value
Bits DB[14:3] control the phase word. The phase word is used
to increase the RF output phase relative to the current phase.
The phase change occurs after a write to Register R0.
Phase Shift = (Phase Value × 360°)/212
For example, Phase Value = 512 increases the phase by 45°.
To us e phase adjustment, Bit DB28 must be set to 1. If phase
adjustment is not used, it is recommended that the phase value
be set to 0.
DB31
CONTROL
BITS
12-BI T PHASE V ALUE
13-BI T LSB FRACTIONAL VALUE
(FRAC)
RESERVED
DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
000P1 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 C3(0) C2(0) C1(1)
P12 P11 ... P2 P1 PHASE V ALUE
0 1 ... 1 1 2047
. . ... . . .
0 0 ... 1 1 3
0 0 ... 1 0 2
0 0 ... 0 1 1
0 0 ... 0 0 0 (RECOMMENDE D)
1 1 ... 1 1 –1
1 1 ... 1 0 –2
1 1 ... 0 1 –3
. . ... . . .
1 0 ... 0 0 –2048
*THE FRAC VALUE IS MADE UP OF THE 12-BI T MSB S TORE D IN
REG ISTE R R0 AND THE 13-BIT LSB ST ORED I N REGIS TER R1.
FRAC V ALUE = 13-BIT LSB + 12-BIT M S B × 2
13
.
DBB DBB
NOTES
1. DBB = DOUBLE - BUFFE RE D BITS .
10849-021
PHASE ADJ
P1 PHASE ADJ
0DISABLED
1ENABLED
F13 F12 ... F2 F1 LSB F RACTIO NAL VAL UE
(FRAC)*
0
1
2
3
.
.
.
8188
8189
8190
8191
0
0
0
0
.
.
.
1
1
1
1
0
0
0
0
.
.
.
1
1
1
1
...
...
...
...
...
...
...
...
...
...
...
0
0
1
1
.
.
.
0
0
1
1
0
1
0
1
.
.
.
0
1
0
1
Figure 26. LSB FRAC Register (R1) Map
Data Sheet ADF4159
Rev. E | Page 17 of 36
R DIVIDER REGISTER (R2) MAP
When Bits DB[2:0] are set to 010, the on-chip R divider register
(Register R2) is programmed (see Figure 27).
Reserved Bits
All reserved bits must be set to 0 for normal operation.
CSR Enable
When Bit DB28 is set to 1, cycle slip reduction (CSR) is enabled.
Cycle slip reduction is a method for improving lock times. Note
that the signal at the PFD must have a 50% duty cycle for cycle
slip reduction to work. In addition, the charge pump current
setting must be set to its minimum value. For more information,
see the Cycle Slip Reduction for Faster Lock Times section.
The cycle slip reduction feature can be used only when the phase
detector polarity setting is positive (Bit DB6 = 1 in Register R3).
CSR cannot be used if the phase detector polarity setting is nega-
tive (Bit DB6 = 0 in Register R3).
Charge Pump Current Setting
Bits DB[27:24] set the charge pump current (see Figure 27).
Set these bits to the charge pump current that the loop filter
is designed with. Best practice is to design the loop filter for a
charge pump current of 2.5 mA or 2.81 mA and then use the
programmable charge pump current to tweak the frequency
response. See the Reference Doubler section for information on
setting the charge pump current when the doubler is enabled.
Prescaler (P/P + 1)
The dual-modulus prescaler (P/P + 1), along with the INT,
FRAC, and fixed modulus values, determines the overall
division ratio from RFIN to the PFD input. Bit DB22 sets the
prescaler value.
Operating at CML levels, the prescaler takes the clock from the
RF input stage and divides it down for the counters. The prescaler
is based on a synchronous 4/5 core. When the prescaler is set to
4/5, the maximum RF frequency allowed is 8 GHz. Therefore,
when operating the ADF4159 at frequencies greater than 8 GHz,
the prescaler must be set to 8/9. The prescaler limits the INT
value as follows:
Prescaler = 4/5: NMIN = 23
Prescaler = 8/9: NMIN = 75
RDIV2
When Bit DB21 is set to 1, a divide-by-2 toggle flip-flop is
inserted between the R counter and the PFD. This feature
can be used to provide a 50% duty cycle signal at the PFD.
Reference Doubler
When Bit DB20 is set to 0, the reference doubler is disabled,
and the REFIN signal is fed directly to the 5-bit R counter. When
Bit DB20 is set to 1, the reference doubler is enabled, and the REFIN
frequency is multiplied by a factor of 2 before the signal is fed into
the 5-bit R counter. When the doubler is disabled, the REFIN
falling edge is the active edge at the PFD input to the fractional
synthesizer. When the doubler is enabled, both the rising and
falling edges of REFIN become active edges at the PFD input.
When the reference doubler is enabled, for optimum phase
noise performance, it is recommended to only use charge pump
current settings 0b0000 to 0b0111, that is, 0.31 mA to 2.5 mA.
In this case, best practice is to design the loop filter to for a
charge pump current of 1.25 mA or 1.57 mA and then use the
programmable charge pump current to tweak the frequency
response.
5-Bit R Counter
The 5-bit R counter (Bits DB[19:15]) allows the input reference
frequency (REFIN) to be divided down to supply the reference
clock to the PFD. Division ratios from 1 to 32 are allowed.
12-Bit CLK1 Divider Value
Bits DB[14:3] program the CLK1 divider value, which determines
the duration of the time step in ramp mode.
ADF4159 Data Sheet
Rev. E | Page 18 of 36
DB31
12-BI T CLK
1
DIV IDER VAL UE
5-BI T R COUNT E R
RESERVED
RESERVED
CSR
PRESCALER
CP
CURRENT
SETTING CONTROL
BITS
DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0CR1 CPI4 CPI3 CPI2 CPI1 0P1 U2 U1 R5 R4 R3 R2 R1 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 C3(0) C2(1) C1(0)
U1REFERENCE
DOUBLER
0DISABLED
1ENABLED
CR1 CYCLE SLIP
REDUCTION
0DISABLED
1ENABLED
R5 R4 R3 R2 R1 R COUNTER DIVIDE RATIO
000 0 1 1
000 1 0 2
0 0 0 1 1 3
0 0 1 0 0 4
. . . . .
. . ...
.. . . .
1 1 1 0 1 29
1 1 1 1 0 30
1 1 1 1 1 31
0 0 0 0 0 32
U2R DIVIDER
0DISABLED
1ENABLED
P1 PRESCALER
04/5
18/9
ICP (mA)
CPI4 CPI3 CPI2 CPI1 5.1k
0 0 0 0 0.31
00 0 10.63
0 0 100.94
00 1 11.25
010 0 1.57
01 0 11.88
0 1 1 0 2.19
01 1 12.5
1 0 0 02.81
1 0 0 13.13
10103.44
10113.75
11004.06
11014.38
11104.69
1 1 1 1 5.0
DBB DBB DBB
RDIV 2 DBB
REFERENCE
DOUBL ER DBB
D12 D11 ... D2 D1
0
0
0
0
.
.
.
1
1
1
1
0
0
0
0
.
.
.
1
1
1
1
...
...
...
...
...
...
...
...
...
...
...
0
0
1
1
.
.
.
0
0
1
1
0
1
0
1
.
.
.
0
1
0
1
0
1
2
3
.
.
.
4092
4093
4094
4095
NOTES
1. DBB = DOUBLE - BUFFE RE D BITS .
CLK1 DIVIDER VALUE
10849-022
Figure 27. R Divider Register (R2) Map
Data Sheet ADF4159
Rev. E | Page 19 of 36
FUNCTION REGISTER (R3) MAP
When Bits DB[2:0] are set to 011, the on-chip function register
(Register R3) is programmed (see Figure 28).
Reserved Bits
All reserved bits except Bit DB17 must be set to 0 for normal
operation. Bit DB17 must be set to 1 for normal operation.
Negative Bleed Current
Bits DB[24:22] set the negative bleed current value (IBLEED).
Calculate IBLEED using the following formula, and then select the
value of Bits DB[24:22] that is closest to the calculated value.
IBLEED = (4 × ICP)/N
where:
ICP is the charge pump current.
N is the N counter value.
Negative Bleed Current Enable
DB21 enables a negative bleed current in the charge pump. When
the charge pump is operating in a nonlinear region, phase noise
and spurious performance can degrade. Negative bleed current
operates by pushing the charge pump operation region away
from this nonlinear region. The programmability feature controls
how far the region of operation is moved. If the current is too
little, the charge pump will remain in the nonlinear region; if
the current is too high, the charge pump will become unstable
or degrade the maximum PFD frequency. It is necessary to exper-
iment with various charge pump currents to find the optimum.
The formula for calculating the optimum negative bleed current
is shown in the Negative Bleed Current section; however, exper-
imentation may show a different current gives the optimum result.
Loss of Lock (LOL)
Bit DB16 enables or disables the loss of lock indication. When
this bit is set to 0, the part indicates loss of lock even when the
reference is removed. This feature provides an advantage over
the standard implementation of lock detect. For more robust
operation, set this bit to 1. The loss of lock does not operate as
expected when negative bleed current is enabled.
N SEL
Bit DB15 can be used to circumvent the issue of pipeline delay
between updates of the integer and fractional values in the
N counter. Typically, the INT value is loaded first, followed by
the FRAC value. This can cause the N counter value to be incor-
rect for a brief period of time equal to the pipeline delay (about
four PFD cycles). This delay has no effect if the INT value was not
updated. However, if the INT value has changed, this incorrect
N counter value can cause the PLL to overshoot in frequency
while it tries to lock to the temporarily incorrect N counter value.
After<