MC100EPT22DR2 - ON Semiconductor

 Semiconductor Components Industries, LLC, 2001

June, 2001 – Rev. 0 1Publication Order Number:

TND301/D

TND301

Clock Management Design

Using Low Skew and Low

Jitter Devices

Prepared by: Paul Hunt

ON Semiconductor

Why Do We Need Clock Management?

Can you imagine the chaos in our world if our clocks or

watches were not synchronized to Greenwich Mean Time?

How would trains, buses, and airplanes run on schedule?

The miniseries Longitude was the story of a man who made

a major technological breakthrough by inventing an

accurate clock that could be carried on sailing ships so

navigators could accurately calculate longitude and know

where the ship was located at any moment in time. Before

this, ships ran aground and many people lost their lives due

to navigational errors. Even though there are fixed time zone

differences throughout the world, all clocks must agree

within fractions of seconds for civilization to work orderly

and without confusion. Clock accuracy is one of the most

important scientific technologies in our world today.

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TECHNICAL NOTE

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Typical Clock Management System

Clock Management of an electronic system (see Figure 1 )

depends on very accurate time keeping. A well–designed

Clock Management scheme begins with a precise Clock

Generator which is the standard Master Clock or Mean Time.

The M aster C lock i s p assed o n t o t he C lock D istribution c ircuit

which “fans out” multiple clocks throughout the system and

activates individual events in the CPUs, ASICs, FPGAs, and

Memory. All events a re s ynchronized t o t he M aster C lock and

requires accurate d evices t o generate a nd d istribute the c locks.

Accurate devices are described as those with low jitter and

low skew. Jitter is uncertainty in the location of the rising or

falling edge of the signal (see Figure 2). Jitter can be random

or deterministic. Jitter is called phase noise in the Master

Clock and increases as it passes through each device. Noise

from power supplies and crosstalk between signals also add

to the total jitter. Jitter can be measured as peak–to–peak or

RMS in picoseconds.

Skew is a time offset of the clocks as they travel

throughout the system (see Figure 3). Skew is defined as

duty–cycle skew, within–device skew, or device–to–device

skew. Skew is reduced by adjusting the delay of signals

within the system. It is similar to propagation delay and is

measured in picoseconds.

Large values of jitter and skew on clocks reduce the

maximum operating frequency of a system.

Clock Generator CPU’s

Master Clock

PLL

(Phase Locked Loop)

with Crystal

Clock

Distribution Back

Plane Additional

Clock

Distribution

Clock Delay,

Division and

Translation

ASIC’s

FPGA’s

Memory

Figure 1. Typical Clock Management System

Figure 2. Jitter

Figure 3. Skew

Skew

OUT1

OUT2

Skew is a fixed difference between outputs caused by many factors including physi-

cal layout, device process variations, and unbalanced loading conditions.

Jitter is the uncertainty caused by many factors including power supply noise, signal

crosstalk, and device physics.

Jitter

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3

Clock Management Highways

Clock Management is included in electronic systems that

contain backplanes (see Figure 4). Backplanes are the

physical highways for clocks. They are multilayer printed

circuit boards that are on the back of a card cage and have

connectors that each circuit card plugs into. The design of

the backplane is very critical to the performance of the Clock

Management system. Many factors must be considered for

a good backplane design.

The Clock Generator is typically on a circuit card with

Clock Distribution circuits. The clocks are distributed

throughout the cards on the backplane and each card may

then redistribute, delay, divide, and translate these clock

signals.

Backplanes are noisy due to the high amount of electronic

signal traffic. Standard connectors are also a problem on a

backplane since they do not offer a good transition due to

impedance mismatch. Most connectors do not offer

differential signal capability and do not provide adequate

ground pins for elimination of crosstalk. Backplanes tend to

slow down signals because they have multiple layers which

add capacitance and delay.

Figure 4. Example of Backplanes

Clock Management systems distribute clocks over backplanes in super–and mini–computers,

communication equipment like PABX, SONET/SDH systems, ATM, and advance test equipment.

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4

The Building Blocks

Clock Generator

The Clock Generator uses a Phase Locked Loop (PLL)

circuit to generate the Master Clock (see Figure 5). A Crystal

Oscillator Circuit generates a low phase noise signal that is

received by a phase d etector. The phase d etector compares t he

phase of the crystal oscillator with the output of the Divide by

N counter. If both phases are the same, the circuit is in LOCK

and a small output pulse from the phase detector is averaged

by the Loop Filter. The Loop Filter outputs a voltage to the

VCO which defines the Master Clock frequency. The Divide

by N counter can be programmed to increase or decrease the

Master Clock frequency. The Master Clock is equal to the

Crystal Oscillator frequency times the value N. This is why a

PLL is sometimes called a frequency multiplier. The PLL is a

feedback circuit; if the Master Clock begins to drift away, the

shift in phase will be discovered by the Phase Detector The

Phase Detector will then generate a wider output pulse which

will be averaged by the Loop Filter and this new value will

push the VCO back in the right direction.

Crystal

Oscillator

Circuit Loop Filter

Phase

Detector

VCO

Voltage Controlled

Oscillator

Divide by N

Master

Clock

Control Input

MC100EP40

MC100EP140

MC100EL1648

NBC12429

NBC12430

MC100EP32

MC100EP33

MC100LVEP34

MC100EP139

MC100EP016

Figure 5. Clock Generation Using Phase Locked Loop Circuit

Clock Distribution

Clock Distribution circuits receive a single differential

input and “fan out” multiple outputs with minimum skew

(see Figure 6).

Figure 6. Clock Distribution Using 1:N

Clock Driver Circuit

1

2

1

N

1:2 Dual 1:3 1:4 1:5 Dual 1:5 1:6 1:10 1:15

MC100EL11 MC100EL13 MC100EL15 MC100EL14 MC100LVEP210 MC100E211 MC100LVEP111 MC100LVE222

MC100LVEL11 MC100LVEL13 MC100LVEL14

MC100EP11 MC100EP14

MC100LVEP11 MC100LVEP14

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5

Delay Lines

Delay Lines are used to synchronize clocks that travel

different distances within the Clock Management system

(see Figure 7). It is dif ficult in the card cage with a backplane

to distribute all clocks to all circuits using the same length

line. The position of the cards in the card cage makes this

impossible. One way to synchronize the clocks in a large

system i s t o use delay line circuits. The signal comes into the

device and is delayed by an amount determined by a

programmable input. This programmable input can be a

parallel word and/or a single analog voltage input.

Figure 7. Example of Clock Delay

1

N

Delay Line

Device

Short Lines

Long Lines

Programmable Input

MC100EP195

MC100EP196

Clock Dividers

Clock Dividers are required to reduce the frequency of

certain clocks within a system.

Figure 8. Example of Clock Division

Divide by 2

MC100EP195

MC100LVEP34

MC100EP139

MC100EP016

Divide by 2

MC100EP33

MC100LVEP34

MC100EP139

MC100EP016

Divide by 2

MC100LVEP34

MC100EP016

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6

Translators

Translators are required in Clock Management systems to

convert voltage levels and amplitudes to other voltage levels

and amplitudes to interface with other logic components.

These could be microprocessors, FPGAs, ASICs, or

Memory all of which could have ECL, CMOS, TTL, LVDS,

GTL, or HSTL inputs and outputs.

Figure 9. Voltage Level Translation

Voltage Level Translation

(High to Low or Low to High) Voltage Level Translation with Amplitude Change

(Small/High to Large/Low or Large/Low to Small High)

Figure 10. Voltage Level and Amplitude Translation

V1

V2

V3

V1

V2

V3

V1

V2

V3

V1

V2

V3

OUT OUTIN IN

TRANSLATOR TABLE

PECL/LVPECL TTL/CMOS LVDS NECL

PECL/LVPECL MC100EP16

MC100LVEP16

MC100LVEL92

MC100EPT21

MC100EPT23

MC100EPT26

MC100EP210S MC100LVEL91

TTL/CMOS MC100EPT20

MC100EPT22 MC100EPT24

LVDS MC100LVEP16

MC100LVEP17

NECL MC100EP90 MC100EPT25

NOTE: For more information, see application note AN1672.

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7

The Challenges: We Have a Better Solution

Clock Management systems require the clocks to have low

jitter and low skew. ECL logic provides less jitter and skew

with a higher operating frequency than other technologies.

ECL logic technology offers a number of advantages over

CMOS, LVDS, and TTL in reducing clock errors caused by

jitter and skew. ECL devices have 1 ps jitter and 25 ps skew

compared t o 1 5 p s j itter a nd 1 00 p s s kew for LVDS and C M OS

devices. (See F igure 11 a n d Figure 12). The f requency o f E CL

logic is 3 Ghz maximum frequency compared to 300 Mhz

maximum frequency for LVDS and CMOS logic (see Figure

13). The rise and fall times of clock signals is very critical for

edge placement. ECL logic provides rise and fall times of 100

ps compared to rise and fall times of 800 ps for LVDS and

CMOS logic (see Figure 14).

ECL logic technologies offer a number of advantages for

reducing the n oise d u e t o c rosstalk an d signal m ismatch o n t he

backplane over CMOS, LVDS, and TTL technologies. ECL

signals are differential signals and can be individually

terminated to match the transmission impedance of the

backplane E CL s ignals h ave a dequate c urrent ( 50 m A) t o drive

a b ackplane a nd c an d eliver s ignals w ith m aximum f requencies

of 3 Ghz. E CL p eak–to–peak o utput s ignals o f 8 00 m V p rovide

a g ood s ignal–to–noise ratio a nd excellent EMI c haracteristics.

100

10

1

1000

100

2002

5

ps

0

Figure 11. Standard I/O rms Jitter Figure 12. Standard I/O Skew

ps

45

40

35

30

25

20

15

10

0

Figure 13. Standard I/O Fmax Figure 14. Standard Rise/Fall Time

Comparisons

ps

Gbit/s

25

1000

10

1

10000

ECL

10

15

20

200320012000

LVDS

CMOS

2002 200320012000

ECL

LVDS

CMOS

2002 200320012000

5

2002 200320012000

ECL

LVDS

CMOS

ECL/PECL

LVDS CMOS

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