MAY 2002
Flex
Q
TMIII Plus
3F3P1020A
FQV202113 · FQV202103 · FQV20293 · FQV20283 · FQV20273 · FQV20263
·
FQV20253· FQV20243
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Page 1 of 1
3.3 Volt Synchronous x10/x20 First-In/First-Out Queue
Memory Organization Device Memory Organization Device
262,144 x 20 / 524,286 x 10 FQV202113 16,384 x 20 / 32,768 x 10 FQV20273
131,072 x 20 / 262,144 x 10 FQV202103 8,192 x 20 / 16,384 x 10 FQV20263
65,536 x 20 / 131,072 x 10 FQV20293 4,096 x 20 / 8,192 x 10 FQV20253
32,768 x 20 / 65,536 x 10 FQV20283 2,048 x 20 / 4,096 x 10 FQV20243
Key Features
• Industry leading First-In/First-Out Queues (up to 166MHz)
• Write cycle time of 6.0ns independent of Read cycle time (Data Setup time = 2.0ns)
• Read cycle time of 6.0ns independent of Write cycle time (Data Access time = 4.0ns)
• User selectable input and output port bus-sizing
• Big Endian/Little Endian user selectable byte representation
• 3.3V power supply
• 5V input tolerant on all control and data input pins
• 5V output tolerant on all flags and data output pins
• Master Reset clears all previously programmed configurations including Write and Read pointers
• Partial Reset clears Write and Read pointers but maintains all previously programmed configurations
• First Word Fall Through (FWFT) and Standard Timing modes
• Presets for eight different Almost Full and Almost Empty offset values
• Parallel/Serial programming of PRAF and PRAE offset values
• Programmable 8-bit or 10-bit parallel programming modes for offset values
• Full, Empty, Almost Full, Almost Empty, and Half Full indicators
• PRAF and PRAE operates in either synchronous or asynchronous modes
• Asynchronous output enable tri-state data output drivers
• Data retransmission with programmable zero or normal latency modes
• Available package: 144 - pin Plastic Thin Quad Flat Pack (TQFP)
• (0°C to 70°C) Commercial operating temperature available for cycle time of 6.0ns and above
• (-40°C to 85°C) Industrial operating temperature available for cycle time of 7.5ns and above
Product Description
HBA’s FlexQ™ III Plus offers industry leading FIFO queuing bandwidth (up to 3.0 Gbps), with a wide range of memory
configurations (from 2,048 x 20 to 262,144 x 20 or 4,096 x 10 to 524,286 x 10). System designer has full flexibility of
implementing deeper and wider queues using FWFT mode and width expansion features. Full, Empty, and Half-Full indicators
allow easy handshaking between transmitters and receivers. User programmable Almost Full and Almost Empty (Parallel/Serial)
indicators allow implementation of virtual queue depths.
5V tolerant on all input and output pins allow easy interfacing with devices operating at higher voltage levels. Asynchronous
Output Enable pin configures the tri-state data output drivers. Independent Write and Read controls provide rate-matching
capability.
Master Reset clears all previously programmed configurations by providing a low pulse on MRST pin. In addition, Write and
Read pointers to the queue are initialized to zero. Partial Reset will not alter previously programmed configurations but will
initialize Write and Read pointers to zero.
In FWFT mode, the first data written into the queue appears on output data bus after the specified latency period at the low to
high transition of RCLK. Subsequent reads from the queue will require asserting REN . This feature is useful when
implementing depth expansion functions. In this mode, DRDY and QRDY are used instead of FULL and
EMPTY respectively.
MAY 2002
Flex
Q
TMIII Plus
3F3P1020A
FQV202113 · FQV202103 · FQV20293 · FQV20283 · FQV20273 · FQV20263
·
FQV20253· FQV20243
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Page 2 of 2
Product Description (Continued)
In Standard mode, always assert REN whenever a read operation. FULL and EMPTY are used instead of DRDY and
QRDY respectively.
Bus matching feature is available with the following configurations:
Input Bus Width Output Bus Width
x10 x10
x10 x20
x20 x10
x20 x20
In addition, Endian Select is available for implementing byte re-ordering on data outputs.
Eight different default offset values are available for Almost Full ( PRAF ) and Almost Empty ( PRAE ) flags. Parallel and Serial
programming of these offset values provide total flexibility other than the pre-defined default values. Both 8-bit and 10-bit
parallel programming modes for offset values can be selected for convenience.
PRAF , PRAE , and HALF are available in either FWFT or Standard mode. PRAF and PRAE can operate in either
synchronous or asynchronous modes.
At any time, data previously read from the queue can be retransmitted by asserting RET pin at the low to high transition of
RCLK for a retransmit operation. Retransmit initializes the Read pointer to zero. Hence, all re-reads will always start from the
physical 0th (Read pointer = zero), location of the queue. Both zero and normal latency timing modes are available for retransmit
operation.
These FlexQ™ III Plus devices have low power consumption, hence minimizing system power requirements. In addition,
industry standard 144 - pin Plastic TQFP is offered to save system board space.
These queues are ideal for applications such as data communication, telecommunication, graphics, multiprocessing, test
equipment, network switching, etc.
.
MAY 2002
Flex
Q
TMIII Plus
3F3P1020A
FQV202113 · FQV202103 · FQV20293 · FQV20283 · FQV20273 · FQV20263
·
FQV20253· FQV20243
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Page 3 of 3
REN
FQV202113
FQV202103
FQV20293
FQV20283
FQV20273
FQV20263
FQV20253
FQV20243
WRTIE CLOCK (WCLK)
x20 or x10 DATA IN (D 19 - 0)
FIRST WORD FALL THROUGH/
SERIAL DATA INPUT (FWFT/SDI)
FULL FLAG / INPUT READY
( )
PROGRAMMABLE
ALMOST-FULL ( )
READ CLOCK (RCLK)
READ ENABLE ( )
OUTPUT ENABLE ( )
x20 or x10 DATA OUT (Q 19 - 0)
RETRANSMIT ( )
EMPTY FLAG / OUTPUT READY
( )
PROGRAMMABLE ALMOST-
EMPTY ( )
PARTIAL RESET ( ) MASTER RESET ( )
Block Diagram of Single Synchronous Queue
262,144 x 20 / 131,072 x 20 / 65,536 x 20 / 32,768 x 20 / 16,384 x 20 / 8,192 x 20 / 4,096 x 20 / 2,048 x 20 /
524,286 x 10 / 262,144 x 10 / 131,072 x 10 / 65,536 x 10 / 32,768 x 10 / 16,384 x 10 / 8,192 x 10 / 4,096 x 10
BIG-ENDIAN / LITTLE-ENDIAN ( )
INTERSPERSED /
NON-INTERSPERSED PARITY (IPAR)
BUS MATCHING 0
(BM0)
BUS MATCHING 1
(BM1)
HALF-FULL FLAG ( )
SERIAL DATA ENABLE
( )
LOAD ( )
WRITE ENABLE ( )
PRST MRST
WEN
LOAD
OE
RET
QRDY/EMPTY
PRAE
PRAF
HALF
ES
SDEN
DRDY/FULL
Figure 1. Single Device Configuration Signal Flow Diagram
MAY 2002
Flex
Q
TMIII Plus
3F3P1020A
FQV202113 · FQV202103 · FQV20293 · FQV20283 · FQV20273 · FQV20263
·
FQV20253· FQV20243
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Page 4 of 4
Offset Register
Write Control
Logic
Write Pointer
SRAM
Input Register Output Register
Flag Logic
Output
Buffer
x20, x10
D19-0
Read Pointer
Read Control
Logic Reset Bus
Configuration
FWFT/SDIIPAR LOAD SDEN
WCLK
FWFT/SDI
SFM
PFS1
PFS0
PRAF
/
FULL DRDY
PRAE
HALF
EMPTY QRDY
/
OE
MRST PRSTRCLKRETZL RET REN
WEN
ES BM1 BM0
x20, x10
Q19-0
Figure 2. Device Architecture
MAY 2002
Flex
Q
TMIII Plus
3F3P1020A
FQV202113 · FQV202103 · FQV20293 · FQV20283 · FQV20273 · FQV20263
·
FQV20253· FQV20243
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Page 5 of 5
WEN
SDEN
DNC1
Vcc
D18
Vcc
D16
D15
D14
BM1
GND
D13
Vcc
D11
D10
D8
Vcc
D12
GND
Q15
Q14
Q13
Vcc
GND
Vcc
Q16
Q11
Q10
Vcc
Vcc
Q9
Q8
Q7
Q12
GND
Q6
D7
D6
D4
Vcc
D2
D1
D0
Q0
Q2
Q3
Q4
Q5
GND
D5
D3
GND
Vcc
Q1
FWFT/SDI
GND
BM0
PFS0
PFS1
Vcc
SFM
WCLK
Vcc
GND
RCLK
RETZL
GND
PRST
MRST
LOAD
FULL/DRDY
PRAF
HALF
ES
IPAR
PRAE
EMPTY/QRDY
RET
REN
Index
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
66
65
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
72
71
70
69
68
67
108
107
106
105
104
103
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
GND
D19
D17
D9
Vcc
Vcc
Vcc
GND
Vcc
GND
GND
Vcc
Q17
Q18
Q19
OE
GND
Vcc
GND
GND
Vcc
GND
GND
DNC1
DNC1
DNC1
DNC1
DNC1
DNC1
DNC1
DNC1
DNC1
DNC1
DNC1
DNC1
DNC1
DNC1
DNC
1
DNC
1
DNC
1
DNC
1
DNC
1
DNC
1
DNC
1
DNC
1
DNC
1
DNC
1
DNC1
DNC1
DNC1
DNC1
DNC1
DNC1
DNC1
DNC1
DNC1
DNC1
DNC1
DNC1
DNC1
DNC1
DNC1
DNC
1
DNC
1
DNC
1
TQFP - 144 (Drw No: PF-03A: Order code: PF)
Top View
NOTES:
1. DNC = Do Not Connect.
Figure 3. Device Pin Out
MAY 2002
Flex
Q
TMIII Plus
3F3P1020A
FQV202113 · FQV202103 · FQV20293 · FQV20283 · FQV20273 · FQV20263
·
FQV20253· FQV20243
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Page 6 of 6
Pin # Pin Name Pin Symbol Input/Output Description
142 Master Reset
MRST Input
Master Reset is required to initialize Write and Read
pointers to the first position of the queue by setting
MRST low. In Standard mode, FULL and PRAF will
go high; EMPTY and PRAE will go low. In FWFT
mode, DRDY will go low and QRDY will go high.
PRAF and PRAE will go to the same state as Standard
mode. In both modes, all data outputs will go low.
Previous programmed configurations will not be
maintained.
143 Partial Reset
PRST Input
Partial Reset is required to initialize Write and Read
pointers to the first position of the queue by setting
PRST low. In Standard mode, FULL and PRAF will
go high; EMPTY and PRAE will go low. In FWFT
mode, DRDY will go low and QRDY will go high.
PRAF and PRAE will go to the same state as Standard
mode. In both modes, all data outputs will go low.
Previous programmed configurations will be
maintained.
144 Write Clock WCLK Input
Writes data into queue during low to high transitions of
WCLK if WEN is set to low.
1 Write Enable WEN Input
Controls write operation into queue or offset registers
during low to high transition of WCLK.
141 Load Enable
LOAD Input
During Master Reset, set LOAD low to select parallel
programming or one of eight default-offset values. Set
LOAD high to select serial programming or one of
eight default offset values. After Master Reset,
LOAD controls write/read, to/from offset registers
during low to high transition of WCLK/RCLK
respectively. Use in conjunction with WEN /REN .
127 Default
Programming 1 PFS1 Input
During Master Reset, select one of eight default-offset
values. Use in conjunction with LOAD and PFS1.
130 Default
Programming 0 PFS0 Input
During Master Reset, select one of eight default-offset
values. Use in conjunction with LOAD and PFS0.
06,10,14,16,
18,20,23,26,
28,30,32,34,
39,41,46,47,
48,51,52,53.
Data Inputs D19-0 Input
20 - bit wide input data bus.
112 Read Clock RCLK Input
Reads data from queue during low to high transitions of
RCLK if REN is set to low.
111 Read Enable
REN Input Controls read operation from queue or offset registers
during low to high transition of RCLK.
109 Output Enable
OE
Input
Setting OE low activates the data output drivers.
Setting OE high deactivates the data output drivers
(High-Z).
Table 1. Pin Descriptions
MAY 2002
Flex
Q
TMIII Plus
3F3P1020A
FQV202113 · FQV202103 · FQV20293 · FQV20283 · FQV20273 · FQV20263
·
FQV20253· FQV20243
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Page 7 of 7
Pin # Pin Name Pin Symbol Input/Output Description
108,107,105,98,
96,92,91,87,
81,77,76,74,
73,72,63,62,
59,58,56,55
Data Outputs Q19-0 Output
20 - bit wide output data bus.
140
First Word Fall
Through/Serial
Data Input
FWFT/SDI Input
Selects FWFT timing or Standard timing mode during
Master Reset. After Master Reset, if serial
programming is selected ( LOAD = high), FWFT/SDI
is used as the serial data input for the offset registers.
Serial data is written during the low to high transition
of WCLK. Use in conjunction with SDEN .
2 Serial Data
Input Enable SDEN Input
If serial programming is selected, setting SDEN low
and LOAD low enables serial data input to be written
into offset registers during the low to high transition of
WCLK.
5 Bus Matching
1 BM1 Input
During Master Reset, set BM1 low to select x20 input
bus width or BM1 high to select x10 input bus width.
131 Bus Matching
0 BM0 Input
During Master Reset, set BM0 low to select x20
output bus width or BM0 high to select x10 output bus
width.
125 Endian Select ES Input
During Master Reset, set ES high to select byte re-
ordering on data outputs or ES low to select no byte
re-ordering on data outputs.
110 Retransmit
RET Input
Data previously read from the queue can be
retransmitted by asserting RET pin at the low to high
transition of RCLK for a retransmit operation.
Retransmit initializes the Read pointer to zero. Hence,
all re-reads will always start from the physical 0th
(Read pointer = zero) location of the queue.
115 Zero Latency
Retransmit RETZL Input
During Master Reset, set RETZL low to select zero
latency retransmit or RETZL high to select normal
latency retransmit.
137 Full/Data Input
Ready Flag FULL / DRDY Output
Queue is full when FULL goes low during the low to
high transition of WCLK. This prohibits further
writes into the queue. In FWFT mode, queue is full
when DRDY goes high during low to high transition
of WCLK. This prohibits further writes into the
queue.
116
Empty/Data
Output Ready
Flag
EMPTY / QRDY Output
Queue is empty when EMPTY goes low during the
low to high transition of RCLK. This prohibits further
reads from the queue. In FWFT mode, queue is empty
when QRDY goes high during the low to high
transition of RCLK. This prohibits further reads from
the queue.
124 Interspersed
Parity IPAR Input
During Master Reset, set IPAR low to select 10-bit
parallel programming mode or IPAR high to select 8-
bit parallel programming mode.
Table 1. Pin Descriptions (Continued)
MAY 2002
Flex
Q
TMIII Plus
3F3P1020A
FQV202113 · FQV202103 · FQV20293 · FQV20283 · FQV20273 · FQV20263
·
FQV20253· FQV20243
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Page 8 of 8
Pin # Pin Name Pin Symbol Input/Output Description
117 Synchronous Partial
Flag Mode SFM Input
During Master Reset, set SFM high to select
Synchronous Partial Flag mode or SFM low to select
Asynchronous Partial Flag mode.
134 Almost Full
PRAF Output
Queue is almost full when PRAF goes low during the
low to high transition of WCLK. Default (Full-offset)
or programmed offset values determine the status of
PRAF .
119 Almost Empty
PRAE Output
Queue is almost empty when PRAE goes low during
the low to high transition of RCLK. Default (Empty
+offset) or programmed offset values determine the
status of PRAE .
129 Half Full
HALF Output Queue is more than half full when HALF goes low.
Triggered by both WCLK and RCLK.
07,08,09,12,
13,15,17,19,
21,25,27,29,
31,33,36,37,
38,40,42,43,
65,68,69,70,
71,75,79,80,
83,84,85,88,
89,94,95,97,
100,101,103,
104,118,120,
122.
Do Not Connect DNC N/A Do not connect.
04,11,24,35,
49,50,60,61,
66,67,78,86,
93,99,106,121,
123,135,136.
Power VCC N/A 3.3V power supply.
03,22,44,45,
54,5764,82,
90,102,113,
114,118,120,
126,128,132,
133,138,139
Ground GND N/A 0V Ground.
Table 1. Pin Descriptions (Continued)
MAY 2002
Flex
Q
TMIII Plus
3F3P1020A
FQV202113 · FQV202103 · FQV20293 · FQV20283 · FQV20273 · FQV20263
·
FQV20253· FQV20243
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Page 9 of 9
Symbol Rating Com’l & Ind’l Unit
VTERM Terminal Voltage with
respect to GND -0.5 to + 4.5 V
TSTG Storage Temperature -55 to +125 °C
IOUT DC Output Current -50 to +50 mA
NOTES:
Absolute Max Ratings are for reference only. Permanent damage to the device may
occur if extended period of operation is outside this range. Standard operation should
fall within the Recommended Operating Conditions.
Table 2. Absolute Maximum Ratings
FQV202113, FQV202103FQV20293, FQV20283
FQV20273, FQV20263, FQV20253, FQV20243
Commercial
Clock = 6ns, 7.5ns, 10ns
Industrial
Clock = 7.5ns, 10ns, 15ns
Symbol Parameter Min. Typ. Max. Min. Typ. Max. Unit
Recommended Operating Conditions
Vcc Supply Voltage Com’l / Ind’l 3.15 3.3 3.45 3.15 3.3 3.45 V
GND Supply Voltage 0 0 0 0 0 0 V
VIH Input High Voltage Com’l /
Ind’l 2.0 - 5.5 2.0 - 5.5 V
VIL Input Low Voltage Com’l /
Ind’l - - 0.8 - - 0.8 V
TA Operating Temperature
Commercial 0 - 70 0 - 70 °C
TA Operating Temperature
Industrial -40 - 85 -40 - 85 °C
DC Electrical Characteristics
ILI(1) Input Leakage Current (any
input) -10 - 10 -10 - 10 µA
ILO Output Leakage Current -10 - 10 -10 - 10 µA
VOH Output Logic “1” Voltage,
IOH=-2mA 2.4 - - 2.4 - - V
VOL Output Logic “0” Voltage, IOL
= 8mA - - 0.4 - - 0.4 V
Power Consumption
ICC1(2,3) Active Power Supply Current
(x10 Input to x10 Output) - - 30 - - 30 mA
ICC1(2,3) Active Power Supply Current
(x20 Input to x20 Output) - - 35 - - 35 mA
ICC2(4) Standby Current - - 15 - - 15 mA
Table 3. DC Specifications
MAY 2002
Flex
Q
TMIII Plus
3F3P1020A
FQV202113 · FQV202103 · FQV20293 · FQV20283 · FQV20273 · FQV20263
·
FQV20253· FQV20243
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Page 10 of 10
Capacitance at 100MHz Ambient Temperature (25°C)
Symbol Parameter Conditions Max. Unit
CIN(2) Input Capacitance VIN= 0V 10 pF
COUT(2,4) Output Capacitance VOUT= 0V 10 pF
NOTES:
1. Measurement with 0.4<=VIN<=Vcc.
2. With output tri-stated ( OE = High).
3. Icc(1,2) is measured with WCLK and RCLK at 20 MHz.
4. Design simulated, not tested.
Table 3. DC Specifications (Continued)
MAY 2002
Flex
Q
TMIII Plus
3F3P1020A
FQV202113 · FQV202103 · FQV20293 · FQV20283 · FQV20273 · FQV20263
·
FQV20253· FQV20243
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Page 11 of 11
Commercial Commercial & Industrial
FQV202113-6
FQV202103-6
FQV20293-6
FQV20283-6
FQV20273-6
FQV20263-6
FQV20253-6
FQV20243-6
FQV202113-7.5
FQV202103-7.5
FQV20293-7.5
FQV20283-7.5
FQV20273-7.5
FQV20263-7.5
FQV20253-7.5
FQV20243-7.5
FQV202113-10
FQV202103-10
FQV20293-10
FQV20283-10
FQV20273-10
FQV20263-10
FQV20253-10
FQV20243-10
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
fS Clock Cycle Frequency - 166 - 133 - 100 MHz
tA Data Access Time 1 4 2 5 2 6.5 ns
tWCLK Write Clock Cycle Time 6 - 7.5 - 10 - ns
tWCLKH Write Clock High Time 2.5 - 3.5 - 4.5 - ns
tWCLKL Write Clock Low Time 2.5 - 3.5 - 4.5 - ns
tRCLK Read Clock Cycle Time 6 - 7.5 - 10 - ns
tRCLKH Read Clock High Time 2.5 - 3.5 - 4.5 - ns
tRCLKL Read Clock Low Time 2.5 - 3.5 - 4.5 - ns
tDS Data Set-up Time 2.0 - 2.5 - 3.5 - ns
tDH Data Hold Time 0.5 - 0.5 - 0.5 - ns
tENS Enable Set-up Time 2.0 - 2.5 - 3.5 - ns
tENH Enable Hold Time 0.5 - 0.5 - 0.5 - ns
tRST Reset Pulse Width(1) 8 - 10 - 10 - ns
tRSTS Reset Set-up Time 10 - 15 15 - ns
tRSTR Reset Recovery Time 10 - 10 - 10 - ns
tRSTF Reset to Flag and Output Time - 10 - 15 - 15 ns
tOLZ Output Enable to Output in Low-Z(1) 0 - 0 - 0 - ns
tOE Output Enable to Output Valid 2 4 2 6 2 6 ns
tOHZ Output Enable to Output in High-Z(1) 2 4 2 6 2 6 ns
tFULL Write Clock to Full Flag - 4 - 5 - 6.5 ns
tEMPTY Read Clock to Empty Flag - 4 - 5 - 6.5 ns
tPRAFS Write Clock to Synchronous Almost-Full Flag - 4 - 5 - 6.5 ns
tPRAES Read Clock to Synchronous Almost-Empty Flag - 4 - 5 - 6.5 ns
tSKEW1 Skew time between Read Clock & Write Clock
for Full Flag / Empty Flag 4 - 5 - 7 - ns
tSKEW2 Skew time between Read Clock & Write Clock
for PRAE & PRAF 6 - 7 - 10 - ns
tLOADS Load Setup Time 2 - 2.5 - 3.5 - ns
tLOADH Load Hold Time 0.5 - 0.5 - 0.5 - ns
Table 4. AC Electrical Characteristics
MAY 2002
Flex
Q
TMIII Plus
3F3P1020A
FQV202113 · FQV202103 · FQV20293 · FQV20283 · FQV20273 · FQV20263
·
FQV20253· FQV20243
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Page 12 of 12
Commercial Commercial & Industrial
FQV202113-6
FQV202103-6
FQV20293-6
FQV20283-6
FQV20273-6
FQV20263-6
FQV20253-6
FQV20243-6
FQV202113-7.5
FQV202103-7.5
FQV20293-7.5
FQV20283-7.5
FQV20273-7.5
FQV20263-7.5
FQV20253-7.5
FQV20243-7.5
FQV202113-10
FQV202103-10
FQV20293-10
FQV20283-10
FQV20273-10
FQV20263-10
FQV20253-10
FQV20243-10
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
tRETS Retransmit Setup Time 3 - 3.5 - 3.5 - ns
tHALF Clock to HALF - 12 - 12.5 - 16 ns
tPRAFA Write Clock to Asynchronous
Programmable Almost-Full Flag - 12 - 12.5 - 16 ns
tPRAEA Read Clock to Asynchronous
Programmable Almost-Empty Flag - 12 - 12.5 - 16 ns
NOTES:
1. Design simulated, not tested.
Table 4. AC Electrical Characteristics (Continued)
MAY 2002
Flex
Q
TMIII Plus
3F3P1020A
FQV202113 · FQV202103 · FQV20293 · FQV20283 · FQV20273 · FQV20263
·
FQV20253· FQV20243
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Page 13 of 13
Input Pulse Levels GND to 3.0V
Input Rise/Fall Times 3ns
Input Timing Reference Levels 1.5V
Output Reference Levels 1.5V
Output Load, clock = 6ns, 7.5ns, 10ns Refer to Figure 4
Table 5. AC Test Condition
Figure 4. AC Test Load
for clock = 6ns, 7.5ns, 10ns
Vcc/2
50 Ω
Z0 = 50 Ω
I/O
MAY 2002
Flex
Q
TMIII Plus
3F3P1020A
FQV202113 · FQV202103 · FQV20293 · FQV20283 · FQV20273 · FQV20263
·
FQV20253· FQV20243
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Page 14 of 14
Pin Functions
MRST Master Reset is required to initialize Write and Read pointers to the first position of the queue by setting
MRST low. In Standard mode, FULL and PRAF will go high; EMPTY and PRAE will go low. In
FWFT mode, DRDY will go low and QRDY will go high. PRAF and PRAE will go to the same state
as Standard mode. In both modes, all data outputs will go low. Previous programmed configurations will
not be maintained.
PRST Partial Reset is required to initialize Write and Read pointers to the first position of the queue by setting
PRST low. In Standard mode, FULL and PRAF will go high; EMPTY and PRAE will go low. In
FWFT mode, DRDY will go low and QRDY will go high. PRAF and PRA
E
will go to the same state
as Standard mode. In both modes, all data outputs will go low. Previous programmed configurations will
be maintained.
WCLK Writes data into queue during low to high transitions of WCLK if WEN is activated. Synchronizes
FULL /DRD
Y
and PRAF flags. WCLK and RCLK are independent of each other.
WEN Controls write operation into queue or offset registers during low to high transition of WCLK.
LOAD During Master Reset, set LOAD low to select parallel programming or one of eight default offset values.
Set LOAD high to select serial programming or one of eight default offset values. After Master Reset,
LOAD controls write/read, to/from offset registers during low to high transition of WCLK/RCLK
respectively for parallel programming. Use in conjunction with WEN /REN . During programming of
offset registers, PRAF and PRA
E
flag status is invalid. For Serial programming, LOAD is used to
enable serial loading of offset registers together with SDEN . Refer to Figure 5 & Table 11 for details.
PFS1 During Master Reset, select one of eight default-offset values. Use in conjunction with LOAD
and PFS1. Refer to Table 11 for details.
PFS0 During Master Reset, select one of eight default-offset values. Use in conjunction with LOAD and
PFS0. Refer to Table 11 for details.
D19-0 20 - bit wide input data bus.
RCLK Reads data from queue during low to high transitions of RCLK if REN is set low. Synchronizes the
EMPT
Y
/QRDY and PRA
E
flags. RCLK and WCLK are independent of each other.
REN Reads data from queue during low to high transitions of RCLK if REN is set low. This also advances the
Read pointer of the queue.
OE Setting OE low activates the data output drivers. Setting OE high deactivates the data output drivers
(High-Z). OE does not control advancement of Read pointer.
Q19-0 20 - bit wide output data bus.
FWFT/SDI Selects FWFT timing or Standard timing mode during Master Reset. After Master Reset, if serial
programming is selected ( LOAD = high), FWFT/SDI is used as the serial data input for the offset
registers. Serial data is written during the low to high transition of WCLK. Use in conjunction with
SDEN . In FWFT mode, DRD
Y
and QRDY is used instead of FULL and EMPT
Y
. Refer to Table 9
for all flags status. In Standard mode, FULL and EMPT
Y
are used instead of DRD
Y
and QRDY .
Refer to Table 9 for all flags status.
SDEN If serial programming is selected, setting SDEN low and LOAD low enables serial data to be written into
offset registers during the low to high transition of WCLK. During serial programming, PRAF and
PRA
E
flags status is invalid. Refer to Figure 5 for details.
MAY 2002
Flex
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TMIII Plus
3F3P1020A
FQV202113 · FQV202103 · FQV20293 · FQV20283 · FQV20273 · FQV20263
·
FQV20253· FQV20243
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Page 15 of 15
Pin Functions (Continued)
BM1 During Master Reset, setting BM1 low selects x20 input bus width. Set BM1 high selects x10 input bus
width. Refer to Table 10 for details.
BM0 During Master Reset, set BM0 low to select x20 output bus width. Set BM0 high to select x10 output
bus width. Refer to Table 10 for details.
ES During Master Reset, Set ES high to select byte re-ordering on data outputs or set ES low to select no
byte re-ordering on data outputs. ES must be static throughout device operation. Refer to Table 10 for
details.
RET Data previously read from the queue can be retransmitted by asserting RE
T
pin at the low to high
transition of RCLK for a retransmit operation. Retransmit initializes the Read pointer to zero. Hence,
all re-reads will always start from the physical 0th (Read pointer = zero), location of the queue. Refer to
Diagram 7 & 8 for details.
RETZL During Master Reset, set RETZ
L
low to select zero latency retransmit or set RETZ
L
high to select
normal latency retransmit.
FULL / DRDY In Standard mode, queue is full when FULL goes low during the low to high transition of WCLK. This
prohibits further writes into the queue and prevents advancement of Write pointer. In FWFT mode,
queue is full when DRD
Y
goes high during the low to high transition of WCLK. This prohibits further
writes into the queue and prevents advancement of Write pointer. Refer to Table 8 & 9 for behavior of
FULL / DRD
Y
.
EMPTY / QRDY In Standard mode, queue is empty when EMPT
Y
goes low during the low to high transition of RCLK.
This prohibits further reads from the queue and prevents advancement of Read pointer. In FWFT mode,
queue is empty when QRDY goes low during the low to high transition of RCLK. This prohibits
further reads from the queue and prevents advancement of Read pointer. Refer to Table 8 & 9 for
behavior of EMPT
Y
/QRDY .
IPAR During Master Reset, set IPAR low to select 10-bit parallel programming mode or set IPAR high to
select 8-bit parallel programming mode. In 10-bit mode, 10-bit wide data input/output bus width is
used for storing/fetching offset values. In 8-bit mode, 8-bit wide data input/output bus is used for
storing/fetching offset values.
SFM During Master Reset, set SFM high to select Synchronous Partial Flag mode or set SFM low to select
Asynchronous Partial Flag mode. In Synchronous mode, PRAF and PRA
E
are synchronous to WCLK
and RCLK respectively. In Asynchronous mode, WCLK synchronizes the assertion of PRAF and de-
assertion of PRA
E
. RCLK synchronizes the assertion of PRA
E
and de-assertion of PRA
E
.
PRAF In Synchronous mode, queue is almost full when PRAF goes low during the low to high transition of
WCLK. Default (Full-offset) or programmed offset values determine the status of PRAF . In
Asynchronous mode, PRAF is triggered by both WCLK and RCLK. Refer to Table 8 & 9 for behavior
of PRAF .
PRAE In Synchronous mode, queue is almost empty when PRA
E
goes low during the low to high transition of
RCLK. Default (Empty+offset) or programmed offset values determine the status of PRA
E
. In
Asynchronous timing mode, PRAF is triggered by both WCLK and RCLK. Refer to Table 8 & 9 for
behavior of PRA
E
.
HALF Queue is more than half full when HAL
F
goes low during the low to high transition of WCLK.
HAL
F
goes high during low to high transition of RCLK when queue is less than half full. Refer to
Table 8 & 9 for details.
MAY 2002
Flex
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TMIII Plus
3F3P1020A
FQV202113 · FQV202103 · FQV20293 · FQV20283 · FQV20273 · FQV20263
·
FQV20253· FQV20243
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Page 16 of 16
LOAD WEN REN
SDEN
WCLK RCLK
FQV20283
FQV20273
FQV20263
FQV20253
FQV20243
Selection / Sequence
0 0 1 1
X
Parallel write to offset
registers:
Empty Offset (Low Byte)
Empty Offset (High Byte)
Full Offset (Low Byte)
Full Offset (High Byte)
Parallel write to
registers:
1. PRAE Low Byte
2. PRAE High Byte
3. PRAF Low Byte
4. PRAF High Byte
0 1 0 1 X
Parallel read from offset
registers:
Empty Offset (Low Byte)
Empty Offset (High Byte)
Full Offset (Low Byte)
Full Offset (High Byte)
Parallel read from
registers:
1. PRAE Low Byte
2. PRAE High Byte
3. PRAF Low Byte
4. PRAF High Byte
0 1 1 0
X
x10 to x10 Mode
Serial shift into registers:
32 bits for the FQV20283
30 bits for the FQV20273
28 bits for the FQV20263
26 bits for the FQV20253
24 bits for the FQV20243
1 bit for each rising WCLK
edge
Starting with Empty Offset
(Low Byte)
Ending with Full Offset
(High Byte)
All Other Modes
Serial shift into registers:
30 bits for the FQV20283
28 bits for the FQV20273
26 bits for the FQV20263
24 bits for the FQV20253
22 bits for the FQV20243
1 bit for each rising WCLK
edge
Starting with Empty Offset
(Low Byte)
Ending with Full Offset
(High Byte)
X 1 1 1 X X No Operation
1 0 X X
X Write Memory
1 X 0 X X
Read Memory
1 1 1 X X X No Operation
Figure 5. Programmable Flag Offset Programming Sequence (FQV20283, FQV20273, FQV20263, FQV20253 and FQV20243)
MAY 2002
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TMIII Plus
3F3P1020A
FQV202113 · FQV202103 · FQV20293 · FQV20283 · FQV20273 · FQV20263
·
FQV20253· FQV20243
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Page 17 of 17
LOAD
WEN REN
SDEN
WCLK RCLK
FQV202113
FQV202103
FQV20293
Selection / Sequence
0 0 1 1
X
Parallel write to offset
registers:
Empty Offset (Low Byte)
Empty Offset (Mid Byte)
Empty Offset (High Byte)
Full Offset (Low Byte)
Full Offset (Mid Byte)
Full Offset (High Byte)
Parallel write to
registers:
1. PRAE Low Byte
2. PRAE Mid Byte
3. PRAE High Byte
4. PRAF Low Byte
5. PRAF Mid Byte
6. PRAF High Byte
0 1 0 1 X
Parallel read from offset
registers:
Empty Offset (Low Byte)
Empty Offset (Mid Byte)
Empty Offset (High Byte)
Full Offset (Low Byte)
Full Offset (Mid Byte)
Full Offset (High Byte)
Parallel read from
registers:
1. PRAE Low Byte
2. PRAE Mid Byte
3. PRAE High Byte
4. PRAF Low Byte
5. PRAF Mid Byte
6. PRAF High Byte
0 1 1 0
X
x10 to x10 Mode
Serial shift into registers:
38 bits for the FQV202113
36 bits for the FQV202103
34 bits for the FQV20293
1 bit for each rising WCLK
edge
Starting with Empty Offset
(Low Byte)
Ending with Full Offset
(High Byte)
All Other Modes
Serial shift into registers:
36 bits for the FQV202113
34 bits for the FQV202103
32 bits for the FQV20293
1 bit for each rising WCLK
edge
Starting with Empty Offset
(Low Byte)
Ending with Full Offset
(High Byte)
X 1 1 1 X X No Operation
1 0 X X
X Write Memory
1 X 0 X X
Read Memory
1 1 1 X X X No Operation
Figure 6. Programmable Flag Offset Programming Sequence (FQV202113, FQV202103, FQV20293)
MAY 2002
Flex
Q
TMIII Plus
3F3P1020A
FQV202113 · FQV202103 · FQV20293 · FQV20283 · FQV20273 · FQV20263
·
FQV20253· FQV20243
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Page 18 of 18
Device PRAF Programming (bits) PRAE Programming (bits)
D/Q15 - 0 Non-IPAR D/Q15 - 0 Non-IPAR
FQV202113 D/Q17 – 10 & D/Q7 – 0 IPAR D/Q17 – 10 & D/Q7 – 0 IPAR
D/Q15 – 0 Non-IPAR D/Q15 – 0 Non-IPAR
FQV202103 D/Q17 – 10 & D/Q7 – 0 IPAR D/Q17 – 10 & D/Q7 – 0 IPAR
D/Q15 - 0 Non-IPAR D/Q15 - 0 Non-IPAR
FQV20293 D/Q17 – 10 & D/Q7 – 0 IPAR D/Q17 – 10 & D/Q7 – 0 IPAR
D/Q14 - 0 Non-IPAR D/Q14 - 0 Non-IPAR
FQV20283 D/Q16 – 10 & D/Q7 – 0 IPAR D/Q16 – 10 & D/Q7 – 0 IPAR
D/Q13 - 0 Non-IPAR D/Q13 - 0 Non-IPAR
FQV20273 D/Q15 – 10 & D/Q7 – 0 IPAR D/Q15 – 10 & D/Q7 – 0 IPAR
D/Q12 - 0 Non-IPAR D/Q12 - 0 Non-IPAR
FQV20263 D/Q14 – 10 & D/Q7 – 0 IPAR D/Q14 – 10 & D/Q7 – 0 IPAR
D/Q11 – 0 Non-IPAR D/Q11 – 0 Non-IPAR
FQV20253 D/Q13 – 10 & D/Q7 – 0 IPAR D/Q13 – 10 & D/Q7 – 0 IPAR
D/Q10 – 0 Non-IPAR D/Q10 – 0 Non-IPAR
FQV20243 D/Q12 – 10 & D/Q7 – 0 IPAR D/Q12 – 10 & D/Q7 – 0 IPAR
Condition Applies to: Write Cycle with x20 input Bus Width and/or
Read Cycle with x20 output Bus Width
Device PRAF Programming (bits) PRAE Programming (bits)
D/Q7 - 0 Low Byte D/Q7 - 0 Low Byte
D/Q7 - 0 Mid Byte D/Q7 - 0 Mid Byte
FQV202113
D/Q1 - 0 High Byte D/Q1 - 0 High Byte
D/Q7 - 0 Low Byte D/Q7 - 0 Low Byte
D/Q7 - 0 Mid Byte D/Q7 - 0 Mid Byte
FQV202103
D/Q0 High Byte D/Q 0 High Byte
D/Q7 - 0 Low Byte D/Q7 - 0 Low Byte
FQV20293 D/Q7 - 0 High Byte D/Q7 - 0 High Byte
D/Q7 - 0 Low Byte D/Q7 - 0 Low Byte
FQV20283 D/Q6 - 0 High Byte D/Q6 - 0 High Byte
D/Q7 - 0 Low Byte D/Q7 - 0 Low Byte
FQV20273 D/Q5 - 0 High Byte D/Q5 - 0 High Byte
D/Q7 - 0 Low Byte D/Q7 - 0 Low Byte
FQV20263 D/Q4 - 0 High Byte D/Q4 - 0 High Byte
D/Q7 - 0 Low Byte D/Q7 - 0 Low Byte
FQV20253 D/Q3 - 0 High Byte D/Q3 - 0 High Byte
D/Q7 - 0 Low Byte D/Q7 - 0 Low Byte
FQV20243 D/Q2 - 0 High Byte D/Q2 - 0 High Byte
Condition Applies to: Write Cycle with x10 input Bus Width or
Read Cycle with x10 output Bus Width (except x10 to x10 mode)
MAY 2002
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TMIII Plus
3F3P1020A
FQV202113 · FQV202103 · FQV20293 · FQV20283 · FQV20273 · FQV20263
·
FQV20253· FQV20243
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Page 19 of 19
Device PRAF Programming (bits) PRAE Programming (bits)
D/Q7 - 0 Low Byte D/Q7 - 0 Low Byte
D/Q7 - 0 Mid Byte D/Q7 - 0 Mid Byte
FQV202113
D/Q2 - 0 High Byte D/Q2 - 0 High Byte
D/Q7 - 0 Low Byte D/Q7 - 0 Low Byte
D/Q7 - 0 Mid Byte D/Q7 - 0 Mid Byte
FQV202103
D/Q1 - 0 High Byte D/Q1 - 0 High Byte
D/Q7 - 0 Low Byte D/Q7 - 0 Low Byte
D/Q7 - 0 Mid Byte D/Q7 - 0 Mid Byte
FQV20293
D/Q0 High Byte D/Q0 High Byte
D/Q7 - 0 Low Byte D/Q7 - 0 Low Byte
FQV20283 D/Q7 - 0 High Byte D/Q7 - 0 High Byte
D/Q7 - 0 Low Byte D/Q7 - 0 Low Byte
FQV20273 D/Q6 - 0 High Byte D/Q6 - 0 High Byte
D/Q7 - 0 Low Byte D/Q7 - 0 Low Byte
FQV20263 D/Q5 - 0 High Byte D/Q5 - 0 High Byte
D/Q7 - 0 Low Byte D/Q7 - 0 Low Byte
FQV20253 D/Q4 - 0 High Byte D/Q4 - 0 High Byte
D/Q7 - 0 Low Byte D/Q7 - 0 Low Byte
FQV20243 D/Q3 - 0 High Byte D/Q3 - 0 High Byte
Condition Applies to: Write Cycle with x10 input Bus Width and
Read Cycle with x10 output Bus Width (only x10 to x10 mode)
Table 6. Parallel Offset Write/Read Cycle Register Location
Device Standard Mode FWFT Mode
FQV202113 262,144 x 20 / 524,288 x10 262,145 x 20 / 524,289 x10
FQV202103 131,072 x 20 / 262,144 x10 131,073 x 20 / 262,145 x 10
FQV20293 65,536 x 20 / 131,072 x 10 65,537,x 20 / 131,073 x 10
FQV20283 32,768 x 20 / 65,536 x 10 32,769 x 20 / 65,537 x 10
FQV20273 16,384 x 20 / 32,768 x 10 16,385 x 20 / 32,769 x 10
FQV20263 8,192 x 20 / 16,384 x 10 8,193 x 20 / 16,385 x 10
FQV20253 4,096 x 20 / 8,192 x 10 4,097 x 20 / 8,193 x 10
FQV20243 2,048 x 20 / 4,096 x 10 2,049 x 20 / 4,097 x 10
Table 7. Maximum Depth of Queue for Standard and FWFT Mode
MAY 2002
Flex
Q
TMIII Plus
3F3P1020A
FQV202113 · FQV202103 · FQV20293 · FQV20283 · FQV20273 · FQV20263
·
FQV20253· FQV20243
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Page 20 of 20
FQV20293, FQV20283, FQV20273, FQV20263, FQV20253, FQV20243
Parallel Offset Write/Read Cycles for x10 Bus Width
Condtion Applies to: Write Cycle with x10 input Bus Width
and/or Read Cycle output with x10 Bus Width
(except FQV20293 x10 to x10 mode)
Data Width
Data Width
56
FQV202113, FQV202103, FQV20293
Parallel Offset Write/Read Cycles for x10 Bus Width
Condtion Applies to: FQV20293 x10 to x10 mode or
FQV202113, FQV202103 for all modes
Low Byte
High Byte
Mid Byte
Low Byte
High Byte
Mid Byte
16
15 13 11 914 12 10 8
High Byte
Low Byte
High Byte
Low Byte
PRAF
PRAE
PRAF
PRAE
PRAF
PRAE
PRAF
PRAF
PRAE
PRAE
1st Cycle
2nd Cycle
3rd Cycle
4th Cycle
3rd Cycle
1st Cycle
2nd Cycle
6th Cycle
4th Cycle
5th Cycle
D/Q8 D/Q6 D/Q4 D/Q2 D/Q0D/Q7 D/Q5 D/Q3 D/Q1
D/Q8 D/Q6 D/Q4 D/Q2 D/Q0D/Q7 D/Q5 D/Q3 D/Q1
7 77
75316420
16
15 13 11 914 12 10 8
56 7 77
75316420
15 13 11 914 12 10 8
1718
D/Q9
56 7 77
75316420
15 13 11 914 12 10 8
D/Q9
56
16
15 13 11 914 12 10 8
7 77
75316420
16
15 13 11 914 12 10 8
1718
MAY 2002
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Q
TMIII Plus
3F3P1020A
FQV202113 · FQV202103 · FQV20293 · FQV20283 · FQV20273 · FQV20263
·
FQV20253· FQV20243
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Page 21 of 21
x10 to x10 Mode All Other Modes
# of Bits for Offset Registers # of Bits for Offset Registers
19 bits for FQV202113
18 bits for FQV202103
17 bits for FQV20293
16 bits for FQV20283
15 bits for FQV20273
14 bits for FQV20263
13 bits for FQV20253
12 bits for FQV20243
18 bits for FQV202113
17 bits for FQV202103
16 bits for FQV20293
15 bits for FQV20283
14 bits for FQV20273
13 bits for FQV20263
12 bits for FQV20253
11 bits for FQV20243
Note: Don’t Care applies to all unused bits Note: Don’t Care applies to all unused bits
Figure 7. Parallel Offset Write/Read Cycle Diagram
MAY 2002
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Q
TMIII Plus
3F3P1020A
FQV202113 · FQV202103 · FQV20293 · FQV20283 · FQV20273 · FQV20263
·
FQV20253· FQV20243
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Page 22 of 22
Data Width
FQV20293, FQV20283, FQV20273, FQV20263, FQV20253, FQV20243
Parallel Offset Write/Read Cycles for x20 Bus Width
Condtion Applies to: Write Cycle with x20 input Bus Width
and/or Read Cycle for x20 output Bus Width
Data Width
Non-Interspersed Parity
Interspersed Parity
PRAF
2nd Cycle
Non-Interspersed Parity
Interspersed Parity
PRAE1st Cycle
Data Width
FQV202113, FQV202103
Parallel Offset Write/Read Cycles for x20 Bus Width
Condtion Applies to: Write Cycle with x20 input Bus Width
and/or Read Cycle for x20 output Bus Width
Non-Interspersed Parity
Interspersed Parity
PRAE1st Cycle
16
16
17
17
Non-Interspersed Parity
Interspersed Parity
PRAE
2nd Cycle
3rd Cycle PRAF
Non-Interspersed Parity
Interspersed Parity
Non-Interspersed Parity
Interspersed Parity
4th Cycle PRAF
D/Q17 D/Q15 D/Q13 D/Q11 D/Q9D/Q16 D/Q14 D/Q12 D/Q10 D/Q8 D/Q6 D/Q4 D/Q2 D/Q0D/Q7 D/Q5 D/Q3 D/Q1
75316420
75316420
815 13 11 914 12 10
815 13 11 914 12 10
D/Q19 D/Q18
D/Q17 D/Q15 D/Q13 D/Q11 D/Q9D/Q16 D/Q14 D/Q12 D/Q10 D/Q8 D/Q6 D/Q4 D/Q2 D/Q0D/Q7 D/Q5 D/Q3 D/Q1
75316420
75316420
815 13 11 914 12 10
815 13 11 914 12 10
D/Q19 D/Q18
75316420
75316420
815 13 11 914 12 10
815 13 11 914 12 10
75316420
75316420
815 13 11 914 12 10
815 13 11 914 12 10
D/Q17 D/Q15 D/Q13 D/Q11 D/Q9D/Q16 D/Q14 D/Q12 D/Q10 D/Q8 D/Q6 D/Q4 D/Q2 D/Q0D/Q7 D/Q5 D/Q3 D/Q1
D/Q19 D/Q18
16
16
17
17
Figure 7. Parallel Offset Write/Read Cycles Diagram (Continued)
MAY 2002
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3F3P1020A
FQV202113 · FQV202103 · FQV20293 · FQV20283 · FQV20273 · FQV20263
·
FQV20253· FQV20243
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Page 23 of 23
FQV202113
BM1 = BM0 = x10 FULL PRAF HALF PRAE EMPTY
0 H H H L L
1 to y(1) H H H L H
(y+1) to 262,144 H H H H H
262,145 to [524,288-(x+1)] H H L H H
(524,288 -x) to 524,287 H L L H H
524,288 L L L H H
FQV202103 FQV202113
BM1 = BM0 =
x10 BM1 ≠
≠≠
≠ BM0 or BM1 = BM0 = x20 FULL PRAF HALF PRAE EMPTY
0 H H H L L
1 to y(1) H H H L H
(y+1) to 131,072 H H H H H
131,073 to [262,144-(x+1)] H H L H H
(262,144 -x) to 262,143 H L L H H
262,144 L L L H H
FQV20293 FQV202103
BM1 = BM0 =
x10 BM1 ≠
≠≠
≠ BM0 or BM1 = BM0 = x20 FULL PRAF HALF PRAE EMPTY
0 H H H L L
1 to y(1) H H H L H
(y+1) to 65,536 H H H H H
65,537 to [131,072-(x+1)] H H L H H
(131,072 -x) to 131,071 H L L H H
131,072 L L L H H
FQV20283 FQV20293
BM1 = BM0 =
x10 BM1 ≠
≠≠
≠ BM0 or BM1 = BM0 = x20 FULL PRAF HALF PRAE EMPTY
0 H H H L L
1 to y(1) H H H L H
(y+1) to 32,768 H H H H H
32,769 to [65,536-(x+1)] H H L H H
(65,536 -x) to 65,535 H L L H H
65,536 L L L H H
FQV20273 FQV20283
BM1 = BM0 =
x10 BM1 ≠
≠≠
≠ BM0 or BM1 = BM0 = x20 FULL PRAF HALF PRAE EMPTY
0 H H H L L
1 to y(1) H H H L H
(y+1) to 16,384 H H H H H
16,385 to [32,768-(x+1)] H H L H H
(32,768 -x) to 32,767 H L L H H
32,768 L L L H H
NOTES:
1. See Table 11 for values x, y.
Table 8. Status Flags (Standard Mode)
MAY 2002
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TMIII Plus
3F3P1020A
FQV202113 · FQV202103 · FQV20293 · FQV20283 · FQV20273 · FQV20263
·
FQV20253· FQV20243
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Page 24 of 24
FQV20263 FQV20273
BM1 = BM0 =
x10 BM1 ≠
≠≠
≠ BM0 or BM1 = BM0 = x20 FULL PRAF HALF PRAE EMPTY
0 H H H L L
1 to y(1) H H H L H
(y+1) to 8,192 H H H H H
8,193 to [16,384-(x+1)] H H L H H
(16,384 –x) to 16,383 H L L H H
16,384 L L L H H
FQV20253 FQV20263
BM1 = BM0 =
x10 BM1 ≠
≠≠
≠ BM0 or BM1 = BM0 = x20 FULL PRAF HALF PRAE EMPTY
0 H H H L L
1 to y(1) H H H L H
(y+1) to 4,096 H H H H H
4,097 to [8,192-(x+1)] H H L H H
(8,192 –x) to 8,191 H L L H H
8,192 L L L H H
FQV20243 FQV20253
BM1 = BM0 =
x10 BM1 ≠
≠≠
≠ BM0 or BM1 = BM0 = x20 FULL PRAF HALF PRAE EMPTY
0 H H H L L
1 to y(1) H H H L H
(y+1) to 2,048 H H H H H
2,049 to [4,096-(x+1)] H H L H H
(4,096 –x) to 4,095 H L L H H
4,096 L L L H H
FQV20243
BM1 ≠
≠≠
≠ BM0 or BM1 = BM0 = x20 FULL PRAF HALF PRAE EMPTY
0 H H H L L
1 to y(1) H H H L H
(y+1) to 1,024 H H H H H
1,025 to [2,048-(x+1)] H H L H H
(2,048–x) to 2,047 H L L H H
2,048 L L L H H
NOTES:
1. See Table 11 for values x, y.
Table 8. Status Flags (Standard Mode) (Continued)
MAY 2002
Flex
Q
TMIII Plus
3F3P1020A
FQV202113 · FQV202103 · FQV20293 · FQV20283 · FQV20273 · FQV20263
·
FQV20253· FQV20243
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Page 25 of 25
FQV202113
BM1 = BM0 = x10 DRDY PRAF HALF PRAE QRDY
0 L H
H L H
1 to y+1(1) L H
H L L
(y+2) to 262,145 L H H H L
262,146 to [524,289-(x+1)] L H L H L
(524,289-x) to 524,288 L L L H L
524,289 H L
L H L
FQV202103 FQV202113
BM1 = BM0 =
x10 BM1 ≠
≠≠
≠ BM0 or BM1 = BM0 = x20 FULL PRAF HALF PRAE EMPTY
0 L H
H L H
1 to y+1(1) L H
H L L
(y+2) to 131,073 L H H H L
131,074 to [262,145-(x+1)] L H L H L
(262,145-x) to 262,144 L L L H L
262,145 H L L H L
FQV20293 FQV202103
BM1 = BM0 =
x10 BM1 ≠
≠≠
≠ BM0 or BM1 = BM0 = x20 FULL PRAF HALF PRAE EMPTY
0 L H
H L H
1 to y+1(1) L H
H L L
(y+2) to 65,637 L H H H L
65,638 to [131,073-(x+1)] L H L H L
(131,073-x) to 131,072 L L L H L
131,073 H L L H L
FQV20283 FQV20293
BM1 = BM0 =
x10 BM1 ≠
≠≠
≠ BM0 or BM1 = BM0 = x20 DRDY PRAF HALF PRAE QRDY
0 L H
H L H
1 to y+1(1) L H
H L L
(y+2) to 32,769 L H H H L
32,770 to [65,537-(x+1)] L H L H L
(65,537 -x) to 65,536 L L L H L
65,537 H L
L H L
FQV20273 FQV20283
BM1 = BM0
= x10 BM1 ≠
≠≠
≠ BM0 or BM1 = BM0 = x20 DRDY PRAF HALF PRAE QRDY
0 L H
H L H
1 to y+1(1) L H
H L L
(y+2) to 16,385 L H H H L
16,386 to [32,769-(x+1)] L H L H L
(32,769-x) to 32,768 L L L H L
32,769 H L
L H L
NOTES:
1. See Table 11 for values x, y.
Table 9. Status Flags (FWFT Mode)
MAY 2002
Flex
Q
TMIII Plus
3F3P1020A
FQV202113 · FQV202103 · FQV20293 · FQV20283 · FQV20273 · FQV20263
·
FQV20253· FQV20243
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Page 26 of 26
FQV20263 FQV20273
BM1 = BM0 =
x10 BM1 ≠
≠≠
≠ BM0 or BM1 = BM0 = x20 DRDY PRAF HALF PRAE QRDY
0 L H
H L H
1 to y+1(1) L H
H L L
(y+2) to 8,193 L H H H L
8,194 to [16,385-(x+1)] L H L H L
(16,385 -x) to 16,384 L L L H L
16,385 H L
L H L
FQV20253 FQV20263
BM1 = BM0 =
x10 BM1 ≠
≠≠
≠ BM0 or BM1 = BM0 = x20 FULL PRAF HALF PRAE EMPTY
0 L H
H L H
1 to y+1(1) L H
H L L
(y+2) to 4,097 L H H H L
4,098 to [8,193-(x+1)] L H L H L
(8,193 -x) to 8,192 L L L H L
8,193 H L L H L
FQV20243 FQV20253
BM1 = BM0 =
x10 BM1 ≠
≠≠
≠ BM0 or BM1 = BM0 = x20 FULL PRAF HALF PRAE EMPTY
0 L H
H L H
1 to y+1(1) L H
H L L
(y+2) to 2,049 L H H H L
2,050 to [4,097-(x+1)] L H L H L
(4,097-x) to 4,096 L L L H L
4,097 H L L H L
FQV20243
BM1 ≠
≠≠
≠ BM0 or BM1 = BM0 = x20 DRDY PRAF HALF PRAE QRDY
0 L H
H L H
1 to y+1(1) L H
H L L
(y+2) to 1,025 L H H H L
1,026 to [2,049 -(x+1)] L H L H L
(2,049 -x) to 2,048 L L L H L
2,049 H L
L H L
NOTES:
1. See Table 11 for values x, y.
Table 9. Status Flags (FWFT Mode) (Continued)
MAY 2002
Flex
Q
TMIII Plus
3F3P1020A
FQV202113 · FQV202103 · FQV20293 · FQV20283 · FQV20273 · FQV20263
·
FQV20253· FQV20243
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Page 27 of 27
ES BM1 BM0 I/O Width D/Q19 - 10 D/Q9 – 0 Sequence
0 0 0 I 20 Byte 2 Byte 1 1st Write
O 20 Byte 2 Byte 1 1st Read
0 0 1 I 20 Byte 2 Byte 1 1st Write
O 10 X Byte 2 1st Read
X Byte 1 2nd Read
0 1 0 I 10 X Byte 2 1st Write
X Byte 1 2nd Write
O 20 Byte 2 Byte 1 1st Read
X 1 1 I 10 X Byte 2 1st Write
X Byte 1 2nd Write
O 10 X Byte 2 1st Read
X Byte 1 2nd Read
1 0 0 I 20 Byte 2 Byte 1 1st Write
O 20 Byte 1 Byte 2 1st Read
1 0 1 I 20 Byte 2 Byte 1 1st Write
O 10 X Byte 1 1st Read
X Byte 2 2nd Read
1 1 0 I 10 X Byte 2 1st Write
X Byte 1 2nd Write
O 20 Byte 1 Byte 2 1st Read
Table 10. Bus-Matching Table
MAY 2002
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Q
TMIII Plus
3F3P1020A
FQV202113 · FQV202103 · FQV20293 · FQV20283 · FQV20273 · FQV20263
·
FQV20253· FQV20243
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Page 28 of 28
FQV20273
FQV20263
FQV20253
FQV20243
LOAD PFS0 PFS1
Offsets x, y
0 0 0 127
0 0 1 511
0 1 0 255
0 1 1 63
1 0 0 1,023
1 0 1 31
1 1 0 15
1 1 1 7
FQV20283
Offsets x, y
FQV202113
FQV202103
FQV20293
LOAD PFS0 PFS1
All Other
Modes
x10 to x10
Mode Offsets x, y
0 0 0 127 127 127
0 0 1 511 16,383 16,383
0 1 0 255 8,191 8,191
0 1 1 63 4,095 4,095
1 0 0 1,023 1,023 1,023
1 0 1 31 2,047 2,047
1 1 0 15 511 511
1 1 1 7 255 255
NOTES:
1. x = PRAF offset, y = PRAE offset.
Table 11. Default Programmable Flag Offsets
MAY 2002
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Q
TMIII Plus
3F3P1020A
FQV202113 · FQV202103 · FQV20293 · FQV20283 · FQV20273 · FQV20263
·
FQV20253· FQV20243
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Page 29 of 29
Timing Diagrams
tRST
tRSTR
tRSTR
tRSTR
tRSTS
FWFT/SDI
tRSTR
tRSTS
tRSTS
PFS1/PFS0
tRSTS
ES
tRSTS
RETZL
tRSTS
SFM
tRSTS
IPAR
Q19 - 0
tRSTF
tRSTF
tRSTF
tRSTF
tRSTF
tRSTS
tRSTS
tRSTS
tRSTS
MRST
REN
WEN
LOAD
RET
SDEN
/EMPTY QRDY
PRAE
PRAF HALF/
/
FULL DRDY
If FW FT = 0, = 1
FULL
If FW FT = 1, = 0
DRDY
If FW FT = 1, = 1QRDY
If FW FT = 0, = 0EMPTY
= 0
OE
= 1
OE
tRSTS
BM1/BM0
Diagram 1. Master Reset Timing
MAY 2002
Flex
Q
TMIII Plus
3F3P1020A
FQV202113 · FQV202103 · FQV20293 · FQV20283 · FQV20273 · FQV20263
·
FQV20253· FQV20243
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Page 30 of 30
tRST
tRSTR
tRSTR
tRSTF
tRSTF
tRSTF
tRSTF
tRSTF
tRSTS
tRSTS
tRSTS
tRSTS
If FWFT = 0, = 1FULL
If FWFT = 1, = 0
DRDY
If FWFT = 1, = 1QRDY
If FWFT = 0, = 0
EMPTY
= 0
OE
= 1
OE
Q19 - 0
RET
SDEN
/EMPTY QRDY
PRAE
PRAF HALF/
/
FULL DRDY
WEN
REN
PRST
Diagram 2. Partial Reset Timing
MAY 2002
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TMIII Plus
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FQV202113 · FQV202103 · FQV20293 · FQV20283 · FQV20273 · FQV20263
·
FQV20253· FQV20243
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Page 31 of 31
DW
i + 1
DW
i
No
Write
No
Write
No
Write
t
WCLK
t
WCLKH
t
WCLKL
t
FULL
t
FULL
t
FULL
t
FULL
t
DS
t
DH
t
DS
t
DH
t
SKEW1
t
ENS
t
ENH
t
ENS
t
ENH
t
A
t
A
Next Data ReadData ReadOutput Register Data
WCLK
D
19 - 0
RCLK
Q
19 - 0
FULL
REN
WEN
12 12
t
SKEW1
NOTES:
1. If the time between a rising edge of RCLK to the rising edge of WCLK is greater or equal than tSKEW1, FULL
___________
will go high (after one WCLK cycle plus tFULL). If tSKEW1 is not met, then FULL
__________
will assert 1 or more
WCLK cycles.
2. LOAD
___________
= High, OE
______
= Low.
Diagram 3. Write Cycle and Full Flag Timing (Standard Mode)
MAY 2002
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Q
TMIII Plus
3F3P1020A
FQV202113 · FQV202103 · FQV20293 · FQV20283 · FQV20273 · FQV20263
·
FQV20253· FQV20243
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Page 32 of 32
DW
1
DW
2
DW
1
Last Word Last Word DW
2
t
RCLK
t
RCLKH
t
RCLKL
t
ENH
t
ENS
t
ENH
t
ENS
t
EMPTY
t
EMPTY
t
EMPTY
t
A
t
A
t
OEN
t
OHZ
t
OLZ
t
OLZ
t
SKEW1
t
ENS
t
ENH
t
ENS
t
ENH
t
ENH
t
ENS
t
DS
t
DH
t
DS
t
DH
t
A
RCLK
Q
19 - 0
WCLK
D
19 - 0
OE
WEN
EMPTY
REN
12
NOTES:
1. If the time between a rising edge of WCLK to the rising edge of RCLK is greater or equal than tSKEW11, EMPTY
______________
will go high (after RCLK cycle plus tEMPTY). If tSKEW1 is not met, then EMPTY
______________
will assert 1 or more
RCLK cycles.
2. LOAD
___________
= High.
3. First word latency: tSKEW1 + tEMPTY + 1 * tRCLK.
Diagram 4. Read Cycle, Empty Flag and First Data Word Latency Timing (Standard Mode)
MAY 2002
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TMIII Plus
3F3P1020A
FQV202113 · FQV202103 · FQV20293 · FQV20283 · FQV20273 · FQV20263
·
FQV20253· FQV20243
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Page 33 of 33
DW
[y+2]
DW
D
DW
[D-1]
DW
[D-x+2]
DW
[D-x+2]
DW
[D-x+1]
DW
[D-x]
DW
[D-x-3]
DW
[(D-1)/2+3]
DW
[(D-1)/2+2]
DW
[(D-1)/2+1]
DW
[y+4]
DW
[y+3]
DW
4
DW
3
DW
2
DW
1
312 12
WCLK
D
19 - 0
RCLK
Q
19 - 0
QRDY
PRAE
HALF
PRAF
DRDY
t
ENS
t
DH
t
DS
t
DS
t
DS
t
DS
t
ENH
t
SKEW1
t
SKEW2
t
FULL
t
HALF
t
A
t
EMPTY
Output Register Data DW
1
WEN
REN
t
PRAES
21
t
PRAFS
NOTES:
1. If the time between a rising edge of WCLK to the rising edge of RCLK is greater or equal than tSKEW1, QRDY
____________
will go low (after two RCLK cycle plus tEMPTY). If tSKEW1 is not met, then QRDY
____________
will assert 1 or more
RCLK cycles.
2. If the time between a rising edge of WCLK to the rising edge of RCLK is greater or equal than tSKEW2, PRAE
___________
will go high (after one RCLK cycle plus tPRAES). If tSKEW2 is not met, then PRAE
___________
will assert 1 or more
RCLK cycles.
3. LOAD
___________
= High, OE
______
= Low.
4. y = PRAE
___________
offset, x = PRAF
___________
offset.
5. D = maximum queue depth. Please refer to Table 7 for Depth.
6. First word latency: tSKEW1 + tEMPTY + 2 * tRCLK
Diagram 5. Write Timing (FWFT Mode)
MAY 2002
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Q
TMIII Plus
3F3P1020A
FQV202113 · FQV202103 · FQV20293 · FQV20283 · FQV20273 · FQV20263
·
FQV20253· FQV20243
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Page 34 of 34
DW
i DWi+1 DW
1 DW2
RCLK
Q
19 - 0
WCLK
t
ENS t
ENH t
RETS
t
A tA
tENS tENH
tA
tSKEW2
t
RETS
t
ENS tENH
tEMPTY
tHALF
tEMPTY
tPRAES
tPRAFS
REN
WEN
RET
EMPTY
PRAE
HALF
PRAF
1 2
1 2
NOTES:
1. Upon completion of retransmit setup, a read operation can begin only after EMPTY returns high.
2. OE = Low.
3. DWi = Words written to the queue after MRST . Where i = 1,2,3… depth.
4. Upon reset completion, there must be more than two words written to the queue for a retransmit setup to be valid.
Diagram 7. Retransmit Timing (Standard Mode)
MAY 2002
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Q
TMIII Plus
3F3P1020A
FQV202113 · FQV202103 · FQV20293 · FQV20283 · FQV20273 · FQV20263
·
FQV20253· FQV20243
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Page 35 of 35
DW3
DW1
DWiDWi+1 DW2
RCLK
Q 19 - 0
WCLK
tENS tENH tRETS
tA
tSKEW2
tRETS
tENS tENH
tEMPTY
tHALF
tEMPTY
tPRAES
tPRAFS
1
tENH
tA
23
DW4
tAtA
tENS
PRAF
HALF
PRAE
QRDY
RET
WEN
REN
12
4
NOTES:
1. Upon completion of retransmit setup, a read operation can begin only after QRDY returns low.
2. OE = Low.
3. DWi = Words written to the queue after MRST . Where i = 1,2,3… depth.
4. Upon reset completion, there must be more than two words written to the queue for a retransmit setup to be valid.
5. Please refer to Table 7 for Depth.
Diagram 8. Retransmit Timing (FWFT Mode)
MAY 2002
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TMIII Plus
3F3P1020A
FQV202113 · FQV202103 · FQV20293 · FQV20283 · FQV20273 · FQV20263
·
FQV20253· FQV20243
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Page 36 of 36
RCLK
Q 19 - 0
WCLK
DWiDWi+1 DW1DW2DW3DW4
tRETS
tENS tENH
tSKEW2
tAtAtAtAtA
tENS tENH
tPRAES
tHALF
tPRAFS
WEN
REN
RET
EMPTY
PRAE
HALF
PRAF
12
1
3
2
NOTES:
1. If the part is empty at the point of retransmit, the Empty Flag ( EMPTY ) will be updated based on RCLK (Retransmit Clock cycle). Valid data will
appear on the output.
2. OE = Low; enables data to be read on outputs Q19 – 0.
3. DW1= first word written to the queue after Master Reset; DW2= second word written to the queue after Master Reset.
4. No more than D-2 may be written to the queue between reset (Master or Partial) and retransmit setup. Therefore, FULL will be high throughout the
retransmit setup procedure. Please refer to Table 7 for Depth.
5. There must be at least two words written to zero latency retransmit from the queue before a retransmit operation can be invoked.
6. RETZL is set Low during MRST .
Diagram 9. Zero Latency Retransmit Timing (Standard Mode)
MAY 2002
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TMIII Plus
3F3P1020A
FQV202113 · FQV202103 · FQV20293 · FQV20283 · FQV20273 · FQV20263
·
FQV20253· FQV20243
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Page 37 of 37
RCLK
Q 19 - 0
WCLK
DWiDW i+1 DW1DW2DW3DW4
tRETS
tENS tENH
tSKEW2
tAtAtAtAtA
tENS tENH
tPRAES
tHALF
tPRAFS
DW5
tA
PRAF
HALF
PRAE
QRDY
RET
WEN
REN
12345
12
NOTES:
1. If the part is empty at the point of retransmit, the output ready flag ( QRDY ) will be updated based on RCLK (Retransmit Clock cycle). Valid data will
appear on the output.
2. No more than D-2 words may be written to the queue between reset (Master or Partial) and retransmit setup. Therefore, DRDY will be low throughout
the retransmit setup procedure. Please refer to Table 7 for Depth.
3. OE = Low.
4. DW1, DW2, DW3 = first, second and third words written to the queue after Master Reset.
5. There must be at least two words written to the queue before a retransmit operation can be invoked.
6. RETZL is set low during MRST .
Diagram 10. Zero Latency Retransmit Timing (FWFT Mode)
MAY 2002
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TMIII Plus
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FQV202113 · FQV202103 · FQV20293 · FQV20283 · FQV20273 · FQV20263
·
FQV20253· FQV20243
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Page 38 of 38
WCLK
SDI
tENHtENS
tLOADHtLOADS
tDS
Offset Offset
tENH
tLOADH
tDH
BIT 0 BIT MSB BIT 0 BIT MSB
LOAD
SDEN
PRAE PRAF
*Refer to Table 12
Diagram 11. Serial Loading of Programmable Flag Registers (Standard and FWFT Mode)
FQV202113 FQV202103 FQV20293 FQV20283 FQV20273 FQV20263 FQV20253 FQV20243
MSB for x10
to x10 18 17 16 15 14 13 12 11
MSB for All
Other Modes 17 16 15 14 13 12 11 10
Table 12. Reference Table for Diagram 11
MAY 2002
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TMIII Plus
3F3P1020A
FQV202113 · FQV202103 · FQV20293 · FQV20283 · FQV20273 · FQV20263
·
FQV20253· FQV20243
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Page 39 of 39
tLOADS
tENS
tLOADH
tENH
tLOADH
tENH
tWCLKH tWCLKL
tWCLK
WCLK
D 19 - 0
PRAE offset
(Low Byte)
PRAF offset
(High Byte)
PRAF offset
(Low Byte)
PRAE offset
(High Byte)
tDS tDH tDS tDH tDS tDH tDS tDH
LOAD
WEN
Diagram 12. Parallel Loading of Programmable Flag Registers (Standard and FWFT Mode)
tLOADS
tENS
tLOADH
tENH
tLOADH
tENH
tRCLKH tRCLKL
tRCLK
RCLK
Q 19 - 0 Data Output Register
tA
PRAE offset
(Low Byte)
PRAE offset
(High Byte)
PRAF offset
(Low Byte)
PRAF offset
(High Byte)
tAtAtA
LOAD
REN
Diagram 13. Parallel Read of Programmable Flag Registers (Standard and FWFT Mode)
MAY 2002
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TMIII Plus
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FQV202113 · FQV202103 · FQV20293 · FQV20283 · FQV20273 · FQV20263
·
FQV20253· FQV20243
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Page 40 of 40
tWC LKH tWCLKL
tENHtENS
tSKEW2
tENS tENH
tPRAFS tPRAFS
12 12
D - ( x + 1 ) words in Queue D - x words in Queue D - ( x + 1 ) words
in Queue
WEN
PRAF
REN
WCLK
RCLK
NOTES:
1. x = PRAF
___________
offset.
2. D = maximum queue depth. Please refer to Table 7 for Depth.
3. If the time between a rising edge of RCLK to the rising edge of WCLK is greater or equal than tSKEW2, PRAF
___________
will go high (after on WCLK cycle plus
tPRAFS). If tSKEW2 is not met, then PRAF
___________
will assert 1 or more WCLK cycles.
4. PRAF
___________
synchronizes to the rising edge of WCLK only.
Diagram 14. Synchronous Programmable Almost-Full Flag Timing (Standard and FWFT Mode)
tWCLKH tWCLKL
tWCLKLtWCLKH
tENS tENH
y words in Queue(2) ; y+1 words in Queue(3) y+1 words in Queue(2) ; y+2 words in Queue(3)
y words in Queue(2) ;
y+1 words in Queue(3)
tPRAEStPRAEStSKEW2
12 1 2
WEN
PRAE
WCLK
RCLK
REN
NOTES:
1. y = PRAE
___________
offset.
2. For Standard Mode.
3. For FWFT Mode.
4. If the time between a rising edge of WCLK to the rising edge of RCLK is greater or equal than tSKEW2, PRAE
___________
will go high (after one RCLK cycle plus
tPRAES). If tSKEW2 is not met, then PRAE
___________
will assert 1 or more RCLK cycles.
5. PRAE
___________
synchronizes to the rising edge of RCLK only.
Diagram 15. Synchronous Programmable Almost-Empty Flag Timing (Standard and FWFT Mode)
MAY 2002
Flex
Q
TMIII Plus
3F3P1020A
FQV202113 · FQV202103 · FQV20293 · FQV20283 · FQV20273 · FQV20263
·
FQV20253· FQV20243
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Page 41 of 41
tWCLKH tWCLKL
tENS tENH
tPRAFA
tPRAFA
tENS
D - ( x + 1) words in Queue
D - x words in
Queue D - ( x + 1) words in Queue
WCLK
WEN
RCLK
REN
PRAF
tENH
NOTES:
1. x = PRAF
___________
offset.
2. D = maximum queue depth. Please refer to Table 7 for Depth.
3. PRAF
___________
is asserted to low on WCLK transition and reset to high on RCLK transition.
4. Select this mode by setting SFM low during Master Reset.
Diagram 16. Asynchronous Programmable Almost-Full Flag Timing (Standard and FWFT Mode)
tENH
tWCLKH tWCLKL
tENS tENH
tPRAEA
tPRAEA
tENS
y words in Queue(2); y+1 words in Queue(3) y+1 words in
Queue(2); y+2
words in Queue (3)
y words in Queue(2); y+1 words in Queue(3)
WCLK
WEN
RCLK
REN
PRAE
NOTES:
1. y = PRAE
___________
offset.
2. For Standard Mode.
3. For FWFT Mode.
4. PRAE
___________
is asserted to low on RCLK transition and reset to high on WCLK transition.
5. Select this mode by setting SFM low during Master Reset.
Diagram 17. Asynchronous Programmable Almost-Empty Flag Timing (Standard and FWFT Mode)
MAY 2002
Flex
Q
TMIII Plus
3F3P1020A
FQV202113 · FQV202103 · FQV20293 · FQV20283 · FQV20273 · FQV20263
·
FQV20253· FQV20243
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Page 42 of 42
D/2 words in Queue(1); [(D+1)/2] words in Queue(2)
D/2 + 1 words in
Queue(1);
[(D+1)/2 + 1] words
in Queue(2)
D/2 words in Queue(1);
[(D+1)/2] words in Queue(2)
tWCLKH tWCLKL
tENS tENH
tHALF
tHALF
tENS
WCLK
RCLK
WEN
HALF
REN
tENH
NOTES:
1. For Standard Mode.
2. For FWFT Mode.
3. Please refer to Table 7 for Depth.
Diagram 18. Half-Full Flag Timing (Standard and FWFT Mode)
MAY 2002
Flex
Q
TMIII Plus
3F3P1020A
FQV202113 · FQV202103 · FQV20293 · FQV20283 · FQV20273 · FQV20263
·
FQV20253· FQV20243
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Page 43 of 43
Order Information:
HBA
Device Family
Device Type
Power
Speed (ns) *
Package**
Temperature Range
XX XXXXX X XX XX X
FQ V202113 (524,288 x 10) Low 6 – 166 MHz PF Blank – Commercial (0°C to 70°C)
(262,144 x 20) 7-5 – 133 MHz I – Industrial (-40° to 85°C)
V202103 (262,144 x 10) 10 – 100 MHz
(131,072 x 20)
V20293 (131,072 x 10)
(65,536 x 20)
V20283 (65,536 x 10)
(32,768 x 20)
V20273 (32,768 x 10)
(16,384 x 20)
V20263 (16,384 x 10)
(8,192 x 20)
V20253 (8,192 x 10)
(4,096 x 20)
V20243 (4,096 x 10)
(2,048 x 20)
*Speed – 6ns available only in Commercial temp (0°C to 70°C)
**Package – 144 - pin Plastic Thin Quad Flat Pack (TQFP)
Example:
FQV20283L6PF (64k x 10, 6ns, Commercial temp)
FQV20273L10PFI (32k x 10, 10ns, Industrial temp)
USA
Taiwan
2107 North First Street, Suite 415
San Jose, CA 95131, USA
www.hba.com
Tel: 408.453.8885
Fax: 408.453.8886
No. 81, Suite 8F-9, Shui-Lee Rd.
Hsinchu, Taiwan, R.O.C.
www.hba.com
Tel: 886.3.516.9119
Fax: 886.3.516.9118
