© Semiconductor Components Industries, LLC, 2015
May, 2020 − Rev. 3
1Publication Order Number:
FAN53200/D
TinyBuck) Regulator,
Digitally Programmable,
5 A, 2.4 MHz
FAN53200
Descriptions
The FAN53200 is a step−down switching voltage regulator that
delivers a digitally programmable output from an input voltage supply
of 2.5 V to 5.5 V. The output voltage is programmed through an I2C
interface capable of operating up to 3.4 Mbps.
Using a proprietary architecture with synchronous rectification, the
FAN53200 is capable of delivering 5 A continuously at over 80%
efficiency, while maintaining over 80% efficiency at load currents as
low as 10 mA. The regulator operates at a nominal fixed frequency of
2.4 MHz, which reduces the value of the external components.
Additional output capacitance can be added to improve regulation
during load transients without affecting stability. Inductance up to
1.2 mH may be used with additional output capacitance.
At moderate and light loads, Pulse Frequency Modulation (PFM) is
used to operate in Power−Save Mode with a typical quiescent current
of 60 mA. At higher loads, the system automatically switches to
fixed−frequency control, operating at 2.4 MHz. In Shutdown Mode,
the supply current drops to 0.1 mA, reducing power consumption. PFM
Mode can be disabled if constant frequency is desired. The FAN53200
is available in a 20−bump, 1.6 x 2.0 mm, WLCSP.
Features
•Quiescent Current in PFM Mode: 60 mA (Typical)
•Digitally Programmable Output Voltage:
♦0.6 −1.3875 V in 12.5 mV Steps
•Best−in−Class Load Transient
•Continuous Output Current Capability: 5 A
•2.5 V to 5.5 V Input Voltage Range
•Programmable Slew Rate for Voltage Transitions
•Fixed−Frequency Operation: 2.4 MHz
•I2C−Compatible Interface Up to 3.4 Mbps
•Internal Soft−Start
•Input Under−Voltage Lockout (UVLO)
•Thermal Shutdown and Overload Protection
•20−Bump Wafer−Level Chip Scale Package (WLCSP)
Applications
•Graphic, and DSP Processors
ARMt, Kraitt, OMAPt, NovaThort, ARMADAt
•Hard Disk Drives
•Tablets, Netbooks, Ultra−Mobile PCs
•Smart Phones
•Gaming Devices
ORDERING INFORMATION
Part Number
Power−Up Defaults I2C Slave
Address Device ID
Device
Marking Package
VSEL0 VSEL1
FAN53200UC35X OFF 1.15 V C0 0000 B9 WLCSP−20
FAN53200UC44X 1.15V 0.85 V C0 0000 CD WLCSP−20
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WLCSP−20
CASE 567SH
1
Figure 1. Typical Application
SW
COUT
L1
VIN
GND
VOUT
CIN
AGND
Core
Processor
(System Load)
GND
VDD
VSEL
SCL
SDA
EN
FAN53200
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Pin Configuration
Figure 2. Pin Assignment (Top View)
Table 1. PIN DESCRIPTIONS
Pin # Name Description
A1 VSEL Voltage Select. When this pin is LOW, VOUT is set by the VSEL0 register. When this pin is HIGH, VOUT is set by
the VSEL1 register.
A2 EN Enable. The device is in Shutdown Mode when this pin is LOW. All registers go to default values when EN pin is
LOW.
A3 SCL I
2
C Serial Clock
A4 VOUT VOUT. Sense pin for VOUT. Connect to COUT
.
B1 SDA I
2
C Serial Data
B2, B3,
C1 – C4
GND Ground. Low−side MOSFET is referenced to this pin. CIN and COUT should be returned with a minimal path to
these pins.
B4 AGND Analog Ground. All signals are referenced to this pin. Avoid routing high dV/dt AC currents through this pin.
D1, D2,
E1, E2
VIN Power Input Voltage. Connect to the input power source. Connect to CIN with minimal path.
D3, D4,
E3, E4
SW Switching Node. Connect to the inductor.
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Table 2. ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Min Max Unit
VIN Voltage on SW, VIN Pins IC Not Switching −0.3 7.0 V
IC Switching −0.3 6.5
Voltage on All Other Pins IC Not Switching −0.3 VIN (Note 1) V
VOUT Voltage on VOUT Pin −0.3 3.0 V
VINOV_SLEW Maximum Slew Rate of VIN > 6.5 V, PWM Switching 100 V/ms
ESD Electrostatic Discharge Protection
Level
Human Body Model per JESD22−A114 2000 V
Charged Device Model per JESD22−C101 1000
TJJunction Temperature −40 +150 °C
TSTG Storage Temperature −65 +150 °C
TLLead Soldering Temperature, 10 Seconds +260 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Lesser of 7.0 V or VIN + 0.3 V
Table 3. RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Typ Max Unit
VIN Supply Voltage Range 2.5 5.5 V
IOUT Output Current 0 5 A
L Inductor 0.33 mH
CIN Input Capacitor 10 mF
COUT Output Capacitor 44 mF
TAOperating Ambient Temperature −40 +85 °C
TJOperating Junction Temperature −40 +125 °C
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
Table 4. THERMAL PROPERTIES
Symbol Parameter Min Typ Max Unit
qJA Junction−to−Ambient Thermal Resistance (Note 2) 38 °C/W
2. See Thermal Considerations in the Application Information section.
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Table 5. ELECTRICAL CHARACTERISTICS Minimum and maximum values are at VIN = 2.5 V to 5.5 V, TA = −40°C to +85°C,
unless otherwise noted. Typical values are at TA = 25°C, VIN = 5 V, and EN = HIGH.
Symbol Parameter Condition Min Typ Max Unit
POWER SUPPLIES
IQQuiescent Current ILOAD = 0 60 mA
ISD H/W Shutdown Supply Current EN = GND 0.1 5.0 mA
S/W Shutdown Supply Current EN = VIN, BUCK_ENx = 0 41 75 mA
VUVLO Under−Voltage Lockout Threshold VIN Rising 2.35 2.45 V
VUVHYST Under−Voltage Lockout Hysteresis 350 mV
EN, VSEL, SDA, SCL
VIH high−Level Input Voltage 1.1 V
VIL low−Level Input Voltage 0.4 V
VLHYST Logic Input Hysteresis Voltage 160 mV
IIN Input Bias Current Input Tied to GND or VIN 0.01 1.00 mA
PGOOD
IOUTL PGOOD Pull−Down Current 1 mA
IOUTH PGOOD HIGH Leakage Current 0.01 1.00 mA
VOUT REGULATION
VREG VOUT DC Accuracy IOUT(DC) = 0, Forced PWM, VOUT = VSEL1
Default Value, 2.5 V ≤ VIN ≤ 5.5 V
−1.5 1.5 %
IOUT(DC) = 0 to 5 A, VOUT = VSEL1, Default
Value, Auto PFM/PWM, 2.5 V ≤ VIN ≤ 4.5 V
−2.0 4.0 %
IOUT(DC) = 0 to 5 A, VOUT = VSEL1, Default
Value, Auto PFM/PWM, 2.5 V ≤ VIN ≤ 5.5 V
−3.0 5.0 %
POWER SWITCH AND PROTECTION
ILIMPK P−MOS Peak Current Limit Open Loop 6.3 7.4 8.5 A
VSDWN Input OVP Shutdown Rising Threshold 6.15 V
Falling Threshold 5.50 5.85 V
FREQUENCY CONTROL
fSW Oscillator Frequency 2.05 2.40 2.75 MHz
ROFF VOUT Pull−Down Resistance EN = 0 or VIN < VUVLO 160 W
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
Table 6. SYSTEM CHARACTERISTICS
Symbol Parameter Min Typ Max Unit
DVOUT_LOAD Load Regulation IOUT = 1 A to 5 A 0.2 mV/A
DVOUT_LINE Line Regulation 3.6 V ≤ VIN ≤ 4.0 V, IOUT = 3 A −0.5 mV/V
VOUT_RIPPLE Ripple Voltage IOUT = 100 mA, PFM Mode 16 mV
IOUT = 2000 mA, PWM Mode 3
ηEfficiency VOUT = 1.15 V, IOUT = 100 mA 87 %
VOUT = 1.15 V, IOUT = 500 mA 88
VOUT = 1.15 V, IOUT = 2 A 88
TSS Soft−Start EN High to 95% of VOUT Target (1.15 V) RLOAD = 50 W340 ms
DVOUT_LOAD_TRAN Load Transient IOUT = 0.1 A ⇔ 1.2 A, TR = TF = 100 ns ±20 mV
DVOUT_LINE_TRAN Line Transient VIN = 3.0 V ⇔ 3.6 V, TR = TF = 10 ms, IOUT = 500 mA ±20 mV
NOTE: The table above is verified by design and bench test while using the following external components: L = 0.33 mH,
DFE252012F−R33M (TOKO), CIN = 10 mF, C2012X5R1A106M (TDK), COUT = 2 x 22 mF, C2012X5R0J226M (TDK).
These parameters are not tested in production. Minimum and maximum values are at VIN = 2.5 V to 5.5 V, VEN = 1.8 V, TA =
−40°C to +85°C; circuit of Figure 1, unless otherwise noted. Typical values are at TA = 25°C, VIN = 3.6 V, VOUT = 1.15 V, VEN =
1.8 V, Auto PFM Mode.
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Typical Characteristics
Unless otherwise specified, VIN = 3.6 V, VOUT = 1.15 V, VEN = 1.8 V, Auto PFM Mode, TA = 25°C; circuit and components according to Figure 1.
Figure 3. Efficiency vs. Load Current and Input
Voltage
Figure 4. Output Regulation vs. Load Current
and Input Voltage
Figure 5. Output Regulation vs. Load Current,
Over−Temperature
Figure 6. PFM Entry / Exit Level vs. Input
Voltage
Figure 7. Output Ripple vs. Load Current Figure 8. Frequency vs. Load Current
74%
76%
78%
80%
82%
84%
86%
88%
90%
92%
94%
0 1000 2000 3000 4000 5000
Load Current (mA)
2.7 VIN
3.6 VIN
5.0 VIN
0
5
10
15
20
25
0 1000 2000 3000
4000
5000
Load Current (mA)
2.7 VIN
3.6 VIN
5.0 VIN
0
5
10
15
20
25
30
35
40
0 1000 2000 3000 4000 5000
Load Current (mA)
−40C
+25C
+85C
200
400
600
800
1,000
1,200
2.5 3.0 3.5 4.0 4.5 5.0 5.5
Input Voltage (V)
PFM Exit
PFM Enter
0
5
10
15
20
25
0 1000 2000 3000 4000 5000
Load Current (mA)
3.6VIN,Auto
3.6VIN,PWM
5.0VIN,Auto
5.0VIN,PWM
0
500
1,000
1,500
2,000
2,500
3,000
0 1000 2000 3000 4000 5000
Load Current (mA)
3.6VIN,Auto
5.0VIN,Auto
Efficiency
VOUT Shift (mV)
VOUT Shift (mV)
Load Current (mA)
Switching Frequency (KHz)
Output Ripple (mVpp)
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Typical Characteristics
Unless otherwise specified, VIN = 3.6 V, VOUT = 1.15 V, VEN = 1.8 V, Auto PFM Mode, TA = 25°C; circuit and components according to Figure 1.
Figure 9. Quiescent Current vs. Input Voltage,
Over−Temperature
Figure 10. Shutdown Current vs. Input
Voltage, Over−Temperature
Figure 11. Load Transient, IOUT = 0.1 A @
1.2 A, Auto PFM Mode, TR = TF = 100 ns
Figure 12. Line Transient, VIN = 3.0 V @ 3.6 V,
TR = TF = 10 ms, IOUT = 500 mA
Figure 13. Startup, Rload = 50 W
20
30
40
50
60
70
80
2.5 3.0 3.5 4.0 4.5 5.0 5.5
Input Supply Voltage (V)
−40C
+25C
+85C
0
10
20
30
40
50
60
2.5 3.0 3.5 4.0 4.5 5.0 5.5
Input Voltage (V)
EN_BUCK=0, −40C
EN_BUCK=0, +25C
EN_BUCK=0, +85C
EN=0, +25C
Input Supply Current (mA)
Input Current (mA)
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Operation Description
The FAN53200 is a step−down switching voltage
regulator that delivers a programmable output voltage from
an input voltage supply of 2.5 V to 5.5 V. Using a proprietary
architecture with synchronous rectification, the FAN53200
is capable of delivering 5 A at over 80% efficiency. The
regulator operates at a nominal frequency of 2.4 MHz at full
load, which reduces the value of the external components to
330 nH for the output inductor and 44 mF for the output
capacitor. High efficiency is maintained at light load with
single−pulse PFM.
The FAN53200 integrates an I2C−compatible interface,
allowing transfers up to 3.4 Mbps. This communication
interface can be used to:
•Dynamically re−program the output voltage in 12.5 mV
steps;
•Reprogram the mode to enable or disable PFM;
•Control voltage transition slew rate; or
•Enable / disable the regulator.
Control Scheme
The FAN53200 uses a proprietary non−linear, fixed−
frequency PWM modulator to deliver a fast load transient
response, while maintaining a constant switching frequency
over a wide range of operating conditions. The regulator
performance is independent of the output capacitor ESR,
allowing for the use of ceramic output capacitors. Although
this type of operation normally results in a switching frequency
that varies with input voltage and load current, an internal
frequency loop holds the switching frequency constant over
a large range of input voltages and load currents.
For very light loads, the FAN53200 operates in
Discontinuous Conduction Mode (DCM) single−pulse
PFM, which produces low output ripple compared with
other PFM architectures. Transition between PWM and
PFM is relatively seamless, providing a smooth transition
between DCM and Continuous Conduction Mode (CCM).
PFM can be disabled by programming the MODE bit
HIGH in the VSEL registers.
Enable and Soft−Start
When the EN pin is LOW; the IC is shut down, all internal
circuits are off, and the part draws very little current. In this
state, I2C cannot be written to or read from. All registers are
reset to default values when EN pin is LOW.
When the OUTPUT_DISCHARGE bit in the CONTROL
register is enabled (logic HIGH) and the EN pin is LOW or
the BUCK_ENx bit is LOW, a load is connected from
VOUT to GND to discharge the output capacitors.
Raising EN while the BUCK_ENx bit is HIGH activates
the part and begins the soft−start cycle. During soft−start, the
modulator’s internal reference is ramped slowly to minimize
surge currents on the input and prevent overshoot of the
output voltage. Synchronous rectification is inhibited
during soft−start, allowing the IC to start into a pre−charged
capacitive load.
If large output capacitance values are used, the regulator
may fail to start. Maximum COUT capacitance for
successfully starting with a heavy constant−current load is
approximately:
COUTMAX [ǒILIMPK *ILOADǓ@320 m
VOUT
(eq. 1)
where COUTMAX is expressed in mF and ILOAD is the load
current during soft−start, expressed in A.
If the regulator is at its current limit for 16 consecutive
current limit cycles, the regulator shuts down and enters
tri−state before reattempting soft−start 1700 ms later. This
limits the duty cycle of full output current during soft−start
to prevent excessive heating.
The IC allows for software enable of the regulator, when
EN is HIGH, through the BUCK_EN bits. Only
BUCK_EN1 is initialized HIGH.
Table 7. HARDWARE AND SOFTWARE ENABLE
Pins Bits Output Voltage
EN VSEL BUCK_EN0 BUCK_EN1 35X 44X
0 X X X OFF OFF
1 0 0 X 0 V0 V
1 0 1 X 1.1 V 1.15 V
1 1 X 0 0 V0 V
1 1 X 1 1.15 V 0.85 V
VSEL Pin and I2C Programming Output Voltage
The output voltage is set by the NSELx control bits in
VSEL0 and VSEL1 registers. The output voltage is given as:
VOUT +0.60 V )NSELx @12.5 mV (eq. 2)
Output voltage can also be controlled by toggling the
VSEL pin LOW or HIGH. VSEL LOW corresponds to
VSEL0 and VSEL HIGH corresponds to VSEL1. Upon
POR, VSEL0 and VSEL1 are reset to their default voltages,
shown in Table 11.
Transition Slew Rate Limiting
When transitioning from a low to high voltage, the IC can
be programmed for one of eight possible slew rates using the
SLEW bits in the CONTROL register (Table 12).
Table 8. TRANSITION SLEW RATE
Decimal Bin Slew Rate
0 000 80 mV / ms
1 001 40 mV / ms
2 010 20 mV / ms
3 011 10 mV / ms
4 100 5 mV / ms
5 101 2.5 mV / ms
6110 1.25 mV / ms
7111 0.625 mV / ms
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Transitions from high to low voltage rely on the output
load to discharge VOUT to the new set point. Once the
high−to−low transition begins, the IC stops switching until
VOUT has reached the new set point.
Under−Voltage Lockout (UVLO)
When EN is HIGH, the under−voltage lockout keeps the
part from operating until the input supply voltage raises high
enough to properly operate. This ensures proper operation of
the regulator during startup or shutdown.
Input Over−Voltage Protection (OVP)
When VIN exceeds VSDWN (about 6.2 V) the IC stops
switching to protect the circuitry from internal spikes above
6.5 V. An internal filter prevents the circuit from shutting
down due to noise spikes.
Current Limiting
A heavy load or short circuit on the output causes the
current in the inductor to increase until a maximum current
threshold is reached in the high−side switch. Upon reaching
this point, the high−side switch turns off, preventing high
currents from causing damage. Sixteen consecutive current
limit cycles in current limit cause the regulator to shut down
and stay off for about 1700 ms before attempting a restart.
Thermal Shutdown
When the die temperature increases, due to a high load
condition and/or high ambient temperature, the output
switching is disabled until the die temperature falls
sufficiently. The junction temperature at which the thermal
shutdown activates is nominally 150°C with a 17°C
hysteresis.
I2C Interface
The FAN53200’s serial interface is compatible with
Standard, Fast, Fast Plus, and HS Mode I2C−Bus®
specifications. The FAN53200’s SCL line is an input and its
SDA line is a bi−directional open−drain output; it can only
pull down the bus when active. The SDA line only pulls
LOW during data reads and when signaling ACK. All data
is shifted in MSB (bit 7) first.
I2C Slave Address
In hex notation, the slave address assumes a 0 LS Bit. The
hex slave address is C0.
Table 9. I
2
C SLAVE ADDRESS
Hex
Bits
7 6 5 4 3 2 1 0
C0 1 1 0 0 0 0 0 R/W
Other slave addresses can be assigned. Contact an
ON Semiconductor representative.
Bus Timing
As shown in Figure 14, data is normally transferred when
SCL is LOW. Data is clocked in on the rising edge of SCL.
Typically, data transitions shortly at or after the falling edge
of SCL to allow ample time for the data to set up before the
next SCL rising edge.
SCL tSU
tH
SDA
Data change allowed
Figure 14. Data Transfer Timing
Each bus transaction begins and ends with SDA and SCL
HIGH. A transaction begins with a START condition, which
is defined as SDA transitioning from 1 to 0 with SCL high,
as shown in Figure 15.
SCL
tHD;STA
SDA Slave Address
MS Bit
Figure 15. START Bit
A transaction ends with a STOP condition, which is
defined as SDA transitioning from 0 to 1 with SCL high, as
shown in Figure 16.
SCL
SDA
Slave Releases Master Drives
ACK(0) or
NACK(1)
tHD;STO
Figure 16. STOP Bit
During a read from the FAN53200, the master issues a
REPEATED START after sending the register address, and
before resending the slave address. The REPEATED
START is a 1 to 0 transition on SDA while SCL is HIGH, as
shown in Figure 17.
SCL
SDA ACK(0) or
NACK(1)
Slave Releases
SLADDR
MS Bit
tHD;STA
tSU;STA
Figure 17. REPEATED START Timing
High−Speed (HS) Mode
The protocols for High−Speed (HS), Low−Speed (LS),
and Fast−Speed (FS) Modes are identical, except the bus
speed for HS mode is 3.4 MHz. HS Mode is entered when
the bus master sends the HS master code 00001XXX after
a START condition. The master code is sent in Fast or
Fast−Plus Mode (less than 1 MHz clock); slaves do not ACK
this transmission.
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The master generates a REPEATED START condition
that causes all slaves on the bus to switch to HS Mode. The
master then sends I2C packets, as described above, using the
HS Mode clock rate and timing.
The bus remains in HS Mode until a STOP bit (Figure 16)
is sent by the master. While in HS Mode, packets are
separated by REPEATED START conditions (Figure 17).
Read and Write Transactions
The following figures outline the sequences for data read
and write. Bus control is signified by the shading of the
packet, defined as
ŸŸŸŸŸŸŸ
ŸŸŸŸŸŸŸ
Master Drives Bus
and
Slave Drives Bus
All addresses and data are MSB first.
Table 10. I
2
C BIT DEFINITIONS
for Figure 18 & Figure 19
Symbol Definition
SSTART, see Figure 15
AACK. The slave drives SDA to 0 to acknowledge
the preceding packet.
ANACK. The slave sends a 1 to NACK the preced-
ing packet.
RRepeated START, see Figure 17
PSTOP, see Figure 16
SSlave Address AReg Addr A A P0
7 bits 8 bits 8 bits
Data
000
Figure 18. Write Transaction
SSlave Address AReg Addr A0
7 bits 8 bits
RSlave Address
7 bits
1 A Data A
8 bits
00 01
P
Figure 19. Read Transaction
Register Description
Table 11. REGISTER MAP
Hex
Address Name Function
00 VSEL0 Controls VOUT settings when VSEL pin = 0
01 VSEL1 Controls VOUT settings when VSEL pin = 1
02 CONTROL Determines whether VOUT output discharge is enabled and also the slew rate of positive transitions
03 ID1 Read−only register identifies vendor and chip type
04 ID2 Read−only register identifies die revision
05 MONITOR Indicates device status
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The following table defines the operation of each register bit.
Table 12. BIT DEFINITIONS
Bit Name 35X 44X Description
VSEL0 R/W Register Address: 00
7BUCK_EN0 0 1 Software buck enable. When EN pin is LOW, the regulator is off. When EN pin is
HIGH, BUCK_EN bit takes precedent.
6 MODE0 0 0 0: Allow Auto PFM Mode during light load.
1: Forced PWM Mode.
5:0 NSEL0 101000 101100 Sets VOUT value from 0.6V to 1.3875 V in 12.5 mV steps (see Equation 2).
VSEL1 R/W Register Address: 01
7BUCK_EN1 1 1 Software buck enable. When EN pin is LOW, the regulator is off. When EN pin is
HIGH, BUCK_EN bit takes precedent.
6 MODE1 0 0 0: Allow Auto PFM Mode during light load.
1: Forced PWM Mode.
5:0 NSEL1 101100 010100 Sets VOUT value from 0.6V to 1.3875 V in 12.5 mV steps (see Equation 2).
CONTROL R/W Register Address: 02
7OUTPUT_DISCHARGE 1 0 0: When the regulator is turned off, VOUT is not discharged.
1: When the regulator is turned off, VOUT discharges through an internal pull−
down.
6:4 SLEW 000 000 Sets the slew rate for positive voltage transitions (see Table 8).
3 Reserved 0 0 Always reads back 0
2 RESET
Reserved
0 0 1: Reset all registers to default values.
0: Always reads back 0
1:0 Reserved 00 00 Always reads back 00
ID1 R Register Address: 03
7:5 VENDOR 100 Signifies ON Semiconductor as the IC vendor
4 Reserved 0 Always reads back 0
3:0 DIE_ID 0000 Refer to ordering information
ID2 R Register Address: 04
7:4 Reserved 0000 Always reads back 0000
3:0 DIE_REV 0001 0000 IC mask revision
MONITOR R Register Address: 05
7PGOOD 1 1: buck is enabled and soft−start is completed
6:0 Not used 0000000 Always reads back 000 0000
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Application Information
Selecting the Inductor
The output inductor must meet both the required
inductance and the energy−handling capability of the
application. The inductor value affects the average current
limit, the output voltage ripple, and the efficiency.
The ripple current (DI) of the regulator is:
DI[VOUT
VIN @ǒVIN *VOUT
L@fSW Ǔ(eq. 3)
The maximum average load current, IMAX(LOAD), is
related to the peak current limit, ILIM(PK)by the ripple
current such that:
IMAX(LOAD) +ILIM(PK) *DI
2(eq. 4)
The FAN53200 is optimized for operation with L =
330 nH, but is stable with inductances up to 1.0 mH
(nominal). The inductor should be rated to maintain at least
80% of its value at ILIM(PK). Failure to do so lowers the
amount of DC current the IC can deliver.
Efficiency is affected by the inductor DCR and inductance
value. Decreasing the inductor value for a given physical
size typically decreases the DCR; but since DI increases, the
RMS current increases, as do core and skin−effect losses.
IRMS +IOUT(DC) 2)DI2
12
Ǹ(eq. 5)
The increased RMS current produces higher losses
through the RDS(ON) of the IC MOSFETs as well as the
inductor ESR.
Increasing the inductor value produces lower RMS
currents, but degrades transient response. For a given
physical inductor size, increased inductance usually results
in an inductor with lower saturation current.
Table 13. EFFECTS OF INDUCTOR VALUE (from
330 nH Recommended) on Regulator Performance
IMAX(LOAD) DVOUT
(E
qua
ti
on
7)
Transient Response
Increase Decrease Degraded
Inductor Current Rating
The current limit circuit can allow substantial peak
currents to flow through L1 under worst−case conditions. If
it is possible for the load to draw such currents, the inductor
should be capable of sustaining the current or failing in a safe
manner.
For space−constrained applications, a lower current rating
for L1 can be used. The FAN53200 may still protect these
inductors in the event of a short circuit, but may not be able
to protect the inductor from failure if the load is able to draw
higher currents than the DC rating of the inductor.
Output Capacitor and VOUT Ripple
Table 14 suggests 0805 capacitors, but 0603 capacitors
may be used if space is at a premium. Due to voltage effects,
the 0603 capacitors have a lower in−circuit capacitance than
the 0805 package, which can degrade transient response and
output ripple.
Increasing COUT has negligible effect on loop stability
and can be increased to reduce output voltage ripple or to
improve transient response. Output voltage ripple, DVOUT,
is calculated by:
DVOUT +DILƪfSW @COUT @ESR2
2@D@(1*D))1
8@fSW @COUTƫ
(eq. 6)
where COUT is the effective output capacitance.
The capacitance of COUT decreases at higher output
voltages, which results in higher DVOUT. Equation 6 is only
valid for Continuous Current Mode (CCM) operation,
which occurs when the regulator is in PWM Mode.
For large COUT values, the regulator may fail to start under
a load. If an inductor value greater than 1.0 mH is used, at
least 30 mF of COUT should be used to ensure stability.
The lowest DVOUT is obtained when the IC is in PWM
Mode and, therefore, operating at 2.4 MHz. In PFM Mode,
fSW is reduced, causing DVOUT to increase.
ESL Effects
The Equivalent Series Inductance (ESL) of the output
capacitor network should be kept low to minimize the
square−wave component of output ripple that results from
the division ratio COUT ESL and the output inductor (LOUT).
The square−wave component due to the ESL can be
estimated as:
DVOUT(SQ) [VIN @ESLCOUT
L1 (eq. 7)
A good practice to minimize this ripple is to use multiple
output capacitors to achieve the desired COUT value. For
example, to obtain COUT = 20 mF, a single 22 mF 0805 would
produce twice the square wave ripple as two x 10 mF 0805.
To minimize ESL, try to use capacitors with the lowest
ratio of length to width. 0805s have lower ESL than 1206s.
If low output ripple is a chief concern, some vendors
produce 0508 or 0612 capacitors with ultra−low ESL.
Placing additional small−value capacitors near the load also
reduces the high−frequency ripple components.
Input Capacitor
The ceramic input capacitors should be placed as close as
possible between the VIN pin and PGND to minimize the
parasitic inductance. If a long wire is used to bring power to
the IC, additional “bulk” capacitance (electrolytic or
tantalum) should be placed between CIN and the power
source lead to reduce under−damped ringing that can occur
between the inductance of the power source leads and CIN.
FAN53200
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12
The effective CIN capacitance value decreases as VIN
increases due to DC bias effects. This has no significant
impact on regulator performance.
Thermal Considerations
Heat is removed from the IC through the solder bumps to
the PCB copper. The junction−to−ambient thermal
resistance (θJA) is largely a function of the PCB layout (size,
copper weight, and trace width) and the temperature rise
from junction to ambient (ΔT).
For the FAN53200UC, qJA is 38°C/W when mounted on
its four−layer evaluation board in still air with two−ounce
outer layer copper weight and one−ounce inner layers.
Halving the copper thickness results in an increased θJA of
48°C/W.
For long−term reliable operation, the IC’s junction
temperature (TJ) should be maintained below 125°C.
To calculate maximum operating temperature (<125°C)
for a specific application:
1. Use efficiency graphs to determine efficiency for
the desired VIN, VOUT, and load conditions.
2. Calculate total power dissipation using:
PT+VOUT ILOAD ǒ1
h*1Ǔ(eq. 8)
where h is efficiency.
Estimate inductor copper losses using:
PL+ILOAD 2 DCRL(eq. 9)
3. Determine IC losses by removing inductor losses
(step 3) from total dissipation:
PIC +PT*PL(eq. 10)
4. Determine device operating temperature:
DT+PIC QJA (eq. 11)
and
TIC +TA)DT
It is important to note that the RDS(ON) of the IC’s power
MOSFETs increases linearly with temperature at about
0.21%/°C. This causes the efficiency (η) to degrade with
increasing die temperature.
Recommended External Components
Table 14. RECOMMENDED CAPACITORS
Component Quantity Vendor Vendor C (mF) Size Rated
COUT 2 Pieces C2012X5R0J226M TDK 22 0805 6.3 V
CIN 1 Piece C2012X5R1A106M TDK 10 0805 10 V
Table 15. RECOMMENDED INDUCTORS
Manufacturer Part# L (nH) DCR (mW)ISAT L W H
TOKO DFE201612E−R47M 470 20 6.1 2.0 1.6 1.2
TOKO DFE252012F−R33M 330 14 8.5 2.5 2.0 1.2
FAN53200
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14
Figure 22. Guidance for Layer 3
Figure 23. Remote Sensing Schematic
EN
SDA
SCL
VSEL
FAN53200
VIN
VOUT
SW
GND
AGND
GND
Core
Processor
(System Load)
L1
CIN
COUT
3. The trace resistance between FAN53200 and CPU should not exceed 30 mW.
This table provides resistance
values for given Copper Oz
2. FB trace connects to “+” side of COUT near the load.
1. For remote sensing, additional output capacitors
should be placed near the load.
VDO
COUT
4.9250025
6.51.550025
9.7150025
19.40.550025
Resistance (mW)
Copper (Oz)Length (mils)Width (mils)
Figure 24. Remote Sensing Guidance, Top Layer
TinyBuck is a registered trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or
other countries.
ARM is a registered trademark of ARM Limited (or its subsidiaries) in the EU and/or elsewhere.
OMAP is a trademark and brand of Texas Instruments Incorporated.
NovaThor is a trademark of ST−Ericsson.
ARMADA is a trademark of Emergency Technology, Inc.
Krait is a trademark of Qualcomm Incorporated.
WLCSP20 2.015x1.615x0.586
CASE 567SH
ISSUE O
DATE 30 NOV 2016
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
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