CY7C4261V-15JC - Cypress Semiconductor

: 5423

CY7C4261V/CY7C4271V

CY7C4281V/CY7C4291V

PRELIMINARY

1 6K/32 K/64 K/128Kx9 Low Voltage D ee p Sy nc FI FOs

Cypress Semiconductor Corporation • 3901 No rth First Str eet • San Jose • CA 95134 • 408-943-2600

October 16

1997-Revised March 13

1998

CY7C

Features

• 3.3V operation for low power consumption and easy

integration into low voltage systems

• High-speed, low-power, f irst-in first-out (FI FO)

memories

• 16K x 9 (CY7C4261V)

• 32K x 9 (CY7C4271V)

• 64K x 9 (CY7C4281V)

• 128K x 9 (CY7C4291V)

• 0.35-micron CMOS for optimum speed/power

• High-speed 67-MH z operation (15 ns read/write cycle

times)

• Low power

—ICC=25 mA

—ISB = 3 mA

• Fully asynchronous and simulta neous read and write

operation

• Empt y, Full , and pr ogrammable Almost Empty and Al-

most Full status fla gs

• Output Enable (OE) pin

• Independent read and wri te enable pins

• Su pports fr ee-running 50% duty c ycle clock input s

• Width Expansion capabilty

• 32-pi n PLCC

• Pin-compatible density upgrade to CY7C42X1V

family

• Pin-compat ible 3.3V solu ti ons for CY7C42 61/71/81/9 1

Functional Descript ion

The CY7C4261/71/81/91V are high-speed, low-power, first-in

fir st-out (FI FO) memories wi th cl oc ked read and writ e int erf a c-

es. All are 9 bits wi de. The CY7C4261/ 71/81/91V ar e pin-com-

patible to the CY7C42x1V Synchronous FIFO family . Program-

mab le fea tures include Almost Full/Al most Empty flags. These

FIFOs pr ovide solutions for a w ide variety of dat a buffer ing needs,

including high-speed data acquisition, multiprocessor interfaces , and

communications buff ering.

These FIFOs have 9-bit input and output ports that are con-

trol led by separate cl ock an d enable signals . The i nput port is

controlled by a free-running clock (WCLK) and two write-en-

abl e pins (WEN1, WEN2/LD).

When WEN 1 is LOW and WEN2/LD is HIGH, data is written into the

FIFO on the rising edge of the WCLK signal. While WEN1 and

WEN2/LD are held active , data is continually written into the FIFO on

each WCLK cycle. The output port is controlled in a similar manner

by a free-running read clock (RCLK) and two read enable pins

(REN1, REN2). In addition, the CY7C4261/71/81/91V has an output

enable pin (OE). The read (RCLK) and write ( WCLK) clocks may be

tied together for single-clock oper ation or the two clocks may be run

independently for asynchronous read/write applications. Clock fre-

quencies up to 100 MHz are achiev ab le. Depth expansion is pos-

sib le us ing one en ab le input f or syst em c ontrol , whi le t he other

enable is controlled by expansion logic to direct the flow of

data.

LogicBlock Diagram

4281V–1

THREE-STATE

OUTPUT REGISTER READ

CONTROL

FLAG

LOGIC

WRITE

CONTROL

WRITE

POINTER READ

POINTER

RESET

LOGIC

INPUT

FLAG

PROGRAM

D0−8

RCLK

Q0−8

WEN1

WCLK

Dual Port

WEN2/LD

REN1 REN2

PAE

PAF

RAM Array

16K/32K

x 9

64K/128K

CY7C4261V/CY7C4271V

CY7C4281V/CY7C4291V

PRELIMINARY

Functional Descripti on (continued )

The CY7C4261/71/81/91V provides four status pins: Empty, Full,

Programmable Almost Emp ty, and Programm able Almost Full. The

Almost Empty/Almost Full flags are programmable to single word

granularity. The programmable flags defaul t to Empty +7 and Full −7.

The flags are synchronous, i.e., they change state relative to

eithe r the rea d cloc k (RCLK) or the write clo ck (WCLK) . When

entering or exiting the Empty and Almost Empty states, the

flags are updated e xclusiv ely by th e RCLK. The flags deno ting

Almost Full, and Full state s are up date d ex cl usiv ely b y WCLK.

The synchronous flag architecture guarantees that the flags

maintain their status for at least one cycle

All configurations are fabricated using an advanced 0.35µ

CMOS technology. Input ESD protection is greater than 2001V, and

latch-up is prev ented by the use of guard rings.

Maximum Ratings

(Abov e which the useful l ife may be imp air ed. For use r guide-

li nes, not tes ted.)

Storage Temperature .......................................−65°C to +150°C

Ambient Temperature with

Po wer Applied....................................................−55°C to +125°C

Supply Voltage to Ground Potential..................−0.5V to +3.6V

DC Voltage Applied to Outputs

in High Z State..............................................−0.5V to VCC+0.5V

DC Input Voltage...........................................−0.5V to VCC+0.5V

Output Current into Outputs (LOW) .............................20 mA

Static Discharge Voltage ...........................................>2001V

(per MIL- STD-883, Method 3015 )

Latch-Up Current.....................................................>200 mA

PLCC

RCLK

VCC

GND

WCLK

WEN2/LD

PAF

PAE

REN1

REN2

4321 313032

14 15 16 17 18 19 20

WEN1

Top View

CY7C4261V

CY7C4271V

Pin Configuration

CY7C4281V

CY7C4291V

Selec tion Gu ide

7C4261/71/81/91V−15 7C4261/71/81/91V−25

Maximum Frequency (MHz) 66.7 40

Maximum Access Time (ns) 10 15

Minimum C ycle Time (ns) 15 25

Minimum Data or Enable Set-Up (ns) 4 6

Minimum Data or Enable Hold (ns) 0 1

Maxim u m Flag Delay (ns) 10 15

Active Power Supply

Current (ICC1) ( m A ) Commercial 25 25

Industrial 30

CY7C4261V CY7C4271V CY7C4281V CY7C4291V

Density 16k x 9 32k x 9 6 4k x 9 128k x 9

Package 32-pin PLCC 32-pin PLCC 32-pi n PLCC 32-pin PLCC

Operating Range

Range Ambient

Temperature VCC

Commercial 0°C to +70°C 3.3V + 300mV

and −600mV

Industrial −40°C to +85 °C 3.3V + 300mV

and −600mV

CY7C4261V/CY7C4271V

CY7C4281V/CY7C4291V

PRELIMINARY

Pin Definitions

Signal Name Description I/O Description

D0−8Data Inputs IData Input s for 9-bit bu s

Q0−8Data Outputs OData Outputs for 9-bit bus

WEN1 Wr ite Enable 1 IThe only write enable when device is configured to have programmable flags. Data is

written on a LOW-to-HIGH transition of WCLK when WEN1 is asserted and FF is HIGH.

If the FIFO is configured to have two write enables, data is written on a LOW -to-HIGH transition

of WCLK when WEN1 is LOW and WEN2/LD and FF are HIGH.

WEN2/LD

Dual Mode Pin Write Enable 2 IIf HIGH at reset , this pin ope rates as a second write enab le. If LO W at res et, this pin

operates as a contro l to write or read the programm able fl ag off sets. WEN1 m ust be

LOW and WEN2 must be HIGH to write data into the FIFO. Data will not be written into the FIFO

if the FF is LOW . If the FIFO is configured to hav e programmable flags, WEN2/LD is held LOW

to write or read the progr ammable f lag offsets.

Load

REN1, REN2 Read Enable

Inputs IEnables the device for Read oper ation. Both REN1 and REN2 must be asserted to

allow a read operation.

WCLK Wr ite Clock IThe ris ing ed ge clocks data into the FIFO when WEN1 is LO W and WEN2/LD is HIGH

and the FIFO is not Full. When LD is asserted, WCLK writes data into the programmable flag-off-

set register .

RCLK Read Clock IThe ri sing edge clocks data o ut of the FI FO when R E N 1 and REN2 are LOW and the FIFO

is not Empty. When WEN2/LD is LO W , RCLK reads data out of the prog rammabl e flag-offset

EF Empty Flag OWhen EF is LO W, the FIFO is empty. EF is synchronized to RCLK.

FF Full Flag OWhen FF is LO W, the FIFO is full . FF is synchronized t o WCLK.

PAE Programmable

Almost Empty OWhen PAE is LOW, the FIFO is almost empty based on the almost empty offset v alue pro-

grammed into the FIFO. P AE is synchronized to RCLK.

PAF Programmable

Almost Full OWhen PAF i s LO W, t he FIFO is almost full based on the almost full offset v alue programmed

in to t he FI FO . PAF is synchronized to WCLK.

RS Reset IResets device to empty co ndition. A reset is required before an initial re ad or write

operation after power-up.

OE Output Enable IWhen OE is LOW, the FIFO’ s data outputs drive t he bus to which they are connected. If OE is

HIGH, the FIFO’s outputs are in High Z (high-impedance) state.

CY7C4261V/CY7C4271V

CY7C4281V/CY7C4291V

PRELIMINARY

Electrical Characteristics Over the Operating Range[1]

Parameter Description Tes t Condi tions

7C4261/71/81/91V-15 7C4261/71/81/91V-25

UnitMin. Max. Min. Max.

VOH Output HIGH Voltage VCC = Mi n. , IOH = −1.0 mA

VCC = 3. 0 V, IOH = −2.0 mA 2.4 2.4 V

VOL Output LOW Voltage VCC = Min., IOL = 4.0 mA

VCC = 3. 0 V, IOL = 8.0 mA 0.4 0.4 V

VIH Input HIGH Voltage 2.0 VCC 2.0 VCC V

VIL Input LOW Voltage −0.5 0.8 −0.5 0.8 V

IIX Input Leakage Current VCC = M ax. −10 +10 −10 +10 µA

IOZL

IOZH Output OFF, High Z

Current OE > VIH,

VSS < VO< VCC −10 +10 −10 +10 µA

ICC1[2] Active Power Supply

Current Com’l 25 25 mA

Ind 30 mA

ISB[3] Average Standby

Current Com’l 3 3 mA

Ind 3mA

Capacitance[4]

Parameter Description Test Conditions Max. Unit

CIN Input Capacitance TA = 25°C , f = 1 MHz,

VCC = 3.3V 5pF

COUT Output Capacitance 7pF

AC Test Loads and Waveforms[5, 6 ]

Notes:

1. See the last page of this specification for Group A subgroup testing information.

2. Input signals switch from 0V to 3V with a rise/fall time of less than 3 ns, clocks and clock enables switch at maximum frequency of 20-Mhz, while data inputs

s witch at 10 MHz. Outputs are unloaded. )

3. All inputs = VCC − 0.2V, exc ept WCLK and RCLK ( which ar e at frequenc y = 0 MHz). All outputs a re unloaded.

4. Tested initially and after any design or process changes that may affect these parameters.

5. CL = 30 pF for all AC paramet ers ex cept for tOHZ.

6. CL = 5 pF for tOHZ.

3.0V

3.3V

OUTPUT

R1=330Ω

R2=510Ω

INCLUDING

JIGAND

SCOPE

GND

90%

10%

90%

10%

≤3ns ≤3ns

OUTPUT 2.0V

Equivalentto: THÉ VENIN EQUIVALENT

4281V–4

200 Ω

ALL INPUT PULSES

4281V–5

CY7C4261V/CY7C4271V

CY7C4281V/CY7C4291V

PRELIMINARY

Swi tch i ng C h ara cteri sti cs Over the Operating Range

Parameter Description

7C4261/71/81/91V-15 7C4261/71/81/91V-25

UnitMin. Max. Min. Max.

tSClock Cycle Frequency 66.7 40 MHz

tAData Acc ess Time 210 215 ns

tCLK Clock C y cle Tim e 15 25 ns

tCLKH Clo ck H IG H T i m e 610 ns

tCLKL Clo ck L OW Tim e 610 ns

tDS Data Set-Up Time 4 6 ns

tDH Data Hold Tim e 0 1 ns

tENS Enable Set-Up Time 4 6 ns

tENH En a ble H o ld Tim e 0 1 ns

tRS Reset Pulse Width[7] 15 25 ns

tRSS R eset Set-Up Time 10 15 ns

tRSR Reset Recovery Time 10 15 ns

tRSF Reset to Flag and Output Time 15 25 ns

tOLZ Ou tput En a bl e to Outp u t in Low Z[8] 0 0 ns

tOE Outp ut En a bl e t o O u tput Valid 310 312 ns

tOHZ Outpu t Enable to Output i n High Z[8] 3 8 3 12 ns

tWFF Write Clock to Full Flag 10 15 ns

tREF Read Cloc k to Empty Flag 10 15 ns

tPAF Clock to Programmable Almost-Full Flag 10 15 ns

tPAE Clock to Programmable Almost-Full Flag 10 15 ns

tSKEW1 Ske w Time between Read Clock and Write Cloc k for

Empty Flag and Ful l Flag 610 ns

tSKEW2 Ske w Time between Read Clock and Write Cloc k for

Almost-Empty Flag and Al most-Full Flag 15 18 ns

Notes:

7. Pulse widths less than minimum values are not allowed.

8. Values guaranteed by design, not currently tested.

CY7C4261V/CY7C4271V

CY7C4281V/CY7C4291V

PRELIMINARY

Swi tch i ng Waveform s

Notes:

9. tSKEW1 is the minim um t ime bet ween a rising RCLK edge and a rising WCLK e dge t o gua rantee that FF will go HIGH during the current clock cycle. If the time between the

rising edge of RCL K and th e rising edge of W CLK is less tha n tSKEW1, t hen FF ma y no t change st ate un til the ne xt WCLK rising edge .

10. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH during the current c lock cycle . It the time be twee n th e

rising edge of WCLK and the rising e dge of RCLK is less tha n tSKEW2, then E F ma y not chan ge state until the ne xt RC LK rising edge .

Write Cycle Timing

tCLKH tCLKL

NO OPERATION

tDS

tSKEW1

tENS

WEN1

tCLK

tDH

tWFF tWFF

tENH

WCLK

D0–D17

REN1, REN2

RCLK

4281V–6

NO OPERATION

WEN2

(if ap pl ic able )

[9]

REN1, REN2

Read Cycle Timing

tCLKH tCLKL

NO OPERATION

tSKEW1

WEN1

tCKL

tOHZ

tREF tREF

RCLK

Q0–Q17

WCLK

tOE

tENS

tOLZ

tENH

VALID DATA

4281V–7

WEN2

[10]

CY7C4261V/CY7C4271V

CY7C4281V/CY7C4291V

PRELIMINARY

Notes:

11. The clocks (RCLK, WCLK) can be free-running during reset.

12. After reset, the outputs will be LOW if OE = 0 and three- state if OE=1.

13. Holding WEN2/LD HIGH during r eset w ill make t he pin ac t as a sec ond en able pin. Ho lding W EN2/LD LOW d uring r eset w ill mak e the pin ac t as a load en able f or the

prog r ammabl e flag o ffset r egis ters.

Swi tch i ng Waveform s (continued)

Reset Timing tRS

tRSR

Q0−Q8

tRSF

tRSF OE=1

OE=0

REN1,

REN2

EF,PAE

FF,PAF

4281V–8

tRSS

tRSR

tRSS

tRSR

tRSS

EN2/LD

WEN1

[11]

[13]

[12]

CY7C4261V/CY7C4271V

CY7C4281V/CY7C4291V

PRELIMINARY

Notes:

14. When tSKEW1 > minimu m specificat ion, tFRL ( maximum) = t CLK + t SKEW2. When tSKEW1 < minimum specification, tFRL (maximum) = either 2*tCLK + tSKEW1 or tCLK + tSKEW1.

The L atency Timing applies only at t he Em pty Boun dary (EF = LO W ).

15. The first word is available the cycle after EF go es HIGH, alwa ys .

Swi tch i ng Waveform s (continued)

(F IRST VALI D WRITE)

First Data Word Latency after Reset withRead and Write

tSKEW1

WEN1

WCLK

Q0–Q8

REN1,

REN2

OE tOE

tENS

tOLZ

tDS

RCLK

tREF

tFRL

D1D2D3D4

D0D1

D0–D8

4281V–9

WEN2

(if applic able)

[14]

[15]

CY7C4261V/CY7C4271V

CY7C4281V/CY7C4291V

PRELIMINARY

Swi tch i ng Waveform s (continued)

DATA WRITE 2

DATA WRITE 1

tENS

tSKEW1

DATA IN OUTPUT REGISTER

Empty Flag Timing

WEN1

WCLK

Q0–Q8

REN1,

REN2

tDS

tENH

RCLK

tREF

tFRL

D0–D8

DATA READ

tSKEW2

tFRL

tREF

tDS

tENS

tENH

4281V–10

tENS

WEN2

(if ap pl ic able )

tENH tENS tENH

tREF

LOW

[14] [14]

CY7C4261V/CY7C4271V

CY7C4281V/CY7C4291V

PRELIMINARY

Swi tch i ng Waveform s (continued)

Q0–Q8

REN1,

REN2

WEN1

WEN2

(if ap pl ic able )

D0–D8

NEXT DATA READ

DATA WRITE

NO WRITE

DATA IN OUTPUT REGISTER

Full Flag Timing

WCLK

RCLK

DATA READ

tSKEW1 tDS

tENS tENH

tWFF

tSKEW1

tENS tENH

tWFF

DATA WRITE

NO WRITE

tWFF

LOW

4281V–11

[9] [9]

CY7C4261V/CY7C4271V

CY7C4281V/CY7C4291V

PRELIMINARY

Notes:

16. tSKEW2 is the minimum time betw een a rising WCLK and a rising RCLK edge f or PAE to change state during that cloc k cycle. If the ti me between the edge of WCLK and the

rising RCLK is l ess than tSKEW2, then PAE may no t change state unt il the ne xt RCLK.

17. PAE offset= n.

18. If a read is preformed on this rising edge of the read clock, there will be Empty + (n−1) words in the FIFO when PAE goes L OW

19. If a write is performed on this rising edge of the write clock, there will be Full − (m−1) words of the FIFO when PAF goes LO W.

20. PAF offset = m.

21. 16K−m words for CY7C4261V, 32K m words for CY7C4271V, 64K − m words f or CY7C4281V, and 128K − m words for CY4291V.

22. tSKEW2 is the mi nimum t ime betw een a rising RC LK edge a nd a r ising WC LK edge f or PAF to change during t hat cloc k cycle. If the time between the rising edge of RCLK

and the rising edge of WCLK is les s than tSKEW2, then PAF ma y not change stat e unti l th e ne xt WCLK.

Swi tch i ng Waveform s (continued)

tENH

Programmable Almost Empty Flag Timing

WCLK

PAE

RCLK

tCLKH

tENS

tCLKL

tENS

tPAE

N + 1 WORDS

IN FIFO

4281V–12

tENH

tENS

tENH

tENS

tPAE

REN1,

REN2

WEN1

WEN2

(if ap pl ic able )

tSKEW2

Note

[16]

Note18

Note

tENH

Programmable Almost Full Flag Timing

WCLK

PAF

RCLK

tCLKH

tENS

FULL −MWORDS

IN FIFO

tCLKL

tENS

FULL −(M+1)WORDS

IN FIFO

4281V–13

tENH

tENS

tENH

tENS

tPAF

REN1,

REN2

WEN1

WEN2

(if applicable)

tSKEW2 tPAF

[21]

[22]

CY7C4261V/CY7C4271V

CY7C4281V/CY7C4291V

PRELIMINARY

Architecture

The CY7C4261/71/81/91V consists of an array of 16k, 32k,

64k, or128k words of 9 bi ts each (i m plemented by a dual-port

array of SRAM cells), a read pointer, a write pointer, control

signals (RCLK, WCLK, REN1, REN2, WEN1, WEN2, RS), and

flags (EF, PAE, PAF, FF).

Resetting the FIFO

Upon power-up, the FIFO must be reset with a Reset (RS)

cycle. This causes the FIFO to enter the Empty condition signified by

EF being LO W . All data outputs (Q0−8) go LOW tRSF aft er the rising

edge of RS . In order for the FIFO to reset to its default state, the user

must not read or write while RS is LOW. All flags are guaranteed to

be vali d tRSF af t er R S is taken LO W.

FIFO Operation

When th e W EN 1 signal is activ e LOW , WEN2 is active HIGH, and

FF is activ e HIGH, data present on the D0−8 pi ns is wri tte n in to th e

FIFO on each r ising edge of the W CLK signal. Similar ly, when the

REN1 and REN2 signals are active LOW and EF is active HIGH, data

in the FIFO memory will be presented on the Q0−8 outputs. New data

will be presented on each rising edge of RCLK while REN1 and

REN2 are active. REN1 and REN 2 must set up tENS before RCLK

for it to be a valid read function. WEN1 and WEN2 must occur tENS

before WCLK for it to be a valid write function.

An output enable (OE) pin is provided to three-state the Q0−8 out-

puts when OE is asserted. When OE is enabled (LOW), data in the

output register will be available to the Q0−8 outputs after tOE. If de vic-

es are cascaded, the OE function will only output dat a on the FIFO

that is read enabled.

The FIFO contains overflow circuitry to disallow additional

writes when the FIF O is full, and underfl ow circuitry to disal low

additional reads when the FIFO is empty. An empty FIFO

maintai ns the data of the last v alid re ad on its Q 0−8 outputs even

after additional r eads occur .

Write Enable 1 (WEN1) - If the FIFO is configured for pro-

gramm able flags , Wri te Enable 1 (WEN1) is the only writ e en-

Swi tch i ng Waveform s (continued)

tENH

WriteProgrammable Registers

WEN2/LD

WCLK

tCLKH

tENS

tCLKL

PAE OFFSE T

LSB

D0–D8

WEN1

tENS

PAF OFFSET

MSB

tCLK

tDS tDH

4281V–14

PAE OFFS ET

MSB PAF OFFSET

LSB

PAF OFFSET

MSB

PAF OFFSET

LSB

tENH

Read Programmable Registers

WEN2/LD

RCLK

tCLKH

tENS

tCLKL

PAE OFFSE T LSB

Q0–Q15

REN1,

REN2

tENS

PAE OFFS ET MSB

tCLK

UNKNOWN

4281V–15

CY7C4261V/CY7C4271V

CY7C4281V/CY7C4291V

PRELIMINARY

able control pin. In this configuration, when Write Enable 1

(WEN1) is LO W, da ta can be loade d i nto the input regi ster an d

RAM arr a y on the LO W-to-HIGH tr an sition of e very wri te cloc k

(WCLK). Data is stored is the RAM array sequentially and in-

dependently of any on-going read operat ion.

Write Enable 2/Loa d (WEN2/LD ) - This i s a dual-p urpose pin.

The FIFO is configured at Reset to have program mable flags

or t o have two write ena bles, which allows f or dept h e xpansion.

If Write En ab le 2/ Load ( WEN2/LD ) is set active HIGH at Reset

(RS=LOW), this pin operates as a second write enable pin.

If the FIFO is conf igured to hav e two write en ables, when Write

Enable (WEN1) is LOW and Write Enable 2/Load (WEN2/LD) is

HIGH, data can be loaded into the input register and RAM arra y on

the LOW-to-HIGH transition of every write clock (WCLK). Data is

stored in the RAM array sequentially and independently of any on-go-

ing read operation.

Programming

When WEN2/ L D i s held LOW during Reset, this pin is the load (LD)

enable for flag offset programming. In this configuration, WEN2/LD

can be used to access the four 9-bit offset registers contained in the

CY7C4261/71/81/91V for writing or reading data to these registers.

When the device is configured for programmable flags and

both WEN2/LD and W EN1 are LOW, the first LO W -to-HIGH transi-

tion of WCLK writes data from the data inputs to the empty offset least

significant bit (LSB) register. The second, third, and fourth

LOW-to-HIGH transitions of WCLK store data in the empty offset

most significant bit (MSB) register, full offset LSB register, and full

offset MSB register, respectively, when WEN2/LD and WEN1 are

LOW. The fifth LOW-to-HIGH transition of WCLK while WEN2/LD

and WEN 1 are LOW write s data to the em pty LSB regi ster ag ain.

Figur e 1

shows the registers sizes and def ault values for the various

device types.

It is not necessary to write to al l the o ffset r egisters at one time.

A subset of the off set reg isters can be written ; then by bringing

th e WEN 2 /LD input HIGH, the FIFO is returned to normal read and

write operation. The next time WEN2/LD is brought LO W , a write op-

eration stores data in the next of fset register in sequence.

The contents of the offset registers can be read to the data

outputs when WEN2/LD is LOW and both RE N1 and R EN2 are

LOW . LOW-to-HIGH transitions of RCLK read register contents to the

data outputs. Writes and reads should not be performed simulta-

neously on the offset registers.

Programmable Flag (PAE, PAF) Operation

Whether the flag offset registers are programmed as de-

scribed in

Ta ble 1

or the default values are used, the programmable

almost-empty flag (PAE) and programmable almost-full flag (PAF)

states are determined by their corresponding offset registers and the

difference between the read and write pointers.

Figure 1. Of fset Register Location and Default Val ues

64k x 9

Empty Offset (LSB) Reg.

DefaultValue= 007h

FullOffset(LSB)Reg

DefaultValue= 007h

(MSB)

Empty Offset (LSB) Reg.

Default Value = 007h

FullOffset(LSB)Reg

Default Value = 007h

(MSB)

4281V–16

128k x 9

(MSB)

Default Value = 000h

Default Value= 000h

16k x 9

Empty Offset (LSB) Reg.

Default Value= 007h

Full Offset (LSB) Reg

Default Value= 007h

(MSB)

Empty Offset (LSB) Reg.

Default Value = 007h

Full Offset (LSB) Reg

Default Value = 007h

(MSB)

32k x9

(MSB)

Default Value = 000h

DefaultValue= 000h

Default Value = 000h

8586

CY7C4261V/CY7C4271V

CY7C4281V/CY7C4291V

PRELIMINARY

The number formed by the empty offset least significant bit

fe rred t o as

and determines the operation of PAE. PAF is synchro-

nized to the LOW-to-HIGH transition of RCLK by one flip-flop and is

LOW when the FIFO contai ns n or fewer unread words. PAE is set

HIGH by the LOW -to-HIGH transition of RCLK when the FIFO con-

tains (n+1) or greater unread words.

The num ber formed by the full offset least signif icant bi t regis -

ter and full offset most significant bit register is referred to as

and determines the operation of PAF. P AE is synchronized to the

LOW-to-HIGH transition of WCLK by one flip-flop and is set LOW

when the number of unread words in the FIFO is greater than or equal

to CY7C4261V (16k − m), CY7C4271V (32k − m), CY7C4281V (64k

− m) and CY7C4291V (128k − m). PAF is set HIGH by the

LOW-to-HIGH transition of WCLK when the number of available

memory locations is gr eater than m.

Width Expansion Configuration

W ord width may be increased simply by connecti ng the corre-

spondi ng input controls signal s of mult iple dev ices. A compos-

it e fl ag s hould be crea ted f or eac h of the end- point stat us fl ags

(EF and FF). The partial status flags (PAE and PAF) can be detected

from any one de vice.

Figure 2

demonstrates a 18-bit word width by

using two CY7C42x1Vs. Any word width can be attained by adding

additional CY7C42x1Vs.

When t he CY7 C42x1V is in a Width Expansi on Configur a tion,

the Read Ena ble (REN2) control input can be grounded (See

Fig-

ure 2

). In this configuration, the Write Enable 2/Load (WEN2/LD) pin

is set to LOW at Reset so that the pin operates as a control to load

and read the programmable flag offsets.

Flag Operation

The CY7C4261/71/ 81/91V de v ices pro vide fi ve fl ag pins to in-

dicat e the condi tion of the FI FO conte nts. Empty, Full, PAE, and

PAF are synchronous.

Full Fla g

The Full Flag (FF) will go LOW when the device is full. Write opera-

tions are inhibited whenever FF is LOW regardless of the state of

WEN1 and WEN2/LD. FF is synchronized to WCLK, i.e., it is exclu-

sively updated by each rising edge of WCLK.

Empty Flag

The Empty Flag (EF) will go LOW when the device is empty. Read

operations are inhibited whenever EF is LOW , regardless of the state

of REN1 and REN2. EF is synchronized to RCLK, i.e., it is exclusively

updated b y each rising edge of RCLK.

Table 1. Writing the Offset Register s

LD WEN WCLK[24] Selection

0 0

0 1 No Operation

1 0 Write Into FIFO

1 1 No Operation

Empty Offset (LSB)

Empty Offset (MSB)

Full Offset (LSB)

Full Offset (MSB)

Table 2. Status Flags

Numbe r of Words in FIFO

FF PAF PAE EFCY7C4261V CY7C4271V CY7C4281V CY7C4291V

0 0 0 0 H H L L

1 to n[24] 1 to n[24] 1 to n[24] 1 to n[24] H H L H

(n+1) to (1638 − (m + 1 ) ) (n+1) to ( 32768 −

(m+1)) (n+1) to ( 65536 −

(m+1)) (n+1) to (131072−

(m+1)) H H H H

(16384 − m)[25] to 16383 (32768 − m)[25] to 32767 (65536 − m)[25] to 65535 (131072 − m)[25] to

131071 H L H H

16384 32768 65536 131072 L L H H

Notes:

23. The same selection sequence applies to reading from the registers. REN1 a nd RE N2 are enab led an d a r ead is per f ormed on the LO W -to- HIGH transi tion of RCLK

24. n = Empty Offset (n=7 default value).

25. m = Full Offset (m=7 default value)..

CY7C4261V/CY7C4271V

CY7C4281V/CY7C4291V

PRELIMINARY

Document #: 38-00656-A

Figure 2. Block Diagram o f 16k/32k/64k/128k x 9 Low Voltage Deep Sync FI FO Memory Used in a Width Expansion

Configuration

4281V–17

FF EF EF

WRITECLOCK(WCLK)

WRITE ENABLE1(WEN1)

WRITE ENABLE2/LOAD

(WEN2/LD)

PROGRAMMABLE(PAF)

FULLFLAG(FF)# 1

CY7C4261V

918

DATAIN (D)

RESET(RS)

READCLOCK(RCLK)

READENABLE1 (REN1)

OUTPUT ENABLE(OE)

PROGRAMMABLE(PAE)

EMPTY FLAG (EF)#1

DATA OUT(Q)

918

ReadEnable2 (REN2)

EMPTY FLAG(EF)#2

FULLFLAG(FF)# 2

Read Enable 2 (REN2)

CY7C4271V

CY7C4281V

CY7C4291V

CY7C4261V

CY7C4271V

CY7C4281V

CY7C4291V

Ordering Information

16Kx9 Low Voltage Deep Sync FI FO

Speed

(ns) Ordering Code Package

Name Package

Type Operating

Range

15 CY7C4261V-15JC J65 32-Lead Plastic Leaded Chip Carrier Commercial

CY7C4261V-15JI J65 32-Lead Plastic Leaded Chip Carrier Industrial

25 CY7C4261V-25JC J65 32-Lead Plastic Leaded Chip Carrier Commercial

32Kx9 Low Voltage Deep Sync FI FO

Speed

(ns) Ordering Code Package

Name Package

Type Operating

Range

15 CY7C4271V-15JC J65 32-Lead Plastic Leaded Chip Carrier Commercial

CY7C4271V-15JI J65 32-Lead Plastic Leaded Chip Carrier Industrial

25 CY7C4271V-25JC J65 32-Lead Plastic Leaded Chip Carrier Commercial

64kx9 Low Voltage Deep Sync FIFO

Speed

(ns) Ordering Code Package

Name Package

Type Operating

Range

15 CY7C4281V-15JC J65 32-Lead Plastic Leaded Chip Carrier Commercial

CY7C4281V-15JI J65 32-Lead Plastic Leaded Chip Carrier Industrial

25 CY7C4281V-25JC J65 32-Lead Plastic Leaded Chip Carrier Commercial

128kx9 Low Voltage Deep Sync FIFO

Speed

(ns) Ordering Code Package

Name Package

Type Operating

Range

15 CY7C4291V-15JC J65 32-Lead Plastic Leaded Chip Carrier Commercial

CY7C4291V-15JI J65 32-Lead Plastic Leaded Chip Carrier Industrial

25 CY7C4291V-25JC J65 32-Lead Plastic Leaded Chip Carrier Commercial

CY7C4261V/CY7C4271V

CY7C4281V/CY7C4291V

PRELIMINARY

of any circui try other than circuitry embodied in a Cypress Semiconduc tor product. Nor does it con vey or imply any lice nse under patent or other rights. Cypress Semiconductor does not authorize

its products for use as critical components in life-suppor t systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

Package Di ag ra m

32-Lead Plastic Leaded Chip Carrier J65